irq.h 2.5 KB

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  1. #ifdef __KERNEL__
  2. #ifndef _ASM_M32R_IRQ_H
  3. #define _ASM_M32R_IRQ_H
  4. #include <linux/config.h>
  5. #if defined(CONFIG_PLAT_M32700UT_Alpha) || defined(CONFIG_PLAT_USRV)
  6. /*
  7. * IRQ definitions for M32700UT
  8. * M32700 Chip: 64 interrupts
  9. * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
  10. */
  11. #define M32700UT_NUM_CPU_IRQ (64)
  12. #define M32700UT_NUM_PLD_IRQ (32)
  13. #define M32700UT_IRQ_BASE 0
  14. #define M32700UT_CPU_IRQ_BASE M32700UT_IRQ_BASE
  15. #define M32700UT_PLD_IRQ_BASE (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
  16. #define NR_IRQS (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ)
  17. #elif defined(CONFIG_PLAT_M32700UT)
  18. /*
  19. * IRQ definitions for M32700UT(Rev.C) + M32R-LAN
  20. * M32700 Chip: 64 interrupts
  21. * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
  22. * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
  23. * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
  24. */
  25. #define M32700UT_NUM_CPU_IRQ (64)
  26. #define M32700UT_NUM_PLD_IRQ (32)
  27. #define M32700UT_NUM_LCD_PLD_IRQ (32)
  28. #define M32700UT_NUM_LAN_PLD_IRQ (32)
  29. #define M32700UT_IRQ_BASE 0
  30. #define M32700UT_CPU_IRQ_BASE (M32700UT_IRQ_BASE)
  31. #define M32700UT_PLD_IRQ_BASE \
  32. (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
  33. #define M32700UT_LCD_PLD_IRQ_BASE \
  34. (M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ)
  35. #define M32700UT_LAN_PLD_IRQ_BASE \
  36. (M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ)
  37. #define NR_IRQS \
  38. (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \
  39. + M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ)
  40. #elif defined(CONFIG_PLAT_OPSPUT)
  41. /*
  42. * IRQ definitions for OPSPUT + M32R-LAN
  43. * OPSP Chip: 64 interrupts
  44. * ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
  45. * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
  46. * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
  47. */
  48. #define OPSPUT_NUM_CPU_IRQ (64)
  49. #define OPSPUT_NUM_PLD_IRQ (32)
  50. #define OPSPUT_NUM_LCD_PLD_IRQ (32)
  51. #define OPSPUT_NUM_LAN_PLD_IRQ (32)
  52. #define OPSPUT_IRQ_BASE 0
  53. #define OPSPUT_CPU_IRQ_BASE (OPSPUT_IRQ_BASE)
  54. #define OPSPUT_PLD_IRQ_BASE \
  55. (OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ)
  56. #define OPSPUT_LCD_PLD_IRQ_BASE \
  57. (OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ)
  58. #define OPSPUT_LAN_PLD_IRQ_BASE \
  59. (OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ)
  60. #define NR_IRQS \
  61. (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
  62. + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
  63. #else
  64. #define NR_IRQS 64
  65. #endif
  66. #define irq_canonicalize(irq) (irq)
  67. #endif /* _ASM_M32R_IRQ_H */
  68. #endif /* __KERNEL__ */