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asm-arm
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arch-s3c2410
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bast-cpld.h

bast-cpld.h 1.7 KB
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  1. /* linux/include/asm-arm/arch-s3c2410/bast-cpld.h
    2. 

  2.  *
    3. 

  3.  * (c) 2003,2004 Simtec Electronics
    4. 

  4.  *  Ben Dooks <ben@simtec.co.uk>
    5. 

  5.  *
    6. 

  6.  * BAST - CPLD control constants
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11.  *
    12. 

  12.  * Changelog:
    13. 

  13.  *  25-May-2003 BJD  Created file, added CTRL1 registers
    14. 

  14.  *  30-Aug-2004 BJD  Updated definitions from 2.4.26 port
    15. 

  15.  *  30-Aug-2004 BJD  Added CTRL3 and CTRL4 definitions
    16. 

  16. */
    17. 

  17. 

  18. #ifndef __ASM_ARCH_BASTCPLD_H
    19. 

  19. #define __ASM_ARCH_BASTCPLD_H
    20. 

  20. 

  21. /* CTRL1 - Audio LR routing */
    22. 

  22. 

  23. #define BAST_CPLD_CTRL1_LRCOFF	    (0x00)
    24. 

  24. #define BAST_CPLD_CTRL1_LRCADC	    (0x01)
    25. 

  25. #define BAST_CPLD_CTRL1_LRCDAC	    (0x02)
    26. 

  26. #define BAST_CPLD_CTRL1_LRCARM	    (0x03)
    27. 

  27. #define BAST_CPLD_CTRL1_LRMASK	    (0x03)
    28. 

  28. 

  29. /* CTRL2 - NAND WP control, IDE Reset assert/check */
    30. 

  30. 

  31. #define BAST_CPLD_CTRL2_WNAND       (0x04)
    32. 

  32. #define BAST_CPLD_CTLR2_IDERST      (0x08)
    33. 

  33. 

  34. /* CTRL3 - rom write control, CPLD identity */
    35. 

  35. 

  36. #define BAST_CPLD_CTRL3_IDMASK      (0x0e)
    37. 

  37. #define BAST_CPLD_CTRL3_ROMWEN      (0x01)
    38. 

  38. 

  39. /* CTRL4 - 8bit LCD interface control/status */
    40. 

  40. 

  41. #define BAST_CPLD_CTRL4_LLAT	    (0x01)
    42. 

  42. #define BAST_CPLD_CTRL4_LCDRW	    (0x02)
    43. 

  43. #define BAST_CPLD_CTRL4_LCDCMD	    (0x04)
    44. 

  44. #define BAST_CPLD_CTRL4_LCDE2	    (0x01)
    45. 

  45. 

  46. /* CTRL5 - DMA routing */
    47. 

  47. 

  48. #define BAST_CPLD_DMA0_PRIIDE      (0<<0)
    49. 

  49. #define BAST_CPLD_DMA0_SECIDE      (1<<0)
    50. 

  50. #define BAST_CPLD_DMA0_ISA15       (2<<0)
    51. 

  51. #define BAST_CPLD_DMA0_ISA36       (3<<0)
    52. 

  52. 

  53. #define BAST_CPLD_DMA1_PRIIDE      (0<<2)
    54. 

  54. #define BAST_CPLD_DMA1_SECIDE      (1<<2)
    55. 

  55. #define BAST_CPLD_DMA1_ISA15       (2<<2)
    56. 

  56. #define BAST_CPLD_DMA1_ISA36       (3<<2)
    57. 

  57. 

  58. #endif /* __ASM_ARCH_BASTCPLD_H */
    59.