sstfb.c 48 KB

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  1. /*
  2. * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
  3. *
  4. * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
  5. *
  6. * Created 15 Jan 2000 by Ghozlane Toumi
  7. *
  8. * Contributions (and many thanks) :
  9. *
  10. * 03/2001 James Simmons <jsimmons@infradead.org>
  11. * 04/2001 Paul Mundt <lethal@chaoticdreams.org>
  12. * 05/2001 Urs Ganse <ursg@uni.de>
  13. * (initial work on voodoo2 port, interlace)
  14. * 09/2002 Helge Deller <deller@gmx.de>
  15. * (enable driver on big-endian machines (hppa), ioctl fixes)
  16. * 12/2002 Helge Deller <deller@gmx.de>
  17. * (port driver to new frambuffer infrastructure)
  18. * 01/2003 Helge Deller <deller@gmx.de>
  19. * (initial work on fb hardware acceleration for voodoo2)
  20. *
  21. */
  22. /*
  23. * The voodoo1 has the following memory mapped address space:
  24. * 0x000000 - 0x3fffff : registers (4MB)
  25. * 0x400000 - 0x7fffff : linear frame buffer (4MB)
  26. * 0x800000 - 0xffffff : texture memory (8MB)
  27. */
  28. /*
  29. * misc notes, TODOs, toASKs, and deep thoughts
  30. -TODO: at one time or another test that the mode is acceptable by the monitor
  31. -ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
  32. wich one should i use ? is there any preferred one ? It seems ARGB is
  33. the one ...
  34. -TODO: in set_var check the validity of timings (hsync vsync)...
  35. -TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
  36. a nop command. so it's ok as long as the commands we pass don't go
  37. through the fifo. warning: issuing a nop command seems to need pci_fifo
  38. -FIXME: in case of failure in the init sequence, be sure we return to a safe
  39. state.
  40. -FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
  41. */
  42. /*
  43. * debug info
  44. * SST_DEBUG : enable debugging
  45. * SST_DEBUG_REG : debug registers
  46. * 0 : no debug
  47. * 1 : dac calls, [un]set_bits, FbiInit
  48. * 2 : insane debug level (log every register read/write)
  49. * SST_DEBUG_FUNC : functions
  50. * 0 : no debug
  51. * 1 : function call / debug ioctl
  52. * 2 : variables
  53. * 3 : flood . you don't want to do that. trust me.
  54. * SST_DEBUG_VAR : debug display/var structs
  55. * 0 : no debug
  56. * 1 : dumps display, fb_var
  57. *
  58. * sstfb specific ioctls:
  59. * toggle vga (0x46db) : toggle vga_pass_through
  60. * fill fb (0x46dc) : fills fb
  61. * test disp (0x46de) : draws a test image
  62. */
  63. #undef SST_DEBUG
  64. /* enable 24/32 bpp functions ? (completely untested!) */
  65. #undef EN_24_32_BPP
  66. /*
  67. Default video mode .
  68. 0 800x600@60 took from glide
  69. 1 640x480@75 took from glide
  70. 2 1024x768@76 std fb.mode
  71. 3 640x480@60 glide default */
  72. #define DEFAULT_MODE 3
  73. /*
  74. * Includes
  75. */
  76. #include <linux/config.h>
  77. #include <linux/string.h>
  78. #include <linux/kernel.h>
  79. #include <linux/module.h>
  80. #include <linux/fb.h>
  81. #include <linux/pci.h>
  82. #include <linux/delay.h>
  83. #include <linux/init.h>
  84. #include <linux/slab.h>
  85. #include <asm/io.h>
  86. #include <asm/ioctl.h>
  87. #include <asm/uaccess.h>
  88. #include <video/sstfb.h>
  89. /* initialized by setup */
  90. static int vgapass; /* enable Vga passthrough cable */
  91. static int mem; /* mem size in MB, 0 = autodetect */
  92. static int clipping = 1; /* use clipping (slower, safer) */
  93. static int gfxclk; /* force FBI freq in Mhz . Dangerous */
  94. static int slowpci; /* slow PCI settings */
  95. static char *mode_option __devinitdata;
  96. enum {
  97. ID_VOODOO1 = 0,
  98. ID_VOODOO2 = 1,
  99. };
  100. #define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
  101. static struct sst_spec voodoo_spec[] __devinitdata = {
  102. { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
  103. { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 },
  104. };
  105. static struct fb_var_screeninfo sstfb_default =
  106. #if ( DEFAULT_MODE == 0 )
  107. { /* 800x600@60, 16 bpp .borowed from glide/sst1/include/sst1init.h */
  108. 800, 600, 800, 600, 0, 0, 16, 0,
  109. {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
  110. 0, 0, -1, -1, 0,
  111. 25000, 86, 41, 23, 1, 127, 4,
  112. 0, FB_VMODE_NONINTERLACED };
  113. #elif ( DEFAULT_MODE == 1 )
  114. {/* 640x480@75, 16 bpp .borowed from glide/sst1/include/sst1init.h */
  115. 640, 480, 640, 480, 0, 0, 16, 0,
  116. {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
  117. 0, 0, -1, -1, 0,
  118. 31746, 118, 17, 16, 1, 63, 3,
  119. 0, FB_VMODE_NONINTERLACED };
  120. #elif ( DEFAULT_MODE == 2 )
  121. { /* 1024x768@76 took from my /etc/fb.modes */
  122. 1024, 768, 1024, 768,0, 0, 16,0,
  123. {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
  124. 0, 0, -1, -1, 0,
  125. 11764, 208, 8, 36, 16, 120, 3 ,
  126. 0, FB_VMODE_NONINTERLACED };
  127. #elif ( DEFAULT_MODE == 3 )
  128. { /* 640x480@60 , 16bpp glide default ?*/
  129. 640, 480, 640, 480, 0, 0, 16, 0,
  130. {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
  131. 0, 0, -1, -1, 0,
  132. 39721 , 38, 26 , 25 ,18 , 96 ,2,
  133. 0, FB_VMODE_NONINTERLACED };
  134. #elif
  135. #error "Invalid DEFAULT_MODE value !"
  136. #endif
  137. /*
  138. * debug functions
  139. */
  140. static void sstfb_drawdebugimage(struct fb_info *info);
  141. static int sstfb_dump_regs(struct fb_info *info);
  142. #if (SST_DEBUG_REG > 0)
  143. static void sst_dbg_print_read_reg(u32 reg, u32 val) {
  144. const char *regname;
  145. switch (reg) {
  146. case FBIINIT0: regname = "FbiInit0"; break;
  147. case FBIINIT1: regname = "FbiInit1"; break;
  148. case FBIINIT2: regname = "FbiInit2"; break;
  149. case FBIINIT3: regname = "FbiInit3"; break;
  150. case FBIINIT4: regname = "FbiInit4"; break;
  151. case FBIINIT5: regname = "FbiInit5"; break;
  152. case FBIINIT6: regname = "FbiInit6"; break;
  153. default: regname = NULL; break;
  154. }
  155. if (regname == NULL)
  156. r_ddprintk("sst_read(%#x): %#x\n", reg, val);
  157. else
  158. r_dprintk(" sst_read(%s): %#x\n", regname, val);
  159. }
  160. static void sst_dbg_print_write_reg(u32 reg, u32 val) {
  161. const char *regname;
  162. switch (reg) {
  163. case FBIINIT0: regname = "FbiInit0"; break;
  164. case FBIINIT1: regname = "FbiInit1"; break;
  165. case FBIINIT2: regname = "FbiInit2"; break;
  166. case FBIINIT3: regname = "FbiInit3"; break;
  167. case FBIINIT4: regname = "FbiInit4"; break;
  168. case FBIINIT5: regname = "FbiInit5"; break;
  169. case FBIINIT6: regname = "FbiInit6"; break;
  170. default: regname = NULL; break;
  171. }
  172. if (regname == NULL)
  173. r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
  174. else
  175. r_dprintk(" sst_write(%s, %#x)\n", regname, val);
  176. }
  177. #else /* (SST_DEBUG_REG > 0) */
  178. # define sst_dbg_print_read_reg(reg, val) do {} while(0)
  179. # define sst_dbg_print_write_reg(reg, val) do {} while(0)
  180. #endif /* (SST_DEBUG_REG > 0) */
  181. /*
  182. * hardware access functions
  183. */
  184. /* register access */
  185. #define sst_read(reg) __sst_read(par->mmio_vbase, reg)
  186. #define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val)
  187. #define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val)
  188. #define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val)
  189. #define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg)
  190. #define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val)
  191. #define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
  192. #define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
  193. static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
  194. {
  195. u32 ret = readl(vbase + reg);
  196. sst_dbg_print_read_reg(reg, ret);
  197. return ret;
  198. }
  199. static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
  200. {
  201. sst_dbg_print_write_reg(reg, val);
  202. writel(val, vbase + reg);
  203. }
  204. static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
  205. {
  206. r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
  207. __sst_write(vbase, reg, __sst_read(vbase, reg) | val);
  208. }
  209. static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
  210. {
  211. r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
  212. __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
  213. }
  214. /*
  215. * wait for the fbi chip. ASK: what happens if the fbi is stuck ?
  216. *
  217. * the FBI is supposed to be ready if we receive 5 time
  218. * in a row a "idle" answer to our requests
  219. */
  220. #define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
  221. static int __sst_wait_idle(u8 __iomem *vbase)
  222. {
  223. int count = 0;
  224. /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
  225. while(1) {
  226. if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
  227. f_dddprintk("status: busy\n");
  228. /* FIXME basicaly, this is a busy wait. maybe not that good. oh well;
  229. * this is a small loop after all.
  230. * Or maybe we should use mdelay() or udelay() here instead ? */
  231. count = 0;
  232. } else {
  233. count++;
  234. f_dddprintk("status: idle(%d)\n", count);
  235. }
  236. if (count >= 5) return 1;
  237. /* XXX do something to avoid hanging the machine if the voodoo is out */
  238. }
  239. }
  240. /* dac access */
  241. /* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
  242. static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
  243. {
  244. u8 ret;
  245. reg &= 0x07;
  246. __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
  247. __sst_wait_idle(vbase);
  248. /* udelay(10); */
  249. ret = __sst_read(vbase, DAC_READ) & 0xff;
  250. r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
  251. return ret;
  252. }
  253. static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
  254. {
  255. r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
  256. reg &= 0x07;
  257. __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
  258. }
  259. /* indexed access to ti/att dacs */
  260. static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
  261. {
  262. u32 ret;
  263. __sst_dac_write(vbase, DACREG_ADDR_I, reg);
  264. ret = __sst_dac_read(vbase, DACREG_DATA_I);
  265. r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
  266. return ret;
  267. }
  268. static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
  269. {
  270. r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
  271. __sst_dac_write(vbase, DACREG_ADDR_I, reg);
  272. __sst_dac_write(vbase, DACREG_DATA_I, val);
  273. }
  274. /* compute the m,n,p , returns the real freq
  275. * (ics datasheet : N <-> N1 , P <-> N2)
  276. *
  277. * Fout= Fref * (M+2)/( 2^P * (N+2))
  278. * we try to get close to the asked freq
  279. * with P as high, and M as low as possible
  280. * range:
  281. * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
  282. * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
  283. * we'll use the lowest limitation, should be precise enouth
  284. */
  285. static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
  286. {
  287. int m, m2, n, p, best_err, fout;
  288. int best_n = -1;
  289. int best_m = -1;
  290. best_err = freq;
  291. p = 3;
  292. /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
  293. while (((1 << p) * freq > VCO_MAX) && (p >= 0))
  294. p--;
  295. if (p == -1)
  296. return -EINVAL;
  297. for (n = 1; n < 32; n++) {
  298. /* calc 2 * m so we can round it later*/
  299. m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
  300. m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
  301. if (m >= 128)
  302. break;
  303. fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
  304. if ((abs(fout - freq) < best_err) && (m > 0)) {
  305. best_n = n;
  306. best_m = m;
  307. best_err = abs(fout - freq);
  308. /* we get the lowest m , allowing 0.5% error in freq*/
  309. if (200*best_err < freq) break;
  310. }
  311. }
  312. if (best_n == -1) /* unlikely, but who knows ? */
  313. return -EINVAL;
  314. t->p = p;
  315. t->n = best_n;
  316. t->m = best_m;
  317. *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
  318. f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
  319. t->m, t->n, t->p, *freq_out);
  320. return 0;
  321. }
  322. /*
  323. * clear lfb screen
  324. */
  325. static void sstfb_clear_screen(struct fb_info *info)
  326. {
  327. /* clear screen */
  328. fb_memset(info->screen_base, 0, info->fix.smem_len);
  329. }
  330. /**
  331. * sstfb_check_var - Optional function. Validates a var passed in.
  332. * @var: frame buffer variable screen structure
  333. * @info: frame buffer structure that represents a single frame buffer
  334. */
  335. static int sstfb_check_var(struct fb_var_screeninfo *var,
  336. struct fb_info *info)
  337. {
  338. struct sstfb_par *par = (struct sstfb_par *) info->par;
  339. int hSyncOff = var->xres + var->right_margin + var->left_margin;
  340. int vSyncOff = var->yres + var->lower_margin + var->upper_margin;
  341. int vBackPorch = var->left_margin, yDim = var->yres;
  342. int vSyncOn = var->vsync_len;
  343. int tiles_in_X, real_length;
  344. unsigned int freq;
  345. if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
  346. eprintk("Pixclock at %ld KHZ out of range\n",
  347. PICOS2KHZ(var->pixclock));
  348. return -EINVAL;
  349. }
  350. var->pixclock = KHZ2PICOS(freq);
  351. if (var->vmode & FB_VMODE_INTERLACED)
  352. vBackPorch += (vBackPorch % 2);
  353. if (var->vmode & FB_VMODE_DOUBLE) {
  354. vBackPorch <<= 1;
  355. yDim <<=1;
  356. vSyncOn <<=1;
  357. vSyncOff <<=1;
  358. }
  359. switch (var->bits_per_pixel) {
  360. case 0 ... 16 :
  361. var->bits_per_pixel = 16;
  362. break;
  363. #ifdef EN_24_32_BPP
  364. case 17 ... 24 :
  365. var->bits_per_pixel = 24;
  366. break;
  367. case 25 ... 32 :
  368. var->bits_per_pixel = 32;
  369. break;
  370. #endif
  371. default :
  372. eprintk("Unsupported bpp %d\n", var->bits_per_pixel);
  373. return -EINVAL;
  374. }
  375. /* validity tests */
  376. if ((var->xres <= 1) || (yDim <= 0 )
  377. || (var->hsync_len <= 1)
  378. || (hSyncOff <= 1)
  379. || (var->left_margin <= 2)
  380. || (vSyncOn <= 0)
  381. || (vSyncOff <= 0)
  382. || (vBackPorch <= 0)) {
  383. return -EINVAL;
  384. }
  385. if (IS_VOODOO2(par)) {
  386. /* Voodoo 2 limits */
  387. tiles_in_X = (var->xres + 63 ) / 64 * 2;
  388. if (((var->xres - 1) >= POW2(11)) || (yDim >= POW2(11))) {
  389. eprintk("Unsupported resolution %dx%d\n",
  390. var->xres, var->yres);
  391. return -EINVAL;
  392. }
  393. if (((var->hsync_len-1) >= POW2(9))
  394. || ((hSyncOff-1) >= POW2(11))
  395. || ((var->left_margin - 2) >= POW2(9))
  396. || (vSyncOn >= POW2(13))
  397. || (vSyncOff >= POW2(13))
  398. || (vBackPorch >= POW2(9))
  399. || (tiles_in_X >= POW2(6))
  400. || (tiles_in_X <= 0)) {
  401. eprintk("Unsupported Timings\n");
  402. return -EINVAL;
  403. }
  404. } else {
  405. /* Voodoo limits */
  406. tiles_in_X = (var->xres + 63 ) / 64;
  407. if (var->vmode) {
  408. eprintk("Interlace/Doublescan not supported %#x\n",
  409. var->vmode);
  410. return -EINVAL;
  411. }
  412. if (((var->xres - 1) >= POW2(10)) || (var->yres >= POW2(10))) {
  413. eprintk("Unsupported resolution %dx%d\n",
  414. var->xres, var->yres);
  415. return -EINVAL;
  416. }
  417. if (((var->hsync_len - 1) >= POW2(8))
  418. || ((hSyncOff-1) >= POW2(10))
  419. || ((var->left_margin - 2) >= POW2(8))
  420. || (vSyncOn >= POW2(12))
  421. || (vSyncOff >= POW2(12))
  422. || (vBackPorch >= POW2(8))
  423. || (tiles_in_X >= POW2(4))
  424. || (tiles_in_X <= 0)) {
  425. eprintk("Unsupported Timings\n");
  426. return -EINVAL;
  427. }
  428. }
  429. /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
  430. /* FIXME: i don't like this... looks wrong */
  431. real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 )
  432. * ((var->bits_per_pixel == 16) ? 2 : 4);
  433. if ((real_length * yDim) > info->fix.smem_len) {
  434. eprintk("Not enough video memory\n");
  435. return -ENOMEM;
  436. }
  437. var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
  438. var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
  439. var->xoffset = 0;
  440. var->yoffset = 0;
  441. var->height = -1;
  442. var->width = -1;
  443. /*
  444. * correct the color bit fields
  445. */
  446. /* var->{red|green|blue}.msb_right = 0; */
  447. switch (var->bits_per_pixel) {
  448. case 16: /* RGB 565 LfbMode 0 */
  449. var->red.length = 5;
  450. var->green.length = 6;
  451. var->blue.length = 5;
  452. var->transp.length = 0;
  453. var->red.offset = 11;
  454. var->green.offset = 5;
  455. var->blue.offset = 0;
  456. var->transp.offset = 0;
  457. break;
  458. #ifdef EN_24_32_BPP
  459. case 24: /* RGB 888 LfbMode 4 */
  460. case 32: /* ARGB 8888 LfbMode 5 */
  461. var->red.length = 8;
  462. var->green.length = 8;
  463. var->blue.length = 8;
  464. var->transp.length = 0;
  465. var->red.offset = 16;
  466. var->green.offset = 8;
  467. var->blue.offset = 0;
  468. var->transp.offset = 0; /* in 24bpp we fake a 32 bpp mode */
  469. break;
  470. #endif
  471. default:
  472. return -EINVAL;
  473. }
  474. return 0;
  475. }
  476. /**
  477. * sstfb_set_par - Optional function. Alters the hardware state.
  478. * @info: frame buffer structure that represents a single frame buffer
  479. */
  480. static int sstfb_set_par(struct fb_info *info)
  481. {
  482. struct sstfb_par *par = (struct sstfb_par *) info->par;
  483. u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
  484. struct pci_dev *sst_dev = par->dev;
  485. unsigned int freq;
  486. int ntiles;
  487. par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin;
  488. par->yDim = info->var.yres;
  489. par->vSyncOn = info->var.vsync_len;
  490. par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin;
  491. par->vBackPorch = info->var.upper_margin;
  492. /* We need par->pll */
  493. sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
  494. if (info->var.vmode & FB_VMODE_INTERLACED)
  495. par->vBackPorch += (par->vBackPorch % 2);
  496. if (info->var.vmode & FB_VMODE_DOUBLE) {
  497. par->vBackPorch <<= 1;
  498. par->yDim <<=1;
  499. par->vSyncOn <<=1;
  500. par->vSyncOff <<=1;
  501. }
  502. if (IS_VOODOO2(par)) {
  503. /* voodoo2 has 32 pixel wide tiles , BUT stange things
  504. happen with odd number of tiles */
  505. par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
  506. } else {
  507. /* voodoo1 has 64 pixels wide tiles. */
  508. par->tiles_in_X = (info->var.xres + 63 ) / 64;
  509. }
  510. f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
  511. f_ddprintk("%-7d %-8d %-7d %-8d\n",
  512. info->var.hsync_len, par->hSyncOff,
  513. par->vSyncOn, par->vSyncOff);
  514. f_ddprintk("left_margin upper_margin xres yres Freq\n");
  515. f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
  516. info->var.left_margin, info->var.upper_margin,
  517. info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
  518. sst_write(NOPCMD, 0);
  519. sst_wait_idle();
  520. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
  521. sst_set_bits(FBIINIT1, VIDEO_RESET);
  522. sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
  523. sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
  524. sst_wait_idle();
  525. /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
  526. sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
  527. sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
  528. sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
  529. sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn);
  530. fbiinit2 = sst_read(FBIINIT2);
  531. fbiinit3 = sst_read(FBIINIT3);
  532. /* everything is reset. we enable fbiinit2/3 remap : dac acces ok */
  533. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
  534. PCI_EN_INIT_WR | PCI_REMAP_DAC );
  535. par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
  536. /* set video clock */
  537. par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
  538. /* disable fbiinit2/3 remap */
  539. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
  540. PCI_EN_INIT_WR);
  541. /* restore fbiinit2/3 */
  542. sst_write(FBIINIT2,fbiinit2);
  543. sst_write(FBIINIT3,fbiinit3);
  544. fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
  545. | EN_DATA_OE
  546. | EN_BLANK_OE
  547. | EN_HVSYNC_OE
  548. | EN_DCLK_OE
  549. /* | (15 << TILES_IN_X_SHIFT) */
  550. | SEL_INPUT_VCLK_2X
  551. /* | (2 << VCLK_2X_SEL_DEL_SHIFT)
  552. | (2 << VCLK_DEL_SHIFT) */;
  553. /* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
  554. in (near) future set them accordingly to revision + resolution (cf glide)
  555. first understand what it stands for :)
  556. FIXME: there are some artefacts... check for the vclk_in_delay
  557. lets try with 6ns delay in both vclk_out & in...
  558. doh... they're still there :\
  559. */
  560. ntiles = par->tiles_in_X;
  561. if (IS_VOODOO2(par)) {
  562. fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
  563. | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
  564. /* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
  565. and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
  566. write our value. BTW due to the dac unable to read odd number of tiles, this
  567. field is always null ... */
  568. fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
  569. }
  570. else
  571. fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
  572. switch (info->var.bits_per_pixel) {
  573. case 16:
  574. fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL;
  575. break;
  576. #ifdef EN_24_32_BPP
  577. case 24:
  578. case 32:
  579. /* sst_set_bits(FBIINIT1, SEL_SOURCE_VCLK_2X_DIV2 | EN_24BPP);*/
  580. fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL | EN_24BPP;
  581. break;
  582. #endif
  583. default:
  584. return -EINVAL;
  585. }
  586. sst_write(FBIINIT1, fbiinit1);
  587. if (IS_VOODOO2(par)) {
  588. sst_write(FBIINIT6, fbiinit6);
  589. fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
  590. if (info->var.vmode & FB_VMODE_INTERLACED)
  591. fbiinit5 |= INTERLACE;
  592. if (info->var.vmode & FB_VMODE_DOUBLE)
  593. fbiinit5 |= VDOUBLESCAN;
  594. if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
  595. fbiinit5 |= HSYNC_HIGH;
  596. if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
  597. fbiinit5 |= VSYNC_HIGH;
  598. sst_write(FBIINIT5, fbiinit5);
  599. }
  600. sst_wait_idle();
  601. sst_unset_bits(FBIINIT1, VIDEO_RESET);
  602. sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
  603. sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
  604. /* disables fbiinit writes */
  605. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
  606. /* set lfbmode : set mode + front buffer for reads/writes
  607. + disable pipeline */
  608. switch (info->var.bits_per_pixel) {
  609. case 16:
  610. lfbmode = LFB_565;
  611. break;
  612. #ifdef EN_24_32_BPP
  613. case 24:
  614. lfbmode = LFB_888;
  615. break;
  616. case 32:
  617. lfbmode = LFB_8888;
  618. break;
  619. #endif
  620. default:
  621. return -EINVAL;
  622. }
  623. #if defined(__BIG_ENDIAN)
  624. /* Enable byte-swizzle functionality in hardware.
  625. * With this enabled, all our read- and write-accesses to
  626. * the voodoo framebuffer can be done in native format, and
  627. * the hardware will automatically convert it to little-endian.
  628. * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */
  629. lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
  630. LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
  631. #endif
  632. if (clipping) {
  633. sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
  634. /*
  635. * Set "clipping" dimensions. If clipping is disabled and
  636. * writes to offscreen areas of the framebuffer are performed,
  637. * the "behaviour is undefined" (_very_ undefined) - Urs
  638. */
  639. /* btw, it requires enabling pixel pipeline in LFBMODE .
  640. off screen read/writes will just wrap and read/print pixels
  641. on screen. Ugly but not that dangerous */
  642. f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
  643. info->var.xres - 1, par->yDim - 1);
  644. sst_write(CLIP_LEFT_RIGHT, info->var.xres);
  645. sst_write(CLIP_LOWY_HIGHY, par->yDim);
  646. sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
  647. } else {
  648. /* no clipping : direct access, no pipeline */
  649. sst_write(LFBMODE, lfbmode);
  650. }
  651. return 0;
  652. }
  653. /**
  654. * sstfb_setcolreg - Optional function. Sets a color register.
  655. * @regno: hardware colormap register
  656. * @red: frame buffer colormap structure
  657. * @green: The green value which can be up to 16 bits wide
  658. * @blue: The blue value which can be up to 16 bits wide.
  659. * @transp: If supported the alpha value which can be up to 16 bits wide.
  660. * @info: frame buffer info structure
  661. */
  662. static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  663. u_int transp, struct fb_info *info)
  664. {
  665. u32 col;
  666. f_dddprintk("sstfb_setcolreg\n");
  667. f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
  668. regno, red, green, blue, transp);
  669. if (regno >= 16)
  670. return -EINVAL;
  671. red >>= (16 - info->var.red.length);
  672. green >>= (16 - info->var.green.length);
  673. blue >>= (16 - info->var.blue.length);
  674. transp >>= (16 - info->var.transp.length);
  675. col = (red << info->var.red.offset)
  676. | (green << info->var.green.offset)
  677. | (blue << info->var.blue.offset)
  678. | (transp << info->var.transp.offset);
  679. ((u32 *)info->pseudo_palette)[regno] = col;
  680. return 0;
  681. }
  682. static int sstfb_ioctl(struct inode *inode, struct file *file,
  683. u_int cmd, u_long arg, struct fb_info *info )
  684. {
  685. struct sstfb_par *par = (struct sstfb_par *) info->par;
  686. struct pci_dev *sst_dev = par->dev;
  687. u32 fbiinit0, tmp, val;
  688. u_long p;
  689. switch (cmd) {
  690. /* dump current FBIINIT values to system log */
  691. case _IO('F', 0xdb): /* 0x46db */
  692. return sstfb_dump_regs(info);
  693. /* fills lfb with #arg pixels */
  694. case _IOW('F', 0xdc, u32): /* 0x46dc */
  695. if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
  696. return -EFAULT;
  697. if (val > info->fix.smem_len)
  698. val = info->fix.smem_len;
  699. printk("filling %#x \n", val);
  700. for (p=0 ; p<val; p+=2)
  701. writew(p >> 6, info->screen_base + p);
  702. return 0;
  703. /* change VGA pass_through mode */
  704. case _IOW('F', 0xdd, u32): /* 0x46dd */
  705. if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
  706. return -EFAULT;
  707. pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
  708. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
  709. tmp | PCI_EN_INIT_WR );
  710. fbiinit0 = sst_read (FBIINIT0);
  711. if (val) {
  712. sst_write(FBIINIT0, fbiinit0 & ~EN_VGA_PASSTHROUGH);
  713. iprintk("Disabling VGA pass-through\n");
  714. } else {
  715. sst_write(FBIINIT0, fbiinit0 | EN_VGA_PASSTHROUGH);
  716. iprintk("Enabling VGA pass-through\n");
  717. }
  718. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
  719. return 0;
  720. /* draw test image */
  721. case _IO('F', 0xde): /* 0x46de */
  722. f_dprintk("test color display at %d bpp\n",
  723. info->var.bits_per_pixel);
  724. sstfb_drawdebugimage(info);
  725. return 0;
  726. }
  727. return -EINVAL;
  728. }
  729. /*
  730. * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
  731. */
  732. #if 0
  733. static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  734. {
  735. struct sstfb_par *par = (struct sstfb_par *) info->par;
  736. u32 stride = info->fix.line_length;
  737. if (!IS_VOODOO2(par))
  738. return;
  739. sst_write(BLTSRCBASEADDR, 0);
  740. sst_write(BLTDSTBASEADDR, 0);
  741. sst_write(BLTROP, BLTROP_COPY);
  742. sst_write(BLTXYSTRIDES, stride | (stride << 16));
  743. sst_write(BLTSRCXY, area->sx | (area->sy << 16));
  744. sst_write(BLTDSTXY, area->dx | (area->dy << 16));
  745. sst_write(BLTSIZE, area->width | (area->height << 16));
  746. sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
  747. (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
  748. sst_wait_idle();
  749. }
  750. #endif
  751. /*
  752. * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
  753. */
  754. static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  755. {
  756. struct sstfb_par *par = (struct sstfb_par *) info->par;
  757. u32 stride = info->fix.line_length;
  758. if (!IS_VOODOO2(par))
  759. return;
  760. sst_write(BLTCLIPX, info->var.xres);
  761. sst_write(BLTCLIPY, info->var.yres);
  762. sst_write(BLTDSTBASEADDR, 0);
  763. sst_write(BLTCOLOR, rect->color);
  764. sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
  765. sst_write(BLTXYSTRIDES, stride | (stride << 16));
  766. sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
  767. sst_write(BLTSIZE, rect->width | (rect->height << 16));
  768. sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
  769. | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
  770. sst_wait_idle();
  771. }
  772. /*
  773. * get lfb size
  774. */
  775. static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize)
  776. {
  777. u8 __iomem *fbbase_virt = info->screen_base;
  778. /* force memsize */
  779. if ((mem >= 1 ) && (mem <= 4)) {
  780. *memsize = (mem * 0x100000);
  781. iprintk("supplied memsize: %#x\n", *memsize);
  782. return 1;
  783. }
  784. writel(0xdeadbeef, fbbase_virt);
  785. writel(0xdeadbeef, fbbase_virt+0x100000);
  786. writel(0xdeadbeef, fbbase_virt+0x200000);
  787. f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
  788. readl(fbbase_virt), readl(fbbase_virt + 0x100000),
  789. readl(fbbase_virt + 0x200000));
  790. writel(0xabcdef01, fbbase_virt);
  791. f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
  792. readl(fbbase_virt), readl(fbbase_virt + 0x100000),
  793. readl(fbbase_virt + 0x200000));
  794. /* checks for 4mb lfb, then 2, then defaults to 1 */
  795. if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
  796. *memsize = 0x400000;
  797. else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
  798. *memsize = 0x200000;
  799. else
  800. *memsize = 0x100000;
  801. f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
  802. return 1;
  803. }
  804. /*
  805. * DAC detection routines
  806. */
  807. /* fbi should be idle, and fifo emty and mem disabled */
  808. /* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
  809. static int __devinit sst_detect_att(struct fb_info *info)
  810. {
  811. struct sstfb_par *par = (struct sstfb_par *) info->par;
  812. int i, mir, dir;
  813. for (i=0; i<3; i++) {
  814. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  815. sst_dac_read(DACREG_RMR); /* read 4 times RMR */
  816. sst_dac_read(DACREG_RMR);
  817. sst_dac_read(DACREG_RMR);
  818. sst_dac_read(DACREG_RMR);
  819. /* the fifth time, CR0 is read */
  820. sst_dac_read(DACREG_RMR);
  821. /* the 6th, manufacturer id register */
  822. mir = sst_dac_read(DACREG_RMR);
  823. /*the 7th, device ID register */
  824. dir = sst_dac_read(DACREG_RMR);
  825. f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
  826. if ((mir == DACREG_MIR_ATT ) && (dir == DACREG_DIR_ATT)) {
  827. return 1;
  828. }
  829. }
  830. return 0;
  831. }
  832. static int __devinit sst_detect_ti(struct fb_info *info)
  833. {
  834. struct sstfb_par *par = (struct sstfb_par *) info->par;
  835. int i, mir, dir;
  836. for (i = 0; i<3; i++) {
  837. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  838. sst_dac_read(DACREG_RMR); /* read 4 times RMR */
  839. sst_dac_read(DACREG_RMR);
  840. sst_dac_read(DACREG_RMR);
  841. sst_dac_read(DACREG_RMR);
  842. /* the fifth time, CR0 is read */
  843. sst_dac_read(DACREG_RMR);
  844. /* the 6th, manufacturer id register */
  845. mir = sst_dac_read(DACREG_RMR);
  846. /*the 7th, device ID register */
  847. dir = sst_dac_read(DACREG_RMR);
  848. f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
  849. if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
  850. return 1;
  851. }
  852. }
  853. return 0;
  854. }
  855. /*
  856. * try to detect ICS5342 ramdac
  857. * we get the 1st byte (M value) of preset f1,f7 and fB
  858. * why those 3 ? mmmh... for now, i'll do it the glide way...
  859. * and ask questions later. anyway, it seems that all the freq registers are
  860. * realy at their default state (cf specs) so i ask again, why those 3 regs ?
  861. * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
  862. * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
  863. * touched...
  864. * is it realy safe ? how can i reset this ramdac ? geee...
  865. */
  866. static int __devinit sst_detect_ics(struct fb_info *info)
  867. {
  868. struct sstfb_par *par = (struct sstfb_par *) info->par;
  869. int m_clk0_1, m_clk0_7, m_clk1_b;
  870. int n_clk0_1, n_clk0_7, n_clk1_b;
  871. int i;
  872. for (i = 0; i<5; i++ ) {
  873. sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
  874. m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
  875. n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
  876. sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
  877. m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
  878. n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
  879. sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
  880. m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
  881. n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
  882. f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
  883. m_clk0_1, m_clk0_7, m_clk1_b);
  884. f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
  885. n_clk0_1, n_clk0_7, n_clk1_b);
  886. if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
  887. && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
  888. && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
  889. return 1;
  890. }
  891. }
  892. return 0;
  893. }
  894. /*
  895. * gfx, video, pci fifo should be reset, dram refresh disabled
  896. * see detect_dac
  897. */
  898. static int sst_set_pll_att_ti(struct fb_info *info,
  899. const struct pll_timing *t, const int clock)
  900. {
  901. struct sstfb_par *par = (struct sstfb_par *) info->par;
  902. u8 cr0, cc;
  903. /* enable indexed mode */
  904. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  905. sst_dac_read(DACREG_RMR); /* 1 time: RMR */
  906. sst_dac_read(DACREG_RMR); /* 2 RMR */
  907. sst_dac_read(DACREG_RMR); /* 3 // */
  908. sst_dac_read(DACREG_RMR); /* 4 // */
  909. cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
  910. sst_dac_write(DACREG_WMA, 0);
  911. sst_dac_read(DACREG_RMR);
  912. sst_dac_read(DACREG_RMR);
  913. sst_dac_read(DACREG_RMR);
  914. sst_dac_read(DACREG_RMR);
  915. sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
  916. | DACREG_CR0_EN_INDEXED
  917. | DACREG_CR0_8BIT
  918. | DACREG_CR0_PWDOWN );
  919. /* so, now we are in indexed mode . dunno if its common, but
  920. i find this way of doing things a little bit weird :p */
  921. udelay(300);
  922. cc = dac_i_read(DACREG_CC_I);
  923. switch (clock) {
  924. case VID_CLOCK:
  925. dac_i_write(DACREG_AC0_I, t->m);
  926. dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
  927. dac_i_write(DACREG_CC_I,
  928. (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
  929. break;
  930. case GFX_CLOCK:
  931. dac_i_write(DACREG_BD0_I, t->m);
  932. dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
  933. dac_i_write(DACREG_CC_I,
  934. (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
  935. break;
  936. default:
  937. dprintk("%s: wrong clock code '%d'\n",
  938. __FUNCTION__, clock);
  939. return 0;
  940. }
  941. udelay(300);
  942. /* power up the dac & return to "normal" non-indexed mode */
  943. dac_i_write(DACREG_CR0_I,
  944. cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
  945. return 1;
  946. }
  947. static int sst_set_pll_ics(struct fb_info *info,
  948. const struct pll_timing *t, const int clock)
  949. {
  950. struct sstfb_par *par = (struct sstfb_par *) info->par;
  951. u8 pll_ctrl;
  952. sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
  953. pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
  954. switch(clock) {
  955. case VID_CLOCK:
  956. sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
  957. sst_dac_write(DACREG_ICS_PLLDATA, t->m);
  958. sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
  959. /* selects freq f0 for clock 0 */
  960. sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
  961. sst_dac_write(DACREG_ICS_PLLDATA,
  962. (pll_ctrl & 0xd8)
  963. | DACREG_ICS_CLK0
  964. | DACREG_ICS_CLK0_0);
  965. break;
  966. case GFX_CLOCK :
  967. sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
  968. sst_dac_write(DACREG_ICS_PLLDATA, t->m);
  969. sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
  970. /* selects freq fA for clock 1 */
  971. sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
  972. sst_dac_write(DACREG_ICS_PLLDATA,
  973. (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
  974. break;
  975. default:
  976. dprintk("%s: wrong clock code '%d'\n",
  977. __FUNCTION__, clock);
  978. return 0;
  979. }
  980. udelay(300);
  981. return 1;
  982. }
  983. static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
  984. {
  985. struct sstfb_par *par = (struct sstfb_par *) info->par;
  986. u8 cr0;
  987. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  988. sst_dac_read(DACREG_RMR); /* read 4 times RMR */
  989. sst_dac_read(DACREG_RMR);
  990. sst_dac_read(DACREG_RMR);
  991. sst_dac_read(DACREG_RMR);
  992. /* the fifth time, CR0 is read */
  993. cr0 = sst_dac_read(DACREG_RMR);
  994. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  995. sst_dac_read(DACREG_RMR); /* read 4 times RMR */
  996. sst_dac_read(DACREG_RMR);
  997. sst_dac_read(DACREG_RMR);
  998. sst_dac_read(DACREG_RMR);
  999. /* cr0 */
  1000. switch(bpp) {
  1001. case 16:
  1002. sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
  1003. break;
  1004. #ifdef EN_24_32_BPP
  1005. case 24:
  1006. case 32:
  1007. sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_24BPP);
  1008. break;
  1009. #endif
  1010. default:
  1011. dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
  1012. break;
  1013. }
  1014. }
  1015. static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
  1016. {
  1017. struct sstfb_par *par = (struct sstfb_par *) info->par;
  1018. switch(bpp) {
  1019. case 16:
  1020. sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
  1021. break;
  1022. #ifdef EN_24_32_BPP
  1023. case 24:
  1024. case 32:
  1025. sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_24BPP);
  1026. break;
  1027. #endif
  1028. default:
  1029. dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
  1030. break;
  1031. }
  1032. }
  1033. /*
  1034. * detect dac type
  1035. * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
  1036. * dram refresh disabled, FbiInit remaped.
  1037. * TODO: mmh.. maybe i shoud put the "prerequisite" in the func ...
  1038. */
  1039. static struct dac_switch dacs[] __devinitdata = {
  1040. { .name = "TI TVP3409",
  1041. .detect = sst_detect_ti,
  1042. .set_pll = sst_set_pll_att_ti,
  1043. .set_vidmod = sst_set_vidmod_att_ti },
  1044. { .name = "AT&T ATT20C409",
  1045. .detect = sst_detect_att,
  1046. .set_pll = sst_set_pll_att_ti,
  1047. .set_vidmod = sst_set_vidmod_att_ti },
  1048. { .name = "ICS ICS5342",
  1049. .detect = sst_detect_ics,
  1050. .set_pll = sst_set_pll_ics,
  1051. .set_vidmod = sst_set_vidmod_ics },
  1052. };
  1053. static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
  1054. {
  1055. int i, ret = 0;
  1056. for (i=0; i<sizeof(dacs)/sizeof(dacs[0]); i++) {
  1057. ret = dacs[i].detect(info);
  1058. if (ret) break;
  1059. }
  1060. if (!ret)
  1061. return 0;
  1062. f_dprintk("%s found %s\n", __FUNCTION__, dacs[i].name);
  1063. par->dac_sw = dacs[i];
  1064. return 1;
  1065. }
  1066. /*
  1067. * Internal Routines
  1068. */
  1069. static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par)
  1070. {
  1071. u32 fbiinit0, fbiinit1, fbiinit4;
  1072. struct pci_dev *dev = par->dev;
  1073. struct pll_timing gfx_timings;
  1074. struct sst_spec *spec;
  1075. int Fout;
  1076. spec = &voodoo_spec[par->type];
  1077. f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 "
  1078. " fbiinit6\n");
  1079. f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
  1080. sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
  1081. sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
  1082. /* disable video clock */
  1083. pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
  1084. /* enable writing to init registers, disable pci fifo */
  1085. pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
  1086. /* reset video */
  1087. sst_set_bits(FBIINIT1, VIDEO_RESET);
  1088. sst_wait_idle();
  1089. /* reset gfx + pci fifo */
  1090. sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
  1091. sst_wait_idle();
  1092. /* unreset fifo */
  1093. /*sst_unset_bits(FBIINIT0, FIFO_RESET);
  1094. sst_wait_idle();*/
  1095. /* unreset FBI */
  1096. /*sst_unset_bits(FBIINIT0, FBI_RESET);
  1097. sst_wait_idle();*/
  1098. /* disable dram refresh */
  1099. sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
  1100. sst_wait_idle();
  1101. /* remap fbinit2/3 to dac */
  1102. pci_write_config_dword(dev, PCI_INIT_ENABLE,
  1103. PCI_EN_INIT_WR | PCI_REMAP_DAC );
  1104. /* detect dac type */
  1105. if (!sst_detect_dactype(info, par)) {
  1106. eprintk("Unknown dac type\n");
  1107. //FIXME watch it: we are not in a safe state, bad bad bad.
  1108. return 0;
  1109. }
  1110. /* set graphic clock */
  1111. par->gfx_clock = spec->default_gfx_clock;
  1112. if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
  1113. iprintk("Using supplied graphic freq : %dMHz\n", gfxclk);
  1114. par->gfx_clock = gfxclk *1000;
  1115. } else if (gfxclk) {
  1116. wprintk ("%dMhz is way out of spec! Using default\n", gfxclk);
  1117. }
  1118. sst_calc_pll(par->gfx_clock, &Fout, &gfx_timings);
  1119. par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
  1120. /* disable fbiinit remap */
  1121. pci_write_config_dword(dev, PCI_INIT_ENABLE,
  1122. PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
  1123. /* defaults init registers */
  1124. /* FbiInit0: unreset gfx, unreset fifo */
  1125. fbiinit0 = FBIINIT0_DEFAULT;
  1126. fbiinit1 = FBIINIT1_DEFAULT;
  1127. fbiinit4 = FBIINIT4_DEFAULT;
  1128. if (vgapass)
  1129. fbiinit0 &= ~EN_VGA_PASSTHROUGH;
  1130. else
  1131. fbiinit0 |= EN_VGA_PASSTHROUGH;
  1132. if (slowpci) {
  1133. fbiinit1 |= SLOW_PCI_WRITES;
  1134. fbiinit4 |= SLOW_PCI_READS;
  1135. } else {
  1136. fbiinit1 &= ~SLOW_PCI_WRITES;
  1137. fbiinit4 &= ~SLOW_PCI_READS;
  1138. }
  1139. sst_write(FBIINIT0, fbiinit0);
  1140. sst_wait_idle();
  1141. sst_write(FBIINIT1, fbiinit1);
  1142. sst_wait_idle();
  1143. sst_write(FBIINIT2, FBIINIT2_DEFAULT);
  1144. sst_wait_idle();
  1145. sst_write(FBIINIT3, FBIINIT3_DEFAULT);
  1146. sst_wait_idle();
  1147. sst_write(FBIINIT4, fbiinit4);
  1148. sst_wait_idle();
  1149. if (IS_VOODOO2(par)) {
  1150. sst_write(FBIINIT6, FBIINIT6_DEFAULT);
  1151. sst_wait_idle();
  1152. }
  1153. pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
  1154. pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
  1155. return 1;
  1156. }
  1157. static void __devexit sst_shutdown(struct fb_info *info)
  1158. {
  1159. struct sstfb_par *par = (struct sstfb_par *) info->par;
  1160. struct pci_dev *dev = par->dev;
  1161. struct pll_timing gfx_timings;
  1162. int Fout;
  1163. /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
  1164. pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
  1165. sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
  1166. sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
  1167. sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
  1168. sst_wait_idle();
  1169. pci_write_config_dword(dev, PCI_INIT_ENABLE,
  1170. PCI_EN_INIT_WR | PCI_REMAP_DAC);
  1171. /* set 20Mhz gfx clock */
  1172. sst_calc_pll(20000, &Fout, &gfx_timings);
  1173. par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
  1174. /* TODO maybe shutdown the dac, vrefresh and so on... */
  1175. pci_write_config_dword(dev, PCI_INIT_ENABLE,
  1176. PCI_EN_INIT_WR);
  1177. sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | EN_VGA_PASSTHROUGH);
  1178. pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
  1179. /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
  1180. * from start ? */
  1181. pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
  1182. }
  1183. /*
  1184. * Interface to the world
  1185. */
  1186. #ifndef MODULE
  1187. static int __init sstfb_setup(char *options)
  1188. {
  1189. char *this_opt;
  1190. if (!options || !*options)
  1191. return 0;
  1192. while ((this_opt = strsep(&options, ",")) != NULL) {
  1193. if (!*this_opt) continue;
  1194. f_ddprintk("option %s\n", this_opt);
  1195. if (!strcmp(this_opt, "vganopass"))
  1196. vgapass = 0;
  1197. else if (!strcmp(this_opt, "vgapass"))
  1198. vgapass = 1;
  1199. else if (!strcmp(this_opt, "clipping"))
  1200. clipping = 1;
  1201. else if (!strcmp(this_opt, "noclipping"))
  1202. clipping = 0;
  1203. else if (!strcmp(this_opt, "fastpci"))
  1204. slowpci = 0;
  1205. else if (!strcmp(this_opt, "slowpci"))
  1206. slowpci = 1;
  1207. else if (!strncmp(this_opt, "mem:",4))
  1208. mem = simple_strtoul (this_opt+4, NULL, 0);
  1209. else if (!strncmp(this_opt, "gfxclk:",7))
  1210. gfxclk = simple_strtoul (this_opt+7, NULL, 0);
  1211. else
  1212. mode_option = this_opt;
  1213. }
  1214. return 0;
  1215. }
  1216. #endif
  1217. static struct fb_ops sstfb_ops = {
  1218. .owner = THIS_MODULE,
  1219. .fb_check_var = sstfb_check_var,
  1220. .fb_set_par = sstfb_set_par,
  1221. .fb_setcolreg = sstfb_setcolreg,
  1222. .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */
  1223. .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */
  1224. .fb_imageblit = cfb_imageblit,
  1225. .fb_cursor = soft_cursor,
  1226. .fb_ioctl = sstfb_ioctl,
  1227. };
  1228. static int __devinit sstfb_probe(struct pci_dev *pdev,
  1229. const struct pci_device_id *id)
  1230. {
  1231. struct fb_info *info;
  1232. struct fb_fix_screeninfo *fix;
  1233. struct sstfb_par *par;
  1234. struct sst_spec *spec;
  1235. int err;
  1236. struct all_info {
  1237. struct fb_info info;
  1238. struct sstfb_par par;
  1239. u32 pseudo_palette[16];
  1240. } *all;
  1241. /* Enable device in PCI config. */
  1242. if ((err=pci_enable_device(pdev))) {
  1243. eprintk("cannot enable device\n");
  1244. return err;
  1245. }
  1246. /* Allocate the fb and par structures. */
  1247. all = kmalloc(sizeof(*all), GFP_KERNEL);
  1248. if (!all)
  1249. return -ENOMEM;
  1250. memset(all, 0, sizeof(*all));
  1251. pci_set_drvdata(pdev, all);
  1252. info = &all->info;
  1253. par = info->par = &all->par;
  1254. fix = &info->fix;
  1255. par->type = id->driver_data;
  1256. spec = &voodoo_spec[par->type];
  1257. f_ddprintk("found device : %s\n", spec->name);
  1258. par->dev = pdev;
  1259. pci_read_config_byte(pdev, PCI_REVISION_ID, &par->revision);
  1260. fix->mmio_start = pci_resource_start(pdev,0);
  1261. fix->mmio_len = 0x400000;
  1262. fix->smem_start = fix->mmio_start + 0x400000;
  1263. if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
  1264. eprintk("cannot reserve mmio memory\n");
  1265. goto fail_mmio_mem;
  1266. }
  1267. if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
  1268. eprintk("cannot reserve fb memory\n");
  1269. goto fail_fb_mem;
  1270. }
  1271. par->mmio_vbase = ioremap_nocache(fix->mmio_start,
  1272. fix->mmio_len);
  1273. if (!par->mmio_vbase) {
  1274. eprintk("cannot remap register area %#lx\n",
  1275. fix->mmio_start);
  1276. goto fail_mmio_remap;
  1277. }
  1278. info->screen_base = ioremap_nocache(fix->smem_start, 0x400000);
  1279. if (!info->screen_base) {
  1280. eprintk("cannot remap framebuffer %#lx\n",
  1281. fix->smem_start);
  1282. goto fail_fb_remap;
  1283. }
  1284. if (!sst_init(info, par)) {
  1285. eprintk("Init failed\n");
  1286. goto fail;
  1287. }
  1288. sst_get_memsize(info, &fix->smem_len);
  1289. strlcpy(fix->id, spec->name, sizeof(fix->id));
  1290. iprintk("%s (revision %d) with %s dac\n",
  1291. fix->id, par->revision, par->dac_sw.name);
  1292. iprintk("framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
  1293. fix->smem_start, info->screen_base,
  1294. fix->smem_len >> 20);
  1295. f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase);
  1296. f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
  1297. f_ddprintk("fbbase_virt: %p\n", info->screen_base);
  1298. info->flags = FBINFO_DEFAULT;
  1299. info->fbops = &sstfb_ops;
  1300. info->pseudo_palette = &all->pseudo_palette;
  1301. fix->type = FB_TYPE_PACKED_PIXELS;
  1302. fix->visual = FB_VISUAL_TRUECOLOR;
  1303. fix->accel = FB_ACCEL_NONE; /* FIXME */
  1304. /*
  1305. * According to the specs, the linelength must be of 1024 *pixels*
  1306. * and the 24bpp mode is in fact a 32 bpp mode.
  1307. */
  1308. fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
  1309. if ( mode_option &&
  1310. fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16)) {
  1311. eprintk("can't set supplied video mode. Using default\n");
  1312. info->var = sstfb_default;
  1313. } else
  1314. info->var = sstfb_default;
  1315. if (sstfb_check_var(&info->var, info)) {
  1316. eprintk("invalid default video mode.\n");
  1317. goto fail;
  1318. }
  1319. if (sstfb_set_par(info)) {
  1320. eprintk("can't set default video mode.\n");
  1321. goto fail;
  1322. }
  1323. fb_alloc_cmap(&info->cmap, 256, 0);
  1324. /* register fb */
  1325. info->device = &pdev->dev;
  1326. if (register_framebuffer(info) < 0) {
  1327. eprintk("can't register framebuffer.\n");
  1328. goto fail;
  1329. }
  1330. if (1) /* set to 0 to see an initial bitmap instead */
  1331. sstfb_clear_screen(info);
  1332. else
  1333. sstfb_drawdebugimage(info);
  1334. printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n",
  1335. info->node, fix->id, info->screen_base);
  1336. return 0;
  1337. fail:
  1338. iounmap(info->screen_base);
  1339. fail_fb_remap:
  1340. iounmap(par->mmio_vbase);
  1341. fail_mmio_remap:
  1342. release_mem_region(fix->smem_start, 0x400000);
  1343. fail_fb_mem:
  1344. release_mem_region(fix->mmio_start, info->fix.mmio_len);
  1345. fail_mmio_mem:
  1346. kfree(info);
  1347. return -ENXIO; /* no voodoo detected */
  1348. }
  1349. static void __devexit sstfb_remove(struct pci_dev *pdev)
  1350. {
  1351. struct sstfb_par *par;
  1352. struct fb_info *info;
  1353. info = pci_get_drvdata(pdev);
  1354. par = (struct sstfb_par *) info->par;
  1355. sst_shutdown(info);
  1356. unregister_framebuffer(info);
  1357. iounmap(info->screen_base);
  1358. iounmap(par->mmio_vbase);
  1359. release_mem_region(info->fix.smem_start, 0x400000);
  1360. release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
  1361. kfree(info);
  1362. }
  1363. static struct pci_device_id sstfb_id_tbl[] = {
  1364. { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO,
  1365. PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO1 },
  1366. { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2,
  1367. PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO2 },
  1368. { 0 },
  1369. };
  1370. static struct pci_driver sstfb_driver = {
  1371. .name = "sstfb",
  1372. .id_table = sstfb_id_tbl,
  1373. .probe = sstfb_probe,
  1374. .remove = __devexit_p(sstfb_remove),
  1375. };
  1376. static int __devinit sstfb_init(void)
  1377. {
  1378. #ifndef MODULE
  1379. char *option = NULL;
  1380. if (fb_get_options("sstfb", &option))
  1381. return -ENODEV;
  1382. sstfb_setup(option);
  1383. #endif
  1384. return pci_register_driver(&sstfb_driver);
  1385. }
  1386. #ifdef MODULE
  1387. static void __devexit sstfb_exit(void)
  1388. {
  1389. pci_unregister_driver(&sstfb_driver);
  1390. }
  1391. #endif
  1392. /*
  1393. * testing and debugging functions
  1394. */
  1395. static int sstfb_dump_regs(struct fb_info *info)
  1396. {
  1397. #ifdef SST_DEBUG
  1398. static struct { u32 reg ; const char *reg_name;} pci_regs[] = {
  1399. { PCI_INIT_ENABLE, "initenable"},
  1400. { PCI_VCLK_ENABLE, "enable vclk"},
  1401. { PCI_VCLK_DISABLE, "disable vclk"},
  1402. };
  1403. static struct { u32 reg ; const char *reg_name;} sst_regs[] = {
  1404. {FBIINIT0,"fbiinit0"},
  1405. {FBIINIT1,"fbiinit1"},
  1406. {FBIINIT2,"fbiinit2"},
  1407. {FBIINIT3,"fbiinit3"},
  1408. {FBIINIT4,"fbiinit4"},
  1409. {FBIINIT5,"fbiinit5"},
  1410. {FBIINIT6,"fbiinit6"},
  1411. {FBIINIT7,"fbiinit7"},
  1412. {LFBMODE,"lfbmode"},
  1413. {FBZMODE,"fbzmode"},
  1414. };
  1415. const int pci_s = sizeof(pci_regs)/sizeof(pci_regs[0]);
  1416. const int sst_s = sizeof(sst_regs)/sizeof(sst_regs[0]);
  1417. struct sstfb_par *par = (struct sstfb_par *) info->par;
  1418. struct pci_dev *dev = par->dev;
  1419. u32 pci_res[pci_s];
  1420. u32 sst_res[sst_s];
  1421. int i;
  1422. for (i=0; i<pci_s; i++) {
  1423. pci_read_config_dword(dev, pci_regs[i].reg, &pci_res[i]);
  1424. }
  1425. for (i=0; i<sst_s; i++) {
  1426. sst_res[i] = sst_read(sst_regs[i].reg);
  1427. }
  1428. dprintk("hardware register dump:\n");
  1429. for (i=0; i<pci_s; i++) {
  1430. dprintk("%s %0#10x\n", pci_regs[i].reg_name, pci_res[i]);
  1431. }
  1432. for (i=0; i<sst_s; i++) {
  1433. dprintk("%s %0#10x\n", sst_regs[i].reg_name, sst_res[i]);
  1434. }
  1435. return 0;
  1436. #else
  1437. return -EINVAL;
  1438. #endif
  1439. }
  1440. static void sstfb_fillrect_softw( struct fb_info *info, const struct fb_fillrect *rect)
  1441. {
  1442. u8 __iomem *fbbase_virt = info->screen_base;
  1443. int x, y, w = info->var.bits_per_pixel == 16 ? 2 : 4;
  1444. u32 color = rect->color, height = rect->height;
  1445. u8 __iomem *p;
  1446. if (w==2) color |= color<<16;
  1447. for (y=rect->dy; height; y++, height--) {
  1448. p = fbbase_virt + y*info->fix.line_length + rect->dx*w;
  1449. x = rect->width;
  1450. if (w==2) x>>=1;
  1451. while (x) {
  1452. writel(color, p);
  1453. p += 4;
  1454. x--;
  1455. }
  1456. }
  1457. }
  1458. static void sstfb_drawrect_XY( struct fb_info *info, int x, int y,
  1459. int w, int h, int color, int hwfunc)
  1460. {
  1461. struct fb_fillrect rect;
  1462. rect.dx = x;
  1463. rect.dy = y;
  1464. rect.height = h;
  1465. rect.width = w;
  1466. rect.color = color;
  1467. rect.rop = ROP_COPY;
  1468. if (hwfunc)
  1469. sstfb_fillrect(info, &rect);
  1470. else
  1471. sstfb_fillrect_softw(info, &rect);
  1472. }
  1473. /* print some squares on the fb */
  1474. static void sstfb_drawdebugimage(struct fb_info *info)
  1475. {
  1476. static int idx;
  1477. /* clear screen */
  1478. sstfb_clear_screen(info);
  1479. idx = (idx+1) & 1;
  1480. /* white rect */
  1481. sstfb_drawrect_XY(info, 0, 0, 50, 50, 0xffff, idx);
  1482. /* blue rect */
  1483. sstfb_drawrect_XY(info, 50, 50, 50, 50, 0x001f, idx);
  1484. /* green rect */
  1485. sstfb_drawrect_XY(info, 100, 100, 80, 80, 0x07e0, idx);
  1486. /* red rect */
  1487. sstfb_drawrect_XY(info, 250, 250, 120, 100, 0xf800, idx);
  1488. }
  1489. module_init(sstfb_init);
  1490. #ifdef MODULE
  1491. module_exit(sstfb_exit);
  1492. #endif
  1493. MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>");
  1494. MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
  1495. MODULE_LICENSE("GPL");
  1496. module_param(mem, int, 0);
  1497. MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
  1498. module_param(vgapass, bool, 0);
  1499. MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
  1500. module_param(clipping, bool, 0);
  1501. MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
  1502. module_param(gfxclk, int, 0);
  1503. MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
  1504. module_param(slowpci, bool, 0);
  1505. MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");