matroxfb_Ti3026.c 26 KB

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  1. /*
  2. *
  3. * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
  4. *
  5. * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
  6. *
  7. * Portions Copyright (c) 2001 Matrox Graphics Inc.
  8. *
  9. * Version: 1.65 2002/08/14
  10. *
  11. * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
  12. *
  13. * Contributors: "menion?" <menion@mindless.com>
  14. * Betatesting, fixes, ideas
  15. *
  16. * "Kurt Garloff" <garloff@suse.de>
  17. * Betatesting, fixes, ideas, videomodes, videomodes timmings
  18. *
  19. * "Tom Rini" <trini@kernel.crashing.org>
  20. * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
  21. *
  22. * "Bibek Sahu" <scorpio@dodds.net>
  23. * Access device through readb|w|l and write b|w|l
  24. * Extensive debugging stuff
  25. *
  26. * "Daniel Haun" <haund@usa.net>
  27. * Testing, hardware cursor fixes
  28. *
  29. * "Scott Wood" <sawst46+@pitt.edu>
  30. * Fixes
  31. *
  32. * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
  33. * Betatesting
  34. *
  35. * "Kelly French" <targon@hazmat.com>
  36. * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
  37. * Betatesting, bug reporting
  38. *
  39. * "Pablo Bianucci" <pbian@pccp.com.ar>
  40. * Fixes, ideas, betatesting
  41. *
  42. * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
  43. * Fixes, enhandcements, ideas, betatesting
  44. *
  45. * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
  46. * PPC betatesting, PPC support, backward compatibility
  47. *
  48. * "Paul Womar" <Paul@pwomar.demon.co.uk>
  49. * "Owen Waller" <O.Waller@ee.qub.ac.uk>
  50. * PPC betatesting
  51. *
  52. * "Thomas Pornin" <pornin@bolet.ens.fr>
  53. * Alpha betatesting
  54. *
  55. * "Pieter van Leuven" <pvl@iae.nl>
  56. * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
  57. * G100 testing
  58. *
  59. * "H. Peter Arvin" <hpa@transmeta.com>
  60. * Ideas
  61. *
  62. * "Cort Dougan" <cort@cs.nmt.edu>
  63. * CHRP fixes and PReP cleanup
  64. *
  65. * "Mark Vojkovich" <mvojkovi@ucsd.edu>
  66. * G400 support
  67. *
  68. * (following author is not in any relation with this code, but his code
  69. * is included in this driver)
  70. *
  71. * Based on framebuffer driver for VBE 2.0 compliant graphic boards
  72. * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
  73. *
  74. * (following author is not in any relation with this code, but his ideas
  75. * were used when writting this driver)
  76. *
  77. * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
  78. *
  79. */
  80. /* make checkconfig does not verify included files... */
  81. #include <linux/config.h>
  82. #include "matroxfb_Ti3026.h"
  83. #include "matroxfb_misc.h"
  84. #include "matroxfb_accel.h"
  85. #include <linux/matroxfb.h>
  86. #ifdef CONFIG_FB_MATROX_MILLENIUM
  87. #define outTi3026 matroxfb_DAC_out
  88. #define inTi3026 matroxfb_DAC_in
  89. #define TVP3026_INDEX 0x00
  90. #define TVP3026_PALWRADD 0x00
  91. #define TVP3026_PALDATA 0x01
  92. #define TVP3026_PIXRDMSK 0x02
  93. #define TVP3026_PALRDADD 0x03
  94. #define TVP3026_CURCOLWRADD 0x04
  95. #define TVP3026_CLOVERSCAN 0x00
  96. #define TVP3026_CLCOLOR0 0x01
  97. #define TVP3026_CLCOLOR1 0x02
  98. #define TVP3026_CLCOLOR2 0x03
  99. #define TVP3026_CURCOLDATA 0x05
  100. #define TVP3026_CURCOLRDADD 0x07
  101. #define TVP3026_CURCTRL 0x09
  102. #define TVP3026_X_DATAREG 0x0A
  103. #define TVP3026_CURRAMDATA 0x0B
  104. #define TVP3026_CURPOSXL 0x0C
  105. #define TVP3026_CURPOSXH 0x0D
  106. #define TVP3026_CURPOSYL 0x0E
  107. #define TVP3026_CURPOSYH 0x0F
  108. #define TVP3026_XSILICONREV 0x01
  109. #define TVP3026_XCURCTRL 0x06
  110. #define TVP3026_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */
  111. #define TVP3026_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
  112. #define TVP3026_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
  113. #define TVP3026_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
  114. #define TVP3026_XCURCTRL_BLANK2048 0x00
  115. #define TVP3026_XCURCTRL_BLANK4096 0x10
  116. #define TVP3026_XCURCTRL_INTERLACED 0x20
  117. #define TVP3026_XCURCTRL_ODD 0x00 /* ext.signal ODD/\EVEN */
  118. #define TVP3026_XCURCTRL_EVEN 0x40 /* ext.signal EVEN/\ODD */
  119. #define TVP3026_XCURCTRL_INDIRECT 0x00
  120. #define TVP3026_XCURCTRL_DIRECT 0x80
  121. #define TVP3026_XLATCHCTRL 0x0F
  122. #define TVP3026_XLATCHCTRL_1_1 0x06
  123. #define TVP3026_XLATCHCTRL_2_1 0x07
  124. #define TVP3026_XLATCHCTRL_4_1 0x06
  125. #define TVP3026_XLATCHCTRL_8_1 0x06
  126. #define TVP3026_XLATCHCTRL_16_1 0x06
  127. #define TVP3026A_XLATCHCTRL_4_3 0x06 /* ??? do not understand... but it works... !!! */
  128. #define TVP3026A_XLATCHCTRL_8_3 0x07
  129. #define TVP3026B_XLATCHCTRL_4_3 0x08
  130. #define TVP3026B_XLATCHCTRL_8_3 0x06 /* ??? do not understand... but it works... !!! */
  131. #define TVP3026_XTRUECOLORCTRL 0x18
  132. #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL 0x00
  133. #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP 0x20
  134. #define TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR 0x80
  135. #define TVP3026_XTRUECOLORCTRL_TRUECOLOR 0x40 /* paletized */
  136. #define TVP3026_XTRUECOLORCTRL_DIRECTCOLOR 0x00
  137. #define TVP3026_XTRUECOLORCTRL_24_ALTERNATE 0x08 /* 5:4/5:2 instead of 4:3/8:3 */
  138. #define TVP3026_XTRUECOLORCTRL_RGB_888 0x16 /* 4:3/8:3 (or 5:4/5:2) */
  139. #define TVP3026_XTRUECOLORCTRL_BGR_888 0x17
  140. #define TVP3026_XTRUECOLORCTRL_ORGB_8888 0x06
  141. #define TVP3026_XTRUECOLORCTRL_BGRO_8888 0x07
  142. #define TVP3026_XTRUECOLORCTRL_RGB_565 0x05
  143. #define TVP3026_XTRUECOLORCTRL_ORGB_1555 0x04
  144. #define TVP3026_XTRUECOLORCTRL_RGB_664 0x03
  145. #define TVP3026_XTRUECOLORCTRL_RGBO_4444 0x01
  146. #define TVP3026_XMUXCTRL 0x19
  147. #define TVP3026_XMUXCTRL_MEMORY_8BIT 0x01 /* - */
  148. #define TVP3026_XMUXCTRL_MEMORY_16BIT 0x02 /* - */
  149. #define TVP3026_XMUXCTRL_MEMORY_32BIT 0x03 /* 2MB RAM, 512K * 4 */
  150. #define TVP3026_XMUXCTRL_MEMORY_64BIT 0x04 /* >2MB RAM, 512K * 8 & more */
  151. #define TVP3026_XMUXCTRL_PIXEL_4BIT 0x40 /* L0,H0,L1,H1... */
  152. #define TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED 0x60 /* H0,L0,H1,L1... */
  153. #define TVP3026_XMUXCTRL_PIXEL_8BIT 0x48
  154. #define TVP3026_XMUXCTRL_PIXEL_16BIT 0x50
  155. #define TVP3026_XMUXCTRL_PIXEL_32BIT 0x58
  156. #define TVP3026_XMUXCTRL_VGA 0x98 /* VGA MEMORY, 8BIT PIXEL */
  157. #define TVP3026_XCLKCTRL 0x1A
  158. #define TVP3026_XCLKCTRL_DIV1 0x00
  159. #define TVP3026_XCLKCTRL_DIV2 0x10
  160. #define TVP3026_XCLKCTRL_DIV4 0x20
  161. #define TVP3026_XCLKCTRL_DIV8 0x30
  162. #define TVP3026_XCLKCTRL_DIV16 0x40
  163. #define TVP3026_XCLKCTRL_DIV32 0x50
  164. #define TVP3026_XCLKCTRL_DIV64 0x60
  165. #define TVP3026_XCLKCTRL_CLKSTOPPED 0x70
  166. #define TVP3026_XCLKCTRL_SRC_CLK0 0x00
  167. #define TVP3026_XCLKCTRL_SRC_CLK1 0x01
  168. #define TVP3026_XCLKCTRL_SRC_CLK2 0x02 /* CLK2 is TTL source*/
  169. #define TVP3026_XCLKCTRL_SRC_NCLK2 0x03 /* not CLK2 is TTL source */
  170. #define TVP3026_XCLKCTRL_SRC_ECLK2 0x04 /* CLK2 and not CLK2 is ECL source */
  171. #define TVP3026_XCLKCTRL_SRC_PLL 0x05
  172. #define TVP3026_XCLKCTRL_SRC_DIS 0x06 /* disable & poweroff internal clock */
  173. #define TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
  174. #define TVP3026_XPALETTEPAGE 0x1C
  175. #define TVP3026_XGENCTRL 0x1D
  176. #define TVP3026_XGENCTRL_HSYNC_POS 0x00
  177. #define TVP3026_XGENCTRL_HSYNC_NEG 0x01
  178. #define TVP3026_XGENCTRL_VSYNC_POS 0x00
  179. #define TVP3026_XGENCTRL_VSYNC_NEG 0x02
  180. #define TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
  181. #define TVP3026_XGENCTRL_BIG_ENDIAN 0x08
  182. #define TVP3026_XGENCTRL_BLACK_0IRE 0x00
  183. #define TVP3026_XGENCTRL_BLACK_75IRE 0x10
  184. #define TVP3026_XGENCTRL_NO_SYNC_ON_GREEN 0x00
  185. #define TVP3026_XGENCTRL_SYNC_ON_GREEN 0x20
  186. #define TVP3026_XGENCTRL_OVERSCAN_DIS 0x00
  187. #define TVP3026_XGENCTRL_OVERSCAN_EN 0x40
  188. #define TVP3026_XMISCCTRL 0x1E
  189. #define TVP3026_XMISCCTRL_DAC_PUP 0x00
  190. #define TVP3026_XMISCCTRL_DAC_PDOWN 0x01
  191. #define TVP3026_XMISCCTRL_DAC_EXT 0x00 /* or 8, bit 3 is ignored */
  192. #define TVP3026_XMISCCTRL_DAC_6BIT 0x04
  193. #define TVP3026_XMISCCTRL_DAC_8BIT 0x0C
  194. #define TVP3026_XMISCCTRL_PSEL_DIS 0x00
  195. #define TVP3026_XMISCCTRL_PSEL_EN 0x10
  196. #define TVP3026_XMISCCTRL_PSEL_LOW 0x00 /* PSEL high selects directcolor */
  197. #define TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
  198. #define TVP3026_XGENIOCTRL 0x2A
  199. #define TVP3026_XGENIODATA 0x2B
  200. #define TVP3026_XPLLADDR 0x2C
  201. #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
  202. #define TVP3026_XPLLDATA_N 0x00
  203. #define TVP3026_XPLLDATA_M 0x01
  204. #define TVP3026_XPLLDATA_P 0x02
  205. #define TVP3026_XPLLDATA_STAT 0x03
  206. #define TVP3026_XPIXPLLDATA 0x2D
  207. #define TVP3026_XMEMPLLDATA 0x2E
  208. #define TVP3026_XLOOPPLLDATA 0x2F
  209. #define TVP3026_XCOLKEYOVRMIN 0x30
  210. #define TVP3026_XCOLKEYOVRMAX 0x31
  211. #define TVP3026_XCOLKEYREDMIN 0x32
  212. #define TVP3026_XCOLKEYREDMAX 0x33
  213. #define TVP3026_XCOLKEYGREENMIN 0x34
  214. #define TVP3026_XCOLKEYGREENMAX 0x35
  215. #define TVP3026_XCOLKEYBLUEMIN 0x36
  216. #define TVP3026_XCOLKEYBLUEMAX 0x37
  217. #define TVP3026_XCOLKEYCTRL 0x38
  218. #define TVP3026_XCOLKEYCTRL_OVR_EN 0x01
  219. #define TVP3026_XCOLKEYCTRL_RED_EN 0x02
  220. #define TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
  221. #define TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
  222. #define TVP3026_XCOLKEYCTRL_NEGATE 0x10
  223. #define TVP3026_XCOLKEYCTRL_ZOOM1 0x00
  224. #define TVP3026_XCOLKEYCTRL_ZOOM2 0x20
  225. #define TVP3026_XCOLKEYCTRL_ZOOM4 0x40
  226. #define TVP3026_XCOLKEYCTRL_ZOOM8 0x60
  227. #define TVP3026_XCOLKEYCTRL_ZOOM16 0x80
  228. #define TVP3026_XCOLKEYCTRL_ZOOM32 0xA0
  229. #define TVP3026_XMEMPLLCTRL 0x39
  230. #define TVP3026_XMEMPLLCTRL_DIV(X) (((X)-1)>>1) /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
  231. #define TVP3026_XMEMPLLCTRL_STROBEMKC4 0x08
  232. #define TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK 0x00 /* MKC4 */
  233. #define TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL 0x10 /* MKC4 */
  234. #define TVP3026_XMEMPLLCTRL_RCLK_PIXPLL 0x00
  235. #define TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL 0x20
  236. #define TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN 0x40 /* dot clock divided by loop pclk N prescaler */
  237. #define TVP3026_XSENSETEST 0x3A
  238. #define TVP3026_XTESTMODEDATA 0x3B
  239. #define TVP3026_XCRCREML 0x3C
  240. #define TVP3026_XCRCREMH 0x3D
  241. #define TVP3026_XCRCBITSEL 0x3E
  242. #define TVP3026_XID 0x3F
  243. static const unsigned char DACseq[] =
  244. { TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
  245. TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
  246. TVP3026_XPALETTEPAGE,
  247. TVP3026_XGENCTRL,
  248. TVP3026_XMISCCTRL,
  249. TVP3026_XGENIOCTRL,
  250. TVP3026_XGENIODATA,
  251. TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
  252. TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
  253. TVP3026_XCOLKEYCTRL,
  254. TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
  255. #define POS3026_XLATCHCTRL 0
  256. #define POS3026_XTRUECOLORCTRL 1
  257. #define POS3026_XMUXCTRL 2
  258. #define POS3026_XCLKCTRL 3
  259. #define POS3026_XGENCTRL 5
  260. #define POS3026_XMISCCTRL 6
  261. #define POS3026_XMEMPLLCTRL 18
  262. #define POS3026_XCURCTRL 20
  263. static const unsigned char MGADACbpp32[] =
  264. { TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
  265. 0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
  266. 0x00,
  267. TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
  268. TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
  269. 0x00,
  270. 0x1E,
  271. 0xFF, 0xFF, 0xFF, 0xFF,
  272. 0xFF, 0xFF, 0xFF, 0xFF,
  273. TVP3026_XCOLKEYCTRL_ZOOM1,
  274. 0x00, 0x00, TVP3026_XCURCTRL_DIS };
  275. static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* in, int* feed, int* post) {
  276. unsigned int fvco;
  277. unsigned int lin, lfeed, lpost;
  278. DBG(__FUNCTION__)
  279. fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost);
  280. fvco >>= (*post = lpost);
  281. *in = 64 - lin;
  282. *feed = 64 - lfeed;
  283. return fvco;
  284. }
  285. static int Ti3026_setpclk(WPMINFO int clk) {
  286. unsigned int f_pll;
  287. unsigned int pixfeed, pixin, pixpost;
  288. struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
  289. DBG(__FUNCTION__)
  290. f_pll = Ti3026_calcclock(PMINFO clk, ACCESS_FBINFO(max_pixel_clock), &pixin, &pixfeed, &pixpost);
  291. hw->DACclk[0] = pixin | 0xC0;
  292. hw->DACclk[1] = pixfeed;
  293. hw->DACclk[2] = pixpost | 0xB0;
  294. {
  295. unsigned int loopfeed, loopin, looppost, loopdiv, z;
  296. unsigned int Bpp;
  297. Bpp = ACCESS_FBINFO(curr.final_bppShift);
  298. if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
  299. loopfeed = 3; /* set lm to any possible value */
  300. loopin = 3 * 32 / Bpp;
  301. } else {
  302. loopfeed = 4;
  303. loopin = 4 * 32 / Bpp;
  304. }
  305. z = (110000 * loopin) / (f_pll * loopfeed);
  306. loopdiv = 0; /* div 2 */
  307. if (z < 2)
  308. looppost = 0;
  309. else if (z < 4)
  310. looppost = 1;
  311. else if (z < 8)
  312. looppost = 2;
  313. else {
  314. looppost = 3;
  315. loopdiv = z/16;
  316. }
  317. if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
  318. hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
  319. hw->DACclk[4] = (65 - loopfeed) | 0x80;
  320. if (ACCESS_FBINFO(accel.ramdac_rev) > 0x20) {
  321. if (isInterleave(MINFO))
  322. hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
  323. else {
  324. hw->DACclk[4] &= ~0xC0;
  325. hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
  326. }
  327. } else {
  328. if (isInterleave(MINFO))
  329. ; /* default... */
  330. else {
  331. hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
  332. hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
  333. }
  334. }
  335. hw->DACclk[5] = looppost | 0xF8;
  336. if (ACCESS_FBINFO(devflags.mga_24bpp_fix))
  337. hw->DACclk[5] ^= 0x40;
  338. } else {
  339. hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
  340. hw->DACclk[4] = 65 - loopfeed;
  341. hw->DACclk[5] = looppost | 0xF0;
  342. }
  343. hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
  344. }
  345. return 0;
  346. }
  347. static int Ti3026_init(WPMINFO struct my_timming* m) {
  348. u_int8_t muxctrl = isInterleave(MINFO) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
  349. struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
  350. DBG(__FUNCTION__)
  351. memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
  352. switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) {
  353. case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
  354. hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
  355. hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
  356. hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
  357. hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
  358. break;
  359. case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1; /* or _4_1, they are same */
  360. hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
  361. hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
  362. hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
  363. hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
  364. break;
  365. case 16:
  366. /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */
  367. hw->DACreg[POS3026_XTRUECOLORCTRL] = (ACCESS_FBINFO(fbcon).var.green.length == 5)? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555 ) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
  368. hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
  369. hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
  370. break;
  371. case 24:
  372. /* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
  373. hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
  374. hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
  375. hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
  376. break;
  377. case 32:
  378. /* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used everytime) */
  379. hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
  380. break;
  381. default:
  382. return 1; /* TODO: failed */
  383. }
  384. if (matroxfb_vgaHWinit(PMINFO m)) return 1;
  385. /* set SYNC */
  386. hw->MiscOutReg = 0xCB;
  387. if (m->sync & FB_SYNC_HOR_HIGH_ACT)
  388. hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
  389. if (m->sync & FB_SYNC_VERT_HIGH_ACT)
  390. hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
  391. if (m->sync & FB_SYNC_ON_GREEN)
  392. hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
  393. /* set DELAY */
  394. if (ACCESS_FBINFO(video.len) < 0x400000)
  395. hw->CRTCEXT[3] |= 0x08;
  396. else if (ACCESS_FBINFO(video.len) > 0x400000)
  397. hw->CRTCEXT[3] |= 0x10;
  398. /* set HWCURSOR */
  399. if (m->interlaced) {
  400. hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
  401. }
  402. if (m->HTotal >= 1536)
  403. hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
  404. /* set interleaving */
  405. hw->MXoptionReg &= ~0x00001000;
  406. if (isInterleave(MINFO)) hw->MXoptionReg |= 0x00001000;
  407. /* set DAC */
  408. Ti3026_setpclk(PMINFO m->pixclock);
  409. return 0;
  410. }
  411. static void ti3026_setMCLK(WPMINFO int fout){
  412. unsigned int f_pll;
  413. unsigned int pclk_m, pclk_n, pclk_p;
  414. unsigned int mclk_m, mclk_n, mclk_p;
  415. unsigned int rfhcnt, mclk_ctl;
  416. int tmout;
  417. DBG(__FUNCTION__)
  418. f_pll = Ti3026_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &mclk_n, &mclk_m, &mclk_p);
  419. /* save pclk */
  420. outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
  421. pclk_n = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
  422. outTi3026(PMINFO TVP3026_XPLLADDR, 0xFD);
  423. pclk_m = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
  424. outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
  425. pclk_p = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
  426. /* stop pclk */
  427. outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
  428. outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
  429. /* set pclk to new mclk */
  430. outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
  431. outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
  432. outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_m);
  433. outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
  434. /* wait for PLL to lock */
  435. for (tmout = 500000; tmout; tmout--) {
  436. if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
  437. break;
  438. udelay(10);
  439. };
  440. if (!tmout)
  441. printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
  442. /* output pclk on mclk pin */
  443. mclk_ctl = inTi3026(PMINFO TVP3026_XMEMPLLCTRL);
  444. outTi3026(PMINFO TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
  445. outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
  446. /* stop MCLK */
  447. outTi3026(PMINFO TVP3026_XPLLADDR, 0xFB);
  448. outTi3026(PMINFO TVP3026_XMEMPLLDATA, 0x00);
  449. /* set mclk to new freq */
  450. outTi3026(PMINFO TVP3026_XPLLADDR, 0xF3);
  451. outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
  452. outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_m);
  453. outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
  454. /* wait for PLL to lock */
  455. for (tmout = 500000; tmout; tmout--) {
  456. if (inTi3026(PMINFO TVP3026_XMEMPLLDATA) & 0x40)
  457. break;
  458. udelay(10);
  459. }
  460. if (!tmout)
  461. printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
  462. f_pll = f_pll * 333 / (10000 << mclk_p);
  463. if (isMilleniumII(MINFO)) {
  464. rfhcnt = (f_pll - 128) / 256;
  465. if (rfhcnt > 15)
  466. rfhcnt = 15;
  467. } else {
  468. rfhcnt = (f_pll - 64) / 128;
  469. if (rfhcnt > 15)
  470. rfhcnt = 0;
  471. }
  472. ACCESS_FBINFO(hw).MXoptionReg = (ACCESS_FBINFO(hw).MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
  473. pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg);
  474. /* output MCLK to MCLK pin */
  475. outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
  476. outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
  477. /* stop PCLK */
  478. outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
  479. outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
  480. /* restore pclk */
  481. outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
  482. outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_n);
  483. outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_m);
  484. outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_p);
  485. /* wait for PLL to lock */
  486. for (tmout = 500000; tmout; tmout--) {
  487. if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
  488. break;
  489. udelay(10);
  490. }
  491. if (!tmout)
  492. printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
  493. }
  494. static void ti3026_ramdac_init(WPMINFO2) {
  495. DBG(__FUNCTION__)
  496. ACCESS_FBINFO(features.pll.vco_freq_min) = 110000;
  497. ACCESS_FBINFO(features.pll.ref_freq) = 114545;
  498. ACCESS_FBINFO(features.pll.feed_div_min) = 2;
  499. ACCESS_FBINFO(features.pll.feed_div_max) = 24;
  500. ACCESS_FBINFO(features.pll.in_div_min) = 2;
  501. ACCESS_FBINFO(features.pll.in_div_max) = 63;
  502. ACCESS_FBINFO(features.pll.post_shift_max) = 3;
  503. if (ACCESS_FBINFO(devflags.noinit))
  504. return;
  505. ti3026_setMCLK(PMINFO 60000);
  506. }
  507. static void Ti3026_restore(WPMINFO2) {
  508. int i;
  509. unsigned char progdac[6];
  510. struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
  511. CRITFLAGS
  512. DBG(__FUNCTION__)
  513. #ifdef DEBUG
  514. dprintk(KERN_INFO "EXTVGA regs: ");
  515. for (i = 0; i < 6; i++)
  516. dprintk("%02X:", hw->CRTCEXT[i]);
  517. dprintk("\n");
  518. #endif
  519. CRITBEGIN
  520. pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
  521. CRITEND
  522. matroxfb_vgaHWrestore(PMINFO2);
  523. CRITBEGIN
  524. ACCESS_FBINFO(crtc1.panpos) = -1;
  525. for (i = 0; i < 6; i++)
  526. mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
  527. for (i = 0; i < 21; i++) {
  528. outTi3026(PMINFO DACseq[i], hw->DACreg[i]);
  529. }
  530. outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
  531. progdac[0] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
  532. progdac[3] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
  533. outTi3026(PMINFO TVP3026_XPLLADDR, 0x15);
  534. progdac[1] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
  535. progdac[4] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
  536. outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
  537. progdac[2] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
  538. progdac[5] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
  539. CRITEND
  540. if (memcmp(hw->DACclk, progdac, 6)) {
  541. /* agrhh... setting up PLL is very slow on Millennium... */
  542. /* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
  543. /* Maybe even we should call schedule() ? */
  544. CRITBEGIN
  545. outTi3026(PMINFO TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
  546. outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
  547. outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0);
  548. outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0);
  549. outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
  550. for (i = 0; i < 3; i++)
  551. outTi3026(PMINFO TVP3026_XPIXPLLDATA, hw->DACclk[i]);
  552. /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
  553. if (hw->MiscOutReg & 0x08) {
  554. int tmout;
  555. outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
  556. for (tmout = 500000; tmout; --tmout) {
  557. if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
  558. break;
  559. udelay(10);
  560. }
  561. CRITEND
  562. if (!tmout)
  563. printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
  564. else
  565. dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
  566. CRITBEGIN
  567. }
  568. outTi3026(PMINFO TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
  569. outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
  570. for (i = 3; i < 6; i++)
  571. outTi3026(PMINFO TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
  572. CRITEND
  573. if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
  574. int tmout;
  575. CRITBEGIN
  576. outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
  577. for (tmout = 500000; tmout; --tmout) {
  578. if (inTi3026(PMINFO TVP3026_XLOOPPLLDATA) & 0x40)
  579. break;
  580. udelay(10);
  581. }
  582. CRITEND
  583. if (!tmout)
  584. printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
  585. else
  586. dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
  587. }
  588. }
  589. #ifdef DEBUG
  590. dprintk(KERN_DEBUG "3026DACregs ");
  591. for (i = 0; i < 21; i++) {
  592. dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
  593. if ((i & 0x7) == 0x7) dprintk("\n" KERN_DEBUG "continuing... ");
  594. }
  595. dprintk("\n" KERN_DEBUG "DACclk ");
  596. for (i = 0; i < 6; i++)
  597. dprintk("C%02X=%02X ", i, hw->DACclk[i]);
  598. dprintk("\n");
  599. #endif
  600. }
  601. static void Ti3026_reset(WPMINFO2) {
  602. DBG(__FUNCTION__)
  603. ti3026_ramdac_init(PMINFO2);
  604. }
  605. static struct matrox_altout ti3026_output = {
  606. .name = "Primary output",
  607. };
  608. static int Ti3026_preinit(WPMINFO2) {
  609. static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
  610. 1024, 1152, 1280, 1600, 1664, 1920,
  611. 2048, 0};
  612. static const int vxres_mill1[] = { 640, 768, 800, 960,
  613. 1024, 1152, 1280, 1600, 1920,
  614. 2048, 0};
  615. struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
  616. DBG(__FUNCTION__)
  617. ACCESS_FBINFO(millenium) = 1;
  618. ACCESS_FBINFO(milleniumII) = (ACCESS_FBINFO(pcidev)->device != PCI_DEVICE_ID_MATROX_MIL);
  619. ACCESS_FBINFO(capable.cfb4) = 1;
  620. ACCESS_FBINFO(capable.text) = 1; /* isMilleniumII(MINFO); */
  621. ACCESS_FBINFO(capable.vxres) = isMilleniumII(MINFO)?vxres_mill2:vxres_mill1;
  622. ACCESS_FBINFO(outputs[0]).data = MINFO;
  623. ACCESS_FBINFO(outputs[0]).output = &ti3026_output;
  624. ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src;
  625. ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
  626. if (ACCESS_FBINFO(devflags.noinit))
  627. return 0;
  628. /* preserve VGA I/O, BIOS and PPC */
  629. hw->MXoptionReg &= 0xC0000100;
  630. hw->MXoptionReg |= 0x002C0000;
  631. if (ACCESS_FBINFO(devflags.novga))
  632. hw->MXoptionReg &= ~0x00000100;
  633. if (ACCESS_FBINFO(devflags.nobios))
  634. hw->MXoptionReg &= ~0x40000000;
  635. if (ACCESS_FBINFO(devflags.nopciretry))
  636. hw->MXoptionReg |= 0x20000000;
  637. pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
  638. ACCESS_FBINFO(accel.ramdac_rev) = inTi3026(PMINFO TVP3026_XSILICONREV);
  639. outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
  640. outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
  641. outTi3026(PMINFO TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
  642. outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
  643. outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0x00);
  644. outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
  645. mga_outb(M_MISC_REG, 0x67);
  646. outTi3026(PMINFO TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
  647. mga_outl(M_RESET, 1);
  648. udelay(250);
  649. mga_outl(M_RESET, 0);
  650. udelay(250);
  651. mga_outl(M_MACCESS, 0x00008000);
  652. udelay(10);
  653. return 0;
  654. }
  655. struct matrox_switch matrox_millennium = {
  656. Ti3026_preinit, Ti3026_reset, Ti3026_init, Ti3026_restore
  657. };
  658. EXPORT_SYMBOL(matrox_millennium);
  659. #endif
  660. MODULE_LICENSE("GPL");