uhci-q.c 39 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553
  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
  19. static void uhci_unlink_generic(struct uhci_hcd *uhci, struct urb *urb);
  20. static void uhci_remove_pending_urbps(struct uhci_hcd *uhci);
  21. static void uhci_free_pending_qhs(struct uhci_hcd *uhci);
  22. static void uhci_free_pending_tds(struct uhci_hcd *uhci);
  23. /*
  24. * Technically, updating td->status here is a race, but it's not really a
  25. * problem. The worst that can happen is that we set the IOC bit again
  26. * generating a spurious interrupt. We could fix this by creating another
  27. * QH and leaving the IOC bit always set, but then we would have to play
  28. * games with the FSBR code to make sure we get the correct order in all
  29. * the cases. I don't think it's worth the effort
  30. */
  31. static inline void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  32. {
  33. if (uhci->is_stopped)
  34. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  35. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  36. }
  37. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  38. {
  39. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  40. }
  41. static inline void uhci_moveto_complete(struct uhci_hcd *uhci,
  42. struct urb_priv *urbp)
  43. {
  44. list_move_tail(&urbp->urb_list, &uhci->complete_list);
  45. }
  46. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  47. {
  48. dma_addr_t dma_handle;
  49. struct uhci_td *td;
  50. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  51. if (!td)
  52. return NULL;
  53. td->dma_handle = dma_handle;
  54. td->link = UHCI_PTR_TERM;
  55. td->buffer = 0;
  56. td->frame = -1;
  57. INIT_LIST_HEAD(&td->list);
  58. INIT_LIST_HEAD(&td->remove_list);
  59. INIT_LIST_HEAD(&td->fl_list);
  60. return td;
  61. }
  62. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  63. u32 token, u32 buffer)
  64. {
  65. td->status = cpu_to_le32(status);
  66. td->token = cpu_to_le32(token);
  67. td->buffer = cpu_to_le32(buffer);
  68. }
  69. /*
  70. * We insert Isochronous URB's directly into the frame list at the beginning
  71. */
  72. static void uhci_insert_td_frame_list(struct uhci_hcd *uhci, struct uhci_td *td, unsigned framenum)
  73. {
  74. framenum &= (UHCI_NUMFRAMES - 1);
  75. td->frame = framenum;
  76. /* Is there a TD already mapped there? */
  77. if (uhci->fl->frame_cpu[framenum]) {
  78. struct uhci_td *ftd, *ltd;
  79. ftd = uhci->fl->frame_cpu[framenum];
  80. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  81. list_add_tail(&td->fl_list, &ftd->fl_list);
  82. td->link = ltd->link;
  83. wmb();
  84. ltd->link = cpu_to_le32(td->dma_handle);
  85. } else {
  86. td->link = uhci->fl->frame[framenum];
  87. wmb();
  88. uhci->fl->frame[framenum] = cpu_to_le32(td->dma_handle);
  89. uhci->fl->frame_cpu[framenum] = td;
  90. }
  91. }
  92. static void uhci_remove_td(struct uhci_hcd *uhci, struct uhci_td *td)
  93. {
  94. /* If it's not inserted, don't remove it */
  95. if (td->frame == -1 && list_empty(&td->fl_list))
  96. return;
  97. if (td->frame != -1 && uhci->fl->frame_cpu[td->frame] == td) {
  98. if (list_empty(&td->fl_list)) {
  99. uhci->fl->frame[td->frame] = td->link;
  100. uhci->fl->frame_cpu[td->frame] = NULL;
  101. } else {
  102. struct uhci_td *ntd;
  103. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  104. uhci->fl->frame[td->frame] = cpu_to_le32(ntd->dma_handle);
  105. uhci->fl->frame_cpu[td->frame] = ntd;
  106. }
  107. } else {
  108. struct uhci_td *ptd;
  109. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  110. ptd->link = td->link;
  111. }
  112. wmb();
  113. td->link = UHCI_PTR_TERM;
  114. list_del_init(&td->fl_list);
  115. td->frame = -1;
  116. }
  117. /*
  118. * Inserts a td list into qh.
  119. */
  120. static void uhci_insert_tds_in_qh(struct uhci_qh *qh, struct urb *urb, __le32 breadth)
  121. {
  122. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  123. struct uhci_td *td;
  124. __le32 *plink;
  125. /* Ordering isn't important here yet since the QH hasn't been */
  126. /* inserted into the schedule yet */
  127. plink = &qh->element;
  128. list_for_each_entry(td, &urbp->td_list, list) {
  129. *plink = cpu_to_le32(td->dma_handle) | breadth;
  130. plink = &td->link;
  131. }
  132. *plink = UHCI_PTR_TERM;
  133. }
  134. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  135. {
  136. if (!list_empty(&td->list))
  137. dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
  138. if (!list_empty(&td->remove_list))
  139. dev_warn(uhci_dev(uhci), "td %p still in remove_list!\n", td);
  140. if (!list_empty(&td->fl_list))
  141. dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  142. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  143. }
  144. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci)
  145. {
  146. dma_addr_t dma_handle;
  147. struct uhci_qh *qh;
  148. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  149. if (!qh)
  150. return NULL;
  151. qh->dma_handle = dma_handle;
  152. qh->element = UHCI_PTR_TERM;
  153. qh->link = UHCI_PTR_TERM;
  154. qh->urbp = NULL;
  155. INIT_LIST_HEAD(&qh->list);
  156. INIT_LIST_HEAD(&qh->remove_list);
  157. return qh;
  158. }
  159. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  160. {
  161. if (!list_empty(&qh->list))
  162. dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  163. if (!list_empty(&qh->remove_list))
  164. dev_warn(uhci_dev(uhci), "qh %p still in remove_list!\n", qh);
  165. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  166. }
  167. /*
  168. * Append this urb's qh after the last qh in skelqh->list
  169. *
  170. * Note that urb_priv.queue_list doesn't have a separate queue head;
  171. * it's a ring with every element "live".
  172. */
  173. static void uhci_insert_qh(struct uhci_hcd *uhci, struct uhci_qh *skelqh, struct urb *urb)
  174. {
  175. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  176. struct urb_priv *turbp;
  177. struct uhci_qh *lqh;
  178. /* Grab the last QH */
  179. lqh = list_entry(skelqh->list.prev, struct uhci_qh, list);
  180. /* Point to the next skelqh */
  181. urbp->qh->link = lqh->link;
  182. wmb(); /* Ordering is important */
  183. /*
  184. * Patch QHs for previous endpoint's queued URBs? HC goes
  185. * here next, not to the next skelqh it now points to.
  186. *
  187. * lqh --> td ... --> qh ... --> td --> qh ... --> td
  188. * | | |
  189. * v v v
  190. * +<----------------+-----------------+
  191. * v
  192. * newqh --> td ... --> td
  193. * |
  194. * v
  195. * ...
  196. *
  197. * The HC could see (and use!) any of these as we write them.
  198. */
  199. lqh->link = cpu_to_le32(urbp->qh->dma_handle) | UHCI_PTR_QH;
  200. if (lqh->urbp) {
  201. list_for_each_entry(turbp, &lqh->urbp->queue_list, queue_list)
  202. turbp->qh->link = lqh->link;
  203. }
  204. list_add_tail(&urbp->qh->list, &skelqh->list);
  205. }
  206. /*
  207. * Start removal of QH from schedule; it finishes next frame.
  208. * TDs should be unlinked before this is called.
  209. */
  210. static void uhci_remove_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  211. {
  212. struct uhci_qh *pqh;
  213. __le32 newlink;
  214. if (!qh)
  215. return;
  216. /*
  217. * Only go through the hoops if it's actually linked in
  218. */
  219. if (!list_empty(&qh->list)) {
  220. /* If our queue is nonempty, make the next URB the head */
  221. if (!list_empty(&qh->urbp->queue_list)) {
  222. struct urb_priv *nurbp;
  223. nurbp = list_entry(qh->urbp->queue_list.next,
  224. struct urb_priv, queue_list);
  225. nurbp->queued = 0;
  226. list_add(&nurbp->qh->list, &qh->list);
  227. newlink = cpu_to_le32(nurbp->qh->dma_handle) | UHCI_PTR_QH;
  228. } else
  229. newlink = qh->link;
  230. /* Fix up the previous QH's queue to link to either
  231. * the new head of this queue or the start of the
  232. * next endpoint's queue. */
  233. pqh = list_entry(qh->list.prev, struct uhci_qh, list);
  234. pqh->link = newlink;
  235. if (pqh->urbp) {
  236. struct urb_priv *turbp;
  237. list_for_each_entry(turbp, &pqh->urbp->queue_list,
  238. queue_list)
  239. turbp->qh->link = newlink;
  240. }
  241. wmb();
  242. /* Leave qh->link in case the HC is on the QH now, it will */
  243. /* continue the rest of the schedule */
  244. qh->element = UHCI_PTR_TERM;
  245. list_del_init(&qh->list);
  246. }
  247. list_del_init(&qh->urbp->queue_list);
  248. qh->urbp = NULL;
  249. uhci_get_current_frame_number(uhci);
  250. if (uhci->frame_number + uhci->is_stopped != uhci->qh_remove_age) {
  251. uhci_free_pending_qhs(uhci);
  252. uhci->qh_remove_age = uhci->frame_number;
  253. }
  254. /* Check to see if the remove list is empty. Set the IOC bit */
  255. /* to force an interrupt so we can remove the QH */
  256. if (list_empty(&uhci->qh_remove_list))
  257. uhci_set_next_interrupt(uhci);
  258. list_add(&qh->remove_list, &uhci->qh_remove_list);
  259. }
  260. static int uhci_fixup_toggle(struct urb *urb, unsigned int toggle)
  261. {
  262. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  263. struct uhci_td *td;
  264. list_for_each_entry(td, &urbp->td_list, list) {
  265. if (toggle)
  266. td->token |= cpu_to_le32(TD_TOKEN_TOGGLE);
  267. else
  268. td->token &= ~cpu_to_le32(TD_TOKEN_TOGGLE);
  269. toggle ^= 1;
  270. }
  271. return toggle;
  272. }
  273. /* This function will append one URB's QH to another URB's QH. This is for */
  274. /* queuing interrupt, control or bulk transfers */
  275. static void uhci_append_queued_urb(struct uhci_hcd *uhci, struct urb *eurb, struct urb *urb)
  276. {
  277. struct urb_priv *eurbp, *urbp, *furbp, *lurbp;
  278. struct uhci_td *lltd;
  279. eurbp = eurb->hcpriv;
  280. urbp = urb->hcpriv;
  281. /* Find the first URB in the queue */
  282. furbp = eurbp;
  283. if (eurbp->queued) {
  284. list_for_each_entry(furbp, &eurbp->queue_list, queue_list)
  285. if (!furbp->queued)
  286. break;
  287. }
  288. lurbp = list_entry(furbp->queue_list.prev, struct urb_priv, queue_list);
  289. lltd = list_entry(lurbp->td_list.prev, struct uhci_td, list);
  290. /* Control transfers always start with toggle 0 */
  291. if (!usb_pipecontrol(urb->pipe))
  292. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  293. usb_pipeout(urb->pipe),
  294. uhci_fixup_toggle(urb,
  295. uhci_toggle(td_token(lltd)) ^ 1));
  296. /* All qh's in the queue need to link to the next queue */
  297. urbp->qh->link = eurbp->qh->link;
  298. wmb(); /* Make sure we flush everything */
  299. lltd->link = cpu_to_le32(urbp->qh->dma_handle) | UHCI_PTR_QH;
  300. list_add_tail(&urbp->queue_list, &furbp->queue_list);
  301. urbp->queued = 1;
  302. }
  303. static void uhci_delete_queued_urb(struct uhci_hcd *uhci, struct urb *urb)
  304. {
  305. struct urb_priv *urbp, *nurbp, *purbp, *turbp;
  306. struct uhci_td *pltd;
  307. unsigned int toggle;
  308. urbp = urb->hcpriv;
  309. if (list_empty(&urbp->queue_list))
  310. return;
  311. nurbp = list_entry(urbp->queue_list.next, struct urb_priv, queue_list);
  312. /*
  313. * Fix up the toggle for the following URBs in the queue.
  314. * Only needed for bulk and interrupt: control and isochronous
  315. * endpoints don't propagate toggles between messages.
  316. */
  317. if (usb_pipebulk(urb->pipe) || usb_pipeint(urb->pipe)) {
  318. if (!urbp->queued)
  319. /* We just set the toggle in uhci_unlink_generic */
  320. toggle = usb_gettoggle(urb->dev,
  321. usb_pipeendpoint(urb->pipe),
  322. usb_pipeout(urb->pipe));
  323. else {
  324. /* If we're in the middle of the queue, grab the */
  325. /* toggle from the TD previous to us */
  326. purbp = list_entry(urbp->queue_list.prev,
  327. struct urb_priv, queue_list);
  328. pltd = list_entry(purbp->td_list.prev,
  329. struct uhci_td, list);
  330. toggle = uhci_toggle(td_token(pltd)) ^ 1;
  331. }
  332. list_for_each_entry(turbp, &urbp->queue_list, queue_list) {
  333. if (!turbp->queued)
  334. break;
  335. toggle = uhci_fixup_toggle(turbp->urb, toggle);
  336. }
  337. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  338. usb_pipeout(urb->pipe), toggle);
  339. }
  340. if (urbp->queued) {
  341. /* We're somewhere in the middle (or end). The case where
  342. * we're at the head is handled in uhci_remove_qh(). */
  343. purbp = list_entry(urbp->queue_list.prev, struct urb_priv,
  344. queue_list);
  345. pltd = list_entry(purbp->td_list.prev, struct uhci_td, list);
  346. if (nurbp->queued)
  347. pltd->link = cpu_to_le32(nurbp->qh->dma_handle) | UHCI_PTR_QH;
  348. else
  349. /* The next URB happens to be the beginning, so */
  350. /* we're the last, end the chain */
  351. pltd->link = UHCI_PTR_TERM;
  352. }
  353. /* urbp->queue_list is handled in uhci_remove_qh() */
  354. }
  355. static struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci, struct urb *urb)
  356. {
  357. struct urb_priv *urbp;
  358. urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC);
  359. if (!urbp)
  360. return NULL;
  361. memset((void *)urbp, 0, sizeof(*urbp));
  362. urbp->inserttime = jiffies;
  363. urbp->fsbrtime = jiffies;
  364. urbp->urb = urb;
  365. INIT_LIST_HEAD(&urbp->td_list);
  366. INIT_LIST_HEAD(&urbp->queue_list);
  367. INIT_LIST_HEAD(&urbp->urb_list);
  368. list_add_tail(&urbp->urb_list, &uhci->urb_list);
  369. urb->hcpriv = urbp;
  370. return urbp;
  371. }
  372. static void uhci_add_td_to_urb(struct urb *urb, struct uhci_td *td)
  373. {
  374. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  375. td->urb = urb;
  376. list_add_tail(&td->list, &urbp->td_list);
  377. }
  378. static void uhci_remove_td_from_urb(struct uhci_td *td)
  379. {
  380. if (list_empty(&td->list))
  381. return;
  382. list_del_init(&td->list);
  383. td->urb = NULL;
  384. }
  385. static void uhci_destroy_urb_priv(struct uhci_hcd *uhci, struct urb *urb)
  386. {
  387. struct uhci_td *td, *tmp;
  388. struct urb_priv *urbp;
  389. urbp = (struct urb_priv *)urb->hcpriv;
  390. if (!urbp)
  391. return;
  392. if (!list_empty(&urbp->urb_list))
  393. dev_warn(uhci_dev(uhci), "urb %p still on uhci->urb_list "
  394. "or uhci->remove_list!\n", urb);
  395. uhci_get_current_frame_number(uhci);
  396. if (uhci->frame_number + uhci->is_stopped != uhci->td_remove_age) {
  397. uhci_free_pending_tds(uhci);
  398. uhci->td_remove_age = uhci->frame_number;
  399. }
  400. /* Check to see if the remove list is empty. Set the IOC bit */
  401. /* to force an interrupt so we can remove the TD's*/
  402. if (list_empty(&uhci->td_remove_list))
  403. uhci_set_next_interrupt(uhci);
  404. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  405. uhci_remove_td_from_urb(td);
  406. uhci_remove_td(uhci, td);
  407. list_add(&td->remove_list, &uhci->td_remove_list);
  408. }
  409. urb->hcpriv = NULL;
  410. kmem_cache_free(uhci_up_cachep, urbp);
  411. }
  412. static void uhci_inc_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  413. {
  414. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  415. if ((!(urb->transfer_flags & URB_NO_FSBR)) && !urbp->fsbr) {
  416. urbp->fsbr = 1;
  417. if (!uhci->fsbr++ && !uhci->fsbrtimeout)
  418. uhci->skel_term_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
  419. }
  420. }
  421. static void uhci_dec_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  422. {
  423. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  424. if ((!(urb->transfer_flags & URB_NO_FSBR)) && urbp->fsbr) {
  425. urbp->fsbr = 0;
  426. if (!--uhci->fsbr)
  427. uhci->fsbrtimeout = jiffies + FSBR_DELAY;
  428. }
  429. }
  430. /*
  431. * Map status to standard result codes
  432. *
  433. * <status> is (td_status(td) & 0xF60000), a.k.a.
  434. * uhci_status_bits(td_status(td)).
  435. * Note: <status> does not include the TD_CTRL_NAK bit.
  436. * <dir_out> is True for output TDs and False for input TDs.
  437. */
  438. static int uhci_map_status(int status, int dir_out)
  439. {
  440. if (!status)
  441. return 0;
  442. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  443. return -EPROTO;
  444. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  445. if (dir_out)
  446. return -EPROTO;
  447. else
  448. return -EILSEQ;
  449. }
  450. if (status & TD_CTRL_BABBLE) /* Babble */
  451. return -EOVERFLOW;
  452. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  453. return -ENOSR;
  454. if (status & TD_CTRL_STALLED) /* Stalled */
  455. return -EPIPE;
  456. WARN_ON(status & TD_CTRL_ACTIVE); /* Active */
  457. return 0;
  458. }
  459. /*
  460. * Control transfers
  461. */
  462. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
  463. {
  464. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  465. struct uhci_td *td;
  466. struct uhci_qh *qh, *skelqh;
  467. unsigned long destination, status;
  468. int maxsze = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  469. int len = urb->transfer_buffer_length;
  470. dma_addr_t data = urb->transfer_dma;
  471. /* The "pipe" thing contains the destination in bits 8--18 */
  472. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  473. /* 3 errors */
  474. status = TD_CTRL_ACTIVE | uhci_maxerr(3);
  475. if (urb->dev->speed == USB_SPEED_LOW)
  476. status |= TD_CTRL_LS;
  477. /*
  478. * Build the TD for the control request setup packet
  479. */
  480. td = uhci_alloc_td(uhci);
  481. if (!td)
  482. return -ENOMEM;
  483. uhci_add_td_to_urb(urb, td);
  484. uhci_fill_td(td, status, destination | uhci_explen(7),
  485. urb->setup_dma);
  486. /*
  487. * If direction is "send", change the packet ID from SETUP (0x2D)
  488. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  489. * set Short Packet Detect (SPD) for all data packets.
  490. */
  491. if (usb_pipeout(urb->pipe))
  492. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  493. else {
  494. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  495. status |= TD_CTRL_SPD;
  496. }
  497. /*
  498. * Build the DATA TD's
  499. */
  500. while (len > 0) {
  501. int pktsze = len;
  502. if (pktsze > maxsze)
  503. pktsze = maxsze;
  504. td = uhci_alloc_td(uhci);
  505. if (!td)
  506. return -ENOMEM;
  507. /* Alternate Data0/1 (start with Data1) */
  508. destination ^= TD_TOKEN_TOGGLE;
  509. uhci_add_td_to_urb(urb, td);
  510. uhci_fill_td(td, status, destination | uhci_explen(pktsze - 1),
  511. data);
  512. data += pktsze;
  513. len -= pktsze;
  514. }
  515. /*
  516. * Build the final TD for control status
  517. */
  518. td = uhci_alloc_td(uhci);
  519. if (!td)
  520. return -ENOMEM;
  521. /*
  522. * It's IN if the pipe is an output pipe or we're not expecting
  523. * data back.
  524. */
  525. destination &= ~TD_TOKEN_PID_MASK;
  526. if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
  527. destination |= USB_PID_IN;
  528. else
  529. destination |= USB_PID_OUT;
  530. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  531. status &= ~TD_CTRL_SPD;
  532. uhci_add_td_to_urb(urb, td);
  533. uhci_fill_td(td, status | TD_CTRL_IOC,
  534. destination | uhci_explen(UHCI_NULL_DATA_SIZE), 0);
  535. qh = uhci_alloc_qh(uhci);
  536. if (!qh)
  537. return -ENOMEM;
  538. urbp->qh = qh;
  539. qh->urbp = urbp;
  540. uhci_insert_tds_in_qh(qh, urb, UHCI_PTR_BREADTH);
  541. /* Low-speed transfers get a different queue, and won't hog the bus.
  542. * Also, some devices enumerate better without FSBR; the easiest way
  543. * to do that is to put URBs on the low-speed queue while the device
  544. * is in the DEFAULT state. */
  545. if (urb->dev->speed == USB_SPEED_LOW ||
  546. urb->dev->state == USB_STATE_DEFAULT)
  547. skelqh = uhci->skel_ls_control_qh;
  548. else {
  549. skelqh = uhci->skel_fs_control_qh;
  550. uhci_inc_fsbr(uhci, urb);
  551. }
  552. if (eurb)
  553. uhci_append_queued_urb(uhci, eurb, urb);
  554. else
  555. uhci_insert_qh(uhci, skelqh, urb);
  556. return -EINPROGRESS;
  557. }
  558. /*
  559. * If control-IN transfer was short, the status packet wasn't sent.
  560. * This routine changes the element pointer in the QH to point at the
  561. * status TD. It's safe to do this even while the QH is live, because
  562. * the hardware only updates the element pointer following a successful
  563. * transfer. The inactive TD for the short packet won't cause an update,
  564. * so the pointer won't get overwritten. The next time the controller
  565. * sees this QH, it will send the status packet.
  566. */
  567. static int usb_control_retrigger_status(struct uhci_hcd *uhci, struct urb *urb)
  568. {
  569. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  570. struct uhci_td *td;
  571. urbp->short_control_packet = 1;
  572. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  573. urbp->qh->element = cpu_to_le32(td->dma_handle);
  574. return -EINPROGRESS;
  575. }
  576. static int uhci_result_control(struct uhci_hcd *uhci, struct urb *urb)
  577. {
  578. struct list_head *tmp, *head;
  579. struct urb_priv *urbp = urb->hcpriv;
  580. struct uhci_td *td;
  581. unsigned int status;
  582. int ret = 0;
  583. if (list_empty(&urbp->td_list))
  584. return -EINVAL;
  585. head = &urbp->td_list;
  586. if (urbp->short_control_packet) {
  587. tmp = head->prev;
  588. goto status_stage;
  589. }
  590. tmp = head->next;
  591. td = list_entry(tmp, struct uhci_td, list);
  592. /* The first TD is the SETUP stage, check the status, but skip */
  593. /* the count */
  594. status = uhci_status_bits(td_status(td));
  595. if (status & TD_CTRL_ACTIVE)
  596. return -EINPROGRESS;
  597. if (status)
  598. goto td_error;
  599. urb->actual_length = 0;
  600. /* The rest of the TD's (but the last) are data */
  601. tmp = tmp->next;
  602. while (tmp != head && tmp->next != head) {
  603. unsigned int ctrlstat;
  604. td = list_entry(tmp, struct uhci_td, list);
  605. tmp = tmp->next;
  606. ctrlstat = td_status(td);
  607. status = uhci_status_bits(ctrlstat);
  608. if (status & TD_CTRL_ACTIVE)
  609. return -EINPROGRESS;
  610. urb->actual_length += uhci_actual_length(ctrlstat);
  611. if (status)
  612. goto td_error;
  613. /* Check to see if we received a short packet */
  614. if (uhci_actual_length(ctrlstat) <
  615. uhci_expected_length(td_token(td))) {
  616. if (urb->transfer_flags & URB_SHORT_NOT_OK) {
  617. ret = -EREMOTEIO;
  618. goto err;
  619. }
  620. if (uhci_packetid(td_token(td)) == USB_PID_IN)
  621. return usb_control_retrigger_status(uhci, urb);
  622. else
  623. return 0;
  624. }
  625. }
  626. status_stage:
  627. td = list_entry(tmp, struct uhci_td, list);
  628. /* Control status stage */
  629. status = td_status(td);
  630. #ifdef I_HAVE_BUGGY_APC_BACKUPS
  631. /* APC BackUPS Pro kludge */
  632. /* It tries to send all of the descriptor instead of the amount */
  633. /* we requested */
  634. if (status & TD_CTRL_IOC && /* IOC is masked out by uhci_status_bits */
  635. status & TD_CTRL_ACTIVE &&
  636. status & TD_CTRL_NAK)
  637. return 0;
  638. #endif
  639. status = uhci_status_bits(status);
  640. if (status & TD_CTRL_ACTIVE)
  641. return -EINPROGRESS;
  642. if (status)
  643. goto td_error;
  644. return 0;
  645. td_error:
  646. ret = uhci_map_status(status, uhci_packetout(td_token(td)));
  647. err:
  648. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  649. /* Some debugging code */
  650. dev_dbg(uhci_dev(uhci), "%s: failed with status %x\n",
  651. __FUNCTION__, status);
  652. if (errbuf) {
  653. /* Print the chain for debugging purposes */
  654. uhci_show_qh(urbp->qh, errbuf, ERRBUF_LEN, 0);
  655. lprintk(errbuf);
  656. }
  657. }
  658. return ret;
  659. }
  660. /*
  661. * Common submit for bulk and interrupt
  662. */
  663. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb, struct uhci_qh *skelqh)
  664. {
  665. struct uhci_td *td;
  666. struct uhci_qh *qh;
  667. unsigned long destination, status;
  668. int maxsze = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  669. int len = urb->transfer_buffer_length;
  670. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  671. dma_addr_t data = urb->transfer_dma;
  672. if (len < 0)
  673. return -EINVAL;
  674. /* The "pipe" thing contains the destination in bits 8--18 */
  675. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  676. status = uhci_maxerr(3) | TD_CTRL_ACTIVE;
  677. if (urb->dev->speed == USB_SPEED_LOW)
  678. status |= TD_CTRL_LS;
  679. if (usb_pipein(urb->pipe))
  680. status |= TD_CTRL_SPD;
  681. /*
  682. * Build the DATA TD's
  683. */
  684. do { /* Allow zero length packets */
  685. int pktsze = maxsze;
  686. if (pktsze >= len) {
  687. pktsze = len;
  688. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  689. status &= ~TD_CTRL_SPD;
  690. }
  691. td = uhci_alloc_td(uhci);
  692. if (!td)
  693. return -ENOMEM;
  694. uhci_add_td_to_urb(urb, td);
  695. uhci_fill_td(td, status, destination | uhci_explen(pktsze - 1) |
  696. (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  697. usb_pipeout(urb->pipe)) << TD_TOKEN_TOGGLE_SHIFT),
  698. data);
  699. data += pktsze;
  700. len -= maxsze;
  701. usb_dotoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  702. usb_pipeout(urb->pipe));
  703. } while (len > 0);
  704. /*
  705. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  706. * is OUT and the transfer_length was an exact multiple of maxsze,
  707. * hence (len = transfer_length - N * maxsze) == 0
  708. * however, if transfer_length == 0, the zero packet was already
  709. * prepared above.
  710. */
  711. if (usb_pipeout(urb->pipe) && (urb->transfer_flags & URB_ZERO_PACKET) &&
  712. !len && urb->transfer_buffer_length) {
  713. td = uhci_alloc_td(uhci);
  714. if (!td)
  715. return -ENOMEM;
  716. uhci_add_td_to_urb(urb, td);
  717. uhci_fill_td(td, status, destination | uhci_explen(UHCI_NULL_DATA_SIZE) |
  718. (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  719. usb_pipeout(urb->pipe)) << TD_TOKEN_TOGGLE_SHIFT),
  720. data);
  721. usb_dotoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  722. usb_pipeout(urb->pipe));
  723. }
  724. /* Set the interrupt-on-completion flag on the last packet.
  725. * A more-or-less typical 4 KB URB (= size of one memory page)
  726. * will require about 3 ms to transfer; that's a little on the
  727. * fast side but not enough to justify delaying an interrupt
  728. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  729. * flag setting. */
  730. td->status |= cpu_to_le32(TD_CTRL_IOC);
  731. qh = uhci_alloc_qh(uhci);
  732. if (!qh)
  733. return -ENOMEM;
  734. urbp->qh = qh;
  735. qh->urbp = urbp;
  736. /* Always breadth first */
  737. uhci_insert_tds_in_qh(qh, urb, UHCI_PTR_BREADTH);
  738. if (eurb)
  739. uhci_append_queued_urb(uhci, eurb, urb);
  740. else
  741. uhci_insert_qh(uhci, skelqh, urb);
  742. return -EINPROGRESS;
  743. }
  744. /*
  745. * Common result for bulk and interrupt
  746. */
  747. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  748. {
  749. struct urb_priv *urbp = urb->hcpriv;
  750. struct uhci_td *td;
  751. unsigned int status = 0;
  752. int ret = 0;
  753. urb->actual_length = 0;
  754. list_for_each_entry(td, &urbp->td_list, list) {
  755. unsigned int ctrlstat = td_status(td);
  756. status = uhci_status_bits(ctrlstat);
  757. if (status & TD_CTRL_ACTIVE)
  758. return -EINPROGRESS;
  759. urb->actual_length += uhci_actual_length(ctrlstat);
  760. if (status)
  761. goto td_error;
  762. if (uhci_actual_length(ctrlstat) <
  763. uhci_expected_length(td_token(td))) {
  764. if (urb->transfer_flags & URB_SHORT_NOT_OK) {
  765. ret = -EREMOTEIO;
  766. goto err;
  767. } else
  768. return 0;
  769. }
  770. }
  771. return 0;
  772. td_error:
  773. ret = uhci_map_status(status, uhci_packetout(td_token(td)));
  774. err:
  775. /*
  776. * Enable this chunk of code if you want to see some more debugging.
  777. * But be careful, it has the tendancy to starve out khubd and prevent
  778. * disconnects from happening successfully if you have a slow debug
  779. * log interface (like a serial console.
  780. */
  781. #if 0
  782. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  783. /* Some debugging code */
  784. dev_dbg(uhci_dev(uhci), "%s: failed with status %x\n",
  785. __FUNCTION__, status);
  786. if (errbuf) {
  787. /* Print the chain for debugging purposes */
  788. uhci_show_qh(urbp->qh, errbuf, ERRBUF_LEN, 0);
  789. lprintk(errbuf);
  790. }
  791. }
  792. #endif
  793. return ret;
  794. }
  795. static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
  796. {
  797. int ret;
  798. /* Can't have low-speed bulk transfers */
  799. if (urb->dev->speed == USB_SPEED_LOW)
  800. return -EINVAL;
  801. ret = uhci_submit_common(uhci, urb, eurb, uhci->skel_bulk_qh);
  802. if (ret == -EINPROGRESS)
  803. uhci_inc_fsbr(uhci, urb);
  804. return ret;
  805. }
  806. static inline int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
  807. {
  808. /* USB 1.1 interrupt transfers only involve one packet per interval;
  809. * that's the uhci_submit_common() "breadth first" policy. Drivers
  810. * can submit urbs of any length, but longer ones might need many
  811. * intervals to complete.
  812. */
  813. return uhci_submit_common(uhci, urb, eurb, uhci->skelqh[__interval_to_skel(urb->interval)]);
  814. }
  815. /*
  816. * Isochronous transfers
  817. */
  818. static int isochronous_find_limits(struct uhci_hcd *uhci, struct urb *urb, unsigned int *start, unsigned int *end)
  819. {
  820. struct urb *last_urb = NULL;
  821. struct urb_priv *up;
  822. int ret = 0;
  823. list_for_each_entry(up, &uhci->urb_list, urb_list) {
  824. struct urb *u = up->urb;
  825. /* look for pending URB's with identical pipe handle */
  826. if ((urb->pipe == u->pipe) && (urb->dev == u->dev) &&
  827. (u->status == -EINPROGRESS) && (u != urb)) {
  828. if (!last_urb)
  829. *start = u->start_frame;
  830. last_urb = u;
  831. }
  832. }
  833. if (last_urb) {
  834. *end = (last_urb->start_frame + last_urb->number_of_packets *
  835. last_urb->interval) & (UHCI_NUMFRAMES-1);
  836. ret = 0;
  837. } else
  838. ret = -1; /* no previous urb found */
  839. return ret;
  840. }
  841. static int isochronous_find_start(struct uhci_hcd *uhci, struct urb *urb)
  842. {
  843. int limits;
  844. unsigned int start = 0, end = 0;
  845. if (urb->number_of_packets > 900) /* 900? Why? */
  846. return -EFBIG;
  847. limits = isochronous_find_limits(uhci, urb, &start, &end);
  848. if (urb->transfer_flags & URB_ISO_ASAP) {
  849. if (limits) {
  850. uhci_get_current_frame_number(uhci);
  851. urb->start_frame = (uhci->frame_number + 10)
  852. & (UHCI_NUMFRAMES - 1);
  853. } else
  854. urb->start_frame = end;
  855. } else {
  856. urb->start_frame &= (UHCI_NUMFRAMES - 1);
  857. /* FIXME: Sanity check */
  858. }
  859. return 0;
  860. }
  861. /*
  862. * Isochronous transfers
  863. */
  864. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  865. {
  866. struct uhci_td *td;
  867. int i, ret, frame;
  868. int status, destination;
  869. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  870. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  871. ret = isochronous_find_start(uhci, urb);
  872. if (ret)
  873. return ret;
  874. frame = urb->start_frame;
  875. for (i = 0; i < urb->number_of_packets; i++, frame += urb->interval) {
  876. if (!urb->iso_frame_desc[i].length)
  877. continue;
  878. td = uhci_alloc_td(uhci);
  879. if (!td)
  880. return -ENOMEM;
  881. uhci_add_td_to_urb(urb, td);
  882. uhci_fill_td(td, status, destination | uhci_explen(urb->iso_frame_desc[i].length - 1),
  883. urb->transfer_dma + urb->iso_frame_desc[i].offset);
  884. if (i + 1 >= urb->number_of_packets)
  885. td->status |= cpu_to_le32(TD_CTRL_IOC);
  886. uhci_insert_td_frame_list(uhci, td, frame);
  887. }
  888. return -EINPROGRESS;
  889. }
  890. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  891. {
  892. struct uhci_td *td;
  893. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  894. int status;
  895. int i, ret = 0;
  896. urb->actual_length = 0;
  897. i = 0;
  898. list_for_each_entry(td, &urbp->td_list, list) {
  899. int actlength;
  900. unsigned int ctrlstat = td_status(td);
  901. if (ctrlstat & TD_CTRL_ACTIVE)
  902. return -EINPROGRESS;
  903. actlength = uhci_actual_length(ctrlstat);
  904. urb->iso_frame_desc[i].actual_length = actlength;
  905. urb->actual_length += actlength;
  906. status = uhci_map_status(uhci_status_bits(ctrlstat),
  907. usb_pipeout(urb->pipe));
  908. urb->iso_frame_desc[i].status = status;
  909. if (status) {
  910. urb->error_count++;
  911. ret = status;
  912. }
  913. i++;
  914. }
  915. return ret;
  916. }
  917. static struct urb *uhci_find_urb_ep(struct uhci_hcd *uhci, struct urb *urb)
  918. {
  919. struct urb_priv *up;
  920. /* We don't match Isoc transfers since they are special */
  921. if (usb_pipeisoc(urb->pipe))
  922. return NULL;
  923. list_for_each_entry(up, &uhci->urb_list, urb_list) {
  924. struct urb *u = up->urb;
  925. if (u->dev == urb->dev && u->status == -EINPROGRESS) {
  926. /* For control, ignore the direction */
  927. if (usb_pipecontrol(urb->pipe) &&
  928. (u->pipe & ~USB_DIR_IN) == (urb->pipe & ~USB_DIR_IN))
  929. return u;
  930. else if (u->pipe == urb->pipe)
  931. return u;
  932. }
  933. }
  934. return NULL;
  935. }
  936. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  937. struct usb_host_endpoint *ep,
  938. struct urb *urb, unsigned mem_flags)
  939. {
  940. int ret;
  941. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  942. unsigned long flags;
  943. struct urb *eurb;
  944. int bustime;
  945. spin_lock_irqsave(&uhci->lock, flags);
  946. ret = urb->status;
  947. if (ret != -EINPROGRESS) /* URB already unlinked! */
  948. goto out;
  949. eurb = uhci_find_urb_ep(uhci, urb);
  950. if (!uhci_alloc_urb_priv(uhci, urb)) {
  951. ret = -ENOMEM;
  952. goto out;
  953. }
  954. switch (usb_pipetype(urb->pipe)) {
  955. case PIPE_CONTROL:
  956. ret = uhci_submit_control(uhci, urb, eurb);
  957. break;
  958. case PIPE_INTERRUPT:
  959. if (!eurb) {
  960. bustime = usb_check_bandwidth(urb->dev, urb);
  961. if (bustime < 0)
  962. ret = bustime;
  963. else {
  964. ret = uhci_submit_interrupt(uhci, urb, eurb);
  965. if (ret == -EINPROGRESS)
  966. usb_claim_bandwidth(urb->dev, urb, bustime, 0);
  967. }
  968. } else { /* inherit from parent */
  969. urb->bandwidth = eurb->bandwidth;
  970. ret = uhci_submit_interrupt(uhci, urb, eurb);
  971. }
  972. break;
  973. case PIPE_BULK:
  974. ret = uhci_submit_bulk(uhci, urb, eurb);
  975. break;
  976. case PIPE_ISOCHRONOUS:
  977. bustime = usb_check_bandwidth(urb->dev, urb);
  978. if (bustime < 0) {
  979. ret = bustime;
  980. break;
  981. }
  982. ret = uhci_submit_isochronous(uhci, urb);
  983. if (ret == -EINPROGRESS)
  984. usb_claim_bandwidth(urb->dev, urb, bustime, 1);
  985. break;
  986. }
  987. if (ret != -EINPROGRESS) {
  988. /* Submit failed, so delete it from the urb_list */
  989. struct urb_priv *urbp = urb->hcpriv;
  990. list_del_init(&urbp->urb_list);
  991. uhci_destroy_urb_priv(uhci, urb);
  992. } else
  993. ret = 0;
  994. out:
  995. spin_unlock_irqrestore(&uhci->lock, flags);
  996. return ret;
  997. }
  998. /*
  999. * Return the result of a transfer
  1000. */
  1001. static void uhci_transfer_result(struct uhci_hcd *uhci, struct urb *urb)
  1002. {
  1003. int ret = -EINPROGRESS;
  1004. struct urb_priv *urbp;
  1005. spin_lock(&urb->lock);
  1006. urbp = (struct urb_priv *)urb->hcpriv;
  1007. if (urb->status != -EINPROGRESS) /* URB already dequeued */
  1008. goto out;
  1009. switch (usb_pipetype(urb->pipe)) {
  1010. case PIPE_CONTROL:
  1011. ret = uhci_result_control(uhci, urb);
  1012. break;
  1013. case PIPE_BULK:
  1014. case PIPE_INTERRUPT:
  1015. ret = uhci_result_common(uhci, urb);
  1016. break;
  1017. case PIPE_ISOCHRONOUS:
  1018. ret = uhci_result_isochronous(uhci, urb);
  1019. break;
  1020. }
  1021. if (ret == -EINPROGRESS)
  1022. goto out;
  1023. urb->status = ret;
  1024. switch (usb_pipetype(urb->pipe)) {
  1025. case PIPE_CONTROL:
  1026. case PIPE_BULK:
  1027. case PIPE_ISOCHRONOUS:
  1028. /* Release bandwidth for Interrupt or Isoc. transfers */
  1029. if (urb->bandwidth)
  1030. usb_release_bandwidth(urb->dev, urb, 1);
  1031. uhci_unlink_generic(uhci, urb);
  1032. break;
  1033. case PIPE_INTERRUPT:
  1034. /* Release bandwidth for Interrupt or Isoc. transfers */
  1035. /* Make sure we don't release if we have a queued URB */
  1036. if (list_empty(&urbp->queue_list) && urb->bandwidth)
  1037. usb_release_bandwidth(urb->dev, urb, 0);
  1038. else
  1039. /* bandwidth was passed on to queued URB, */
  1040. /* so don't let usb_unlink_urb() release it */
  1041. urb->bandwidth = 0;
  1042. uhci_unlink_generic(uhci, urb);
  1043. break;
  1044. default:
  1045. dev_info(uhci_dev(uhci), "%s: unknown pipe type %d "
  1046. "for urb %p\n",
  1047. __FUNCTION__, usb_pipetype(urb->pipe), urb);
  1048. }
  1049. /* Move it from uhci->urb_list to uhci->complete_list */
  1050. uhci_moveto_complete(uhci, urbp);
  1051. out:
  1052. spin_unlock(&urb->lock);
  1053. }
  1054. static void uhci_unlink_generic(struct uhci_hcd *uhci, struct urb *urb)
  1055. {
  1056. struct list_head *head;
  1057. struct uhci_td *td;
  1058. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  1059. int prevactive = 0;
  1060. uhci_dec_fsbr(uhci, urb); /* Safe since it checks */
  1061. /*
  1062. * Now we need to find out what the last successful toggle was
  1063. * so we can update the local data toggle for the next transfer
  1064. *
  1065. * There are 2 ways the last successful completed TD is found:
  1066. *
  1067. * 1) The TD is NOT active and the actual length < expected length
  1068. * 2) The TD is NOT active and it's the last TD in the chain
  1069. *
  1070. * and a third way the first uncompleted TD is found:
  1071. *
  1072. * 3) The TD is active and the previous TD is NOT active
  1073. *
  1074. * Control and Isochronous ignore the toggle, so this is safe
  1075. * for all types
  1076. *
  1077. * FIXME: The toggle fixups won't be 100% reliable until we
  1078. * change over to using a single queue for each endpoint and
  1079. * stop the queue before unlinking.
  1080. */
  1081. head = &urbp->td_list;
  1082. list_for_each_entry(td, head, list) {
  1083. unsigned int ctrlstat = td_status(td);
  1084. if (!(ctrlstat & TD_CTRL_ACTIVE) &&
  1085. (uhci_actual_length(ctrlstat) <
  1086. uhci_expected_length(td_token(td)) ||
  1087. td->list.next == head))
  1088. usb_settoggle(urb->dev, uhci_endpoint(td_token(td)),
  1089. uhci_packetout(td_token(td)),
  1090. uhci_toggle(td_token(td)) ^ 1);
  1091. else if ((ctrlstat & TD_CTRL_ACTIVE) && !prevactive)
  1092. usb_settoggle(urb->dev, uhci_endpoint(td_token(td)),
  1093. uhci_packetout(td_token(td)),
  1094. uhci_toggle(td_token(td)));
  1095. prevactive = ctrlstat & TD_CTRL_ACTIVE;
  1096. }
  1097. uhci_delete_queued_urb(uhci, urb);
  1098. /* The interrupt loop will reclaim the QH's */
  1099. uhci_remove_qh(uhci, urbp->qh);
  1100. urbp->qh = NULL;
  1101. }
  1102. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
  1103. {
  1104. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1105. unsigned long flags;
  1106. struct urb_priv *urbp;
  1107. spin_lock_irqsave(&uhci->lock, flags);
  1108. urbp = urb->hcpriv;
  1109. if (!urbp) /* URB was never linked! */
  1110. goto done;
  1111. list_del_init(&urbp->urb_list);
  1112. uhci_unlink_generic(uhci, urb);
  1113. uhci_get_current_frame_number(uhci);
  1114. if (uhci->frame_number + uhci->is_stopped != uhci->urb_remove_age) {
  1115. uhci_remove_pending_urbps(uhci);
  1116. uhci->urb_remove_age = uhci->frame_number;
  1117. }
  1118. /* If we're the first, set the next interrupt bit */
  1119. if (list_empty(&uhci->urb_remove_list))
  1120. uhci_set_next_interrupt(uhci);
  1121. list_add_tail(&urbp->urb_list, &uhci->urb_remove_list);
  1122. done:
  1123. spin_unlock_irqrestore(&uhci->lock, flags);
  1124. return 0;
  1125. }
  1126. static int uhci_fsbr_timeout(struct uhci_hcd *uhci, struct urb *urb)
  1127. {
  1128. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  1129. struct list_head *head;
  1130. struct uhci_td *td;
  1131. int count = 0;
  1132. uhci_dec_fsbr(uhci, urb);
  1133. urbp->fsbr_timeout = 1;
  1134. /*
  1135. * Ideally we would want to fix qh->element as well, but it's
  1136. * read/write by the HC, so that can introduce a race. It's not
  1137. * really worth the hassle
  1138. */
  1139. head = &urbp->td_list;
  1140. list_for_each_entry(td, head, list) {
  1141. /*
  1142. * Make sure we don't do the last one (since it'll have the
  1143. * TERM bit set) as well as we skip every so many TD's to
  1144. * make sure it doesn't hog the bandwidth
  1145. */
  1146. if (td->list.next != head && (count % DEPTH_INTERVAL) ==
  1147. (DEPTH_INTERVAL - 1))
  1148. td->link |= UHCI_PTR_DEPTH;
  1149. count++;
  1150. }
  1151. return 0;
  1152. }
  1153. static void uhci_free_pending_qhs(struct uhci_hcd *uhci)
  1154. {
  1155. struct uhci_qh *qh, *tmp;
  1156. list_for_each_entry_safe(qh, tmp, &uhci->qh_remove_list, remove_list) {
  1157. list_del_init(&qh->remove_list);
  1158. uhci_free_qh(uhci, qh);
  1159. }
  1160. }
  1161. static void uhci_free_pending_tds(struct uhci_hcd *uhci)
  1162. {
  1163. struct uhci_td *td, *tmp;
  1164. list_for_each_entry_safe(td, tmp, &uhci->td_remove_list, remove_list) {
  1165. list_del_init(&td->remove_list);
  1166. uhci_free_td(uhci, td);
  1167. }
  1168. }
  1169. static void
  1170. uhci_finish_urb(struct usb_hcd *hcd, struct urb *urb, struct pt_regs *regs)
  1171. __releases(uhci->lock)
  1172. __acquires(uhci->lock)
  1173. {
  1174. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1175. uhci_destroy_urb_priv(uhci, urb);
  1176. spin_unlock(&uhci->lock);
  1177. usb_hcd_giveback_urb(hcd, urb, regs);
  1178. spin_lock(&uhci->lock);
  1179. }
  1180. static void uhci_finish_completion(struct uhci_hcd *uhci, struct pt_regs *regs)
  1181. {
  1182. struct urb_priv *urbp, *tmp;
  1183. list_for_each_entry_safe(urbp, tmp, &uhci->complete_list, urb_list) {
  1184. struct urb *urb = urbp->urb;
  1185. list_del_init(&urbp->urb_list);
  1186. uhci_finish_urb(uhci_to_hcd(uhci), urb, regs);
  1187. }
  1188. }
  1189. static void uhci_remove_pending_urbps(struct uhci_hcd *uhci)
  1190. {
  1191. /* Splice the urb_remove_list onto the end of the complete_list */
  1192. list_splice_init(&uhci->urb_remove_list, uhci->complete_list.prev);
  1193. }
  1194. /* Process events in the schedule, but only in one thread at a time */
  1195. static void uhci_scan_schedule(struct uhci_hcd *uhci, struct pt_regs *regs)
  1196. {
  1197. struct urb_priv *urbp, *tmp;
  1198. /* Don't allow re-entrant calls */
  1199. if (uhci->scan_in_progress) {
  1200. uhci->need_rescan = 1;
  1201. return;
  1202. }
  1203. uhci->scan_in_progress = 1;
  1204. rescan:
  1205. uhci->need_rescan = 0;
  1206. uhci_clear_next_interrupt(uhci);
  1207. uhci_get_current_frame_number(uhci);
  1208. if (uhci->frame_number + uhci->is_stopped != uhci->qh_remove_age)
  1209. uhci_free_pending_qhs(uhci);
  1210. if (uhci->frame_number + uhci->is_stopped != uhci->td_remove_age)
  1211. uhci_free_pending_tds(uhci);
  1212. if (uhci->frame_number + uhci->is_stopped != uhci->urb_remove_age)
  1213. uhci_remove_pending_urbps(uhci);
  1214. /* Walk the list of pending URBs to see which ones completed
  1215. * (must be _safe because uhci_transfer_result() dequeues URBs) */
  1216. list_for_each_entry_safe(urbp, tmp, &uhci->urb_list, urb_list) {
  1217. struct urb *urb = urbp->urb;
  1218. /* Checks the status and does all of the magic necessary */
  1219. uhci_transfer_result(uhci, urb);
  1220. }
  1221. uhci_finish_completion(uhci, regs);
  1222. /* If the controller is stopped, we can finish these off right now */
  1223. if (uhci->is_stopped) {
  1224. uhci_free_pending_qhs(uhci);
  1225. uhci_free_pending_tds(uhci);
  1226. uhci_remove_pending_urbps(uhci);
  1227. }
  1228. if (uhci->need_rescan)
  1229. goto rescan;
  1230. uhci->scan_in_progress = 0;
  1231. if (list_empty(&uhci->urb_remove_list) &&
  1232. list_empty(&uhci->td_remove_list) &&
  1233. list_empty(&uhci->qh_remove_list))
  1234. uhci_clear_next_interrupt(uhci);
  1235. else
  1236. uhci_set_next_interrupt(uhci);
  1237. /* Wake up anyone waiting for an URB to complete */
  1238. wake_up_all(&uhci->waitqh);
  1239. }
  1240. static void check_fsbr(struct uhci_hcd *uhci)
  1241. {
  1242. struct urb_priv *up;
  1243. list_for_each_entry(up, &uhci->urb_list, urb_list) {
  1244. struct urb *u = up->urb;
  1245. spin_lock(&u->lock);
  1246. /* Check if the FSBR timed out */
  1247. if (up->fsbr && !up->fsbr_timeout && time_after_eq(jiffies, up->fsbrtime + IDLE_TIMEOUT))
  1248. uhci_fsbr_timeout(uhci, u);
  1249. spin_unlock(&u->lock);
  1250. }
  1251. /* Really disable FSBR */
  1252. if (!uhci->fsbr && uhci->fsbrtimeout && time_after_eq(jiffies, uhci->fsbrtimeout)) {
  1253. uhci->fsbrtimeout = 0;
  1254. uhci->skel_term_qh->link = UHCI_PTR_TERM;
  1255. }
  1256. }