ehci-mem.c 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236
  1. /*
  2. * Copyright (c) 2001 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* this file is part of ehci-hcd.c */
  19. /*-------------------------------------------------------------------------*/
  20. /*
  21. * There's basically three types of memory:
  22. * - data used only by the HCD ... kmalloc is fine
  23. * - async and periodic schedules, shared by HC and HCD ... these
  24. * need to use dma_pool or dma_alloc_coherent
  25. * - driver buffers, read/written by HC ... single shot DMA mapped
  26. *
  27. * There's also PCI "register" data, which is memory mapped.
  28. * No memory seen by this driver is pageable.
  29. */
  30. /*-------------------------------------------------------------------------*/
  31. /* Allocate the key transfer structures from the previously allocated pool */
  32. static inline void ehci_qtd_init (struct ehci_qtd *qtd, dma_addr_t dma)
  33. {
  34. memset (qtd, 0, sizeof *qtd);
  35. qtd->qtd_dma = dma;
  36. qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
  37. qtd->hw_next = EHCI_LIST_END;
  38. qtd->hw_alt_next = EHCI_LIST_END;
  39. INIT_LIST_HEAD (&qtd->qtd_list);
  40. }
  41. static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, int flags)
  42. {
  43. struct ehci_qtd *qtd;
  44. dma_addr_t dma;
  45. qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
  46. if (qtd != NULL) {
  47. ehci_qtd_init (qtd, dma);
  48. }
  49. return qtd;
  50. }
  51. static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
  52. {
  53. dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
  54. }
  55. static void qh_destroy (struct kref *kref)
  56. {
  57. struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref);
  58. struct ehci_hcd *ehci = qh->ehci;
  59. /* clean qtds first, and know this is not linked */
  60. if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
  61. ehci_dbg (ehci, "unused qh not empty!\n");
  62. BUG ();
  63. }
  64. if (qh->dummy)
  65. ehci_qtd_free (ehci, qh->dummy);
  66. usb_put_dev (qh->dev);
  67. dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
  68. }
  69. static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, int flags)
  70. {
  71. struct ehci_qh *qh;
  72. dma_addr_t dma;
  73. qh = (struct ehci_qh *)
  74. dma_pool_alloc (ehci->qh_pool, flags, &dma);
  75. if (!qh)
  76. return qh;
  77. memset (qh, 0, sizeof *qh);
  78. kref_init(&qh->kref);
  79. qh->ehci = ehci;
  80. qh->qh_dma = dma;
  81. // INIT_LIST_HEAD (&qh->qh_list);
  82. INIT_LIST_HEAD (&qh->qtd_list);
  83. /* dummy td enables safe urb queuing */
  84. qh->dummy = ehci_qtd_alloc (ehci, flags);
  85. if (qh->dummy == NULL) {
  86. ehci_dbg (ehci, "no dummy td\n");
  87. dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
  88. qh = NULL;
  89. }
  90. return qh;
  91. }
  92. /* to share a qh (cpu threads, or hc) */
  93. static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
  94. {
  95. kref_get(&qh->kref);
  96. return qh;
  97. }
  98. static inline void qh_put (struct ehci_qh *qh)
  99. {
  100. kref_put(&qh->kref, qh_destroy);
  101. }
  102. /*-------------------------------------------------------------------------*/
  103. /* The queue heads and transfer descriptors are managed from pools tied
  104. * to each of the "per device" structures.
  105. * This is the initialisation and cleanup code.
  106. */
  107. static void ehci_mem_cleanup (struct ehci_hcd *ehci)
  108. {
  109. if (ehci->async)
  110. qh_put (ehci->async);
  111. ehci->async = NULL;
  112. /* DMA consistent memory and pools */
  113. if (ehci->qtd_pool)
  114. dma_pool_destroy (ehci->qtd_pool);
  115. ehci->qtd_pool = NULL;
  116. if (ehci->qh_pool) {
  117. dma_pool_destroy (ehci->qh_pool);
  118. ehci->qh_pool = NULL;
  119. }
  120. if (ehci->itd_pool)
  121. dma_pool_destroy (ehci->itd_pool);
  122. ehci->itd_pool = NULL;
  123. if (ehci->sitd_pool)
  124. dma_pool_destroy (ehci->sitd_pool);
  125. ehci->sitd_pool = NULL;
  126. if (ehci->periodic)
  127. dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
  128. ehci->periodic_size * sizeof (u32),
  129. ehci->periodic, ehci->periodic_dma);
  130. ehci->periodic = NULL;
  131. /* shadow periodic table */
  132. kfree(ehci->pshadow);
  133. ehci->pshadow = NULL;
  134. }
  135. /* remember to add cleanup code (above) if you add anything here */
  136. static int ehci_mem_init (struct ehci_hcd *ehci, int flags)
  137. {
  138. int i;
  139. /* QTDs for control/bulk/intr transfers */
  140. ehci->qtd_pool = dma_pool_create ("ehci_qtd",
  141. ehci_to_hcd(ehci)->self.controller,
  142. sizeof (struct ehci_qtd),
  143. 32 /* byte alignment (for hw parts) */,
  144. 4096 /* can't cross 4K */);
  145. if (!ehci->qtd_pool) {
  146. goto fail;
  147. }
  148. /* QHs for control/bulk/intr transfers */
  149. ehci->qh_pool = dma_pool_create ("ehci_qh",
  150. ehci_to_hcd(ehci)->self.controller,
  151. sizeof (struct ehci_qh),
  152. 32 /* byte alignment (for hw parts) */,
  153. 4096 /* can't cross 4K */);
  154. if (!ehci->qh_pool) {
  155. goto fail;
  156. }
  157. ehci->async = ehci_qh_alloc (ehci, flags);
  158. if (!ehci->async) {
  159. goto fail;
  160. }
  161. /* ITD for high speed ISO transfers */
  162. ehci->itd_pool = dma_pool_create ("ehci_itd",
  163. ehci_to_hcd(ehci)->self.controller,
  164. sizeof (struct ehci_itd),
  165. 32 /* byte alignment (for hw parts) */,
  166. 4096 /* can't cross 4K */);
  167. if (!ehci->itd_pool) {
  168. goto fail;
  169. }
  170. /* SITD for full/low speed split ISO transfers */
  171. ehci->sitd_pool = dma_pool_create ("ehci_sitd",
  172. ehci_to_hcd(ehci)->self.controller,
  173. sizeof (struct ehci_sitd),
  174. 32 /* byte alignment (for hw parts) */,
  175. 4096 /* can't cross 4K */);
  176. if (!ehci->sitd_pool) {
  177. goto fail;
  178. }
  179. /* Hardware periodic table */
  180. ehci->periodic = (__le32 *)
  181. dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
  182. ehci->periodic_size * sizeof(__le32),
  183. &ehci->periodic_dma, 0);
  184. if (ehci->periodic == NULL) {
  185. goto fail;
  186. }
  187. for (i = 0; i < ehci->periodic_size; i++)
  188. ehci->periodic [i] = EHCI_LIST_END;
  189. /* software shadow of hardware table */
  190. ehci->pshadow = kmalloc (ehci->periodic_size * sizeof (void *), flags);
  191. if (ehci->pshadow == NULL) {
  192. goto fail;
  193. }
  194. memset (ehci->pshadow, 0, ehci->periodic_size * sizeof (void *));
  195. return 0;
  196. fail:
  197. ehci_dbg (ehci, "couldn't init memory\n");
  198. ehci_mem_cleanup (ehci);
  199. return -ENOMEM;
  200. }