ehci-dbg.c 22 KB

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  1. /*
  2. * Copyright (c) 2001-2002 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* this file is part of ehci-hcd.c */
  19. #define ehci_dbg(ehci, fmt, args...) \
  20. dev_dbg (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
  21. #define ehci_err(ehci, fmt, args...) \
  22. dev_err (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
  23. #define ehci_info(ehci, fmt, args...) \
  24. dev_info (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
  25. #define ehci_warn(ehci, fmt, args...) \
  26. dev_warn (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
  27. #ifdef EHCI_VERBOSE_DEBUG
  28. # define vdbg dbg
  29. # define ehci_vdbg ehci_dbg
  30. #else
  31. # define vdbg(fmt,args...) do { } while (0)
  32. # define ehci_vdbg(ehci, fmt, args...) do { } while (0)
  33. #endif
  34. #ifdef DEBUG
  35. /* check the values in the HCSPARAMS register
  36. * (host controller _Structural_ parameters)
  37. * see EHCI spec, Table 2-4 for each value
  38. */
  39. static void dbg_hcs_params (struct ehci_hcd *ehci, char *label)
  40. {
  41. u32 params = readl (&ehci->caps->hcs_params);
  42. ehci_dbg (ehci,
  43. "%s hcs_params 0x%x dbg=%d%s cc=%d pcc=%d%s%s ports=%d\n",
  44. label, params,
  45. HCS_DEBUG_PORT (params),
  46. HCS_INDICATOR (params) ? " ind" : "",
  47. HCS_N_CC (params),
  48. HCS_N_PCC (params),
  49. HCS_PORTROUTED (params) ? "" : " ordered",
  50. HCS_PPC (params) ? "" : " !ppc",
  51. HCS_N_PORTS (params)
  52. );
  53. /* Port routing, per EHCI 0.95 Spec, Section 2.2.5 */
  54. if (HCS_PORTROUTED (params)) {
  55. int i;
  56. char buf [46], tmp [7], byte;
  57. buf[0] = 0;
  58. for (i = 0; i < HCS_N_PORTS (params); i++) {
  59. // FIXME MIPS won't readb() ...
  60. byte = readb (&ehci->caps->portroute[(i>>1)]);
  61. sprintf(tmp, "%d ",
  62. ((i & 0x1) ? ((byte)&0xf) : ((byte>>4)&0xf)));
  63. strcat(buf, tmp);
  64. }
  65. ehci_dbg (ehci, "%s portroute %s\n",
  66. label, buf);
  67. }
  68. }
  69. #else
  70. static inline void dbg_hcs_params (struct ehci_hcd *ehci, char *label) {}
  71. #endif
  72. #ifdef DEBUG
  73. /* check the values in the HCCPARAMS register
  74. * (host controller _Capability_ parameters)
  75. * see EHCI Spec, Table 2-5 for each value
  76. * */
  77. static void dbg_hcc_params (struct ehci_hcd *ehci, char *label)
  78. {
  79. u32 params = readl (&ehci->caps->hcc_params);
  80. if (HCC_ISOC_CACHE (params)) {
  81. ehci_dbg (ehci,
  82. "%s hcc_params %04x caching frame %s%s%s\n",
  83. label, params,
  84. HCC_PGM_FRAMELISTLEN (params) ? "256/512/1024" : "1024",
  85. HCC_CANPARK (params) ? " park" : "",
  86. HCC_64BIT_ADDR (params) ? " 64 bit addr" : "");
  87. } else {
  88. ehci_dbg (ehci,
  89. "%s hcc_params %04x thresh %d uframes %s%s%s\n",
  90. label,
  91. params,
  92. HCC_ISOC_THRES (params),
  93. HCC_PGM_FRAMELISTLEN (params) ? "256/512/1024" : "1024",
  94. HCC_CANPARK (params) ? " park" : "",
  95. HCC_64BIT_ADDR (params) ? " 64 bit addr" : "");
  96. }
  97. }
  98. #else
  99. static inline void dbg_hcc_params (struct ehci_hcd *ehci, char *label) {}
  100. #endif
  101. #ifdef DEBUG
  102. static void __attribute__((__unused__))
  103. dbg_qtd (const char *label, struct ehci_hcd *ehci, struct ehci_qtd *qtd)
  104. {
  105. ehci_dbg (ehci, "%s td %p n%08x %08x t%08x p0=%08x\n", label, qtd,
  106. le32_to_cpup (&qtd->hw_next),
  107. le32_to_cpup (&qtd->hw_alt_next),
  108. le32_to_cpup (&qtd->hw_token),
  109. le32_to_cpup (&qtd->hw_buf [0]));
  110. if (qtd->hw_buf [1])
  111. ehci_dbg (ehci, " p1=%08x p2=%08x p3=%08x p4=%08x\n",
  112. le32_to_cpup (&qtd->hw_buf [1]),
  113. le32_to_cpup (&qtd->hw_buf [2]),
  114. le32_to_cpup (&qtd->hw_buf [3]),
  115. le32_to_cpup (&qtd->hw_buf [4]));
  116. }
  117. static void __attribute__((__unused__))
  118. dbg_qh (const char *label, struct ehci_hcd *ehci, struct ehci_qh *qh)
  119. {
  120. ehci_dbg (ehci, "%s qh %p n%08x info %x %x qtd %x\n", label,
  121. qh, qh->hw_next, qh->hw_info1, qh->hw_info2,
  122. qh->hw_current);
  123. dbg_qtd ("overlay", ehci, (struct ehci_qtd *) &qh->hw_qtd_next);
  124. }
  125. static void __attribute__((__unused__))
  126. dbg_itd (const char *label, struct ehci_hcd *ehci, struct ehci_itd *itd)
  127. {
  128. ehci_dbg (ehci, "%s [%d] itd %p, next %08x, urb %p\n",
  129. label, itd->frame, itd, le32_to_cpu(itd->hw_next), itd->urb);
  130. ehci_dbg (ehci,
  131. " trans: %08x %08x %08x %08x %08x %08x %08x %08x\n",
  132. le32_to_cpu(itd->hw_transaction[0]),
  133. le32_to_cpu(itd->hw_transaction[1]),
  134. le32_to_cpu(itd->hw_transaction[2]),
  135. le32_to_cpu(itd->hw_transaction[3]),
  136. le32_to_cpu(itd->hw_transaction[4]),
  137. le32_to_cpu(itd->hw_transaction[5]),
  138. le32_to_cpu(itd->hw_transaction[6]),
  139. le32_to_cpu(itd->hw_transaction[7]));
  140. ehci_dbg (ehci,
  141. " buf: %08x %08x %08x %08x %08x %08x %08x\n",
  142. le32_to_cpu(itd->hw_bufp[0]),
  143. le32_to_cpu(itd->hw_bufp[1]),
  144. le32_to_cpu(itd->hw_bufp[2]),
  145. le32_to_cpu(itd->hw_bufp[3]),
  146. le32_to_cpu(itd->hw_bufp[4]),
  147. le32_to_cpu(itd->hw_bufp[5]),
  148. le32_to_cpu(itd->hw_bufp[6]));
  149. ehci_dbg (ehci, " index: %d %d %d %d %d %d %d %d\n",
  150. itd->index[0], itd->index[1], itd->index[2],
  151. itd->index[3], itd->index[4], itd->index[5],
  152. itd->index[6], itd->index[7]);
  153. }
  154. static void __attribute__((__unused__))
  155. dbg_sitd (const char *label, struct ehci_hcd *ehci, struct ehci_sitd *sitd)
  156. {
  157. ehci_dbg (ehci, "%s [%d] sitd %p, next %08x, urb %p\n",
  158. label, sitd->frame, sitd, le32_to_cpu(sitd->hw_next), sitd->urb);
  159. ehci_dbg (ehci,
  160. " addr %08x sched %04x result %08x buf %08x %08x\n",
  161. le32_to_cpu(sitd->hw_fullspeed_ep),
  162. le32_to_cpu(sitd->hw_uframe),
  163. le32_to_cpu(sitd->hw_results),
  164. le32_to_cpu(sitd->hw_buf [0]),
  165. le32_to_cpu(sitd->hw_buf [1]));
  166. }
  167. static int __attribute__((__unused__))
  168. dbg_status_buf (char *buf, unsigned len, const char *label, u32 status)
  169. {
  170. return scnprintf (buf, len,
  171. "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
  172. label, label [0] ? " " : "", status,
  173. (status & STS_ASS) ? " Async" : "",
  174. (status & STS_PSS) ? " Periodic" : "",
  175. (status & STS_RECL) ? " Recl" : "",
  176. (status & STS_HALT) ? " Halt" : "",
  177. (status & STS_IAA) ? " IAA" : "",
  178. (status & STS_FATAL) ? " FATAL" : "",
  179. (status & STS_FLR) ? " FLR" : "",
  180. (status & STS_PCD) ? " PCD" : "",
  181. (status & STS_ERR) ? " ERR" : "",
  182. (status & STS_INT) ? " INT" : ""
  183. );
  184. }
  185. static int __attribute__((__unused__))
  186. dbg_intr_buf (char *buf, unsigned len, const char *label, u32 enable)
  187. {
  188. return scnprintf (buf, len,
  189. "%s%sintrenable %02x%s%s%s%s%s%s",
  190. label, label [0] ? " " : "", enable,
  191. (enable & STS_IAA) ? " IAA" : "",
  192. (enable & STS_FATAL) ? " FATAL" : "",
  193. (enable & STS_FLR) ? " FLR" : "",
  194. (enable & STS_PCD) ? " PCD" : "",
  195. (enable & STS_ERR) ? " ERR" : "",
  196. (enable & STS_INT) ? " INT" : ""
  197. );
  198. }
  199. static const char *const fls_strings [] =
  200. { "1024", "512", "256", "??" };
  201. static int
  202. dbg_command_buf (char *buf, unsigned len, const char *label, u32 command)
  203. {
  204. return scnprintf (buf, len,
  205. "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
  206. label, label [0] ? " " : "", command,
  207. (command & CMD_PARK) ? "park" : "(park)",
  208. CMD_PARK_CNT (command),
  209. (command >> 16) & 0x3f,
  210. (command & CMD_LRESET) ? " LReset" : "",
  211. (command & CMD_IAAD) ? " IAAD" : "",
  212. (command & CMD_ASE) ? " Async" : "",
  213. (command & CMD_PSE) ? " Periodic" : "",
  214. fls_strings [(command >> 2) & 0x3],
  215. (command & CMD_RESET) ? " Reset" : "",
  216. (command & CMD_RUN) ? "RUN" : "HALT"
  217. );
  218. }
  219. static int
  220. dbg_port_buf (char *buf, unsigned len, const char *label, int port, u32 status)
  221. {
  222. char *sig;
  223. /* signaling state */
  224. switch (status & (3 << 10)) {
  225. case 0 << 10: sig = "se0"; break;
  226. case 1 << 10: sig = "k"; break; /* low speed */
  227. case 2 << 10: sig = "j"; break;
  228. default: sig = "?"; break;
  229. }
  230. return scnprintf (buf, len,
  231. "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
  232. label, label [0] ? " " : "", port, status,
  233. (status & PORT_POWER) ? " POWER" : "",
  234. (status & PORT_OWNER) ? " OWNER" : "",
  235. sig,
  236. (status & PORT_RESET) ? " RESET" : "",
  237. (status & PORT_SUSPEND) ? " SUSPEND" : "",
  238. (status & PORT_RESUME) ? " RESUME" : "",
  239. (status & PORT_OCC) ? " OCC" : "",
  240. (status & PORT_OC) ? " OC" : "",
  241. (status & PORT_PEC) ? " PEC" : "",
  242. (status & PORT_PE) ? " PE" : "",
  243. (status & PORT_CSC) ? " CSC" : "",
  244. (status & PORT_CONNECT) ? " CONNECT" : ""
  245. );
  246. }
  247. #else
  248. static inline void __attribute__((__unused__))
  249. dbg_qh (char *label, struct ehci_hcd *ehci, struct ehci_qh *qh)
  250. {}
  251. static inline int __attribute__((__unused__))
  252. dbg_status_buf (char *buf, unsigned len, const char *label, u32 status)
  253. { return 0; }
  254. static inline int __attribute__((__unused__))
  255. dbg_command_buf (char *buf, unsigned len, const char *label, u32 command)
  256. { return 0; }
  257. static inline int __attribute__((__unused__))
  258. dbg_intr_buf (char *buf, unsigned len, const char *label, u32 enable)
  259. { return 0; }
  260. static inline int __attribute__((__unused__))
  261. dbg_port_buf (char *buf, unsigned len, const char *label, int port, u32 status)
  262. { return 0; }
  263. #endif /* DEBUG */
  264. /* functions have the "wrong" filename when they're output... */
  265. #define dbg_status(ehci, label, status) { \
  266. char _buf [80]; \
  267. dbg_status_buf (_buf, sizeof _buf, label, status); \
  268. ehci_dbg (ehci, "%s\n", _buf); \
  269. }
  270. #define dbg_cmd(ehci, label, command) { \
  271. char _buf [80]; \
  272. dbg_command_buf (_buf, sizeof _buf, label, command); \
  273. ehci_dbg (ehci, "%s\n", _buf); \
  274. }
  275. #define dbg_port(ehci, label, port, status) { \
  276. char _buf [80]; \
  277. dbg_port_buf (_buf, sizeof _buf, label, port, status); \
  278. ehci_dbg (ehci, "%s\n", _buf); \
  279. }
  280. /*-------------------------------------------------------------------------*/
  281. #ifdef STUB_DEBUG_FILES
  282. static inline void create_debug_files (struct ehci_hcd *bus) { }
  283. static inline void remove_debug_files (struct ehci_hcd *bus) { }
  284. #else
  285. /* troubleshooting help: expose state in driverfs */
  286. #define speed_char(info1) ({ char tmp; \
  287. switch (info1 & (3 << 12)) { \
  288. case 0 << 12: tmp = 'f'; break; \
  289. case 1 << 12: tmp = 'l'; break; \
  290. case 2 << 12: tmp = 'h'; break; \
  291. default: tmp = '?'; break; \
  292. }; tmp; })
  293. static inline char token_mark (__le32 token)
  294. {
  295. __u32 v = le32_to_cpu (token);
  296. if (v & QTD_STS_ACTIVE)
  297. return '*';
  298. if (v & QTD_STS_HALT)
  299. return '-';
  300. if (!IS_SHORT_READ (v))
  301. return ' ';
  302. /* tries to advance through hw_alt_next */
  303. return '/';
  304. }
  305. static void qh_lines (
  306. struct ehci_hcd *ehci,
  307. struct ehci_qh *qh,
  308. char **nextp,
  309. unsigned *sizep
  310. )
  311. {
  312. u32 scratch;
  313. u32 hw_curr;
  314. struct list_head *entry;
  315. struct ehci_qtd *td;
  316. unsigned temp;
  317. unsigned size = *sizep;
  318. char *next = *nextp;
  319. char mark;
  320. if (qh->hw_qtd_next == EHCI_LIST_END) /* NEC does this */
  321. mark = '@';
  322. else
  323. mark = token_mark (qh->hw_token);
  324. if (mark == '/') { /* qh_alt_next controls qh advance? */
  325. if ((qh->hw_alt_next & QTD_MASK) == ehci->async->hw_alt_next)
  326. mark = '#'; /* blocked */
  327. else if (qh->hw_alt_next == EHCI_LIST_END)
  328. mark = '.'; /* use hw_qtd_next */
  329. /* else alt_next points to some other qtd */
  330. }
  331. scratch = le32_to_cpup (&qh->hw_info1);
  332. hw_curr = (mark == '*') ? le32_to_cpup (&qh->hw_current) : 0;
  333. temp = scnprintf (next, size,
  334. "qh/%p dev%d %cs ep%d %08x %08x (%08x%c %s nak%d)",
  335. qh, scratch & 0x007f,
  336. speed_char (scratch),
  337. (scratch >> 8) & 0x000f,
  338. scratch, le32_to_cpup (&qh->hw_info2),
  339. le32_to_cpup (&qh->hw_token), mark,
  340. (__constant_cpu_to_le32 (QTD_TOGGLE) & qh->hw_token)
  341. ? "data1" : "data0",
  342. (le32_to_cpup (&qh->hw_alt_next) >> 1) & 0x0f);
  343. size -= temp;
  344. next += temp;
  345. /* hc may be modifying the list as we read it ... */
  346. list_for_each (entry, &qh->qtd_list) {
  347. td = list_entry (entry, struct ehci_qtd, qtd_list);
  348. scratch = le32_to_cpup (&td->hw_token);
  349. mark = ' ';
  350. if (hw_curr == td->qtd_dma)
  351. mark = '*';
  352. else if (qh->hw_qtd_next == cpu_to_le32(td->qtd_dma))
  353. mark = '+';
  354. else if (QTD_LENGTH (scratch)) {
  355. if (td->hw_alt_next == ehci->async->hw_alt_next)
  356. mark = '#';
  357. else if (td->hw_alt_next != EHCI_LIST_END)
  358. mark = '/';
  359. }
  360. temp = snprintf (next, size,
  361. "\n\t%p%c%s len=%d %08x urb %p",
  362. td, mark, ({ char *tmp;
  363. switch ((scratch>>8)&0x03) {
  364. case 0: tmp = "out"; break;
  365. case 1: tmp = "in"; break;
  366. case 2: tmp = "setup"; break;
  367. default: tmp = "?"; break;
  368. } tmp;}),
  369. (scratch >> 16) & 0x7fff,
  370. scratch,
  371. td->urb);
  372. if (temp < 0)
  373. temp = 0;
  374. else if (size < temp)
  375. temp = size;
  376. size -= temp;
  377. next += temp;
  378. if (temp == size)
  379. goto done;
  380. }
  381. temp = snprintf (next, size, "\n");
  382. if (temp < 0)
  383. temp = 0;
  384. else if (size < temp)
  385. temp = size;
  386. size -= temp;
  387. next += temp;
  388. done:
  389. *sizep = size;
  390. *nextp = next;
  391. }
  392. static ssize_t
  393. show_async (struct class_device *class_dev, char *buf)
  394. {
  395. struct usb_bus *bus;
  396. struct usb_hcd *hcd;
  397. struct ehci_hcd *ehci;
  398. unsigned long flags;
  399. unsigned temp, size;
  400. char *next;
  401. struct ehci_qh *qh;
  402. *buf = 0;
  403. bus = class_get_devdata(class_dev);
  404. hcd = bus->hcpriv;
  405. ehci = hcd_to_ehci (hcd);
  406. next = buf;
  407. size = PAGE_SIZE;
  408. /* dumps a snapshot of the async schedule.
  409. * usually empty except for long-term bulk reads, or head.
  410. * one QH per line, and TDs we know about
  411. */
  412. spin_lock_irqsave (&ehci->lock, flags);
  413. for (qh = ehci->async->qh_next.qh; size > 0 && qh; qh = qh->qh_next.qh)
  414. qh_lines (ehci, qh, &next, &size);
  415. if (ehci->reclaim && size > 0) {
  416. temp = scnprintf (next, size, "\nreclaim =\n");
  417. size -= temp;
  418. next += temp;
  419. for (qh = ehci->reclaim; size > 0 && qh; qh = qh->reclaim)
  420. qh_lines (ehci, qh, &next, &size);
  421. }
  422. spin_unlock_irqrestore (&ehci->lock, flags);
  423. return strlen (buf);
  424. }
  425. static CLASS_DEVICE_ATTR (async, S_IRUGO, show_async, NULL);
  426. #define DBG_SCHED_LIMIT 64
  427. static ssize_t
  428. show_periodic (struct class_device *class_dev, char *buf)
  429. {
  430. struct usb_bus *bus;
  431. struct usb_hcd *hcd;
  432. struct ehci_hcd *ehci;
  433. unsigned long flags;
  434. union ehci_shadow p, *seen;
  435. unsigned temp, size, seen_count;
  436. char *next;
  437. unsigned i;
  438. __le32 tag;
  439. if (!(seen = kmalloc (DBG_SCHED_LIMIT * sizeof *seen, SLAB_ATOMIC)))
  440. return 0;
  441. seen_count = 0;
  442. bus = class_get_devdata(class_dev);
  443. hcd = bus->hcpriv;
  444. ehci = hcd_to_ehci (hcd);
  445. next = buf;
  446. size = PAGE_SIZE;
  447. temp = scnprintf (next, size, "size = %d\n", ehci->periodic_size);
  448. size -= temp;
  449. next += temp;
  450. /* dump a snapshot of the periodic schedule.
  451. * iso changes, interrupt usually doesn't.
  452. */
  453. spin_lock_irqsave (&ehci->lock, flags);
  454. for (i = 0; i < ehci->periodic_size; i++) {
  455. p = ehci->pshadow [i];
  456. if (likely (!p.ptr))
  457. continue;
  458. tag = Q_NEXT_TYPE (ehci->periodic [i]);
  459. temp = scnprintf (next, size, "%4d: ", i);
  460. size -= temp;
  461. next += temp;
  462. do {
  463. switch (tag) {
  464. case Q_TYPE_QH:
  465. temp = scnprintf (next, size, " qh%d-%04x/%p",
  466. p.qh->period,
  467. le32_to_cpup (&p.qh->hw_info2)
  468. /* uframe masks */
  469. & (QH_CMASK | QH_SMASK),
  470. p.qh);
  471. size -= temp;
  472. next += temp;
  473. /* don't repeat what follows this qh */
  474. for (temp = 0; temp < seen_count; temp++) {
  475. if (seen [temp].ptr != p.ptr)
  476. continue;
  477. if (p.qh->qh_next.ptr)
  478. temp = scnprintf (next, size,
  479. " ...");
  480. p.ptr = NULL;
  481. break;
  482. }
  483. /* show more info the first time around */
  484. if (temp == seen_count && p.ptr) {
  485. u32 scratch = le32_to_cpup (
  486. &p.qh->hw_info1);
  487. struct ehci_qtd *qtd;
  488. char *type = "";
  489. /* count tds, get ep direction */
  490. temp = 0;
  491. list_for_each_entry (qtd,
  492. &p.qh->qtd_list,
  493. qtd_list) {
  494. temp++;
  495. switch (0x03 & (le32_to_cpu (
  496. qtd->hw_token) >> 8)) {
  497. case 0: type = "out"; continue;
  498. case 1: type = "in"; continue;
  499. }
  500. }
  501. temp = scnprintf (next, size,
  502. " (%c%d ep%d%s "
  503. "[%d/%d] q%d p%d)",
  504. speed_char (scratch),
  505. scratch & 0x007f,
  506. (scratch >> 8) & 0x000f, type,
  507. p.qh->usecs, p.qh->c_usecs,
  508. temp,
  509. 0x7ff & (scratch >> 16));
  510. if (seen_count < DBG_SCHED_LIMIT)
  511. seen [seen_count++].qh = p.qh;
  512. } else
  513. temp = 0;
  514. if (p.qh) {
  515. tag = Q_NEXT_TYPE (p.qh->hw_next);
  516. p = p.qh->qh_next;
  517. }
  518. break;
  519. case Q_TYPE_FSTN:
  520. temp = scnprintf (next, size,
  521. " fstn-%8x/%p", p.fstn->hw_prev,
  522. p.fstn);
  523. tag = Q_NEXT_TYPE (p.fstn->hw_next);
  524. p = p.fstn->fstn_next;
  525. break;
  526. case Q_TYPE_ITD:
  527. temp = scnprintf (next, size,
  528. " itd/%p", p.itd);
  529. tag = Q_NEXT_TYPE (p.itd->hw_next);
  530. p = p.itd->itd_next;
  531. break;
  532. case Q_TYPE_SITD:
  533. temp = scnprintf (next, size,
  534. " sitd%d-%04x/%p",
  535. p.sitd->stream->interval,
  536. le32_to_cpup (&p.sitd->hw_uframe)
  537. & 0x0000ffff,
  538. p.sitd);
  539. tag = Q_NEXT_TYPE (p.sitd->hw_next);
  540. p = p.sitd->sitd_next;
  541. break;
  542. }
  543. size -= temp;
  544. next += temp;
  545. } while (p.ptr);
  546. temp = scnprintf (next, size, "\n");
  547. size -= temp;
  548. next += temp;
  549. }
  550. spin_unlock_irqrestore (&ehci->lock, flags);
  551. kfree (seen);
  552. return PAGE_SIZE - size;
  553. }
  554. static CLASS_DEVICE_ATTR (periodic, S_IRUGO, show_periodic, NULL);
  555. #undef DBG_SCHED_LIMIT
  556. static ssize_t
  557. show_registers (struct class_device *class_dev, char *buf)
  558. {
  559. struct usb_bus *bus;
  560. struct usb_hcd *hcd;
  561. struct ehci_hcd *ehci;
  562. unsigned long flags;
  563. unsigned temp, size, i;
  564. char *next, scratch [80];
  565. static char fmt [] = "%*s\n";
  566. static char label [] = "";
  567. bus = class_get_devdata(class_dev);
  568. hcd = bus->hcpriv;
  569. ehci = hcd_to_ehci (hcd);
  570. next = buf;
  571. size = PAGE_SIZE;
  572. spin_lock_irqsave (&ehci->lock, flags);
  573. if (bus->controller->power.power_state.event) {
  574. size = scnprintf (next, size,
  575. "bus %s, device %s (driver " DRIVER_VERSION ")\n"
  576. "%s\n"
  577. "SUSPENDED (no register access)\n",
  578. hcd->self.controller->bus->name,
  579. hcd->self.controller->bus_id,
  580. hcd->product_desc);
  581. goto done;
  582. }
  583. /* Capability Registers */
  584. i = HC_VERSION(readl (&ehci->caps->hc_capbase));
  585. temp = scnprintf (next, size,
  586. "bus %s, device %s (driver " DRIVER_VERSION ")\n"
  587. "%s\n"
  588. "EHCI %x.%02x, hcd state %d\n",
  589. hcd->self.controller->bus->name,
  590. hcd->self.controller->bus_id,
  591. hcd->product_desc,
  592. i >> 8, i & 0x0ff, hcd->state);
  593. size -= temp;
  594. next += temp;
  595. #ifdef CONFIG_PCI
  596. /* EHCI 0.96 and later may have "extended capabilities" */
  597. if (hcd->self.controller->bus == &pci_bus_type) {
  598. struct pci_dev *pdev;
  599. u32 offset, cap, cap2;
  600. unsigned count = 256/4;
  601. pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
  602. offset = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
  603. while (offset && count--) {
  604. pci_read_config_dword (pdev, offset, &cap);
  605. switch (cap & 0xff) {
  606. case 1:
  607. temp = scnprintf (next, size,
  608. "ownership %08x%s%s\n", cap,
  609. (cap & (1 << 24)) ? " linux" : "",
  610. (cap & (1 << 16)) ? " firmware" : "");
  611. size -= temp;
  612. next += temp;
  613. offset += 4;
  614. pci_read_config_dword (pdev, offset, &cap2);
  615. temp = scnprintf (next, size,
  616. "SMI sts/enable 0x%08x\n", cap2);
  617. size -= temp;
  618. next += temp;
  619. break;
  620. case 0: /* illegal reserved capability */
  621. cap = 0;
  622. /* FALLTHROUGH */
  623. default: /* unknown */
  624. break;
  625. }
  626. temp = (cap >> 8) & 0xff;
  627. }
  628. }
  629. #endif
  630. // FIXME interpret both types of params
  631. i = readl (&ehci->caps->hcs_params);
  632. temp = scnprintf (next, size, "structural params 0x%08x\n", i);
  633. size -= temp;
  634. next += temp;
  635. i = readl (&ehci->caps->hcc_params);
  636. temp = scnprintf (next, size, "capability params 0x%08x\n", i);
  637. size -= temp;
  638. next += temp;
  639. /* Operational Registers */
  640. temp = dbg_status_buf (scratch, sizeof scratch, label,
  641. readl (&ehci->regs->status));
  642. temp = scnprintf (next, size, fmt, temp, scratch);
  643. size -= temp;
  644. next += temp;
  645. temp = dbg_command_buf (scratch, sizeof scratch, label,
  646. readl (&ehci->regs->command));
  647. temp = scnprintf (next, size, fmt, temp, scratch);
  648. size -= temp;
  649. next += temp;
  650. temp = dbg_intr_buf (scratch, sizeof scratch, label,
  651. readl (&ehci->regs->intr_enable));
  652. temp = scnprintf (next, size, fmt, temp, scratch);
  653. size -= temp;
  654. next += temp;
  655. temp = scnprintf (next, size, "uframe %04x\n",
  656. readl (&ehci->regs->frame_index));
  657. size -= temp;
  658. next += temp;
  659. for (i = 1; i <= HCS_N_PORTS (ehci->hcs_params); i++) {
  660. temp = dbg_port_buf (scratch, sizeof scratch, label, i,
  661. readl (&ehci->regs->port_status [i - 1]));
  662. temp = scnprintf (next, size, fmt, temp, scratch);
  663. size -= temp;
  664. next += temp;
  665. if (i == HCS_DEBUG_PORT(ehci->hcs_params) && ehci->debug) {
  666. temp = scnprintf (next, size,
  667. " debug control %08x\n",
  668. readl (&ehci->debug->control));
  669. size -= temp;
  670. next += temp;
  671. }
  672. }
  673. if (ehci->reclaim) {
  674. temp = scnprintf (next, size, "reclaim qh %p%s\n",
  675. ehci->reclaim,
  676. ehci->reclaim_ready ? " ready" : "");
  677. size -= temp;
  678. next += temp;
  679. }
  680. #ifdef EHCI_STATS
  681. temp = scnprintf (next, size,
  682. "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
  683. ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
  684. ehci->stats.lost_iaa);
  685. size -= temp;
  686. next += temp;
  687. temp = scnprintf (next, size, "complete %ld unlink %ld\n",
  688. ehci->stats.complete, ehci->stats.unlink);
  689. size -= temp;
  690. next += temp;
  691. #endif
  692. done:
  693. spin_unlock_irqrestore (&ehci->lock, flags);
  694. return PAGE_SIZE - size;
  695. }
  696. static CLASS_DEVICE_ATTR (registers, S_IRUGO, show_registers, NULL);
  697. static inline void create_debug_files (struct ehci_hcd *ehci)
  698. {
  699. struct class_device *cldev = ehci_to_hcd(ehci)->self.class_dev;
  700. class_device_create_file(cldev, &class_device_attr_async);
  701. class_device_create_file(cldev, &class_device_attr_periodic);
  702. class_device_create_file(cldev, &class_device_attr_registers);
  703. }
  704. static inline void remove_debug_files (struct ehci_hcd *ehci)
  705. {
  706. struct class_device *cldev = ehci_to_hcd(ehci)->self.class_dev;
  707. class_device_remove_file(cldev, &class_device_attr_async);
  708. class_device_remove_file(cldev, &class_device_attr_periodic);
  709. class_device_remove_file(cldev, &class_device_attr_registers);
  710. }
  711. #endif /* STUB_DEBUG_FILES */