omap_udc.h 6.6 KB

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  1. /*
  2. * omap_udc.h -- for omap 3.2 udc, with OTG support
  3. *
  4. * 2004 (C) Texas Instruments, Inc.
  5. * 2004 (C) David Brownell
  6. */
  7. /*
  8. * USB device/endpoint management registers
  9. */
  10. #define UDC_REG(offset) __REG16(UDC_BASE + (offset))
  11. #define UDC_REV_REG UDC_REG(0x0) /* Revision */
  12. #define UDC_EP_NUM_REG UDC_REG(0x4) /* Which endpoint */
  13. # define UDC_SETUP_SEL (1 << 6)
  14. # define UDC_EP_SEL (1 << 5)
  15. # define UDC_EP_DIR (1 << 4)
  16. /* low 4 bits for endpoint number */
  17. #define UDC_DATA_REG UDC_REG(0x08) /* Endpoint FIFO */
  18. #define UDC_CTRL_REG UDC_REG(0x0C) /* Endpoint control */
  19. # define UDC_CLR_HALT (1 << 7)
  20. # define UDC_SET_HALT (1 << 6)
  21. # define UDC_CLRDATA_TOGGLE (1 << 3)
  22. # define UDC_SET_FIFO_EN (1 << 2)
  23. # define UDC_CLR_EP (1 << 1)
  24. # define UDC_RESET_EP (1 << 0)
  25. #define UDC_STAT_FLG_REG UDC_REG(0x10) /* Endpoint status */
  26. # define UDC_NO_RXPACKET (1 << 15)
  27. # define UDC_MISS_IN (1 << 14)
  28. # define UDC_DATA_FLUSH (1 << 13)
  29. # define UDC_ISO_ERR (1 << 12)
  30. # define UDC_ISO_FIFO_EMPTY (1 << 9)
  31. # define UDC_ISO_FIFO_FULL (1 << 8)
  32. # define UDC_EP_HALTED (1 << 6)
  33. # define UDC_STALL (1 << 5)
  34. # define UDC_NAK (1 << 4)
  35. # define UDC_ACK (1 << 3)
  36. # define UDC_FIFO_EN (1 << 2)
  37. # define UDC_NON_ISO_FIFO_EMPTY (1 << 1)
  38. # define UDC_NON_ISO_FIFO_FULL (1 << 0)
  39. #define UDC_RXFSTAT_REG UDC_REG(0x14) /* OUT bytecount */
  40. #define UDC_SYSCON1_REG UDC_REG(0x18) /* System config 1 */
  41. # define UDC_CFG_LOCK (1 << 8)
  42. # define UDC_DATA_ENDIAN (1 << 7)
  43. # define UDC_DMA_ENDIAN (1 << 6)
  44. # define UDC_NAK_EN (1 << 4)
  45. # define UDC_AUTODECODE_DIS (1 << 3)
  46. # define UDC_SELF_PWR (1 << 2)
  47. # define UDC_SOFF_DIS (1 << 1)
  48. # define UDC_PULLUP_EN (1 << 0)
  49. #define UDC_SYSCON2_REG UDC_REG(0x1C) /* System config 2 */
  50. # define UDC_RMT_WKP (1 << 6)
  51. # define UDC_STALL_CMD (1 << 5)
  52. # define UDC_DEV_CFG (1 << 3)
  53. # define UDC_CLR_CFG (1 << 2)
  54. #define UDC_DEVSTAT_REG UDC_REG(0x20) /* Device status */
  55. # define UDC_B_HNP_ENABLE (1 << 9)
  56. # define UDC_A_HNP_SUPPORT (1 << 8)
  57. # define UDC_A_ALT_HNP_SUPPORT (1 << 7)
  58. # define UDC_R_WK_OK (1 << 6)
  59. # define UDC_USB_RESET (1 << 5)
  60. # define UDC_SUS (1 << 4)
  61. # define UDC_CFG (1 << 3)
  62. # define UDC_ADD (1 << 2)
  63. # define UDC_DEF (1 << 1)
  64. # define UDC_ATT (1 << 0)
  65. #define UDC_SOF_REG UDC_REG(0x24) /* Start of frame */
  66. # define UDC_FT_LOCK (1 << 12)
  67. # define UDC_TS_OK (1 << 11)
  68. # define UDC_TS 0x03ff
  69. #define UDC_IRQ_EN_REG UDC_REG(0x28) /* Interrupt enable */
  70. # define UDC_SOF_IE (1 << 7)
  71. # define UDC_EPN_RX_IE (1 << 5)
  72. # define UDC_EPN_TX_IE (1 << 4)
  73. # define UDC_DS_CHG_IE (1 << 3)
  74. # define UDC_EP0_IE (1 << 0)
  75. #define UDC_DMA_IRQ_EN_REG UDC_REG(0x2C) /* DMA irq enable */
  76. /* rx/tx dma channels numbered 1-3 not 0-2 */
  77. # define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2))
  78. # define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3))
  79. # define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4))
  80. #define UDC_IRQ_SRC_REG UDC_REG(0x30) /* Interrupt source */
  81. # define UDC_TXN_DONE (1 << 10)
  82. # define UDC_RXN_CNT (1 << 9)
  83. # define UDC_RXN_EOT (1 << 8)
  84. # define UDC_SOF (1 << 7)
  85. # define UDC_EPN_RX (1 << 5)
  86. # define UDC_EPN_TX (1 << 4)
  87. # define UDC_DS_CHG (1 << 3)
  88. # define UDC_SETUP (1 << 2)
  89. # define UDC_EP0_RX (1 << 1)
  90. # define UDC_EP0_TX (1 << 0)
  91. # define UDC_IRQ_SRC_MASK 0x7bf
  92. #define UDC_EPN_STAT_REG UDC_REG(0x34) /* EP irq status */
  93. #define UDC_DMAN_STAT_REG UDC_REG(0x38) /* DMA irq status */
  94. # define UDC_DMA_RX_SB (1 << 12)
  95. # define UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf)
  96. # define UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf)
  97. /* DMA configuration registers: up to three channels in each direction. */
  98. #define UDC_RXDMA_CFG_REG UDC_REG(0x40) /* 3 eps for RX DMA */
  99. # define UDC_DMA_REQ (1 << 12)
  100. #define UDC_TXDMA_CFG_REG UDC_REG(0x44) /* 3 eps for TX DMA */
  101. #define UDC_DATA_DMA_REG UDC_REG(0x48) /* rx/tx fifo addr */
  102. /* rx/tx dma control, numbering channels 1-3 not 0-2 */
  103. #define UDC_TXDMA_REG(chan) UDC_REG(0x50 - 4 + 4 * (chan))
  104. # define UDC_TXN_EOT (1 << 15) /* bytes vs packets */
  105. # define UDC_TXN_START (1 << 14) /* start transfer */
  106. # define UDC_TXN_TSC 0x03ff /* units in xfer */
  107. #define UDC_RXDMA_REG(chan) UDC_REG(0x60 - 4 + 4 * (chan))
  108. # define UDC_RXN_STOP (1 << 15) /* enable EOT irq */
  109. # define UDC_RXN_TC 0x00ff /* packets in xfer */
  110. /*
  111. * Endpoint configuration registers (used before CFG_LOCK is set)
  112. * UDC_EP_TX_REG(0) is unused
  113. */
  114. #define UDC_EP_RX_REG(endpoint) UDC_REG(0x80 + (endpoint)*4)
  115. # define UDC_EPN_RX_VALID (1 << 15)
  116. # define UDC_EPN_RX_DB (1 << 14)
  117. /* buffer size in bits 13, 12 */
  118. # define UDC_EPN_RX_ISO (1 << 11)
  119. /* buffer pointer in low 11 bits */
  120. #define UDC_EP_TX_REG(endpoint) UDC_REG(0xc0 + (endpoint)*4)
  121. /* same bitfields as in RX_REG */
  122. /*-------------------------------------------------------------------------*/
  123. struct omap_req {
  124. struct usb_request req;
  125. struct list_head queue;
  126. unsigned dma_bytes;
  127. unsigned mapped:1;
  128. };
  129. struct omap_ep {
  130. struct usb_ep ep;
  131. struct list_head queue;
  132. unsigned long irqs;
  133. struct list_head iso;
  134. const struct usb_endpoint_descriptor *desc;
  135. char name[14];
  136. u16 maxpacket;
  137. u8 bEndpointAddress;
  138. u8 bmAttributes;
  139. unsigned double_buf:1;
  140. unsigned stopped:1;
  141. unsigned fnf:1;
  142. unsigned has_dma:1;
  143. u8 ackwait;
  144. u8 dma_channel;
  145. u16 dma_counter;
  146. int lch;
  147. struct omap_udc *udc;
  148. struct timer_list timer;
  149. };
  150. struct omap_udc {
  151. struct usb_gadget gadget;
  152. struct usb_gadget_driver *driver;
  153. spinlock_t lock;
  154. struct omap_ep ep[32];
  155. u16 devstat;
  156. u16 clr_halt;
  157. struct otg_transceiver *transceiver;
  158. struct list_head iso;
  159. unsigned softconnect:1;
  160. unsigned vbus_active:1;
  161. unsigned ep0_pending:1;
  162. unsigned ep0_in:1;
  163. unsigned ep0_set_config:1;
  164. unsigned ep0_reset_config:1;
  165. unsigned ep0_setup:1;
  166. struct completion *done;
  167. };
  168. /*-------------------------------------------------------------------------*/
  169. #ifdef DEBUG
  170. #define DBG(stuff...) printk(KERN_DEBUG "udc: " stuff)
  171. #else
  172. #define DBG(stuff...) do{}while(0)
  173. #endif
  174. #ifdef VERBOSE
  175. # define VDBG DBG
  176. #else
  177. # define VDBG(stuff...) do{}while(0)
  178. #endif
  179. #define ERR(stuff...) printk(KERN_ERR "udc: " stuff)
  180. #define WARN(stuff...) printk(KERN_WARNING "udc: " stuff)
  181. #define INFO(stuff...) printk(KERN_INFO "udc: " stuff)
  182. /*-------------------------------------------------------------------------*/
  183. #define MOD_CONF_CTRL_0_REG __REG32(MOD_CONF_CTRL_0)
  184. #define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */
  185. #define FUNC_MUX_CTRL_0_REG __REG32(FUNC_MUX_CTRL_0)
  186. #define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */
  187. #define VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */
  188. #define HMC_1510 ((MOD_CONF_CTRL_0_REG >> 1) & 0x3f)
  189. #define HMC_1610 (OTG_SYSCON_2_REG & 0x3f)
  190. #define HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610)