initio.c 94 KB

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  1. /**************************************************************************
  2. * Initio 9100 device driver for Linux.
  3. *
  4. * Copyright (c) 1994-1998 Initio Corporation
  5. * Copyright (c) 1998 Bas Vermeulen <bvermeul@blackstar.xs4all.nl>
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; see the file COPYING. If not, write to
  20. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * --------------------------------------------------------------------------
  23. *
  24. * Redistribution and use in source and binary forms, with or without
  25. * modification, are permitted provided that the following conditions
  26. * are met:
  27. * 1. Redistributions of source code must retain the above copyright
  28. * notice, this list of conditions, and the following disclaimer,
  29. * without modification, immediately at the beginning of the file.
  30. * 2. Redistributions in binary form must reproduce the above copyright
  31. * notice, this list of conditions and the following disclaimer in the
  32. * documentation and/or other materials provided with the distribution.
  33. * 3. The name of the author may not be used to endorse or promote products
  34. * derived from this software without specific prior written permission.
  35. *
  36. * Where this Software is combined with software released under the terms of
  37. * the GNU General Public License ("GPL") and the terms of the GPL would require the
  38. * combined work to also be released under the terms of the GPL, the terms
  39. * and conditions of this License will apply in addition to those of the
  40. * GPL with the exception of any terms or conditions of this License that
  41. * conflict with, or are expressly prohibited by, the GPL.
  42. *
  43. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  44. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  45. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  46. * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  47. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  48. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  49. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  51. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  52. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  53. * SUCH DAMAGE.
  54. *
  55. *************************************************************************
  56. *
  57. * DESCRIPTION:
  58. *
  59. * This is the Linux low-level SCSI driver for Initio INI-9X00U/UW SCSI host
  60. * adapters
  61. *
  62. * 08/06/97 hc - v1.01h
  63. * - Support inic-940 and inic-935
  64. * 09/26/97 hc - v1.01i
  65. * - Make correction from J.W. Schultz suggestion
  66. * 10/13/97 hc - Support reset function
  67. * 10/21/97 hc - v1.01j
  68. * - Support 32 LUN (SCSI 3)
  69. * 01/14/98 hc - v1.01k
  70. * - Fix memory allocation problem
  71. * 03/04/98 hc - v1.01l
  72. * - Fix tape rewind which will hang the system problem
  73. * - Set can_queue to tul_num_scb
  74. * 06/25/98 hc - v1.01m
  75. * - Get it work for kernel version >= 2.1.75
  76. * - Dynamic assign SCSI bus reset holding time in init_tulip()
  77. * 07/02/98 hc - v1.01n
  78. * - Support 0002134A
  79. * 08/07/98 hc - v1.01o
  80. * - Change the tul_abort_srb routine to use scsi_done. <01>
  81. * 09/07/98 hl - v1.02
  82. * - Change the INI9100U define and proc_dir_entry to
  83. * reflect the newer Kernel 2.1.118, but the v1.o1o
  84. * should work with Kernel 2.1.118.
  85. * 09/20/98 wh - v1.02a
  86. * - Support Abort command.
  87. * - Handle reset routine.
  88. * 09/21/98 hl - v1.03
  89. * - remove comments.
  90. * 12/09/98 bv - v1.03a
  91. * - Removed unused code
  92. * 12/13/98 bv - v1.03b
  93. * - Remove cli() locking for kernels >= 2.1.95. This uses
  94. * spinlocks to serialize access to the pSRB_head and
  95. * pSRB_tail members of the HCS structure.
  96. * 09/01/99 bv - v1.03d
  97. * - Fixed a deadlock problem in SMP.
  98. * 21/01/99 bv - v1.03e
  99. * - Add support for the Domex 3192U PCI SCSI
  100. * This is a slightly modified patch by
  101. * Brian Macy <bmacy@sunshinecomputing.com>
  102. * 22/02/99 bv - v1.03f
  103. * - Didn't detect the INIC-950 in 2.0.x correctly.
  104. * Now fixed.
  105. * 05/07/99 bv - v1.03g
  106. * - Changed the assumption that HZ = 100
  107. * 10/17/03 mc - v1.04
  108. * - added new DMA API support
  109. * 06/01/04 jmd - v1.04a
  110. * - Re-add reset_bus support
  111. **************************************************************************/
  112. #include <linux/module.h>
  113. #include <linux/errno.h>
  114. #include <linux/delay.h>
  115. #include <linux/pci.h>
  116. #include <linux/init.h>
  117. #include <linux/blkdev.h>
  118. #include <linux/spinlock.h>
  119. #include <linux/stat.h>
  120. #include <linux/config.h>
  121. #include <linux/kernel.h>
  122. #include <linux/proc_fs.h>
  123. #include <linux/string.h>
  124. #include <linux/interrupt.h>
  125. #include <linux/ioport.h>
  126. #include <linux/sched.h>
  127. #include <linux/slab.h>
  128. #include <linux/jiffies.h>
  129. #include <asm/io.h>
  130. #include <scsi/scsi.h>
  131. #include <scsi/scsi_cmnd.h>
  132. #include <scsi/scsi_device.h>
  133. #include <scsi/scsi_host.h>
  134. #include <scsi/scsi_tcq.h>
  135. #include "initio.h"
  136. #define SENSE_SIZE 14
  137. #define i91u_MAXQUEUE 2
  138. #define i91u_REVID "Initio INI-9X00U/UW SCSI device driver; Revision: 1.04a"
  139. #define INI_VENDOR_ID 0x1101 /* Initio's PCI vendor ID */
  140. #define DMX_VENDOR_ID 0x134a /* Domex's PCI vendor ID */
  141. #define I950_DEVICE_ID 0x9500 /* Initio's inic-950 product ID */
  142. #define I940_DEVICE_ID 0x9400 /* Initio's inic-940 product ID */
  143. #define I935_DEVICE_ID 0x9401 /* Initio's inic-935 product ID */
  144. #define I920_DEVICE_ID 0x0002 /* Initio's other product ID */
  145. #ifdef DEBUG_i91u
  146. static unsigned int i91u_debug = DEBUG_DEFAULT;
  147. #endif
  148. #define TULSZ(sz) (sizeof(sz) / sizeof(sz[0]))
  149. #define TUL_RDWORD(x,y) (short)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) ))
  150. typedef struct PCI_ID_Struc {
  151. unsigned short vendor_id;
  152. unsigned short device_id;
  153. } PCI_ID;
  154. static int tul_num_ch = 4; /* Maximum 4 adapters */
  155. static int tul_num_scb;
  156. static int tul_tag_enable = 1;
  157. static SCB *tul_scb;
  158. #ifdef DEBUG_i91u
  159. static int setup_debug = 0;
  160. #endif
  161. static void i91uSCBPost(BYTE * pHcb, BYTE * pScb);
  162. static const PCI_ID i91u_pci_devices[] = {
  163. { INI_VENDOR_ID, I950_DEVICE_ID },
  164. { INI_VENDOR_ID, I940_DEVICE_ID },
  165. { INI_VENDOR_ID, I935_DEVICE_ID },
  166. { INI_VENDOR_ID, I920_DEVICE_ID },
  167. { DMX_VENDOR_ID, I920_DEVICE_ID },
  168. };
  169. #define DEBUG_INTERRUPT 0
  170. #define DEBUG_QUEUE 0
  171. #define DEBUG_STATE 0
  172. #define INT_DISC 0
  173. /*--- external functions --*/
  174. static void tul_se2_wait(void);
  175. /*--- forward refrence ---*/
  176. static SCB *tul_find_busy_scb(HCS * pCurHcb, WORD tarlun);
  177. static SCB *tul_find_done_scb(HCS * pCurHcb);
  178. static int tulip_main(HCS * pCurHcb);
  179. static int tul_next_state(HCS * pCurHcb);
  180. static int tul_state_1(HCS * pCurHcb);
  181. static int tul_state_2(HCS * pCurHcb);
  182. static int tul_state_3(HCS * pCurHcb);
  183. static int tul_state_4(HCS * pCurHcb);
  184. static int tul_state_5(HCS * pCurHcb);
  185. static int tul_state_6(HCS * pCurHcb);
  186. static int tul_state_7(HCS * pCurHcb);
  187. static int tul_xfer_data_in(HCS * pCurHcb);
  188. static int tul_xfer_data_out(HCS * pCurHcb);
  189. static int tul_xpad_in(HCS * pCurHcb);
  190. static int tul_xpad_out(HCS * pCurHcb);
  191. static int tul_status_msg(HCS * pCurHcb);
  192. static int tul_msgin(HCS * pCurHcb);
  193. static int tul_msgin_sync(HCS * pCurHcb);
  194. static int tul_msgin_accept(HCS * pCurHcb);
  195. static int tul_msgout_reject(HCS * pCurHcb);
  196. static int tul_msgin_extend(HCS * pCurHcb);
  197. static int tul_msgout_ide(HCS * pCurHcb);
  198. static int tul_msgout_abort_targ(HCS * pCurHcb);
  199. static int tul_msgout_abort_tag(HCS * pCurHcb);
  200. static int tul_bus_device_reset(HCS * pCurHcb);
  201. static void tul_select_atn(HCS * pCurHcb, SCB * pCurScb);
  202. static void tul_select_atn3(HCS * pCurHcb, SCB * pCurScb);
  203. static void tul_select_atn_stop(HCS * pCurHcb, SCB * pCurScb);
  204. static int int_tul_busfree(HCS * pCurHcb);
  205. static int int_tul_scsi_rst(HCS * pCurHcb);
  206. static int int_tul_bad_seq(HCS * pCurHcb);
  207. static int int_tul_resel(HCS * pCurHcb);
  208. static int tul_sync_done(HCS * pCurHcb);
  209. static int wdtr_done(HCS * pCurHcb);
  210. static int wait_tulip(HCS * pCurHcb);
  211. static int tul_wait_done_disc(HCS * pCurHcb);
  212. static int tul_wait_disc(HCS * pCurHcb);
  213. static void tulip_scsi(HCS * pCurHcb);
  214. static int tul_post_scsi_rst(HCS * pCurHcb);
  215. static void tul_se2_ew_en(WORD CurBase);
  216. static void tul_se2_ew_ds(WORD CurBase);
  217. static int tul_se2_rd_all(WORD CurBase);
  218. static void tul_se2_update_all(WORD CurBase); /* setup default pattern */
  219. static void tul_read_eeprom(WORD CurBase);
  220. /* ---- INTERNAL VARIABLES ---- */
  221. static HCS tul_hcs[MAX_SUPPORTED_ADAPTERS];
  222. static INI_ADPT_STRUCT i91u_adpt[MAX_SUPPORTED_ADAPTERS];
  223. /*NVRAM nvram, *nvramp = &nvram; */
  224. static NVRAM i91unvram;
  225. static NVRAM *i91unvramp;
  226. static UCHAR i91udftNvRam[64] =
  227. {
  228. /*----------- header -----------*/
  229. 0x25, 0xc9, /* Signature */
  230. 0x40, /* Size */
  231. 0x01, /* Revision */
  232. /* -- Host Adapter Structure -- */
  233. 0x95, /* ModelByte0 */
  234. 0x00, /* ModelByte1 */
  235. 0x00, /* ModelInfo */
  236. 0x01, /* NumOfCh */
  237. NBC1_DEFAULT, /* BIOSConfig1 */
  238. 0, /* BIOSConfig2 */
  239. 0, /* HAConfig1 */
  240. 0, /* HAConfig2 */
  241. /* SCSI channel 0 and target Structure */
  242. 7, /* SCSIid */
  243. NCC1_DEFAULT, /* SCSIconfig1 */
  244. 0, /* SCSIconfig2 */
  245. 0x10, /* NumSCSItarget */
  246. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  247. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  248. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  249. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  250. /* SCSI channel 1 and target Structure */
  251. 7, /* SCSIid */
  252. NCC1_DEFAULT, /* SCSIconfig1 */
  253. 0, /* SCSIconfig2 */
  254. 0x10, /* NumSCSItarget */
  255. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  256. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  257. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  258. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  259. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  260. 0, 0}; /* - CheckSum - */
  261. static UCHAR tul_rate_tbl[8] = /* fast 20 */
  262. {
  263. /* nanosecond devide by 4 */
  264. 12, /* 50ns, 20M */
  265. 18, /* 75ns, 13.3M */
  266. 25, /* 100ns, 10M */
  267. 31, /* 125ns, 8M */
  268. 37, /* 150ns, 6.6M */
  269. 43, /* 175ns, 5.7M */
  270. 50, /* 200ns, 5M */
  271. 62 /* 250ns, 4M */
  272. };
  273. static void tul_do_pause(unsigned amount)
  274. { /* Pause for amount jiffies */
  275. unsigned long the_time = jiffies + amount;
  276. while (time_before_eq(jiffies, the_time));
  277. }
  278. /*-- forward reference --*/
  279. /*******************************************************************
  280. Use memeory refresh time ~ 15us * 2
  281. ********************************************************************/
  282. void tul_se2_wait(void)
  283. {
  284. #if 1
  285. udelay(30);
  286. #else
  287. UCHAR readByte;
  288. readByte = TUL_RD(0, 0x61);
  289. if ((readByte & 0x10) == 0x10) {
  290. for (;;) {
  291. readByte = TUL_RD(0, 0x61);
  292. if ((readByte & 0x10) == 0x10)
  293. break;
  294. }
  295. for (;;) {
  296. readByte = TUL_RD(0, 0x61);
  297. if ((readByte & 0x10) != 0x10)
  298. break;
  299. }
  300. } else {
  301. for (;;) {
  302. readByte = TUL_RD(0, 0x61);
  303. if ((readByte & 0x10) == 0x10)
  304. break;
  305. }
  306. for (;;) {
  307. readByte = TUL_RD(0, 0x61);
  308. if ((readByte & 0x10) != 0x10)
  309. break;
  310. }
  311. }
  312. #endif
  313. }
  314. /******************************************************************
  315. Input: instruction for Serial E2PROM
  316. EX: se2_rd(0 call se2_instr() to send address and read command
  317. StartBit OP_Code Address Data
  318. --------- -------- ------------------ -------
  319. 1 1 , 0 A5,A4,A3,A2,A1,A0 D15-D0
  320. +-----------------------------------------------------
  321. |
  322. CS -----+
  323. +--+ +--+ +--+ +--+ +--+
  324. ^ | ^ | ^ | ^ | ^ |
  325. | | | | | | | | | |
  326. CLK -------+ +--+ +--+ +--+ +--+ +--
  327. (leading edge trigger)
  328. +--1-----1--+
  329. | SB OP | OP A5 A4
  330. DI ----+ +--0------------------
  331. (address and cmd sent to nvram)
  332. -------------------------------------------+
  333. |
  334. DO +---
  335. (data sent from nvram)
  336. ******************************************************************/
  337. static void tul_se2_instr(WORD CurBase, UCHAR instr)
  338. {
  339. int i;
  340. UCHAR b;
  341. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2DO); /* cs+start bit */
  342. tul_se2_wait();
  343. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK | SE2DO); /* +CLK */
  344. tul_se2_wait();
  345. for (i = 0; i < 8; i++) {
  346. if (instr & 0x80)
  347. b = SE2CS | SE2DO; /* -CLK+dataBit */
  348. else
  349. b = SE2CS; /* -CLK */
  350. TUL_WR(CurBase + TUL_NVRAM, b);
  351. tul_se2_wait();
  352. TUL_WR(CurBase + TUL_NVRAM, b | SE2CLK); /* +CLK */
  353. tul_se2_wait();
  354. instr <<= 1;
  355. }
  356. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  357. tul_se2_wait();
  358. return;
  359. }
  360. /******************************************************************
  361. Function name : tul_se2_ew_en
  362. Description : Enable erase/write state of serial EEPROM
  363. ******************************************************************/
  364. void tul_se2_ew_en(WORD CurBase)
  365. {
  366. tul_se2_instr(CurBase, 0x30); /* EWEN */
  367. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  368. tul_se2_wait();
  369. return;
  370. }
  371. /************************************************************************
  372. Disable erase/write state of serial EEPROM
  373. *************************************************************************/
  374. void tul_se2_ew_ds(WORD CurBase)
  375. {
  376. tul_se2_instr(CurBase, 0); /* EWDS */
  377. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  378. tul_se2_wait();
  379. return;
  380. }
  381. /******************************************************************
  382. Input :address of Serial E2PROM
  383. Output :value stored in Serial E2PROM
  384. *******************************************************************/
  385. static USHORT tul_se2_rd(WORD CurBase, ULONG adr)
  386. {
  387. UCHAR instr, readByte;
  388. USHORT readWord;
  389. int i;
  390. instr = (UCHAR) (adr | 0x80);
  391. tul_se2_instr(CurBase, instr); /* READ INSTR */
  392. readWord = 0;
  393. for (i = 15; i >= 0; i--) {
  394. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  395. tul_se2_wait();
  396. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  397. /* sample data after the following edge of clock */
  398. readByte = TUL_RD(CurBase, TUL_NVRAM);
  399. readByte &= SE2DI;
  400. readWord += (readByte << i);
  401. tul_se2_wait(); /* 6/20/95 */
  402. }
  403. TUL_WR(CurBase + TUL_NVRAM, 0); /* no chip select */
  404. tul_se2_wait();
  405. return readWord;
  406. }
  407. /******************************************************************
  408. Input: new value in Serial E2PROM, address of Serial E2PROM
  409. *******************************************************************/
  410. static void tul_se2_wr(WORD CurBase, UCHAR adr, USHORT writeWord)
  411. {
  412. UCHAR readByte;
  413. UCHAR instr;
  414. int i;
  415. instr = (UCHAR) (adr | 0x40);
  416. tul_se2_instr(CurBase, instr); /* WRITE INSTR */
  417. for (i = 15; i >= 0; i--) {
  418. if (writeWord & 0x8000)
  419. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2DO); /* -CLK+dataBit 1 */
  420. else
  421. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK+dataBit 0 */
  422. tul_se2_wait();
  423. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  424. tul_se2_wait();
  425. writeWord <<= 1;
  426. }
  427. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  428. tul_se2_wait();
  429. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  430. tul_se2_wait();
  431. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* +CS */
  432. tul_se2_wait();
  433. for (;;) {
  434. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  435. tul_se2_wait();
  436. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  437. tul_se2_wait();
  438. if ((readByte = TUL_RD(CurBase, TUL_NVRAM)) & SE2DI)
  439. break; /* write complete */
  440. }
  441. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  442. return;
  443. }
  444. /***********************************************************************
  445. Read SCSI H/A configuration parameters from serial EEPROM
  446. ************************************************************************/
  447. int tul_se2_rd_all(WORD CurBase)
  448. {
  449. int i;
  450. ULONG chksum = 0;
  451. USHORT *np;
  452. i91unvramp = &i91unvram;
  453. np = (USHORT *) i91unvramp;
  454. for (i = 0; i < 32; i++) {
  455. *np++ = tul_se2_rd(CurBase, i);
  456. }
  457. /*--------------------Is signature "ini" ok ? ----------------*/
  458. if (i91unvramp->NVM_Signature != INI_SIGNATURE)
  459. return -1;
  460. /*---------------------- Is ckecksum ok ? ----------------------*/
  461. np = (USHORT *) i91unvramp;
  462. for (i = 0; i < 31; i++)
  463. chksum += *np++;
  464. if (i91unvramp->NVM_CheckSum != (USHORT) chksum)
  465. return -1;
  466. return 1;
  467. }
  468. /***********************************************************************
  469. Update SCSI H/A configuration parameters from serial EEPROM
  470. ************************************************************************/
  471. void tul_se2_update_all(WORD CurBase)
  472. { /* setup default pattern */
  473. int i;
  474. ULONG chksum = 0;
  475. USHORT *np, *np1;
  476. i91unvramp = &i91unvram;
  477. /* Calculate checksum first */
  478. np = (USHORT *) i91udftNvRam;
  479. for (i = 0; i < 31; i++)
  480. chksum += *np++;
  481. *np = (USHORT) chksum;
  482. tul_se2_ew_en(CurBase); /* Enable write */
  483. np = (USHORT *) i91udftNvRam;
  484. np1 = (USHORT *) i91unvramp;
  485. for (i = 0; i < 32; i++, np++, np1++) {
  486. if (*np != *np1) {
  487. tul_se2_wr(CurBase, i, *np);
  488. }
  489. }
  490. tul_se2_ew_ds(CurBase); /* Disable write */
  491. return;
  492. }
  493. /*************************************************************************
  494. Function name : read_eeprom
  495. **************************************************************************/
  496. void tul_read_eeprom(WORD CurBase)
  497. {
  498. UCHAR gctrl;
  499. i91unvramp = &i91unvram;
  500. /*------Enable EEProm programming ---*/
  501. gctrl = TUL_RD(CurBase, TUL_GCTRL);
  502. TUL_WR(CurBase + TUL_GCTRL, gctrl | TUL_GCTRL_EEPROM_BIT);
  503. if (tul_se2_rd_all(CurBase) != 1) {
  504. tul_se2_update_all(CurBase); /* setup default pattern */
  505. tul_se2_rd_all(CurBase); /* load again */
  506. }
  507. /*------ Disable EEProm programming ---*/
  508. gctrl = TUL_RD(CurBase, TUL_GCTRL);
  509. TUL_WR(CurBase + TUL_GCTRL, gctrl & ~TUL_GCTRL_EEPROM_BIT);
  510. } /* read_eeprom */
  511. static int Addi91u_into_Adapter_table(WORD wBIOS, WORD wBASE, BYTE bInterrupt,
  512. BYTE bBus, BYTE bDevice)
  513. {
  514. int i, j;
  515. for (i = 0; i < MAX_SUPPORTED_ADAPTERS; i++) {
  516. if (i91u_adpt[i].ADPT_BIOS < wBIOS)
  517. continue;
  518. if (i91u_adpt[i].ADPT_BIOS == wBIOS) {
  519. if (i91u_adpt[i].ADPT_BASE == wBASE) {
  520. if (i91u_adpt[i].ADPT_Bus != 0xFF)
  521. return 1;
  522. } else if (i91u_adpt[i].ADPT_BASE < wBASE)
  523. continue;
  524. }
  525. for (j = MAX_SUPPORTED_ADAPTERS - 1; j > i; j--) {
  526. i91u_adpt[j].ADPT_BASE = i91u_adpt[j - 1].ADPT_BASE;
  527. i91u_adpt[j].ADPT_INTR = i91u_adpt[j - 1].ADPT_INTR;
  528. i91u_adpt[j].ADPT_BIOS = i91u_adpt[j - 1].ADPT_BIOS;
  529. i91u_adpt[j].ADPT_Bus = i91u_adpt[j - 1].ADPT_Bus;
  530. i91u_adpt[j].ADPT_Device = i91u_adpt[j - 1].ADPT_Device;
  531. }
  532. i91u_adpt[i].ADPT_BASE = wBASE;
  533. i91u_adpt[i].ADPT_INTR = bInterrupt;
  534. i91u_adpt[i].ADPT_BIOS = wBIOS;
  535. i91u_adpt[i].ADPT_Bus = bBus;
  536. i91u_adpt[i].ADPT_Device = bDevice;
  537. return 0;
  538. }
  539. return 1;
  540. }
  541. static void init_i91uAdapter_table(void)
  542. {
  543. int i;
  544. for (i = 0; i < MAX_SUPPORTED_ADAPTERS; i++) { /* Initialize adapter structure */
  545. i91u_adpt[i].ADPT_BIOS = 0xffff;
  546. i91u_adpt[i].ADPT_BASE = 0xffff;
  547. i91u_adpt[i].ADPT_INTR = 0xff;
  548. i91u_adpt[i].ADPT_Bus = 0xff;
  549. i91u_adpt[i].ADPT_Device = 0xff;
  550. }
  551. return;
  552. }
  553. static void tul_stop_bm(HCS * pCurHcb)
  554. {
  555. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */
  556. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
  557. /* wait Abort DMA xfer done */
  558. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & XABT) == 0);
  559. }
  560. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  561. }
  562. /***************************************************************************/
  563. static void get_tulipPCIConfig(HCS * pCurHcb, int ch_idx)
  564. {
  565. pCurHcb->HCS_Base = i91u_adpt[ch_idx].ADPT_BASE; /* Supply base address */
  566. pCurHcb->HCS_BIOS = i91u_adpt[ch_idx].ADPT_BIOS; /* Supply BIOS address */
  567. pCurHcb->HCS_Intr = i91u_adpt[ch_idx].ADPT_INTR; /* Supply interrupt line */
  568. return;
  569. }
  570. /***************************************************************************/
  571. static int tul_reset_scsi(HCS * pCurHcb, int seconds)
  572. {
  573. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_RST_BUS);
  574. while (!((pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt)) & TSS_SCSIRST_INT));
  575. /* reset tulip chip */
  576. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, 0);
  577. /* Stall for a while, wait for target's firmware ready,make it 2 sec ! */
  578. /* SONY 5200 tape drive won't work if only stall for 1 sec */
  579. tul_do_pause(seconds * HZ);
  580. TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  581. return (SCSI_RESET_SUCCESS);
  582. }
  583. /***************************************************************************/
  584. static int init_tulip(HCS * pCurHcb, SCB * scbp, int tul_num_scb,
  585. BYTE * pbBiosAdr, int seconds)
  586. {
  587. int i;
  588. BYTE *pwFlags;
  589. BYTE *pbHeads;
  590. SCB *pTmpScb, *pPrevScb = NULL;
  591. pCurHcb->HCS_NumScbs = tul_num_scb;
  592. pCurHcb->HCS_Semaph = 1;
  593. spin_lock_init(&pCurHcb->HCS_SemaphLock);
  594. pCurHcb->HCS_JSStatus0 = 0;
  595. pCurHcb->HCS_Scb = scbp;
  596. pCurHcb->HCS_NxtPend = scbp;
  597. pCurHcb->HCS_NxtAvail = scbp;
  598. for (i = 0, pTmpScb = scbp; i < tul_num_scb; i++, pTmpScb++) {
  599. pTmpScb->SCB_TagId = i;
  600. if (i != 0)
  601. pPrevScb->SCB_NxtScb = pTmpScb;
  602. pPrevScb = pTmpScb;
  603. }
  604. pPrevScb->SCB_NxtScb = NULL;
  605. pCurHcb->HCS_ScbEnd = pTmpScb;
  606. pCurHcb->HCS_FirstAvail = scbp;
  607. pCurHcb->HCS_LastAvail = pPrevScb;
  608. spin_lock_init(&pCurHcb->HCS_AvailLock);
  609. pCurHcb->HCS_FirstPend = NULL;
  610. pCurHcb->HCS_LastPend = NULL;
  611. pCurHcb->HCS_FirstBusy = NULL;
  612. pCurHcb->HCS_LastBusy = NULL;
  613. pCurHcb->HCS_FirstDone = NULL;
  614. pCurHcb->HCS_LastDone = NULL;
  615. pCurHcb->HCS_ActScb = NULL;
  616. pCurHcb->HCS_ActTcs = NULL;
  617. tul_read_eeprom(pCurHcb->HCS_Base);
  618. /*---------- get H/A configuration -------------*/
  619. if (i91unvramp->NVM_SCSIInfo[0].NVM_NumOfTarg == 8)
  620. pCurHcb->HCS_MaxTar = 8;
  621. else
  622. pCurHcb->HCS_MaxTar = 16;
  623. pCurHcb->HCS_Config = i91unvramp->NVM_SCSIInfo[0].NVM_ChConfig1;
  624. pCurHcb->HCS_SCSI_ID = i91unvramp->NVM_SCSIInfo[0].NVM_ChSCSIID;
  625. pCurHcb->HCS_IdMask = ~(1 << pCurHcb->HCS_SCSI_ID);
  626. #ifdef CHK_PARITY
  627. /* Enable parity error response */
  628. TUL_WR(pCurHcb->HCS_Base + TUL_PCMD, TUL_RD(pCurHcb->HCS_Base, TUL_PCMD) | 0x40);
  629. #endif
  630. /* Mask all the interrupt */
  631. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  632. tul_stop_bm(pCurHcb);
  633. /* --- Initialize the tulip --- */
  634. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_RST_CHIP);
  635. /* program HBA's SCSI ID */
  636. TUL_WR(pCurHcb->HCS_Base + TUL_SScsiId, pCurHcb->HCS_SCSI_ID << 4);
  637. /* Enable Initiator Mode ,phase latch,alternate sync period mode,
  638. disable SCSI reset */
  639. if (pCurHcb->HCS_Config & HCC_EN_PAR)
  640. pCurHcb->HCS_SConf1 = (TSC_INITDEFAULT | TSC_EN_SCSI_PAR);
  641. else
  642. pCurHcb->HCS_SConf1 = (TSC_INITDEFAULT);
  643. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_SConf1);
  644. /* Enable HW reselect */
  645. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT);
  646. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, 0);
  647. /* selection time out = 250 ms */
  648. TUL_WR(pCurHcb->HCS_Base + TUL_STimeOut, 153);
  649. /*--------- Enable SCSI terminator -----*/
  650. TUL_WR(pCurHcb->HCS_Base + TUL_XCtrl, (pCurHcb->HCS_Config & (HCC_ACT_TERM1 | HCC_ACT_TERM2)));
  651. TUL_WR(pCurHcb->HCS_Base + TUL_GCTRL1,
  652. ((pCurHcb->HCS_Config & HCC_AUTO_TERM) >> 4) | (TUL_RD(pCurHcb->HCS_Base, TUL_GCTRL1) & 0xFE));
  653. for (i = 0,
  654. pwFlags = & (i91unvramp->NVM_SCSIInfo[0].NVM_Targ0Config),
  655. pbHeads = pbBiosAdr + 0x180;
  656. i < pCurHcb->HCS_MaxTar;
  657. i++, pwFlags++) {
  658. pCurHcb->HCS_Tcs[i].TCS_Flags = *pwFlags & ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  659. if (pCurHcb->HCS_Tcs[i].TCS_Flags & TCF_EN_255)
  660. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = TCF_DRV_255_63;
  661. else
  662. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = 0;
  663. pCurHcb->HCS_Tcs[i].TCS_JS_Period = 0;
  664. pCurHcb->HCS_Tcs[i].TCS_SConfig0 = pCurHcb->HCS_SConf1;
  665. pCurHcb->HCS_Tcs[i].TCS_DrvHead = *pbHeads++;
  666. if (pCurHcb->HCS_Tcs[i].TCS_DrvHead == 255)
  667. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = TCF_DRV_255_63;
  668. else
  669. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = 0;
  670. pCurHcb->HCS_Tcs[i].TCS_DrvSector = *pbHeads++;
  671. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~TCF_BUSY;
  672. pCurHcb->HCS_ActTags[i] = 0;
  673. pCurHcb->HCS_MaxTags[i] = 0xFF;
  674. } /* for */
  675. printk("i91u: PCI Base=0x%04X, IRQ=%d, BIOS=0x%04X0, SCSI ID=%d\n",
  676. pCurHcb->HCS_Base, pCurHcb->HCS_Intr,
  677. pCurHcb->HCS_BIOS, pCurHcb->HCS_SCSI_ID);
  678. /*------------------- reset SCSI Bus ---------------------------*/
  679. if (pCurHcb->HCS_Config & HCC_SCSI_RESET) {
  680. printk("i91u: Reset SCSI Bus ... \n");
  681. tul_reset_scsi(pCurHcb, seconds);
  682. }
  683. TUL_WR(pCurHcb->HCS_Base + TUL_SCFG1, 0x17);
  684. TUL_WR(pCurHcb->HCS_Base + TUL_SIntEnable, 0xE9);
  685. return (0);
  686. }
  687. /***************************************************************************/
  688. static SCB *tul_alloc_scb(HCS * hcsp)
  689. {
  690. SCB *pTmpScb;
  691. ULONG flags;
  692. spin_lock_irqsave(&(hcsp->HCS_AvailLock), flags);
  693. if ((pTmpScb = hcsp->HCS_FirstAvail) != NULL) {
  694. #if DEBUG_QUEUE
  695. printk("find scb at %08lx\n", (ULONG) pTmpScb);
  696. #endif
  697. if ((hcsp->HCS_FirstAvail = pTmpScb->SCB_NxtScb) == NULL)
  698. hcsp->HCS_LastAvail = NULL;
  699. pTmpScb->SCB_NxtScb = NULL;
  700. pTmpScb->SCB_Status = SCB_RENT;
  701. }
  702. spin_unlock_irqrestore(&(hcsp->HCS_AvailLock), flags);
  703. return (pTmpScb);
  704. }
  705. /***************************************************************************/
  706. static void tul_release_scb(HCS * hcsp, SCB * scbp)
  707. {
  708. ULONG flags;
  709. #if DEBUG_QUEUE
  710. printk("Release SCB %lx; ", (ULONG) scbp);
  711. #endif
  712. spin_lock_irqsave(&(hcsp->HCS_AvailLock), flags);
  713. scbp->SCB_Srb = NULL;
  714. scbp->SCB_Status = 0;
  715. scbp->SCB_NxtScb = NULL;
  716. if (hcsp->HCS_LastAvail != NULL) {
  717. hcsp->HCS_LastAvail->SCB_NxtScb = scbp;
  718. hcsp->HCS_LastAvail = scbp;
  719. } else {
  720. hcsp->HCS_FirstAvail = scbp;
  721. hcsp->HCS_LastAvail = scbp;
  722. }
  723. spin_unlock_irqrestore(&(hcsp->HCS_AvailLock), flags);
  724. }
  725. /***************************************************************************/
  726. static void tul_append_pend_scb(HCS * pCurHcb, SCB * scbp)
  727. {
  728. #if DEBUG_QUEUE
  729. printk("Append pend SCB %lx; ", (ULONG) scbp);
  730. #endif
  731. scbp->SCB_Status = SCB_PEND;
  732. scbp->SCB_NxtScb = NULL;
  733. if (pCurHcb->HCS_LastPend != NULL) {
  734. pCurHcb->HCS_LastPend->SCB_NxtScb = scbp;
  735. pCurHcb->HCS_LastPend = scbp;
  736. } else {
  737. pCurHcb->HCS_FirstPend = scbp;
  738. pCurHcb->HCS_LastPend = scbp;
  739. }
  740. }
  741. /***************************************************************************/
  742. static void tul_push_pend_scb(HCS * pCurHcb, SCB * scbp)
  743. {
  744. #if DEBUG_QUEUE
  745. printk("Push pend SCB %lx; ", (ULONG) scbp);
  746. #endif
  747. scbp->SCB_Status = SCB_PEND;
  748. if ((scbp->SCB_NxtScb = pCurHcb->HCS_FirstPend) != NULL) {
  749. pCurHcb->HCS_FirstPend = scbp;
  750. } else {
  751. pCurHcb->HCS_FirstPend = scbp;
  752. pCurHcb->HCS_LastPend = scbp;
  753. }
  754. }
  755. /***************************************************************************/
  756. static SCB *tul_find_first_pend_scb(HCS * pCurHcb)
  757. {
  758. SCB *pFirstPend;
  759. pFirstPend = pCurHcb->HCS_FirstPend;
  760. while (pFirstPend != NULL) {
  761. if (pFirstPend->SCB_Opcode != ExecSCSI) {
  762. return (pFirstPend);
  763. }
  764. if (pFirstPend->SCB_TagMsg == 0) {
  765. if ((pCurHcb->HCS_ActTags[pFirstPend->SCB_Target] == 0) &&
  766. !(pCurHcb->HCS_Tcs[pFirstPend->SCB_Target].TCS_Flags & TCF_BUSY)) {
  767. return (pFirstPend);
  768. }
  769. } else {
  770. if ((pCurHcb->HCS_ActTags[pFirstPend->SCB_Target] >=
  771. pCurHcb->HCS_MaxTags[pFirstPend->SCB_Target]) |
  772. (pCurHcb->HCS_Tcs[pFirstPend->SCB_Target].TCS_Flags & TCF_BUSY)) {
  773. pFirstPend = pFirstPend->SCB_NxtScb;
  774. continue;
  775. }
  776. return (pFirstPend);
  777. }
  778. pFirstPend = pFirstPend->SCB_NxtScb;
  779. }
  780. return (pFirstPend);
  781. }
  782. /***************************************************************************/
  783. static void tul_unlink_pend_scb(HCS * pCurHcb, SCB * pCurScb)
  784. {
  785. SCB *pTmpScb, *pPrevScb;
  786. #if DEBUG_QUEUE
  787. printk("unlink pend SCB %lx; ", (ULONG) pCurScb);
  788. #endif
  789. pPrevScb = pTmpScb = pCurHcb->HCS_FirstPend;
  790. while (pTmpScb != NULL) {
  791. if (pCurScb == pTmpScb) { /* Unlink this SCB */
  792. if (pTmpScb == pCurHcb->HCS_FirstPend) {
  793. if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL)
  794. pCurHcb->HCS_LastPend = NULL;
  795. } else {
  796. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  797. if (pTmpScb == pCurHcb->HCS_LastPend)
  798. pCurHcb->HCS_LastPend = pPrevScb;
  799. }
  800. pTmpScb->SCB_NxtScb = NULL;
  801. break;
  802. }
  803. pPrevScb = pTmpScb;
  804. pTmpScb = pTmpScb->SCB_NxtScb;
  805. }
  806. return;
  807. }
  808. /***************************************************************************/
  809. static void tul_append_busy_scb(HCS * pCurHcb, SCB * scbp)
  810. {
  811. #if DEBUG_QUEUE
  812. printk("append busy SCB %lx; ", (ULONG) scbp);
  813. #endif
  814. if (scbp->SCB_TagMsg)
  815. pCurHcb->HCS_ActTags[scbp->SCB_Target]++;
  816. else
  817. pCurHcb->HCS_Tcs[scbp->SCB_Target].TCS_Flags |= TCF_BUSY;
  818. scbp->SCB_Status = SCB_BUSY;
  819. scbp->SCB_NxtScb = NULL;
  820. if (pCurHcb->HCS_LastBusy != NULL) {
  821. pCurHcb->HCS_LastBusy->SCB_NxtScb = scbp;
  822. pCurHcb->HCS_LastBusy = scbp;
  823. } else {
  824. pCurHcb->HCS_FirstBusy = scbp;
  825. pCurHcb->HCS_LastBusy = scbp;
  826. }
  827. }
  828. /***************************************************************************/
  829. static SCB *tul_pop_busy_scb(HCS * pCurHcb)
  830. {
  831. SCB *pTmpScb;
  832. if ((pTmpScb = pCurHcb->HCS_FirstBusy) != NULL) {
  833. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  834. pCurHcb->HCS_LastBusy = NULL;
  835. pTmpScb->SCB_NxtScb = NULL;
  836. if (pTmpScb->SCB_TagMsg)
  837. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  838. else
  839. pCurHcb->HCS_Tcs[pTmpScb->SCB_Target].TCS_Flags &= ~TCF_BUSY;
  840. }
  841. #if DEBUG_QUEUE
  842. printk("Pop busy SCB %lx; ", (ULONG) pTmpScb);
  843. #endif
  844. return (pTmpScb);
  845. }
  846. /***************************************************************************/
  847. static void tul_unlink_busy_scb(HCS * pCurHcb, SCB * pCurScb)
  848. {
  849. SCB *pTmpScb, *pPrevScb;
  850. #if DEBUG_QUEUE
  851. printk("unlink busy SCB %lx; ", (ULONG) pCurScb);
  852. #endif
  853. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy;
  854. while (pTmpScb != NULL) {
  855. if (pCurScb == pTmpScb) { /* Unlink this SCB */
  856. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  857. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  858. pCurHcb->HCS_LastBusy = NULL;
  859. } else {
  860. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  861. if (pTmpScb == pCurHcb->HCS_LastBusy)
  862. pCurHcb->HCS_LastBusy = pPrevScb;
  863. }
  864. pTmpScb->SCB_NxtScb = NULL;
  865. if (pTmpScb->SCB_TagMsg)
  866. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  867. else
  868. pCurHcb->HCS_Tcs[pTmpScb->SCB_Target].TCS_Flags &= ~TCF_BUSY;
  869. break;
  870. }
  871. pPrevScb = pTmpScb;
  872. pTmpScb = pTmpScb->SCB_NxtScb;
  873. }
  874. return;
  875. }
  876. /***************************************************************************/
  877. SCB *tul_find_busy_scb(HCS * pCurHcb, WORD tarlun)
  878. {
  879. SCB *pTmpScb, *pPrevScb;
  880. WORD scbp_tarlun;
  881. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy;
  882. while (pTmpScb != NULL) {
  883. scbp_tarlun = (pTmpScb->SCB_Lun << 8) | (pTmpScb->SCB_Target);
  884. if (scbp_tarlun == tarlun) { /* Unlink this SCB */
  885. break;
  886. }
  887. pPrevScb = pTmpScb;
  888. pTmpScb = pTmpScb->SCB_NxtScb;
  889. }
  890. #if DEBUG_QUEUE
  891. printk("find busy SCB %lx; ", (ULONG) pTmpScb);
  892. #endif
  893. return (pTmpScb);
  894. }
  895. /***************************************************************************/
  896. static void tul_append_done_scb(HCS * pCurHcb, SCB * scbp)
  897. {
  898. #if DEBUG_QUEUE
  899. printk("append done SCB %lx; ", (ULONG) scbp);
  900. #endif
  901. scbp->SCB_Status = SCB_DONE;
  902. scbp->SCB_NxtScb = NULL;
  903. if (pCurHcb->HCS_LastDone != NULL) {
  904. pCurHcb->HCS_LastDone->SCB_NxtScb = scbp;
  905. pCurHcb->HCS_LastDone = scbp;
  906. } else {
  907. pCurHcb->HCS_FirstDone = scbp;
  908. pCurHcb->HCS_LastDone = scbp;
  909. }
  910. }
  911. /***************************************************************************/
  912. SCB *tul_find_done_scb(HCS * pCurHcb)
  913. {
  914. SCB *pTmpScb;
  915. if ((pTmpScb = pCurHcb->HCS_FirstDone) != NULL) {
  916. if ((pCurHcb->HCS_FirstDone = pTmpScb->SCB_NxtScb) == NULL)
  917. pCurHcb->HCS_LastDone = NULL;
  918. pTmpScb->SCB_NxtScb = NULL;
  919. }
  920. #if DEBUG_QUEUE
  921. printk("find done SCB %lx; ", (ULONG) pTmpScb);
  922. #endif
  923. return (pTmpScb);
  924. }
  925. /***************************************************************************/
  926. static int tul_abort_srb(HCS * pCurHcb, struct scsi_cmnd *srbp)
  927. {
  928. ULONG flags;
  929. SCB *pTmpScb, *pPrevScb;
  930. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  931. if ((pCurHcb->HCS_Semaph == 0) && (pCurHcb->HCS_ActScb == NULL)) {
  932. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  933. /* disable Jasmin SCSI Int */
  934. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  935. tulip_main(pCurHcb);
  936. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  937. pCurHcb->HCS_Semaph = 1;
  938. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  939. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  940. return SCSI_ABORT_SNOOZE;
  941. }
  942. pPrevScb = pTmpScb = pCurHcb->HCS_FirstPend; /* Check Pend queue */
  943. while (pTmpScb != NULL) {
  944. /* 07/27/98 */
  945. if (pTmpScb->SCB_Srb == srbp) {
  946. if (pTmpScb == pCurHcb->HCS_ActScb) {
  947. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  948. return SCSI_ABORT_BUSY;
  949. } else if (pTmpScb == pCurHcb->HCS_FirstPend) {
  950. if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL)
  951. pCurHcb->HCS_LastPend = NULL;
  952. } else {
  953. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  954. if (pTmpScb == pCurHcb->HCS_LastPend)
  955. pCurHcb->HCS_LastPend = pPrevScb;
  956. }
  957. pTmpScb->SCB_HaStat = HOST_ABORTED;
  958. pTmpScb->SCB_Flags |= SCF_DONE;
  959. if (pTmpScb->SCB_Flags & SCF_POST)
  960. (*pTmpScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pTmpScb);
  961. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  962. return SCSI_ABORT_SUCCESS;
  963. }
  964. pPrevScb = pTmpScb;
  965. pTmpScb = pTmpScb->SCB_NxtScb;
  966. }
  967. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  968. while (pTmpScb != NULL) {
  969. if (pTmpScb->SCB_Srb == srbp) {
  970. if (pTmpScb == pCurHcb->HCS_ActScb) {
  971. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  972. return SCSI_ABORT_BUSY;
  973. } else if (pTmpScb->SCB_TagMsg == 0) {
  974. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  975. return SCSI_ABORT_BUSY;
  976. } else {
  977. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  978. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  979. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  980. pCurHcb->HCS_LastBusy = NULL;
  981. } else {
  982. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  983. if (pTmpScb == pCurHcb->HCS_LastBusy)
  984. pCurHcb->HCS_LastBusy = pPrevScb;
  985. }
  986. pTmpScb->SCB_NxtScb = NULL;
  987. pTmpScb->SCB_HaStat = HOST_ABORTED;
  988. pTmpScb->SCB_Flags |= SCF_DONE;
  989. if (pTmpScb->SCB_Flags & SCF_POST)
  990. (*pTmpScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pTmpScb);
  991. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  992. return SCSI_ABORT_SUCCESS;
  993. }
  994. }
  995. pPrevScb = pTmpScb;
  996. pTmpScb = pTmpScb->SCB_NxtScb;
  997. }
  998. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  999. return (SCSI_ABORT_NOT_RUNNING);
  1000. }
  1001. /***************************************************************************/
  1002. static int tul_bad_seq(HCS * pCurHcb)
  1003. {
  1004. SCB *pCurScb;
  1005. printk("tul_bad_seg c=%d\n", pCurHcb->HCS_Index);
  1006. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) {
  1007. tul_unlink_busy_scb(pCurHcb, pCurScb);
  1008. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1009. pCurScb->SCB_TaStat = 0;
  1010. tul_append_done_scb(pCurHcb, pCurScb);
  1011. }
  1012. tul_stop_bm(pCurHcb);
  1013. tul_reset_scsi(pCurHcb, 8); /* 7/29/98 */
  1014. return (tul_post_scsi_rst(pCurHcb));
  1015. }
  1016. #if 0
  1017. /************************************************************************/
  1018. static int tul_device_reset(HCS * pCurHcb, struct scsi_cmnd *pSrb,
  1019. unsigned int target, unsigned int ResetFlags)
  1020. {
  1021. ULONG flags;
  1022. SCB *pScb;
  1023. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1024. if (ResetFlags & SCSI_RESET_ASYNCHRONOUS) {
  1025. if ((pCurHcb->HCS_Semaph == 0) && (pCurHcb->HCS_ActScb == NULL)) {
  1026. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1027. /* disable Jasmin SCSI Int */
  1028. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1029. tulip_main(pCurHcb);
  1030. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1031. pCurHcb->HCS_Semaph = 1;
  1032. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1033. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1034. return SCSI_RESET_SNOOZE;
  1035. }
  1036. pScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  1037. while (pScb != NULL) {
  1038. if (pScb->SCB_Srb == pSrb)
  1039. break;
  1040. pScb = pScb->SCB_NxtScb;
  1041. }
  1042. if (pScb == NULL) {
  1043. printk("Unable to Reset - No SCB Found\n");
  1044. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1045. return SCSI_RESET_NOT_RUNNING;
  1046. }
  1047. }
  1048. if ((pScb = tul_alloc_scb(pCurHcb)) == NULL) {
  1049. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1050. return SCSI_RESET_NOT_RUNNING;
  1051. }
  1052. pScb->SCB_Opcode = BusDevRst;
  1053. pScb->SCB_Flags = SCF_POST;
  1054. pScb->SCB_Target = target;
  1055. pScb->SCB_Mode = 0;
  1056. pScb->SCB_Srb = NULL;
  1057. if (ResetFlags & SCSI_RESET_SYNCHRONOUS) {
  1058. pScb->SCB_Srb = pSrb;
  1059. }
  1060. tul_push_pend_scb(pCurHcb, pScb); /* push this SCB to Pending queue */
  1061. if (pCurHcb->HCS_Semaph == 1) {
  1062. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1063. /* disable Jasmin SCSI Int */
  1064. pCurHcb->HCS_Semaph = 0;
  1065. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1066. tulip_main(pCurHcb);
  1067. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1068. pCurHcb->HCS_Semaph = 1;
  1069. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1070. }
  1071. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1072. return SCSI_RESET_PENDING;
  1073. }
  1074. static int tul_reset_scsi_bus(HCS * pCurHcb)
  1075. {
  1076. ULONG flags;
  1077. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1078. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1079. pCurHcb->HCS_Semaph = 0;
  1080. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1081. tul_stop_bm(pCurHcb);
  1082. tul_reset_scsi(pCurHcb, 2); /* 7/29/98 */
  1083. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1084. tul_post_scsi_rst(pCurHcb);
  1085. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1086. tulip_main(pCurHcb);
  1087. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1088. pCurHcb->HCS_Semaph = 1;
  1089. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1090. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1091. return (SCSI_RESET_SUCCESS | SCSI_RESET_HOST_RESET);
  1092. }
  1093. #endif /* 0 */
  1094. /************************************************************************/
  1095. static void tul_exec_scb(HCS * pCurHcb, SCB * pCurScb)
  1096. {
  1097. ULONG flags;
  1098. pCurScb->SCB_Mode = 0;
  1099. pCurScb->SCB_SGIdx = 0;
  1100. pCurScb->SCB_SGMax = pCurScb->SCB_SGLen;
  1101. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1102. tul_append_pend_scb(pCurHcb, pCurScb); /* Append this SCB to Pending queue */
  1103. /* VVVVV 07/21/98 */
  1104. if (pCurHcb->HCS_Semaph == 1) {
  1105. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1106. /* disable Jasmin SCSI Int */
  1107. pCurHcb->HCS_Semaph = 0;
  1108. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1109. tulip_main(pCurHcb);
  1110. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1111. pCurHcb->HCS_Semaph = 1;
  1112. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1113. }
  1114. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1115. return;
  1116. }
  1117. /***************************************************************************/
  1118. static int tul_isr(HCS * pCurHcb)
  1119. {
  1120. /* Enter critical section */
  1121. if (TUL_RD(pCurHcb->HCS_Base, TUL_Int) & TSS_INT_PENDING) {
  1122. if (pCurHcb->HCS_Semaph == 1) {
  1123. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1124. /* Disable Tulip SCSI Int */
  1125. pCurHcb->HCS_Semaph = 0;
  1126. tulip_main(pCurHcb);
  1127. pCurHcb->HCS_Semaph = 1;
  1128. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1129. return (1);
  1130. }
  1131. }
  1132. return (0);
  1133. }
  1134. /***************************************************************************/
  1135. int tulip_main(HCS * pCurHcb)
  1136. {
  1137. SCB *pCurScb;
  1138. for (;;) {
  1139. tulip_scsi(pCurHcb); /* Call tulip_scsi */
  1140. while ((pCurScb = tul_find_done_scb(pCurHcb)) != NULL) { /* find done entry */
  1141. if (pCurScb->SCB_TaStat == INI_QUEUE_FULL) {
  1142. pCurHcb->HCS_MaxTags[pCurScb->SCB_Target] =
  1143. pCurHcb->HCS_ActTags[pCurScb->SCB_Target] - 1;
  1144. pCurScb->SCB_TaStat = 0;
  1145. tul_append_pend_scb(pCurHcb, pCurScb);
  1146. continue;
  1147. }
  1148. if (!(pCurScb->SCB_Mode & SCM_RSENS)) { /* not in auto req. sense mode */
  1149. if (pCurScb->SCB_TaStat == 2) {
  1150. /* clr sync. nego flag */
  1151. if (pCurScb->SCB_Flags & SCF_SENSE) {
  1152. BYTE len;
  1153. len = pCurScb->SCB_SenseLen;
  1154. if (len == 0)
  1155. len = 1;
  1156. pCurScb->SCB_BufLen = pCurScb->SCB_SenseLen;
  1157. pCurScb->SCB_BufPtr = pCurScb->SCB_SensePtr;
  1158. pCurScb->SCB_Flags &= ~(SCF_SG | SCF_DIR); /* for xfer_data_in */
  1159. /* pCurScb->SCB_Flags |= SCF_NO_DCHK; */
  1160. /* so, we won't report worng direction in xfer_data_in,
  1161. and won't report HOST_DO_DU in state_6 */
  1162. pCurScb->SCB_Mode = SCM_RSENS;
  1163. pCurScb->SCB_Ident &= 0xBF; /* Disable Disconnect */
  1164. pCurScb->SCB_TagMsg = 0;
  1165. pCurScb->SCB_TaStat = 0;
  1166. pCurScb->SCB_CDBLen = 6;
  1167. pCurScb->SCB_CDB[0] = SCSICMD_RequestSense;
  1168. pCurScb->SCB_CDB[1] = 0;
  1169. pCurScb->SCB_CDB[2] = 0;
  1170. pCurScb->SCB_CDB[3] = 0;
  1171. pCurScb->SCB_CDB[4] = len;
  1172. pCurScb->SCB_CDB[5] = 0;
  1173. tul_push_pend_scb(pCurHcb, pCurScb);
  1174. break;
  1175. }
  1176. }
  1177. } else { /* in request sense mode */
  1178. if (pCurScb->SCB_TaStat == 2) { /* check contition status again after sending
  1179. requset sense cmd 0x3 */
  1180. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1181. }
  1182. pCurScb->SCB_TaStat = 2;
  1183. }
  1184. pCurScb->SCB_Flags |= SCF_DONE;
  1185. if (pCurScb->SCB_Flags & SCF_POST) {
  1186. (*pCurScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pCurScb);
  1187. }
  1188. } /* while */
  1189. /* find_active: */
  1190. if (TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0) & TSS_INT_PENDING)
  1191. continue;
  1192. if (pCurHcb->HCS_ActScb) { /* return to OS and wait for xfer_done_ISR/Selected_ISR */
  1193. return 1; /* return to OS, enable interrupt */
  1194. }
  1195. /* Check pending SCB */
  1196. if (tul_find_first_pend_scb(pCurHcb) == NULL) {
  1197. return 1; /* return to OS, enable interrupt */
  1198. }
  1199. } /* End of for loop */
  1200. /* statement won't reach here */
  1201. }
  1202. /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
  1203. /***************************************************************************/
  1204. /***************************************************************************/
  1205. /***************************************************************************/
  1206. /***************************************************************************/
  1207. /***************************************************************************/
  1208. void tulip_scsi(HCS * pCurHcb)
  1209. {
  1210. SCB *pCurScb;
  1211. TCS *pCurTcb;
  1212. /* make sure to service interrupt asap */
  1213. if ((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0)) & TSS_INT_PENDING) {
  1214. pCurHcb->HCS_Phase = pCurHcb->HCS_JSStatus0 & TSS_PH_MASK;
  1215. pCurHcb->HCS_JSStatus1 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1);
  1216. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  1217. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* SCSI bus reset detected */
  1218. int_tul_scsi_rst(pCurHcb);
  1219. return;
  1220. }
  1221. if (pCurHcb->HCS_JSInt & TSS_RESEL_INT) { /* if selected/reselected interrupt */
  1222. if (int_tul_resel(pCurHcb) == 0)
  1223. tul_next_state(pCurHcb);
  1224. return;
  1225. }
  1226. if (pCurHcb->HCS_JSInt & TSS_SEL_TIMEOUT) {
  1227. int_tul_busfree(pCurHcb);
  1228. return;
  1229. }
  1230. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  1231. int_tul_busfree(pCurHcb); /* unexpected bus free or sel timeout */
  1232. return;
  1233. }
  1234. if (pCurHcb->HCS_JSInt & (TSS_FUNC_COMP | TSS_BUS_SERV)) { /* func complete or Bus service */
  1235. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL)
  1236. tul_next_state(pCurHcb);
  1237. return;
  1238. }
  1239. }
  1240. if (pCurHcb->HCS_ActScb != NULL)
  1241. return;
  1242. if ((pCurScb = tul_find_first_pend_scb(pCurHcb)) == NULL)
  1243. return;
  1244. /* program HBA's SCSI ID & target SCSI ID */
  1245. TUL_WR(pCurHcb->HCS_Base + TUL_SScsiId,
  1246. (pCurHcb->HCS_SCSI_ID << 4) | (pCurScb->SCB_Target & 0x0F));
  1247. if (pCurScb->SCB_Opcode == ExecSCSI) {
  1248. pCurTcb = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  1249. if (pCurScb->SCB_TagMsg)
  1250. pCurTcb->TCS_DrvFlags |= TCF_DRV_EN_TAG;
  1251. else
  1252. pCurTcb->TCS_DrvFlags &= ~TCF_DRV_EN_TAG;
  1253. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurTcb->TCS_JS_Period);
  1254. if ((pCurTcb->TCS_Flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) { /* do wdtr negotiation */
  1255. tul_select_atn_stop(pCurHcb, pCurScb);
  1256. } else {
  1257. if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync negotiation */
  1258. tul_select_atn_stop(pCurHcb, pCurScb);
  1259. } else {
  1260. if (pCurScb->SCB_TagMsg)
  1261. tul_select_atn3(pCurHcb, pCurScb);
  1262. else
  1263. tul_select_atn(pCurHcb, pCurScb);
  1264. }
  1265. }
  1266. if (pCurScb->SCB_Flags & SCF_POLL) {
  1267. while (wait_tulip(pCurHcb) != -1) {
  1268. if (tul_next_state(pCurHcb) == -1)
  1269. break;
  1270. }
  1271. }
  1272. } else if (pCurScb->SCB_Opcode == BusDevRst) {
  1273. tul_select_atn_stop(pCurHcb, pCurScb);
  1274. pCurScb->SCB_NxtStat = 8;
  1275. if (pCurScb->SCB_Flags & SCF_POLL) {
  1276. while (wait_tulip(pCurHcb) != -1) {
  1277. if (tul_next_state(pCurHcb) == -1)
  1278. break;
  1279. }
  1280. }
  1281. } else if (pCurScb->SCB_Opcode == AbortCmd) {
  1282. if (tul_abort_srb(pCurHcb, pCurScb->SCB_Srb) != 0) {
  1283. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1284. tul_release_scb(pCurHcb, pCurScb);
  1285. } else {
  1286. pCurScb->SCB_Opcode = BusDevRst;
  1287. tul_select_atn_stop(pCurHcb, pCurScb);
  1288. pCurScb->SCB_NxtStat = 8;
  1289. }
  1290. /* 08/03/98 */
  1291. } else {
  1292. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1293. pCurScb->SCB_HaStat = 0x16; /* bad command */
  1294. tul_append_done_scb(pCurHcb, pCurScb);
  1295. }
  1296. return;
  1297. }
  1298. /***************************************************************************/
  1299. int tul_next_state(HCS * pCurHcb)
  1300. {
  1301. int next;
  1302. next = pCurHcb->HCS_ActScb->SCB_NxtStat;
  1303. for (;;) {
  1304. switch (next) {
  1305. case 1:
  1306. next = tul_state_1(pCurHcb);
  1307. break;
  1308. case 2:
  1309. next = tul_state_2(pCurHcb);
  1310. break;
  1311. case 3:
  1312. next = tul_state_3(pCurHcb);
  1313. break;
  1314. case 4:
  1315. next = tul_state_4(pCurHcb);
  1316. break;
  1317. case 5:
  1318. next = tul_state_5(pCurHcb);
  1319. break;
  1320. case 6:
  1321. next = tul_state_6(pCurHcb);
  1322. break;
  1323. case 7:
  1324. next = tul_state_7(pCurHcb);
  1325. break;
  1326. case 8:
  1327. return (tul_bus_device_reset(pCurHcb));
  1328. default:
  1329. return (tul_bad_seq(pCurHcb));
  1330. }
  1331. if (next <= 0)
  1332. return next;
  1333. }
  1334. }
  1335. /***************************************************************************/
  1336. /* sTate after selection with attention & stop */
  1337. int tul_state_1(HCS * pCurHcb)
  1338. {
  1339. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1340. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1341. #if DEBUG_STATE
  1342. printk("-s1-");
  1343. #endif
  1344. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1345. tul_append_busy_scb(pCurHcb, pCurScb);
  1346. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1347. /* ATN on */
  1348. if (pCurHcb->HCS_Phase == MSG_OUT) {
  1349. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, (TSC_EN_BUS_IN | TSC_HW_RESELECT));
  1350. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  1351. if (pCurScb->SCB_TagMsg) {
  1352. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagMsg);
  1353. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagId);
  1354. }
  1355. if ((pCurTcb->TCS_Flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) {
  1356. pCurTcb->TCS_Flags |= TCF_WDTR_DONE;
  1357. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1358. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 2); /* Extended msg length */
  1359. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* Sync request */
  1360. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* Start from 16 bits */
  1361. } else if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) {
  1362. pCurTcb->TCS_Flags |= TCF_SYNC_DONE;
  1363. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1364. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* extended msg length */
  1365. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* sync request */
  1366. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, tul_rate_tbl[pCurTcb->TCS_Flags & TCF_SCSI_RATE]);
  1367. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MAX_OFFSET); /* REQ/ACK offset */
  1368. }
  1369. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1370. if (wait_tulip(pCurHcb) == -1)
  1371. return (-1);
  1372. }
  1373. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1374. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1375. return (3);
  1376. }
  1377. /***************************************************************************/
  1378. /* state after selection with attention */
  1379. /* state after selection with attention3 */
  1380. int tul_state_2(HCS * pCurHcb)
  1381. {
  1382. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1383. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1384. #if DEBUG_STATE
  1385. printk("-s2-");
  1386. #endif
  1387. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1388. tul_append_busy_scb(pCurHcb, pCurScb);
  1389. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1390. if (pCurHcb->HCS_JSStatus1 & TSS_CMD_PH_CMP) {
  1391. return (4);
  1392. }
  1393. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1394. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1395. return (3);
  1396. }
  1397. /***************************************************************************/
  1398. /* state before CDB xfer is done */
  1399. int tul_state_3(HCS * pCurHcb)
  1400. {
  1401. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1402. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1403. int i;
  1404. #if DEBUG_STATE
  1405. printk("-s3-");
  1406. #endif
  1407. for (;;) {
  1408. switch (pCurHcb->HCS_Phase) {
  1409. case CMD_OUT: /* Command out phase */
  1410. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  1411. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  1412. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1413. if (wait_tulip(pCurHcb) == -1)
  1414. return (-1);
  1415. if (pCurHcb->HCS_Phase == CMD_OUT) {
  1416. return (tul_bad_seq(pCurHcb));
  1417. }
  1418. return (4);
  1419. case MSG_IN: /* Message in phase */
  1420. pCurScb->SCB_NxtStat = 3;
  1421. if (tul_msgin(pCurHcb) == -1)
  1422. return (-1);
  1423. break;
  1424. case STATUS_IN: /* Status phase */
  1425. if (tul_status_msg(pCurHcb) == -1)
  1426. return (-1);
  1427. break;
  1428. case MSG_OUT: /* Message out phase */
  1429. if (pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) {
  1430. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1431. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1432. if (wait_tulip(pCurHcb) == -1)
  1433. return (-1);
  1434. } else {
  1435. pCurTcb->TCS_Flags |= TCF_SYNC_DONE;
  1436. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1437. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* ext. msg len */
  1438. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* sync request */
  1439. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, tul_rate_tbl[pCurTcb->TCS_Flags & TCF_SCSI_RATE]);
  1440. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MAX_OFFSET); /* REQ/ACK offset */
  1441. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1442. if (wait_tulip(pCurHcb) == -1)
  1443. return (-1);
  1444. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1445. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7));
  1446. }
  1447. break;
  1448. default:
  1449. return (tul_bad_seq(pCurHcb));
  1450. }
  1451. }
  1452. }
  1453. /***************************************************************************/
  1454. int tul_state_4(HCS * pCurHcb)
  1455. {
  1456. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1457. #if DEBUG_STATE
  1458. printk("-s4-");
  1459. #endif
  1460. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_NO_XF) {
  1461. return (6); /* Go to state 6 */
  1462. }
  1463. for (;;) {
  1464. if (pCurScb->SCB_BufLen == 0)
  1465. return (6); /* Go to state 6 */
  1466. switch (pCurHcb->HCS_Phase) {
  1467. case STATUS_IN: /* Status phase */
  1468. if ((pCurScb->SCB_Flags & SCF_DIR) != 0) { /* if direction bit set then report data underrun */
  1469. pCurScb->SCB_HaStat = HOST_DO_DU;
  1470. }
  1471. if ((tul_status_msg(pCurHcb)) == -1)
  1472. return (-1);
  1473. break;
  1474. case MSG_IN: /* Message in phase */
  1475. pCurScb->SCB_NxtStat = 0x4;
  1476. if (tul_msgin(pCurHcb) == -1)
  1477. return (-1);
  1478. break;
  1479. case MSG_OUT: /* Message out phase */
  1480. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1481. pCurScb->SCB_BufLen = 0;
  1482. pCurScb->SCB_HaStat = HOST_DO_DU;
  1483. if (tul_msgout_ide(pCurHcb) == -1)
  1484. return (-1);
  1485. return (6); /* Go to state 6 */
  1486. } else {
  1487. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1488. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1489. if (wait_tulip(pCurHcb) == -1)
  1490. return (-1);
  1491. }
  1492. break;
  1493. case DATA_IN: /* Data in phase */
  1494. return (tul_xfer_data_in(pCurHcb));
  1495. case DATA_OUT: /* Data out phase */
  1496. return (tul_xfer_data_out(pCurHcb));
  1497. default:
  1498. return (tul_bad_seq(pCurHcb));
  1499. }
  1500. }
  1501. }
  1502. /***************************************************************************/
  1503. /* state after dma xfer done or phase change before xfer done */
  1504. int tul_state_5(HCS * pCurHcb)
  1505. {
  1506. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1507. long cnt, xcnt; /* cannot use unsigned !! code: if (xcnt < 0) */
  1508. #if DEBUG_STATE
  1509. printk("-s5-");
  1510. #endif
  1511. /*------ get remaining count -------*/
  1512. cnt = TUL_RDLONG(pCurHcb->HCS_Base, TUL_SCnt0) & 0x0FFFFFF;
  1513. if (TUL_RD(pCurHcb->HCS_Base, TUL_XCmd) & 0x20) {
  1514. /* ----------------------- DATA_IN ----------------------------- */
  1515. /* check scsi parity error */
  1516. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1517. pCurScb->SCB_HaStat = HOST_DO_DU;
  1518. }
  1519. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* DMA xfer pending, Send STOP */
  1520. /* tell Hardware scsi xfer has been terminated */
  1521. TUL_WR(pCurHcb->HCS_Base + TUL_XCtrl, TUL_RD(pCurHcb->HCS_Base, TUL_XCtrl) | 0x80);
  1522. /* wait until DMA xfer not pending */
  1523. while (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND);
  1524. }
  1525. } else {
  1526. /*-------- DATA OUT -----------*/
  1527. if ((TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1) & TSS_XFER_CMP) == 0) {
  1528. if (pCurHcb->HCS_ActTcs->TCS_JS_Period & TSC_WIDE_SCSI)
  1529. cnt += (TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F) << 1;
  1530. else
  1531. cnt += (TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F);
  1532. }
  1533. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */
  1534. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT);
  1535. /* wait Abort DMA xfer done */
  1536. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & XABT) == 0);
  1537. }
  1538. if ((cnt == 1) && (pCurHcb->HCS_Phase == DATA_OUT)) {
  1539. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1540. if (wait_tulip(pCurHcb) == -1) {
  1541. return (-1);
  1542. }
  1543. cnt = 0;
  1544. } else {
  1545. if ((TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1) & TSS_XFER_CMP) == 0)
  1546. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1547. }
  1548. }
  1549. if (cnt == 0) {
  1550. pCurScb->SCB_BufLen = 0;
  1551. return (6); /* Go to state 6 */
  1552. }
  1553. /* Update active data pointer */
  1554. xcnt = (long) pCurScb->SCB_BufLen - cnt; /* xcnt== bytes already xferred */
  1555. pCurScb->SCB_BufLen = (U32) cnt; /* cnt == bytes left to be xferred */
  1556. if (pCurScb->SCB_Flags & SCF_SG) {
  1557. register SG *sgp;
  1558. ULONG i;
  1559. sgp = &pCurScb->SCB_SGList[pCurScb->SCB_SGIdx];
  1560. for (i = pCurScb->SCB_SGIdx; i < pCurScb->SCB_SGMax; sgp++, i++) {
  1561. xcnt -= (long) sgp->SG_Len;
  1562. if (xcnt < 0) { /* this sgp xfer half done */
  1563. xcnt += (long) sgp->SG_Len; /* xcnt == bytes xferred in this sgp */
  1564. sgp->SG_Ptr += (U32) xcnt; /* new ptr to be xfer */
  1565. sgp->SG_Len -= (U32) xcnt; /* new len to be xfer */
  1566. pCurScb->SCB_BufPtr += ((U32) (i - pCurScb->SCB_SGIdx) << 3);
  1567. /* new SG table ptr */
  1568. pCurScb->SCB_SGLen = (BYTE) (pCurScb->SCB_SGMax - i);
  1569. /* new SG table len */
  1570. pCurScb->SCB_SGIdx = (WORD) i;
  1571. /* for next disc and come in this loop */
  1572. return (4); /* Go to state 4 */
  1573. }
  1574. /* else (xcnt >= 0 , i.e. this sgp already xferred */
  1575. } /* for */
  1576. return (6); /* Go to state 6 */
  1577. } else {
  1578. pCurScb->SCB_BufPtr += (U32) xcnt;
  1579. }
  1580. return (4); /* Go to state 4 */
  1581. }
  1582. /***************************************************************************/
  1583. /* state after Data phase */
  1584. int tul_state_6(HCS * pCurHcb)
  1585. {
  1586. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1587. #if DEBUG_STATE
  1588. printk("-s6-");
  1589. #endif
  1590. for (;;) {
  1591. switch (pCurHcb->HCS_Phase) {
  1592. case STATUS_IN: /* Status phase */
  1593. if ((tul_status_msg(pCurHcb)) == -1)
  1594. return (-1);
  1595. break;
  1596. case MSG_IN: /* Message in phase */
  1597. pCurScb->SCB_NxtStat = 6;
  1598. if ((tul_msgin(pCurHcb)) == -1)
  1599. return (-1);
  1600. break;
  1601. case MSG_OUT: /* Message out phase */
  1602. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1603. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1604. if (wait_tulip(pCurHcb) == -1)
  1605. return (-1);
  1606. break;
  1607. case DATA_IN: /* Data in phase */
  1608. return (tul_xpad_in(pCurHcb));
  1609. case DATA_OUT: /* Data out phase */
  1610. return (tul_xpad_out(pCurHcb));
  1611. default:
  1612. return (tul_bad_seq(pCurHcb));
  1613. }
  1614. }
  1615. }
  1616. /***************************************************************************/
  1617. int tul_state_7(HCS * pCurHcb)
  1618. {
  1619. int cnt, i;
  1620. #if DEBUG_STATE
  1621. printk("-s7-");
  1622. #endif
  1623. /* flush SCSI FIFO */
  1624. cnt = TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F;
  1625. if (cnt) {
  1626. for (i = 0; i < cnt; i++)
  1627. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1628. }
  1629. switch (pCurHcb->HCS_Phase) {
  1630. case DATA_IN: /* Data in phase */
  1631. case DATA_OUT: /* Data out phase */
  1632. return (tul_bad_seq(pCurHcb));
  1633. default:
  1634. return (6); /* Go to state 6 */
  1635. }
  1636. }
  1637. /***************************************************************************/
  1638. int tul_xfer_data_in(HCS * pCurHcb)
  1639. {
  1640. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1641. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_DOUT) {
  1642. return (6); /* wrong direction */
  1643. }
  1644. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, pCurScb->SCB_BufLen);
  1645. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_DMA_IN); /* 7/25/95 */
  1646. if (pCurScb->SCB_Flags & SCF_SG) { /* S/G xfer */
  1647. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, ((ULONG) pCurScb->SCB_SGLen) << 3);
  1648. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1649. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_SG_IN);
  1650. } else {
  1651. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, pCurScb->SCB_BufLen);
  1652. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1653. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_IN);
  1654. }
  1655. pCurScb->SCB_NxtStat = 0x5;
  1656. return (0); /* return to OS, wait xfer done , let jas_isr come in */
  1657. }
  1658. /***************************************************************************/
  1659. int tul_xfer_data_out(HCS * pCurHcb)
  1660. {
  1661. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1662. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_DIN) {
  1663. return (6); /* wrong direction */
  1664. }
  1665. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, pCurScb->SCB_BufLen);
  1666. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_DMA_OUT);
  1667. if (pCurScb->SCB_Flags & SCF_SG) { /* S/G xfer */
  1668. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, ((ULONG) pCurScb->SCB_SGLen) << 3);
  1669. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1670. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_SG_OUT);
  1671. } else {
  1672. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, pCurScb->SCB_BufLen);
  1673. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1674. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_OUT);
  1675. }
  1676. pCurScb->SCB_NxtStat = 0x5;
  1677. return (0); /* return to OS, wait xfer done , let jas_isr come in */
  1678. }
  1679. /***************************************************************************/
  1680. int tul_xpad_in(HCS * pCurHcb)
  1681. {
  1682. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1683. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1684. if ((pCurScb->SCB_Flags & SCF_DIR) != SCF_NO_DCHK) {
  1685. pCurScb->SCB_HaStat = HOST_DO_DU; /* over run */
  1686. }
  1687. for (;;) {
  1688. if (pCurTcb->TCS_JS_Period & TSC_WIDE_SCSI)
  1689. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 2);
  1690. else
  1691. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1692. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1693. if ((wait_tulip(pCurHcb)) == -1) {
  1694. return (-1);
  1695. }
  1696. if (pCurHcb->HCS_Phase != DATA_IN) {
  1697. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1698. return (6);
  1699. }
  1700. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1701. }
  1702. }
  1703. int tul_xpad_out(HCS * pCurHcb)
  1704. {
  1705. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1706. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1707. if ((pCurScb->SCB_Flags & SCF_DIR) != SCF_NO_DCHK) {
  1708. pCurScb->SCB_HaStat = HOST_DO_DU; /* over run */
  1709. }
  1710. for (;;) {
  1711. if (pCurTcb->TCS_JS_Period & TSC_WIDE_SCSI)
  1712. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 2);
  1713. else
  1714. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1715. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 0);
  1716. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1717. if ((wait_tulip(pCurHcb)) == -1) {
  1718. return (-1);
  1719. }
  1720. if (pCurHcb->HCS_Phase != DATA_OUT) { /* Disable wide CPU to allow read 16 bits */
  1721. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT);
  1722. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1723. return (6);
  1724. }
  1725. }
  1726. }
  1727. /***************************************************************************/
  1728. int tul_status_msg(HCS * pCurHcb)
  1729. { /* status & MSG_IN */
  1730. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1731. BYTE msg;
  1732. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_CMD_COMP);
  1733. if ((wait_tulip(pCurHcb)) == -1) {
  1734. return (-1);
  1735. }
  1736. /* get status */
  1737. pCurScb->SCB_TaStat = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1738. if (pCurHcb->HCS_Phase == MSG_OUT) {
  1739. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1740. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_PARITY);
  1741. } else {
  1742. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP);
  1743. }
  1744. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1745. return (wait_tulip(pCurHcb));
  1746. }
  1747. if (pCurHcb->HCS_Phase == MSG_IN) {
  1748. msg = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1749. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) { /* Parity error */
  1750. if ((tul_msgin_accept(pCurHcb)) == -1)
  1751. return (-1);
  1752. if (pCurHcb->HCS_Phase != MSG_OUT)
  1753. return (tul_bad_seq(pCurHcb));
  1754. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_PARITY);
  1755. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1756. return (wait_tulip(pCurHcb));
  1757. }
  1758. if (msg == 0) { /* Command complete */
  1759. if ((pCurScb->SCB_TaStat & 0x18) == 0x10) { /* No link support */
  1760. return (tul_bad_seq(pCurHcb));
  1761. }
  1762. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1763. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1764. return tul_wait_done_disc(pCurHcb);
  1765. }
  1766. if ((msg == MSG_LINK_COMP) || (msg == MSG_LINK_FLAG)) {
  1767. if ((pCurScb->SCB_TaStat & 0x18) == 0x10)
  1768. return (tul_msgin_accept(pCurHcb));
  1769. }
  1770. }
  1771. return (tul_bad_seq(pCurHcb));
  1772. }
  1773. /***************************************************************************/
  1774. /* scsi bus free */
  1775. int int_tul_busfree(HCS * pCurHcb)
  1776. {
  1777. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1778. if (pCurScb != NULL) {
  1779. if (pCurScb->SCB_Status & SCB_SELECT) { /* selection timeout */
  1780. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1781. pCurScb->SCB_HaStat = HOST_SEL_TOUT;
  1782. tul_append_done_scb(pCurHcb, pCurScb);
  1783. } else { /* Unexpected bus free */
  1784. tul_unlink_busy_scb(pCurHcb, pCurScb);
  1785. pCurScb->SCB_HaStat = HOST_BUS_FREE;
  1786. tul_append_done_scb(pCurHcb, pCurScb);
  1787. }
  1788. pCurHcb->HCS_ActScb = NULL;
  1789. pCurHcb->HCS_ActTcs = NULL;
  1790. }
  1791. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  1792. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  1793. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  1794. return (-1);
  1795. }
  1796. /***************************************************************************/
  1797. /* scsi bus reset */
  1798. static int int_tul_scsi_rst(HCS * pCurHcb)
  1799. {
  1800. SCB *pCurScb;
  1801. int i;
  1802. /* if DMA xfer is pending, abort DMA xfer */
  1803. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & 0x01) {
  1804. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
  1805. /* wait Abort DMA xfer done */
  1806. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & 0x04) == 0);
  1807. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1808. }
  1809. /* Abort all active & disconnected scb */
  1810. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  1811. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1812. tul_append_done_scb(pCurHcb, pCurScb);
  1813. }
  1814. pCurHcb->HCS_ActScb = NULL;
  1815. pCurHcb->HCS_ActTcs = NULL;
  1816. /* clr sync nego. done flag */
  1817. for (i = 0; i < pCurHcb->HCS_MaxTar; i++) {
  1818. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  1819. }
  1820. return (-1);
  1821. }
  1822. /***************************************************************************/
  1823. /* scsi reselection */
  1824. int int_tul_resel(HCS * pCurHcb)
  1825. {
  1826. SCB *pCurScb;
  1827. TCS *pCurTcb;
  1828. BYTE tag, msg = 0;
  1829. BYTE tar, lun;
  1830. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) {
  1831. if (pCurScb->SCB_Status & SCB_SELECT) { /* if waiting for selection complete */
  1832. pCurScb->SCB_Status &= ~SCB_SELECT;
  1833. }
  1834. pCurHcb->HCS_ActScb = NULL;
  1835. }
  1836. /* --------- get target id---------------------- */
  1837. tar = TUL_RD(pCurHcb->HCS_Base, TUL_SBusId);
  1838. /* ------ get LUN from Identify message----------- */
  1839. lun = TUL_RD(pCurHcb->HCS_Base, TUL_SIdent) & 0x0F;
  1840. /* 07/22/98 from 0x1F -> 0x0F */
  1841. pCurTcb = &pCurHcb->HCS_Tcs[tar];
  1842. pCurHcb->HCS_ActTcs = pCurTcb;
  1843. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1844. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurTcb->TCS_JS_Period);
  1845. /* ------------- tag queueing ? ------------------- */
  1846. if (pCurTcb->TCS_DrvFlags & TCF_DRV_EN_TAG) {
  1847. if ((tul_msgin_accept(pCurHcb)) == -1)
  1848. return (-1);
  1849. if (pCurHcb->HCS_Phase != MSG_IN)
  1850. goto no_tag;
  1851. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1852. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1853. if ((wait_tulip(pCurHcb)) == -1)
  1854. return (-1);
  1855. msg = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* Read Tag Message */
  1856. if ((msg < MSG_STAG) || (msg > MSG_OTAG)) /* Is simple Tag */
  1857. goto no_tag;
  1858. if ((tul_msgin_accept(pCurHcb)) == -1)
  1859. return (-1);
  1860. if (pCurHcb->HCS_Phase != MSG_IN)
  1861. goto no_tag;
  1862. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1863. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1864. if ((wait_tulip(pCurHcb)) == -1)
  1865. return (-1);
  1866. tag = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* Read Tag ID */
  1867. pCurScb = pCurHcb->HCS_Scb + tag;
  1868. if ((pCurScb->SCB_Target != tar) || (pCurScb->SCB_Lun != lun)) {
  1869. return tul_msgout_abort_tag(pCurHcb);
  1870. }
  1871. if (pCurScb->SCB_Status != SCB_BUSY) { /* 03/24/95 */
  1872. return tul_msgout_abort_tag(pCurHcb);
  1873. }
  1874. pCurHcb->HCS_ActScb = pCurScb;
  1875. if ((tul_msgin_accept(pCurHcb)) == -1)
  1876. return (-1);
  1877. } else { /* No tag */
  1878. no_tag:
  1879. if ((pCurScb = tul_find_busy_scb(pCurHcb, tar | (lun << 8))) == NULL) {
  1880. return tul_msgout_abort_targ(pCurHcb);
  1881. }
  1882. pCurHcb->HCS_ActScb = pCurScb;
  1883. if (!(pCurTcb->TCS_DrvFlags & TCF_DRV_EN_TAG)) {
  1884. if ((tul_msgin_accept(pCurHcb)) == -1)
  1885. return (-1);
  1886. }
  1887. }
  1888. return 0;
  1889. }
  1890. /***************************************************************************/
  1891. static int int_tul_bad_seq(HCS * pCurHcb)
  1892. { /* target wrong phase */
  1893. SCB *pCurScb;
  1894. int i;
  1895. tul_reset_scsi(pCurHcb, 10);
  1896. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  1897. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1898. tul_append_done_scb(pCurHcb, pCurScb);
  1899. }
  1900. for (i = 0; i < pCurHcb->HCS_MaxTar; i++) {
  1901. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  1902. }
  1903. return (-1);
  1904. }
  1905. /***************************************************************************/
  1906. int tul_msgout_abort_targ(HCS * pCurHcb)
  1907. {
  1908. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1909. if (tul_msgin_accept(pCurHcb) == -1)
  1910. return (-1);
  1911. if (pCurHcb->HCS_Phase != MSG_OUT)
  1912. return (tul_bad_seq(pCurHcb));
  1913. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_ABORT);
  1914. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1915. return tul_wait_disc(pCurHcb);
  1916. }
  1917. /***************************************************************************/
  1918. int tul_msgout_abort_tag(HCS * pCurHcb)
  1919. {
  1920. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1921. if (tul_msgin_accept(pCurHcb) == -1)
  1922. return (-1);
  1923. if (pCurHcb->HCS_Phase != MSG_OUT)
  1924. return (tul_bad_seq(pCurHcb));
  1925. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_ABORT_TAG);
  1926. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1927. return tul_wait_disc(pCurHcb);
  1928. }
  1929. /***************************************************************************/
  1930. int tul_msgin(HCS * pCurHcb)
  1931. {
  1932. TCS *pCurTcb;
  1933. for (;;) {
  1934. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1935. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1936. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1937. if ((wait_tulip(pCurHcb)) == -1)
  1938. return (-1);
  1939. switch (TUL_RD(pCurHcb->HCS_Base, TUL_SFifo)) {
  1940. case MSG_DISC: /* Disconnect msg */
  1941. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1942. return tul_wait_disc(pCurHcb);
  1943. case MSG_SDP:
  1944. case MSG_RESTORE:
  1945. case MSG_NOP:
  1946. tul_msgin_accept(pCurHcb);
  1947. break;
  1948. case MSG_REJ: /* Clear ATN first */
  1949. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal,
  1950. (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1951. pCurTcb = pCurHcb->HCS_ActTcs;
  1952. if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync nego */
  1953. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1954. }
  1955. tul_msgin_accept(pCurHcb);
  1956. break;
  1957. case MSG_EXTEND: /* extended msg */
  1958. tul_msgin_extend(pCurHcb);
  1959. break;
  1960. case MSG_IGNOREWIDE:
  1961. tul_msgin_accept(pCurHcb);
  1962. break;
  1963. /* get */
  1964. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1965. if (wait_tulip(pCurHcb) == -1)
  1966. return -1;
  1967. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 0); /* put pad */
  1968. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* get IGNORE field */
  1969. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* get pad */
  1970. tul_msgin_accept(pCurHcb);
  1971. break;
  1972. case MSG_COMP:
  1973. {
  1974. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1975. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1976. return tul_wait_done_disc(pCurHcb);
  1977. }
  1978. default:
  1979. tul_msgout_reject(pCurHcb);
  1980. break;
  1981. }
  1982. if (pCurHcb->HCS_Phase != MSG_IN)
  1983. return (pCurHcb->HCS_Phase);
  1984. }
  1985. /* statement won't reach here */
  1986. }
  1987. /***************************************************************************/
  1988. int tul_msgout_reject(HCS * pCurHcb)
  1989. {
  1990. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1991. if ((tul_msgin_accept(pCurHcb)) == -1)
  1992. return (-1);
  1993. if (pCurHcb->HCS_Phase == MSG_OUT) {
  1994. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_REJ); /* Msg reject */
  1995. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1996. return (wait_tulip(pCurHcb));
  1997. }
  1998. return (pCurHcb->HCS_Phase);
  1999. }
  2000. /***************************************************************************/
  2001. int tul_msgout_ide(HCS * pCurHcb)
  2002. {
  2003. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_IDE); /* Initiator Detected Error */
  2004. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2005. return (wait_tulip(pCurHcb));
  2006. }
  2007. /***************************************************************************/
  2008. int tul_msgin_extend(HCS * pCurHcb)
  2009. {
  2010. BYTE len, idx;
  2011. if (tul_msgin_accept(pCurHcb) != MSG_IN)
  2012. return (pCurHcb->HCS_Phase);
  2013. /* Get extended msg length */
  2014. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  2015. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  2016. if (wait_tulip(pCurHcb) == -1)
  2017. return (-1);
  2018. len = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  2019. pCurHcb->HCS_Msg[0] = len;
  2020. for (idx = 1; len != 0; len--) {
  2021. if ((tul_msgin_accept(pCurHcb)) != MSG_IN)
  2022. return (pCurHcb->HCS_Phase);
  2023. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  2024. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  2025. if (wait_tulip(pCurHcb) == -1)
  2026. return (-1);
  2027. pCurHcb->HCS_Msg[idx++] = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  2028. }
  2029. if (pCurHcb->HCS_Msg[1] == 1) { /* if it's synchronous data transfer request */
  2030. if (pCurHcb->HCS_Msg[0] != 3) /* if length is not right */
  2031. return (tul_msgout_reject(pCurHcb));
  2032. if (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_SYNC_NEGO) { /* Set OFFSET=0 to do async, nego back */
  2033. pCurHcb->HCS_Msg[3] = 0;
  2034. } else {
  2035. if ((tul_msgin_sync(pCurHcb) == 0) &&
  2036. (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_SYNC_DONE)) {
  2037. tul_sync_done(pCurHcb);
  2038. return (tul_msgin_accept(pCurHcb));
  2039. }
  2040. }
  2041. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2042. if ((tul_msgin_accept(pCurHcb)) != MSG_OUT)
  2043. return (pCurHcb->HCS_Phase);
  2044. /* sync msg out */
  2045. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  2046. tul_sync_done(pCurHcb);
  2047. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  2048. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3);
  2049. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1);
  2050. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[2]);
  2051. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[3]);
  2052. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2053. return (wait_tulip(pCurHcb));
  2054. }
  2055. if ((pCurHcb->HCS_Msg[0] != 2) || (pCurHcb->HCS_Msg[1] != 3))
  2056. return (tul_msgout_reject(pCurHcb));
  2057. /* if it's WIDE DATA XFER REQ */
  2058. if (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_WDTR) {
  2059. pCurHcb->HCS_Msg[2] = 0;
  2060. } else {
  2061. if (pCurHcb->HCS_Msg[2] > 2) /* > 32 bits */
  2062. return (tul_msgout_reject(pCurHcb));
  2063. if (pCurHcb->HCS_Msg[2] == 2) { /* == 32 */
  2064. pCurHcb->HCS_Msg[2] = 1;
  2065. } else {
  2066. if ((pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_WDTR) == 0) {
  2067. wdtr_done(pCurHcb);
  2068. if ((pCurHcb->HCS_ActTcs->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0)
  2069. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2070. return (tul_msgin_accept(pCurHcb));
  2071. }
  2072. }
  2073. }
  2074. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2075. if (tul_msgin_accept(pCurHcb) != MSG_OUT)
  2076. return (pCurHcb->HCS_Phase);
  2077. /* WDTR msg out */
  2078. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  2079. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 2);
  2080. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3);
  2081. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[2]);
  2082. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2083. return (wait_tulip(pCurHcb));
  2084. }
  2085. /***************************************************************************/
  2086. int tul_msgin_sync(HCS * pCurHcb)
  2087. {
  2088. char default_period;
  2089. default_period = tul_rate_tbl[pCurHcb->HCS_ActTcs->TCS_Flags & TCF_SCSI_RATE];
  2090. if (pCurHcb->HCS_Msg[3] > MAX_OFFSET) {
  2091. pCurHcb->HCS_Msg[3] = MAX_OFFSET;
  2092. if (pCurHcb->HCS_Msg[2] < default_period) {
  2093. pCurHcb->HCS_Msg[2] = default_period;
  2094. return 1;
  2095. }
  2096. if (pCurHcb->HCS_Msg[2] >= 59) { /* Change to async */
  2097. pCurHcb->HCS_Msg[3] = 0;
  2098. }
  2099. return 1;
  2100. }
  2101. /* offset requests asynchronous transfers ? */
  2102. if (pCurHcb->HCS_Msg[3] == 0) {
  2103. return 0;
  2104. }
  2105. if (pCurHcb->HCS_Msg[2] < default_period) {
  2106. pCurHcb->HCS_Msg[2] = default_period;
  2107. return 1;
  2108. }
  2109. if (pCurHcb->HCS_Msg[2] >= 59) {
  2110. pCurHcb->HCS_Msg[3] = 0;
  2111. return 1;
  2112. }
  2113. return 0;
  2114. }
  2115. /***************************************************************************/
  2116. int wdtr_done(HCS * pCurHcb)
  2117. {
  2118. pCurHcb->HCS_ActTcs->TCS_Flags &= ~TCF_SYNC_DONE;
  2119. pCurHcb->HCS_ActTcs->TCS_Flags |= TCF_WDTR_DONE;
  2120. pCurHcb->HCS_ActTcs->TCS_JS_Period = 0;
  2121. if (pCurHcb->HCS_Msg[2]) { /* if 16 bit */
  2122. pCurHcb->HCS_ActTcs->TCS_JS_Period |= TSC_WIDE_SCSI;
  2123. }
  2124. pCurHcb->HCS_ActTcs->TCS_SConfig0 &= ~TSC_ALT_PERIOD;
  2125. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_ActTcs->TCS_SConfig0);
  2126. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurHcb->HCS_ActTcs->TCS_JS_Period);
  2127. return 1;
  2128. }
  2129. /***************************************************************************/
  2130. int tul_sync_done(HCS * pCurHcb)
  2131. {
  2132. int i;
  2133. pCurHcb->HCS_ActTcs->TCS_Flags |= TCF_SYNC_DONE;
  2134. if (pCurHcb->HCS_Msg[3]) {
  2135. pCurHcb->HCS_ActTcs->TCS_JS_Period |= pCurHcb->HCS_Msg[3];
  2136. for (i = 0; i < 8; i++) {
  2137. if (tul_rate_tbl[i] >= pCurHcb->HCS_Msg[2]) /* pick the big one */
  2138. break;
  2139. }
  2140. pCurHcb->HCS_ActTcs->TCS_JS_Period |= (i << 4);
  2141. pCurHcb->HCS_ActTcs->TCS_SConfig0 |= TSC_ALT_PERIOD;
  2142. }
  2143. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_ActTcs->TCS_SConfig0);
  2144. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurHcb->HCS_ActTcs->TCS_JS_Period);
  2145. return (-1);
  2146. }
  2147. int tul_post_scsi_rst(HCS * pCurHcb)
  2148. {
  2149. SCB *pCurScb;
  2150. TCS *pCurTcb;
  2151. int i;
  2152. pCurHcb->HCS_ActScb = NULL;
  2153. pCurHcb->HCS_ActTcs = NULL;
  2154. pCurHcb->HCS_Flags = 0;
  2155. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  2156. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  2157. tul_append_done_scb(pCurHcb, pCurScb);
  2158. }
  2159. /* clear sync done flag */
  2160. pCurTcb = &pCurHcb->HCS_Tcs[0];
  2161. for (i = 0; i < pCurHcb->HCS_MaxTar; pCurTcb++, i++) {
  2162. pCurTcb->TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  2163. /* Initialize the sync. xfer register values to an asyn xfer */
  2164. pCurTcb->TCS_JS_Period = 0;
  2165. pCurTcb->TCS_SConfig0 = pCurHcb->HCS_SConf1;
  2166. pCurHcb->HCS_ActTags[0] = 0; /* 07/22/98 */
  2167. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~TCF_BUSY; /* 07/22/98 */
  2168. } /* for */
  2169. return (-1);
  2170. }
  2171. /***************************************************************************/
  2172. void tul_select_atn_stop(HCS * pCurHcb, SCB * pCurScb)
  2173. {
  2174. pCurScb->SCB_Status |= SCB_SELECT;
  2175. pCurScb->SCB_NxtStat = 0x1;
  2176. pCurHcb->HCS_ActScb = pCurScb;
  2177. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2178. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SELATNSTOP);
  2179. return;
  2180. }
  2181. /***************************************************************************/
  2182. void tul_select_atn(HCS * pCurHcb, SCB * pCurScb)
  2183. {
  2184. int i;
  2185. pCurScb->SCB_Status |= SCB_SELECT;
  2186. pCurScb->SCB_NxtStat = 0x2;
  2187. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  2188. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  2189. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  2190. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2191. pCurHcb->HCS_ActScb = pCurScb;
  2192. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SEL_ATN);
  2193. return;
  2194. }
  2195. /***************************************************************************/
  2196. void tul_select_atn3(HCS * pCurHcb, SCB * pCurScb)
  2197. {
  2198. int i;
  2199. pCurScb->SCB_Status |= SCB_SELECT;
  2200. pCurScb->SCB_NxtStat = 0x2;
  2201. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  2202. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagMsg);
  2203. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagId);
  2204. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  2205. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  2206. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2207. pCurHcb->HCS_ActScb = pCurScb;
  2208. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SEL_ATN3);
  2209. return;
  2210. }
  2211. /***************************************************************************/
  2212. /* SCSI Bus Device Reset */
  2213. int tul_bus_device_reset(HCS * pCurHcb)
  2214. {
  2215. SCB *pCurScb = pCurHcb->HCS_ActScb;
  2216. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  2217. SCB *pTmpScb, *pPrevScb;
  2218. BYTE tar;
  2219. if (pCurHcb->HCS_Phase != MSG_OUT) {
  2220. return (int_tul_bad_seq(pCurHcb)); /* Unexpected phase */
  2221. }
  2222. tul_unlink_pend_scb(pCurHcb, pCurScb);
  2223. tul_release_scb(pCurHcb, pCurScb);
  2224. tar = pCurScb->SCB_Target; /* target */
  2225. pCurTcb->TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE | TCF_BUSY);
  2226. /* clr sync. nego & WDTR flags 07/22/98 */
  2227. /* abort all SCB with same target */
  2228. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  2229. while (pTmpScb != NULL) {
  2230. if (pTmpScb->SCB_Target == tar) {
  2231. /* unlink it */
  2232. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  2233. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  2234. pCurHcb->HCS_LastBusy = NULL;
  2235. } else {
  2236. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  2237. if (pTmpScb == pCurHcb->HCS_LastBusy)
  2238. pCurHcb->HCS_LastBusy = pPrevScb;
  2239. }
  2240. pTmpScb->SCB_HaStat = HOST_ABORTED;
  2241. tul_append_done_scb(pCurHcb, pTmpScb);
  2242. }
  2243. /* Previous haven't change */
  2244. else {
  2245. pPrevScb = pTmpScb;
  2246. }
  2247. pTmpScb = pTmpScb->SCB_NxtScb;
  2248. }
  2249. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_DEVRST);
  2250. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2251. return tul_wait_disc(pCurHcb);
  2252. }
  2253. /***************************************************************************/
  2254. int tul_msgin_accept(HCS * pCurHcb)
  2255. {
  2256. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  2257. return (wait_tulip(pCurHcb));
  2258. }
  2259. /***************************************************************************/
  2260. int wait_tulip(HCS * pCurHcb)
  2261. {
  2262. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2263. & TSS_INT_PENDING));
  2264. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2265. pCurHcb->HCS_Phase = pCurHcb->HCS_JSStatus0 & TSS_PH_MASK;
  2266. pCurHcb->HCS_JSStatus1 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1);
  2267. if (pCurHcb->HCS_JSInt & TSS_RESEL_INT) { /* if SCSI bus reset detected */
  2268. return (int_tul_resel(pCurHcb));
  2269. }
  2270. if (pCurHcb->HCS_JSInt & TSS_SEL_TIMEOUT) { /* if selected/reselected timeout interrupt */
  2271. return (int_tul_busfree(pCurHcb));
  2272. }
  2273. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2274. return (int_tul_scsi_rst(pCurHcb));
  2275. }
  2276. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2277. if (pCurHcb->HCS_Flags & HCF_EXPECT_DONE_DISC) {
  2278. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2279. tul_unlink_busy_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2280. pCurHcb->HCS_ActScb->SCB_HaStat = 0;
  2281. tul_append_done_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2282. pCurHcb->HCS_ActScb = NULL;
  2283. pCurHcb->HCS_ActTcs = NULL;
  2284. pCurHcb->HCS_Flags &= ~HCF_EXPECT_DONE_DISC;
  2285. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2286. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2287. return (-1);
  2288. }
  2289. if (pCurHcb->HCS_Flags & HCF_EXPECT_DISC) {
  2290. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2291. pCurHcb->HCS_ActScb = NULL;
  2292. pCurHcb->HCS_ActTcs = NULL;
  2293. pCurHcb->HCS_Flags &= ~HCF_EXPECT_DISC;
  2294. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2295. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2296. return (-1);
  2297. }
  2298. return (int_tul_busfree(pCurHcb));
  2299. }
  2300. if (pCurHcb->HCS_JSInt & (TSS_FUNC_COMP | TSS_BUS_SERV)) {
  2301. return (pCurHcb->HCS_Phase);
  2302. }
  2303. return (pCurHcb->HCS_Phase);
  2304. }
  2305. /***************************************************************************/
  2306. int tul_wait_disc(HCS * pCurHcb)
  2307. {
  2308. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2309. & TSS_INT_PENDING));
  2310. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2311. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2312. return (int_tul_scsi_rst(pCurHcb));
  2313. }
  2314. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2315. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2316. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2317. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2318. pCurHcb->HCS_ActScb = NULL;
  2319. return (-1);
  2320. }
  2321. return (tul_bad_seq(pCurHcb));
  2322. }
  2323. /***************************************************************************/
  2324. int tul_wait_done_disc(HCS * pCurHcb)
  2325. {
  2326. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2327. & TSS_INT_PENDING));
  2328. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2329. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2330. return (int_tul_scsi_rst(pCurHcb));
  2331. }
  2332. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2333. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2334. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2335. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2336. tul_unlink_busy_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2337. tul_append_done_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2338. pCurHcb->HCS_ActScb = NULL;
  2339. return (-1);
  2340. }
  2341. return (tul_bad_seq(pCurHcb));
  2342. }
  2343. static irqreturn_t i91u_intr(int irqno, void *dev_id, struct pt_regs *regs)
  2344. {
  2345. struct Scsi_Host *dev = dev_id;
  2346. unsigned long flags;
  2347. spin_lock_irqsave(dev->host_lock, flags);
  2348. tul_isr((HCS *)dev->base);
  2349. spin_unlock_irqrestore(dev->host_lock, flags);
  2350. return IRQ_HANDLED;
  2351. }
  2352. static int tul_NewReturnNumberOfAdapters(void)
  2353. {
  2354. struct pci_dev *pDev = NULL; /* Start from none */
  2355. int iAdapters = 0;
  2356. long dRegValue;
  2357. WORD wBIOS;
  2358. int i = 0;
  2359. init_i91uAdapter_table();
  2360. for (i = 0; i < TULSZ(i91u_pci_devices); i++)
  2361. {
  2362. while ((pDev = pci_find_device(i91u_pci_devices[i].vendor_id, i91u_pci_devices[i].device_id, pDev)) != NULL) {
  2363. if (pci_enable_device(pDev))
  2364. continue;
  2365. pci_read_config_dword(pDev, 0x44, (u32 *) & dRegValue);
  2366. wBIOS = (UWORD) (dRegValue & 0xFF);
  2367. if (((dRegValue & 0xFF00) >> 8) == 0xFF)
  2368. dRegValue = 0;
  2369. wBIOS = (wBIOS << 8) + ((UWORD) ((dRegValue & 0xFF00) >> 8));
  2370. if (pci_set_dma_mask(pDev, 0xffffffff)) {
  2371. printk(KERN_WARNING
  2372. "i91u: Could not set 32 bit DMA mask\n");
  2373. continue;
  2374. }
  2375. if (Addi91u_into_Adapter_table(wBIOS,
  2376. (pDev->resource[0].start),
  2377. pDev->irq,
  2378. pDev->bus->number,
  2379. (pDev->devfn >> 3)
  2380. ) == 0)
  2381. iAdapters++;
  2382. }
  2383. }
  2384. return (iAdapters);
  2385. }
  2386. static int i91u_detect(struct scsi_host_template * tpnt)
  2387. {
  2388. HCS *pHCB;
  2389. struct Scsi_Host *hreg;
  2390. unsigned long i; /* 01/14/98 */
  2391. int ok = 0, iAdapters;
  2392. ULONG dBiosAdr;
  2393. BYTE *pbBiosAdr;
  2394. /* Get total number of adapters in the motherboard */
  2395. iAdapters = tul_NewReturnNumberOfAdapters();
  2396. if (iAdapters == 0) /* If no tulip founded, return */
  2397. return (0);
  2398. tul_num_ch = (iAdapters > tul_num_ch) ? tul_num_ch : iAdapters;
  2399. /* Update actually channel number */
  2400. if (tul_tag_enable) { /* 1.01i */
  2401. tul_num_scb = MAX_TARGETS * i91u_MAXQUEUE;
  2402. } else {
  2403. tul_num_scb = MAX_TARGETS + 3; /* 1-tape, 1-CD_ROM, 1- extra */
  2404. } /* Update actually SCBs per adapter */
  2405. /* Get total memory needed for HCS */
  2406. i = tul_num_ch * sizeof(HCS);
  2407. memset((unsigned char *) &tul_hcs[0], 0, i); /* Initialize tul_hcs 0 */
  2408. /* Get total memory needed for SCB */
  2409. for (; tul_num_scb >= MAX_TARGETS + 3; tul_num_scb--) {
  2410. i = tul_num_ch * tul_num_scb * sizeof(SCB);
  2411. if ((tul_scb = (SCB *) kmalloc(i, GFP_ATOMIC | GFP_DMA)) != NULL)
  2412. break;
  2413. }
  2414. if (tul_scb == NULL) {
  2415. printk("i91u: SCB memory allocation error\n");
  2416. return (0);
  2417. }
  2418. memset((unsigned char *) tul_scb, 0, i);
  2419. for (i = 0, pHCB = &tul_hcs[0]; /* Get pointer for control block */
  2420. i < tul_num_ch;
  2421. i++, pHCB++) {
  2422. get_tulipPCIConfig(pHCB, i);
  2423. dBiosAdr = pHCB->HCS_BIOS;
  2424. dBiosAdr = (dBiosAdr << 4);
  2425. pbBiosAdr = phys_to_virt(dBiosAdr);
  2426. init_tulip(pHCB, tul_scb + (i * tul_num_scb), tul_num_scb, pbBiosAdr, 10);
  2427. request_region(pHCB->HCS_Base, 256, "i91u"); /* Register */
  2428. pHCB->HCS_Index = i; /* 7/29/98 */
  2429. hreg = scsi_register(tpnt, sizeof(HCS));
  2430. if(hreg == NULL) {
  2431. release_region(pHCB->HCS_Base, 256);
  2432. return 0;
  2433. }
  2434. hreg->io_port = pHCB->HCS_Base;
  2435. hreg->n_io_port = 0xff;
  2436. hreg->can_queue = tul_num_scb; /* 03/05/98 */
  2437. hreg->unique_id = pHCB->HCS_Base;
  2438. hreg->max_id = pHCB->HCS_MaxTar;
  2439. hreg->max_lun = 32; /* 10/21/97 */
  2440. hreg->irq = pHCB->HCS_Intr;
  2441. hreg->this_id = pHCB->HCS_SCSI_ID; /* Assign HCS index */
  2442. hreg->base = (unsigned long)pHCB;
  2443. hreg->sg_tablesize = TOTAL_SG_ENTRY; /* Maximun support is 32 */
  2444. /* Initial tulip chip */
  2445. ok = request_irq(pHCB->HCS_Intr, i91u_intr, SA_INTERRUPT | SA_SHIRQ, "i91u", hreg);
  2446. if (ok < 0) {
  2447. printk(KERN_WARNING "i91u: unable to request IRQ %d\n\n", pHCB->HCS_Intr);
  2448. return 0;
  2449. }
  2450. }
  2451. tpnt->this_id = -1;
  2452. tpnt->can_queue = 1;
  2453. return 1;
  2454. }
  2455. static void i91uBuildSCB(HCS * pHCB, SCB * pSCB, struct scsi_cmnd * SCpnt)
  2456. { /* Create corresponding SCB */
  2457. struct scatterlist *pSrbSG;
  2458. SG *pSG; /* Pointer to SG list */
  2459. int i;
  2460. long TotalLen;
  2461. dma_addr_t dma_addr;
  2462. pSCB->SCB_Post = i91uSCBPost; /* i91u's callback routine */
  2463. pSCB->SCB_Srb = SCpnt;
  2464. pSCB->SCB_Opcode = ExecSCSI;
  2465. pSCB->SCB_Flags = SCF_POST; /* After SCSI done, call post routine */
  2466. pSCB->SCB_Target = SCpnt->device->id;
  2467. pSCB->SCB_Lun = SCpnt->device->lun;
  2468. pSCB->SCB_Ident = SCpnt->device->lun | DISC_ALLOW;
  2469. pSCB->SCB_Flags |= SCF_SENSE; /* Turn on auto request sense */
  2470. dma_addr = dma_map_single(&pHCB->pci_dev->dev, SCpnt->sense_buffer,
  2471. SENSE_SIZE, DMA_FROM_DEVICE);
  2472. pSCB->SCB_SensePtr = cpu_to_le32((u32)dma_addr);
  2473. pSCB->SCB_SenseLen = cpu_to_le32(SENSE_SIZE);
  2474. SCpnt->SCp.ptr = (char *)(unsigned long)dma_addr;
  2475. pSCB->SCB_CDBLen = SCpnt->cmd_len;
  2476. pSCB->SCB_HaStat = 0;
  2477. pSCB->SCB_TaStat = 0;
  2478. memcpy(&pSCB->SCB_CDB[0], &SCpnt->cmnd, SCpnt->cmd_len);
  2479. if (SCpnt->device->tagged_supported) { /* Tag Support */
  2480. pSCB->SCB_TagMsg = SIMPLE_QUEUE_TAG; /* Do simple tag only */
  2481. } else {
  2482. pSCB->SCB_TagMsg = 0; /* No tag support */
  2483. }
  2484. /* todo handle map_sg error */
  2485. if (SCpnt->use_sg) {
  2486. dma_addr = dma_map_single(&pHCB->pci_dev->dev, &pSCB->SCB_SGList[0],
  2487. sizeof(struct SG_Struc) * TOTAL_SG_ENTRY,
  2488. DMA_BIDIRECTIONAL);
  2489. pSCB->SCB_BufPtr = cpu_to_le32((u32)dma_addr);
  2490. SCpnt->SCp.dma_handle = dma_addr;
  2491. pSrbSG = (struct scatterlist *) SCpnt->request_buffer;
  2492. pSCB->SCB_SGLen = dma_map_sg(&pHCB->pci_dev->dev, pSrbSG,
  2493. SCpnt->use_sg, SCpnt->sc_data_direction);
  2494. pSCB->SCB_Flags |= SCF_SG; /* Turn on SG list flag */
  2495. for (i = 0, TotalLen = 0, pSG = &pSCB->SCB_SGList[0]; /* 1.01g */
  2496. i < pSCB->SCB_SGLen; i++, pSG++, pSrbSG++) {
  2497. pSG->SG_Ptr = cpu_to_le32((u32)sg_dma_address(pSrbSG));
  2498. TotalLen += pSG->SG_Len = cpu_to_le32((u32)sg_dma_len(pSrbSG));
  2499. }
  2500. pSCB->SCB_BufLen = (SCpnt->request_bufflen > TotalLen) ?
  2501. TotalLen : SCpnt->request_bufflen;
  2502. } else if (SCpnt->request_bufflen) { /* Non SG */
  2503. dma_addr = dma_map_single(&pHCB->pci_dev->dev, SCpnt->request_buffer,
  2504. SCpnt->request_bufflen,
  2505. SCpnt->sc_data_direction);
  2506. SCpnt->SCp.dma_handle = dma_addr;
  2507. pSCB->SCB_BufPtr = cpu_to_le32((u32)dma_addr);
  2508. pSCB->SCB_BufLen = cpu_to_le32((u32)SCpnt->request_bufflen);
  2509. pSCB->SCB_SGLen = 0;
  2510. } else {
  2511. pSCB->SCB_BufLen = 0;
  2512. pSCB->SCB_SGLen = 0;
  2513. }
  2514. }
  2515. static int i91u_queuecommand(struct scsi_cmnd *cmd,
  2516. void (*done)(struct scsi_cmnd *))
  2517. {
  2518. HCS *pHCB = (HCS *) cmd->device->host->base;
  2519. register SCB *pSCB;
  2520. cmd->scsi_done = done;
  2521. pSCB = tul_alloc_scb(pHCB);
  2522. if (!pSCB)
  2523. return SCSI_MLQUEUE_HOST_BUSY;
  2524. i91uBuildSCB(pHCB, pSCB, cmd);
  2525. tul_exec_scb(pHCB, pSCB);
  2526. return 0;
  2527. }
  2528. #if 0 /* no new EH yet */
  2529. /*
  2530. * Abort a queued command
  2531. * (commands that are on the bus can't be aborted easily)
  2532. */
  2533. static int i91u_abort(struct scsi_cmnd * SCpnt)
  2534. {
  2535. HCS *pHCB;
  2536. pHCB = (HCS *) SCpnt->device->host->base;
  2537. return tul_abort_srb(pHCB, SCpnt);
  2538. }
  2539. /*
  2540. * Reset registers, reset a hanging bus and
  2541. * kill active and disconnected commands for target w/o soft reset
  2542. */
  2543. static int i91u_reset(struct scsi_cmnd * SCpnt, unsigned int reset_flags)
  2544. { /* I need Host Control Block Information */
  2545. HCS *pHCB;
  2546. pHCB = (HCS *) SCpnt->device->host->base;
  2547. if (reset_flags & (SCSI_RESET_SUGGEST_BUS_RESET | SCSI_RESET_SUGGEST_HOST_RESET))
  2548. return tul_reset_scsi_bus(pHCB);
  2549. else
  2550. return tul_device_reset(pHCB, SCpnt, SCpnt->device->id, reset_flags);
  2551. }
  2552. #endif
  2553. static int i91u_bus_reset(struct scsi_cmnd * SCpnt)
  2554. {
  2555. HCS *pHCB;
  2556. pHCB = (HCS *) SCpnt->device->host->base;
  2557. spin_lock_irq(SCpnt->device->host->host_lock);
  2558. tul_reset_scsi(pHCB, 0);
  2559. spin_unlock_irq(SCpnt->device->host->host_lock);
  2560. return SUCCESS;
  2561. }
  2562. /*
  2563. * Return the "logical geometry"
  2564. */
  2565. static int i91u_biosparam(struct scsi_device *sdev, struct block_device *dev,
  2566. sector_t capacity, int *info_array)
  2567. {
  2568. HCS *pHcb; /* Point to Host adapter control block */
  2569. TCS *pTcb;
  2570. pHcb = (HCS *) sdev->host->base;
  2571. pTcb = &pHcb->HCS_Tcs[sdev->id];
  2572. if (pTcb->TCS_DrvHead) {
  2573. info_array[0] = pTcb->TCS_DrvHead;
  2574. info_array[1] = pTcb->TCS_DrvSector;
  2575. info_array[2] = (unsigned long)capacity / pTcb->TCS_DrvHead / pTcb->TCS_DrvSector;
  2576. } else {
  2577. if (pTcb->TCS_DrvFlags & TCF_DRV_255_63) {
  2578. info_array[0] = 255;
  2579. info_array[1] = 63;
  2580. info_array[2] = (unsigned long)capacity / 255 / 63;
  2581. } else {
  2582. info_array[0] = 64;
  2583. info_array[1] = 32;
  2584. info_array[2] = (unsigned long)capacity >> 11;
  2585. }
  2586. }
  2587. #if defined(DEBUG_BIOSPARAM)
  2588. if (i91u_debug & debug_biosparam) {
  2589. printk("bios geometry: head=%d, sec=%d, cyl=%d\n",
  2590. info_array[0], info_array[1], info_array[2]);
  2591. printk("WARNING: check, if the bios geometry is correct.\n");
  2592. }
  2593. #endif
  2594. return 0;
  2595. }
  2596. static void i91u_unmap_cmnd(struct pci_dev *pci_dev, struct scsi_cmnd *cmnd)
  2597. {
  2598. /* auto sense buffer */
  2599. if (cmnd->SCp.ptr) {
  2600. dma_unmap_single(&pci_dev->dev,
  2601. (dma_addr_t)((unsigned long)cmnd->SCp.ptr),
  2602. SENSE_SIZE, DMA_FROM_DEVICE);
  2603. cmnd->SCp.ptr = NULL;
  2604. }
  2605. /* request buffer */
  2606. if (cmnd->use_sg) {
  2607. dma_unmap_single(&pci_dev->dev, cmnd->SCp.dma_handle,
  2608. sizeof(struct SG_Struc) * TOTAL_SG_ENTRY,
  2609. DMA_BIDIRECTIONAL);
  2610. dma_unmap_sg(&pci_dev->dev, cmnd->request_buffer,
  2611. cmnd->use_sg,
  2612. cmnd->sc_data_direction);
  2613. } else if (cmnd->request_bufflen) {
  2614. dma_unmap_single(&pci_dev->dev, cmnd->SCp.dma_handle,
  2615. cmnd->request_bufflen,
  2616. cmnd->sc_data_direction);
  2617. }
  2618. }
  2619. /*****************************************************************************
  2620. Function name : i91uSCBPost
  2621. Description : This is callback routine be called when tulip finish one
  2622. SCSI command.
  2623. Input : pHCB - Pointer to host adapter control block.
  2624. pSCB - Pointer to SCSI control block.
  2625. Output : None.
  2626. Return : None.
  2627. *****************************************************************************/
  2628. static void i91uSCBPost(BYTE * pHcb, BYTE * pScb)
  2629. {
  2630. struct scsi_cmnd *pSRB; /* Pointer to SCSI request block */
  2631. HCS *pHCB;
  2632. SCB *pSCB;
  2633. pHCB = (HCS *) pHcb;
  2634. pSCB = (SCB *) pScb;
  2635. if ((pSRB = pSCB->SCB_Srb) == 0) {
  2636. printk("i91uSCBPost: SRB pointer is empty\n");
  2637. tul_release_scb(pHCB, pSCB); /* Release SCB for current channel */
  2638. return;
  2639. }
  2640. switch (pSCB->SCB_HaStat) {
  2641. case 0x0:
  2642. case 0xa: /* Linked command complete without error and linked normally */
  2643. case 0xb: /* Linked command complete without error interrupt generated */
  2644. pSCB->SCB_HaStat = 0;
  2645. break;
  2646. case 0x11: /* Selection time out-The initiator selection or target
  2647. reselection was not complete within the SCSI Time out period */
  2648. pSCB->SCB_HaStat = DID_TIME_OUT;
  2649. break;
  2650. case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus
  2651. phase sequence was requested by the target. The host adapter
  2652. will generate a SCSI Reset Condition, notifying the host with
  2653. a SCRD interrupt */
  2654. pSCB->SCB_HaStat = DID_RESET;
  2655. break;
  2656. case 0x1a: /* SCB Aborted. 07/21/98 */
  2657. pSCB->SCB_HaStat = DID_ABORT;
  2658. break;
  2659. case 0x12: /* Data overrun/underrun-The target attempted to transfer more data
  2660. than was allocated by the Data Length field or the sum of the
  2661. Scatter / Gather Data Length fields. */
  2662. case 0x13: /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */
  2663. case 0x16: /* Invalid SCB Operation Code. */
  2664. default:
  2665. printk("ini9100u: %x %x\n", pSCB->SCB_HaStat, pSCB->SCB_TaStat);
  2666. pSCB->SCB_HaStat = DID_ERROR; /* Couldn't find any better */
  2667. break;
  2668. }
  2669. pSRB->result = pSCB->SCB_TaStat | (pSCB->SCB_HaStat << 16);
  2670. if (pSRB == NULL) {
  2671. printk("pSRB is NULL\n");
  2672. }
  2673. i91u_unmap_cmnd(pHCB->pci_dev, pSRB);
  2674. pSRB->scsi_done(pSRB); /* Notify system DONE */
  2675. tul_release_scb(pHCB, pSCB); /* Release SCB for current channel */
  2676. }
  2677. /*
  2678. * Release ressources
  2679. */
  2680. static int i91u_release(struct Scsi_Host *hreg)
  2681. {
  2682. free_irq(hreg->irq, hreg);
  2683. release_region(hreg->io_port, 256);
  2684. return 0;
  2685. }
  2686. MODULE_LICENSE("Dual BSD/GPL");
  2687. static struct scsi_host_template driver_template = {
  2688. .proc_name = "INI9100U",
  2689. .name = i91u_REVID,
  2690. .detect = i91u_detect,
  2691. .release = i91u_release,
  2692. .queuecommand = i91u_queuecommand,
  2693. // .abort = i91u_abort,
  2694. // .reset = i91u_reset,
  2695. .eh_bus_reset_handler = i91u_bus_reset,
  2696. .bios_param = i91u_biosparam,
  2697. .can_queue = 1,
  2698. .this_id = 1,
  2699. .sg_tablesize = SG_ALL,
  2700. .cmd_per_lun = 1,
  2701. .use_clustering = ENABLE_CLUSTERING,
  2702. };
  2703. #include "scsi_module.c"