gdth.c 203 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-04 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-04 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.2.x, 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.73 2004/03/31 13:33:03 achim
  34. * Special command 0xfd implemented to detect 64-bit DMA support
  35. *
  36. * Revision 1.72 2004/03/17 08:56:04 achim
  37. * 64-bit DMA only enabled if FW >= x.43
  38. *
  39. * Revision 1.71 2004/03/05 15:51:29 achim
  40. * Screen service: separate message buffer, bugfixes
  41. *
  42. * Revision 1.70 2004/02/27 12:19:07 achim
  43. * Bugfix: Reset bit in config (0xfe) call removed
  44. *
  45. * Revision 1.69 2004/02/20 09:50:24 achim
  46. * Compatibility changes for kernels < 2.4.20
  47. * Bugfix screen service command size
  48. * pci_set_dma_mask() error handling added
  49. *
  50. * Revision 1.68 2004/02/19 15:46:54 achim
  51. * 64-bit DMA bugfixes
  52. * Drive size bugfix for drives > 1TB
  53. *
  54. * Revision 1.67 2004/01/14 13:11:57 achim
  55. * Tool access over /proc no longer supported
  56. * Bugfixes IOCTLs
  57. *
  58. * Revision 1.66 2003/12/19 15:04:06 achim
  59. * Bugfixes support for drives > 2TB
  60. *
  61. * Revision 1.65 2003/12/15 11:21:56 achim
  62. * 64-bit DMA support added
  63. * Support for drives > 2 TB implemented
  64. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  65. *
  66. * Revision 1.64 2003/09/17 08:30:26 achim
  67. * EISA/ISA controller scan disabled
  68. * Command line switch probe_eisa_isa added
  69. *
  70. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  71. * Minor cleanups in gdth_ioctl.
  72. *
  73. * Revision 1.62 2003/02/27 15:01:59 achim
  74. * Dynamic DMA mapping implemented
  75. * New (character device) IOCTL interface added
  76. * Other controller related changes made
  77. *
  78. * Revision 1.61 2002/11/08 13:09:52 boji
  79. * Added support for XSCALE based RAID Controllers
  80. * Fixed SCREENSERVICE initialization in SMP cases
  81. * Added checks for gdth_polling before GDTH_HA_LOCK
  82. *
  83. * Revision 1.60 2002/02/05 09:35:22 achim
  84. * MODULE_LICENSE only if kernel >= 2.4.11
  85. *
  86. * Revision 1.59 2002/01/30 09:46:33 achim
  87. * Small changes
  88. *
  89. * Revision 1.58 2002/01/29 15:30:02 achim
  90. * Set default value of shared_access to Y
  91. * New status S_CACHE_RESERV for clustering added
  92. *
  93. * Revision 1.57 2001/08/21 11:16:35 achim
  94. * Bugfix free_irq()
  95. *
  96. * Revision 1.56 2001/08/09 11:19:39 achim
  97. * Scsi_Host_Template changes
  98. *
  99. * Revision 1.55 2001/08/09 10:11:28 achim
  100. * Command HOST_UNFREEZE_IO before cache service init.
  101. *
  102. * Revision 1.54 2001/07/20 13:48:12 achim
  103. * Expand: gdth_analyse_hdrive() removed
  104. *
  105. * Revision 1.53 2001/07/17 09:52:49 achim
  106. * Small OEM related change
  107. *
  108. * Revision 1.52 2001/06/19 15:06:20 achim
  109. * New host command GDT_UNFREEZE_IO added
  110. *
  111. * Revision 1.51 2001/05/22 06:42:37 achim
  112. * PCI: Subdevice ID added
  113. *
  114. * Revision 1.50 2001/05/17 13:42:16 achim
  115. * Support for Intel Storage RAID Controllers added
  116. *
  117. * Revision 1.50 2001/05/17 12:12:34 achim
  118. * Support for Intel Storage RAID Controllers added
  119. *
  120. * Revision 1.49 2001/03/15 15:07:17 achim
  121. * New __setup interface for boot command line options added
  122. *
  123. * Revision 1.48 2001/02/06 12:36:28 achim
  124. * Bugfix Cluster protocol
  125. *
  126. * Revision 1.47 2001/01/10 14:42:06 achim
  127. * New switch shared_access added
  128. *
  129. * Revision 1.46 2001/01/09 08:11:35 achim
  130. * gdth_command() removed
  131. * meaning of Scsi_Pointer members changed
  132. *
  133. * Revision 1.45 2000/11/16 12:02:24 achim
  134. * Changes for kernel 2.4
  135. *
  136. * Revision 1.44 2000/10/11 08:44:10 achim
  137. * Clustering changes: New flag media_changed added
  138. *
  139. * Revision 1.43 2000/09/20 12:59:01 achim
  140. * DPMEM remap functions for all PCI controller types implemented
  141. * Small changes for ia64 platform
  142. *
  143. * Revision 1.42 2000/07/20 09:04:50 achim
  144. * Small changes for kernel 2.4
  145. *
  146. * Revision 1.41 2000/07/04 14:11:11 achim
  147. * gdth_analyse_hdrive() added to rescan drives after online expansion
  148. *
  149. * Revision 1.40 2000/06/27 11:24:16 achim
  150. * Changes Clustering, Screenservice
  151. *
  152. * Revision 1.39 2000/06/15 13:09:04 achim
  153. * Changes for gdth_do_cmd()
  154. *
  155. * Revision 1.38 2000/06/15 12:08:43 achim
  156. * Bugfix gdth_sync_event(), service SCREENSERVICE
  157. * Data direction for command 0xc2 changed to DOU
  158. *
  159. * Revision 1.37 2000/05/25 13:50:10 achim
  160. * New driver parameter virt_ctr added
  161. *
  162. * Revision 1.36 2000/05/04 08:50:46 achim
  163. * Event buffer now in gdth_ha_str
  164. *
  165. * Revision 1.35 2000/03/03 10:44:08 achim
  166. * New event_string only valid for the RP controller family
  167. *
  168. * Revision 1.34 2000/03/02 14:55:29 achim
  169. * New mechanism for async. event handling implemented
  170. *
  171. * Revision 1.33 2000/02/21 15:37:37 achim
  172. * Bugfix Alpha platform + DPMEM above 4GB
  173. *
  174. * Revision 1.32 2000/02/14 16:17:37 achim
  175. * Bugfix sense_buffer[] + raw devices
  176. *
  177. * Revision 1.31 2000/02/10 10:29:00 achim
  178. * Delete sense_buffer[0], if command OK
  179. *
  180. * Revision 1.30 1999/11/02 13:42:39 achim
  181. * ARRAY_DRV_LIST2 implemented
  182. * Now 255 log. and 100 host drives supported
  183. *
  184. * Revision 1.29 1999/10/05 13:28:47 achim
  185. * GDT_CLUST_RESET added
  186. *
  187. * Revision 1.28 1999/08/12 13:44:54 achim
  188. * MOUNTALL removed
  189. * Cluster drives -> removeable drives
  190. *
  191. * Revision 1.27 1999/06/22 07:22:38 achim
  192. * Small changes
  193. *
  194. * Revision 1.26 1999/06/10 16:09:12 achim
  195. * Cluster Host Drive support: Bugfixes
  196. *
  197. * Revision 1.25 1999/06/01 16:03:56 achim
  198. * gdth_init_pci(): Manipulate config. space to start RP controller
  199. *
  200. * Revision 1.24 1999/05/26 11:53:06 achim
  201. * Cluster Host Drive support added
  202. *
  203. * Revision 1.23 1999/03/26 09:12:31 achim
  204. * Default value for hdr_channel set to 0
  205. *
  206. * Revision 1.22 1999/03/22 16:27:16 achim
  207. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  208. *
  209. * Revision 1.21 1999/03/16 13:40:34 achim
  210. * Problems with reserved drives solved
  211. * gdth_eh_bus_reset() implemented
  212. *
  213. * Revision 1.20 1999/03/10 09:08:13 achim
  214. * Bugfix: Corrections in gdth_direction_tab[] made
  215. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  216. *
  217. * Revision 1.19 1999/03/05 14:38:16 achim
  218. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  219. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  220. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  221. * with BIOS disabled and memory test set to Intensive
  222. * Enhanced /proc support
  223. *
  224. * Revision 1.18 1999/02/24 09:54:33 achim
  225. * Command line parameter hdr_channel implemented
  226. * Bugfix for EISA controllers + Linux 2.2.x
  227. *
  228. * Revision 1.17 1998/12/17 15:58:11 achim
  229. * Command line parameters implemented
  230. * Changes for Alpha platforms
  231. * PCI controller scan changed
  232. * SMP support improved (spin_lock_irqsave(),...)
  233. * New async. events, new scan/reserve commands included
  234. *
  235. * Revision 1.16 1998/09/28 16:08:46 achim
  236. * GDT_PCIMPR: DPMEM remapping, if required
  237. * mdelay() added
  238. *
  239. * Revision 1.15 1998/06/03 14:54:06 achim
  240. * gdth_delay(), gdth_flush() implemented
  241. * Bugfix: gdth_release() changed
  242. *
  243. * Revision 1.14 1998/05/22 10:01:17 achim
  244. * mj: pcibios_strerror() removed
  245. * Improved SMP support (if version >= 2.1.95)
  246. * gdth_halt(): halt_called flag added (if version < 2.1)
  247. *
  248. * Revision 1.13 1998/04/16 09:14:57 achim
  249. * Reserve drives (for raw service) implemented
  250. * New error handling code enabled
  251. * Get controller name from board_info() IOCTL
  252. * Final round of PCI device driver patches by Martin Mares
  253. *
  254. * Revision 1.12 1998/03/03 09:32:37 achim
  255. * Fibre channel controller support added
  256. *
  257. * Revision 1.11 1998/01/27 16:19:14 achim
  258. * SA_SHIRQ added
  259. * add_timer()/del_timer() instead of GDTH_TIMER
  260. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  261. * New error handling included
  262. *
  263. * Revision 1.10 1997/10/31 12:29:57 achim
  264. * Read heads/sectors from host drive
  265. *
  266. * Revision 1.9 1997/09/04 10:07:25 achim
  267. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  268. * register_reboot_notifier() to get a notify on shutown used
  269. *
  270. * Revision 1.8 1997/04/02 12:14:30 achim
  271. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  272. *
  273. * Revision 1.7 1997/03/12 13:33:37 achim
  274. * gdth_reset() changed, new async. events
  275. *
  276. * Revision 1.6 1997/03/04 14:01:11 achim
  277. * Shutdown routine gdth_halt() implemented
  278. *
  279. * Revision 1.5 1997/02/21 09:08:36 achim
  280. * New controller included (RP, RP1, RP2 series)
  281. * IOCTL interface implemented
  282. *
  283. * Revision 1.4 1996/07/05 12:48:55 achim
  284. * Function gdth_bios_param() implemented
  285. * New constant GDTH_MAXC_P_L inserted
  286. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  287. * Function gdth_reset() changed
  288. *
  289. * Revision 1.3 1996/05/10 09:04:41 achim
  290. * Small changes for Linux 1.2.13
  291. *
  292. * Revision 1.2 1996/05/09 12:45:27 achim
  293. * Loadable module support implemented
  294. * /proc support corrections made
  295. *
  296. * Revision 1.1 1996/04/11 07:35:57 achim
  297. * Initial revision
  298. *
  299. ************************************************************************/
  300. /* All GDT Disk Array Controllers are fully supported by this driver.
  301. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  302. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  303. * list of all controller types.
  304. *
  305. * If you have one or more GDT3000/3020 EISA controllers with
  306. * controller BIOS disabled, you have to set the IRQ values with the
  307. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  308. * the IRQ values for the EISA controllers.
  309. *
  310. * After the optional list of IRQ values, other possible
  311. * command line options are:
  312. * disable:Y disable driver
  313. * disable:N enable driver
  314. * reserve_mode:0 reserve no drives for the raw service
  315. * reserve_mode:1 reserve all not init., removable drives
  316. * reserve_mode:2 reserve all not init. drives
  317. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  318. * h- controller no., b- channel no.,
  319. * t- target ID, l- LUN
  320. * reverse_scan:Y reverse scan order for PCI controllers
  321. * reverse_scan:N scan PCI controllers like BIOS
  322. * max_ids:x x - target ID count per channel (1..MAXID)
  323. * rescan:Y rescan all channels/IDs
  324. * rescan:N use all devices found until now
  325. * virt_ctr:Y map every channel to a virtual controller
  326. * virt_ctr:N use multi channel support
  327. * hdr_channel:x x - number of virtual bus for host drives
  328. * shared_access:Y disable driver reserve/release protocol to
  329. * access a shared resource from several nodes,
  330. * appropiate controller firmware required
  331. * shared_access:N enable driver reserve/release protocol
  332. * probe_eisa_isa:Y scan for EISA/ISA controllers
  333. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  334. * force_dma32:Y use only 32 bit DMA mode
  335. * force_dma32:N use 64 bit DMA mode, if supported
  336. *
  337. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  338. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  339. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  340. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  341. *
  342. * When loading the gdth driver as a module, the same options are available.
  343. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  344. * options changes slightly. You must replace all ',' between options
  345. * with ' ' and all ':' with '=' and you must use
  346. * '1' in place of 'Y' and '0' in place of 'N'.
  347. *
  348. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  349. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  350. * probe_eisa_isa=0 force_dma32=0"
  351. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  352. */
  353. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  354. * ptr: Chaining
  355. * this_residual: Command priority
  356. * buffer: phys. DMA sense buffer
  357. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  358. * buffers_residual: Timeout value
  359. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  360. * Message: Additional info (gdth_do_cmd()), DMA direction
  361. * have_data_in: Flag for gdth_wait_completion()
  362. * sent_command: Opcode special command
  363. * phase: Service/parameter/return code special command
  364. */
  365. /* interrupt coalescing */
  366. /* #define INT_COAL */
  367. /* statistics */
  368. #define GDTH_STATISTICS
  369. #include <linux/module.h>
  370. #include <linux/version.h>
  371. #include <linux/kernel.h>
  372. #include <linux/types.h>
  373. #include <linux/pci.h>
  374. #include <linux/string.h>
  375. #include <linux/ctype.h>
  376. #include <linux/ioport.h>
  377. #include <linux/delay.h>
  378. #include <linux/sched.h>
  379. #include <linux/interrupt.h>
  380. #include <linux/in.h>
  381. #include <linux/proc_fs.h>
  382. #include <linux/time.h>
  383. #include <linux/timer.h>
  384. #ifdef GDTH_RTC
  385. #include <linux/mc146818rtc.h>
  386. #endif
  387. #include <linux/reboot.h>
  388. #include <asm/dma.h>
  389. #include <asm/system.h>
  390. #include <asm/io.h>
  391. #include <asm/uaccess.h>
  392. #include <linux/spinlock.h>
  393. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  394. #include <linux/blkdev.h>
  395. #else
  396. #include <linux/blk.h>
  397. #include "sd.h"
  398. #endif
  399. #include "scsi.h"
  400. #include <scsi/scsi_host.h>
  401. #include "gdth.h"
  402. #include "gdth_kcompat.h"
  403. static void gdth_delay(int milliseconds);
  404. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  405. static irqreturn_t gdth_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  406. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  407. static int gdth_async_event(int hanum);
  408. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  409. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  410. static void gdth_next(int hanum);
  411. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  412. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  413. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  414. ushort idx, gdth_evt_data *evt);
  415. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  416. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  417. gdth_evt_str *estr);
  418. static void gdth_clear_events(void);
  419. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  420. char *buffer,ushort count);
  421. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  422. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  423. static int gdth_search_eisa(ushort eisa_adr);
  424. static int gdth_search_isa(ulong32 bios_adr);
  425. static int gdth_search_pci(gdth_pci_str *pcistr);
  426. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  427. ushort vendor, ushort dev);
  428. static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
  429. static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
  430. static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
  431. static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
  432. static void gdth_enable_int(int hanum);
  433. static int gdth_get_status(unchar *pIStatus,int irq);
  434. static int gdth_test_busy(int hanum);
  435. static int gdth_get_cmd_index(int hanum);
  436. static void gdth_release_event(int hanum);
  437. static int gdth_wait(int hanum,int index,ulong32 time);
  438. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  439. ulong64 p2,ulong64 p3);
  440. static int gdth_search_drives(int hanum);
  441. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  442. static const char *gdth_ctr_name(int hanum);
  443. static int gdth_open(struct inode *inode, struct file *filep);
  444. static int gdth_close(struct inode *inode, struct file *filep);
  445. static int gdth_ioctl(struct inode *inode, struct file *filep,
  446. unsigned int cmd, unsigned long arg);
  447. static void gdth_flush(int hanum);
  448. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  449. #ifdef DEBUG_GDTH
  450. static unchar DebugState = DEBUG_GDTH;
  451. #ifdef __SERIAL__
  452. #define MAX_SERBUF 160
  453. static void ser_init(void);
  454. static void ser_puts(char *str);
  455. static void ser_putc(char c);
  456. static int ser_printk(const char *fmt, ...);
  457. static char strbuf[MAX_SERBUF+1];
  458. #ifdef __COM2__
  459. #define COM_BASE 0x2f8
  460. #else
  461. #define COM_BASE 0x3f8
  462. #endif
  463. static void ser_init()
  464. {
  465. unsigned port=COM_BASE;
  466. outb(0x80,port+3);
  467. outb(0,port+1);
  468. /* 19200 Baud, if 9600: outb(12,port) */
  469. outb(6, port);
  470. outb(3,port+3);
  471. outb(0,port+1);
  472. /*
  473. ser_putc('I');
  474. ser_putc(' ');
  475. */
  476. }
  477. static void ser_puts(char *str)
  478. {
  479. char *ptr;
  480. ser_init();
  481. for (ptr=str;*ptr;++ptr)
  482. ser_putc(*ptr);
  483. }
  484. static void ser_putc(char c)
  485. {
  486. unsigned port=COM_BASE;
  487. while ((inb(port+5) & 0x20)==0);
  488. outb(c,port);
  489. if (c==0x0a)
  490. {
  491. while ((inb(port+5) & 0x20)==0);
  492. outb(0x0d,port);
  493. }
  494. }
  495. static int ser_printk(const char *fmt, ...)
  496. {
  497. va_list args;
  498. int i;
  499. va_start(args,fmt);
  500. i = vsprintf(strbuf,fmt,args);
  501. ser_puts(strbuf);
  502. va_end(args);
  503. return i;
  504. }
  505. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  506. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  507. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  508. #else /* !__SERIAL__ */
  509. #define TRACE(a) {if (DebugState==1) {printk a;}}
  510. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  511. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  512. #endif
  513. #else /* !DEBUG */
  514. #define TRACE(a)
  515. #define TRACE2(a)
  516. #define TRACE3(a)
  517. #endif
  518. #ifdef GDTH_STATISTICS
  519. static ulong32 max_rq=0, max_index=0, max_sg=0;
  520. #ifdef INT_COAL
  521. static ulong32 max_int_coal=0;
  522. #endif
  523. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  524. static struct timer_list gdth_timer;
  525. #endif
  526. #define PTR2USHORT(a) (ushort)(ulong)(a)
  527. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  528. #define INDEX_OK(i,t) ((i)<sizeof(t)/sizeof((t)[0]))
  529. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  530. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  531. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  532. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  533. #define gdth_readb(addr) readb(addr)
  534. #define gdth_readw(addr) readw(addr)
  535. #define gdth_readl(addr) readl(addr)
  536. #define gdth_writeb(b,addr) writeb((b),(addr))
  537. #define gdth_writew(b,addr) writew((b),(addr))
  538. #define gdth_writel(b,addr) writel((b),(addr))
  539. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  540. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  541. static unchar gdth_polling; /* polling if TRUE */
  542. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  543. static int wait_index,wait_hanum; /* gdth_wait() */
  544. static int gdth_ctr_count = 0; /* controller count */
  545. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  546. static int gdth_ctr_released = 0; /* gdth_release() */
  547. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  548. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  549. static unchar gdth_write_through = FALSE; /* write through */
  550. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  551. static int elastidx;
  552. static int eoldidx;
  553. static int major;
  554. #define DIN 1 /* IN data direction */
  555. #define DOU 2 /* OUT data direction */
  556. #define DNO DIN /* no data transfer */
  557. #define DUN DIN /* unknown data direction */
  558. static unchar gdth_direction_tab[0x100] = {
  559. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  560. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  561. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  562. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  563. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  564. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  565. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  566. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  567. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  568. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  569. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  570. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  571. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  572. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  573. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  574. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  575. };
  576. /* LILO and modprobe/insmod parameters */
  577. /* IRQ list for GDT3000/3020 EISA controllers */
  578. static int irq[MAXHA] __initdata =
  579. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  580. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  581. /* disable driver flag */
  582. static int disable __initdata = 0;
  583. /* reserve flag */
  584. static int reserve_mode = 1;
  585. /* reserve list */
  586. static int reserve_list[MAX_RES_ARGS] =
  587. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  588. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  589. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  590. /* scan order for PCI controllers */
  591. static int reverse_scan = 0;
  592. /* virtual channel for the host drives */
  593. static int hdr_channel = 0;
  594. /* max. IDs per channel */
  595. static int max_ids = MAXID;
  596. /* rescan all IDs */
  597. static int rescan = 0;
  598. /* map channels to virtual controllers */
  599. static int virt_ctr = 0;
  600. /* shared access */
  601. static int shared_access = 1;
  602. /* enable support for EISA and ISA controllers */
  603. static int probe_eisa_isa = 0;
  604. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  605. static int force_dma32 = 0;
  606. /* parameters for modprobe/insmod */
  607. module_param_array(irq, int, NULL, 0);
  608. module_param(disable, int, 0);
  609. module_param(reserve_mode, int, 0);
  610. module_param_array(reserve_list, int, NULL, 0);
  611. module_param(reverse_scan, int, 0);
  612. module_param(hdr_channel, int, 0);
  613. module_param(max_ids, int, 0);
  614. module_param(rescan, int, 0);
  615. module_param(virt_ctr, int, 0);
  616. module_param(shared_access, int, 0);
  617. module_param(probe_eisa_isa, int, 0);
  618. module_param(force_dma32, int, 0);
  619. MODULE_AUTHOR("Achim Leubner");
  620. MODULE_LICENSE("GPL");
  621. /* ioctl interface */
  622. static struct file_operations gdth_fops = {
  623. .ioctl = gdth_ioctl,
  624. .open = gdth_open,
  625. .release = gdth_close,
  626. };
  627. #include "gdth_proc.h"
  628. #include "gdth_proc.c"
  629. /* notifier block to get a notify on system shutdown/halt/reboot */
  630. static struct notifier_block gdth_notifier = {
  631. gdth_halt, NULL, 0
  632. };
  633. static void gdth_delay(int milliseconds)
  634. {
  635. if (milliseconds == 0) {
  636. udelay(1);
  637. } else {
  638. mdelay(milliseconds);
  639. }
  640. }
  641. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  642. {
  643. *cyls = size /HEADS/SECS;
  644. if (*cyls <= MAXCYLS) {
  645. *heads = HEADS;
  646. *secs = SECS;
  647. } else { /* too high for 64*32 */
  648. *cyls = size /MEDHEADS/MEDSECS;
  649. if (*cyls <= MAXCYLS) {
  650. *heads = MEDHEADS;
  651. *secs = MEDSECS;
  652. } else { /* too high for 127*63 */
  653. *cyls = size /BIGHEADS/BIGSECS;
  654. *heads = BIGHEADS;
  655. *secs = BIGSECS;
  656. }
  657. }
  658. }
  659. /* controller search and initialization functions */
  660. static int __init gdth_search_eisa(ushort eisa_adr)
  661. {
  662. ulong32 id;
  663. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  664. id = inl(eisa_adr+ID0REG);
  665. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  666. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  667. return 0; /* not EISA configured */
  668. return 1;
  669. }
  670. if (id == GDT3_ID) /* GDT3000 */
  671. return 1;
  672. return 0;
  673. }
  674. static int __init gdth_search_isa(ulong32 bios_adr)
  675. {
  676. void __iomem *addr;
  677. ulong32 id;
  678. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  679. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  680. id = gdth_readl(addr);
  681. iounmap(addr);
  682. if (id == GDT2_ID) /* GDT2000 */
  683. return 1;
  684. }
  685. return 0;
  686. }
  687. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  688. {
  689. ushort device, cnt;
  690. TRACE(("gdth_search_pci()\n"));
  691. cnt = 0;
  692. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  693. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  694. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  695. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  696. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  697. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  698. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  699. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  700. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  701. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  702. PCI_DEVICE_ID_INTEL_SRC);
  703. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  704. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  705. return cnt;
  706. }
  707. /* Vortex only makes RAID controllers.
  708. * We do not really want to specify all 550 ids here, so wildcard match.
  709. */
  710. static struct pci_device_id gdthtable[] __attribute_used__ = {
  711. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  712. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  713. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  714. {0}
  715. };
  716. MODULE_DEVICE_TABLE(pci,gdthtable);
  717. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  718. ushort vendor, ushort device)
  719. {
  720. ulong base0, base1, base2;
  721. struct pci_dev *pdev;
  722. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  723. *cnt, vendor, device));
  724. pdev = NULL;
  725. while ((pdev = pci_find_device(vendor, device, pdev))
  726. != NULL) {
  727. if (pci_enable_device(pdev))
  728. continue;
  729. if (*cnt >= MAXHA)
  730. return;
  731. /* GDT PCI controller found, resources are already in pdev */
  732. pcistr[*cnt].pdev = pdev;
  733. pcistr[*cnt].vendor_id = vendor;
  734. pcistr[*cnt].device_id = device;
  735. pcistr[*cnt].subdevice_id = pdev->subsystem_device;
  736. pcistr[*cnt].bus = pdev->bus->number;
  737. pcistr[*cnt].device_fn = pdev->devfn;
  738. pcistr[*cnt].irq = pdev->irq;
  739. base0 = pci_resource_flags(pdev, 0);
  740. base1 = pci_resource_flags(pdev, 1);
  741. base2 = pci_resource_flags(pdev, 2);
  742. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  743. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  744. if (!(base0 & IORESOURCE_MEM))
  745. continue;
  746. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  747. } else { /* GDT6110, GDT6120, .. */
  748. if (!(base0 & IORESOURCE_MEM) ||
  749. !(base2 & IORESOURCE_MEM) ||
  750. !(base1 & IORESOURCE_IO))
  751. continue;
  752. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  753. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  754. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  755. }
  756. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  757. pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
  758. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  759. (*cnt)++;
  760. }
  761. }
  762. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  763. {
  764. gdth_pci_str temp;
  765. int i, changed;
  766. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  767. if (cnt == 0)
  768. return;
  769. do {
  770. changed = FALSE;
  771. for (i = 0; i < cnt-1; ++i) {
  772. if (!reverse_scan) {
  773. if ((pcistr[i].bus > pcistr[i+1].bus) ||
  774. (pcistr[i].bus == pcistr[i+1].bus &&
  775. PCI_SLOT(pcistr[i].device_fn) >
  776. PCI_SLOT(pcistr[i+1].device_fn))) {
  777. temp = pcistr[i];
  778. pcistr[i] = pcistr[i+1];
  779. pcistr[i+1] = temp;
  780. changed = TRUE;
  781. }
  782. } else {
  783. if ((pcistr[i].bus < pcistr[i+1].bus) ||
  784. (pcistr[i].bus == pcistr[i+1].bus &&
  785. PCI_SLOT(pcistr[i].device_fn) <
  786. PCI_SLOT(pcistr[i+1].device_fn))) {
  787. temp = pcistr[i];
  788. pcistr[i] = pcistr[i+1];
  789. pcistr[i+1] = temp;
  790. changed = TRUE;
  791. }
  792. }
  793. }
  794. } while (changed);
  795. }
  796. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  797. {
  798. ulong32 retries,id;
  799. unchar prot_ver,eisacf,i,irq_found;
  800. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  801. /* disable board interrupts, deinitialize services */
  802. outb(0xff,eisa_adr+EDOORREG);
  803. outb(0x00,eisa_adr+EDENABREG);
  804. outb(0x00,eisa_adr+EINTENABREG);
  805. outb(0xff,eisa_adr+LDOORREG);
  806. retries = INIT_RETRIES;
  807. gdth_delay(20);
  808. while (inb(eisa_adr+EDOORREG) != 0xff) {
  809. if (--retries == 0) {
  810. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  811. return 0;
  812. }
  813. gdth_delay(1);
  814. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  815. }
  816. prot_ver = inb(eisa_adr+MAILBOXREG);
  817. outb(0xff,eisa_adr+EDOORREG);
  818. if (prot_ver != PROTOCOL_VERSION) {
  819. printk("GDT-EISA: Illegal protocol version\n");
  820. return 0;
  821. }
  822. ha->bmic = eisa_adr;
  823. ha->brd_phys = (ulong32)eisa_adr >> 12;
  824. outl(0,eisa_adr+MAILBOXREG);
  825. outl(0,eisa_adr+MAILBOXREG+4);
  826. outl(0,eisa_adr+MAILBOXREG+8);
  827. outl(0,eisa_adr+MAILBOXREG+12);
  828. /* detect IRQ */
  829. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  830. ha->oem_id = OEM_ID_ICP;
  831. ha->type = GDT_EISA;
  832. ha->stype = id;
  833. outl(1,eisa_adr+MAILBOXREG+8);
  834. outb(0xfe,eisa_adr+LDOORREG);
  835. retries = INIT_RETRIES;
  836. gdth_delay(20);
  837. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  838. if (--retries == 0) {
  839. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  840. return 0;
  841. }
  842. gdth_delay(1);
  843. }
  844. ha->irq = inb(eisa_adr+MAILBOXREG);
  845. outb(0xff,eisa_adr+EDOORREG);
  846. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  847. /* check the result */
  848. if (ha->irq == 0) {
  849. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  850. for (i = 0, irq_found = FALSE;
  851. i < MAXHA && irq[i] != 0xff; ++i) {
  852. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  853. irq_found = TRUE;
  854. break;
  855. }
  856. }
  857. if (irq_found) {
  858. ha->irq = irq[i];
  859. irq[i] = 0;
  860. printk("GDT-EISA: Can not detect controller IRQ,\n");
  861. printk("Use IRQ setting from command line (IRQ = %d)\n",
  862. ha->irq);
  863. } else {
  864. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  865. printk("the controller BIOS or use command line parameters\n");
  866. return 0;
  867. }
  868. }
  869. } else {
  870. eisacf = inb(eisa_adr+EISAREG) & 7;
  871. if (eisacf > 4) /* level triggered */
  872. eisacf -= 4;
  873. ha->irq = gdth_irq_tab[eisacf];
  874. ha->oem_id = OEM_ID_ICP;
  875. ha->type = GDT_EISA;
  876. ha->stype = id;
  877. }
  878. ha->dma64_support = 0;
  879. return 1;
  880. }
  881. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  882. {
  883. register gdt2_dpram_str __iomem *dp2_ptr;
  884. int i;
  885. unchar irq_drq,prot_ver;
  886. ulong32 retries;
  887. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  888. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  889. if (ha->brd == NULL) {
  890. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  891. return 0;
  892. }
  893. dp2_ptr = ha->brd;
  894. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  895. /* reset interface area */
  896. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  897. if (gdth_readl(&dp2_ptr->u) != 0) {
  898. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  899. iounmap(ha->brd);
  900. return 0;
  901. }
  902. /* disable board interrupts, read DRQ and IRQ */
  903. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  904. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  905. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  906. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  907. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  908. for (i=0; i<3; ++i) {
  909. if ((irq_drq & 1)==0)
  910. break;
  911. irq_drq >>= 1;
  912. }
  913. ha->drq = gdth_drq_tab[i];
  914. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  915. for (i=1; i<5; ++i) {
  916. if ((irq_drq & 1)==0)
  917. break;
  918. irq_drq >>= 1;
  919. }
  920. ha->irq = gdth_irq_tab[i];
  921. /* deinitialize services */
  922. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  923. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  924. gdth_writeb(0, &dp2_ptr->io.event);
  925. retries = INIT_RETRIES;
  926. gdth_delay(20);
  927. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  928. if (--retries == 0) {
  929. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  930. iounmap(ha->brd);
  931. return 0;
  932. }
  933. gdth_delay(1);
  934. }
  935. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  936. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  937. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  938. if (prot_ver != PROTOCOL_VERSION) {
  939. printk("GDT-ISA: Illegal protocol version\n");
  940. iounmap(ha->brd);
  941. return 0;
  942. }
  943. ha->oem_id = OEM_ID_ICP;
  944. ha->type = GDT_ISA;
  945. ha->ic_all_size = sizeof(dp2_ptr->u);
  946. ha->stype= GDT2_ID;
  947. ha->brd_phys = bios_adr >> 4;
  948. /* special request to controller BIOS */
  949. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  950. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  951. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  952. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  953. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  954. gdth_writeb(0, &dp2_ptr->io.event);
  955. retries = INIT_RETRIES;
  956. gdth_delay(20);
  957. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  958. if (--retries == 0) {
  959. printk("GDT-ISA: Initialization error\n");
  960. iounmap(ha->brd);
  961. return 0;
  962. }
  963. gdth_delay(1);
  964. }
  965. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  966. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  967. ha->dma64_support = 0;
  968. return 1;
  969. }
  970. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  971. {
  972. register gdt6_dpram_str __iomem *dp6_ptr;
  973. register gdt6c_dpram_str __iomem *dp6c_ptr;
  974. register gdt6m_dpram_str __iomem *dp6m_ptr;
  975. ulong32 retries;
  976. unchar prot_ver;
  977. ushort command;
  978. int i, found = FALSE;
  979. TRACE(("gdth_init_pci()\n"));
  980. if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
  981. ha->oem_id = OEM_ID_INTEL;
  982. else
  983. ha->oem_id = OEM_ID_ICP;
  984. ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
  985. ha->stype = (ulong32)pcistr->device_id;
  986. ha->subdevice_id = pcistr->subdevice_id;
  987. ha->irq = pcistr->irq;
  988. ha->pdev = pcistr->pdev;
  989. if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  990. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  991. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  992. if (ha->brd == NULL) {
  993. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  994. return 0;
  995. }
  996. /* check and reset interface area */
  997. dp6_ptr = ha->brd;
  998. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  999. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1000. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1001. pcistr->dpmem);
  1002. found = FALSE;
  1003. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1004. iounmap(ha->brd);
  1005. ha->brd = ioremap(i, sizeof(ushort));
  1006. if (ha->brd == NULL) {
  1007. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1008. return 0;
  1009. }
  1010. if (gdth_readw(ha->brd) != 0xffff) {
  1011. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1012. continue;
  1013. }
  1014. iounmap(ha->brd);
  1015. pci_write_config_dword(pcistr->pdev,
  1016. PCI_BASE_ADDRESS_0, i);
  1017. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1018. if (ha->brd == NULL) {
  1019. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1020. return 0;
  1021. }
  1022. dp6_ptr = ha->brd;
  1023. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1024. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1025. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1026. found = TRUE;
  1027. break;
  1028. }
  1029. }
  1030. if (!found) {
  1031. printk("GDT-PCI: No free address found!\n");
  1032. iounmap(ha->brd);
  1033. return 0;
  1034. }
  1035. }
  1036. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1037. if (gdth_readl(&dp6_ptr->u) != 0) {
  1038. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1039. iounmap(ha->brd);
  1040. return 0;
  1041. }
  1042. /* disable board interrupts, deinit services */
  1043. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1044. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1045. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1046. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1047. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1048. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1049. gdth_writeb(0, &dp6_ptr->io.event);
  1050. retries = INIT_RETRIES;
  1051. gdth_delay(20);
  1052. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1053. if (--retries == 0) {
  1054. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1055. iounmap(ha->brd);
  1056. return 0;
  1057. }
  1058. gdth_delay(1);
  1059. }
  1060. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1061. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1062. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1063. if (prot_ver != PROTOCOL_VERSION) {
  1064. printk("GDT-PCI: Illegal protocol version\n");
  1065. iounmap(ha->brd);
  1066. return 0;
  1067. }
  1068. ha->type = GDT_PCI;
  1069. ha->ic_all_size = sizeof(dp6_ptr->u);
  1070. /* special command to controller BIOS */
  1071. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1072. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1073. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1074. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1075. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1076. gdth_writeb(0, &dp6_ptr->io.event);
  1077. retries = INIT_RETRIES;
  1078. gdth_delay(20);
  1079. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1080. if (--retries == 0) {
  1081. printk("GDT-PCI: Initialization error\n");
  1082. iounmap(ha->brd);
  1083. return 0;
  1084. }
  1085. gdth_delay(1);
  1086. }
  1087. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1088. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1089. ha->dma64_support = 0;
  1090. } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1091. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1092. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1093. pcistr->dpmem,ha->irq));
  1094. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1095. if (ha->brd == NULL) {
  1096. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1097. iounmap(ha->brd);
  1098. return 0;
  1099. }
  1100. /* check and reset interface area */
  1101. dp6c_ptr = ha->brd;
  1102. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1103. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1104. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1105. pcistr->dpmem);
  1106. found = FALSE;
  1107. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1108. iounmap(ha->brd);
  1109. ha->brd = ioremap(i, sizeof(ushort));
  1110. if (ha->brd == NULL) {
  1111. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1112. return 0;
  1113. }
  1114. if (gdth_readw(ha->brd) != 0xffff) {
  1115. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1116. continue;
  1117. }
  1118. iounmap(ha->brd);
  1119. pci_write_config_dword(pcistr->pdev,
  1120. PCI_BASE_ADDRESS_2, i);
  1121. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1122. if (ha->brd == NULL) {
  1123. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1124. return 0;
  1125. }
  1126. dp6c_ptr = ha->brd;
  1127. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1128. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1129. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1130. found = TRUE;
  1131. break;
  1132. }
  1133. }
  1134. if (!found) {
  1135. printk("GDT-PCI: No free address found!\n");
  1136. iounmap(ha->brd);
  1137. return 0;
  1138. }
  1139. }
  1140. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1141. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1142. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1143. iounmap(ha->brd);
  1144. return 0;
  1145. }
  1146. /* disable board interrupts, deinit services */
  1147. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1148. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1149. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1150. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1151. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1152. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1153. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1154. retries = INIT_RETRIES;
  1155. gdth_delay(20);
  1156. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1157. if (--retries == 0) {
  1158. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1159. iounmap(ha->brd);
  1160. return 0;
  1161. }
  1162. gdth_delay(1);
  1163. }
  1164. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1165. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1166. if (prot_ver != PROTOCOL_VERSION) {
  1167. printk("GDT-PCI: Illegal protocol version\n");
  1168. iounmap(ha->brd);
  1169. return 0;
  1170. }
  1171. ha->type = GDT_PCINEW;
  1172. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1173. /* special command to controller BIOS */
  1174. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1175. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1176. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1177. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1178. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1179. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1180. retries = INIT_RETRIES;
  1181. gdth_delay(20);
  1182. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1183. if (--retries == 0) {
  1184. printk("GDT-PCI: Initialization error\n");
  1185. iounmap(ha->brd);
  1186. return 0;
  1187. }
  1188. gdth_delay(1);
  1189. }
  1190. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1191. ha->dma64_support = 0;
  1192. } else { /* MPR */
  1193. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1194. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1195. if (ha->brd == NULL) {
  1196. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1197. return 0;
  1198. }
  1199. /* manipulate config. space to enable DPMEM, start RP controller */
  1200. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1201. command |= 6;
  1202. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1203. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1204. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1205. i = 0xFEFF0001UL;
  1206. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1207. gdth_delay(1);
  1208. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1209. pci_resource_start(pcistr->pdev, 8));
  1210. dp6m_ptr = ha->brd;
  1211. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1212. * Aditional check needed for Xscale based RAID controllers */
  1213. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1214. gdth_delay(1);
  1215. /* check and reset interface area */
  1216. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1217. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1218. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1219. pcistr->dpmem);
  1220. found = FALSE;
  1221. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1222. iounmap(ha->brd);
  1223. ha->brd = ioremap(i, sizeof(ushort));
  1224. if (ha->brd == NULL) {
  1225. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1226. return 0;
  1227. }
  1228. if (gdth_readw(ha->brd) != 0xffff) {
  1229. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1230. continue;
  1231. }
  1232. iounmap(ha->brd);
  1233. pci_write_config_dword(pcistr->pdev,
  1234. PCI_BASE_ADDRESS_0, i);
  1235. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1236. if (ha->brd == NULL) {
  1237. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1238. return 0;
  1239. }
  1240. dp6m_ptr = ha->brd;
  1241. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1242. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1243. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1244. found = TRUE;
  1245. break;
  1246. }
  1247. }
  1248. if (!found) {
  1249. printk("GDT-PCI: No free address found!\n");
  1250. iounmap(ha->brd);
  1251. return 0;
  1252. }
  1253. }
  1254. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1255. /* disable board interrupts, deinit services */
  1256. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1257. &dp6m_ptr->i960r.edoor_en_reg);
  1258. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1259. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1260. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1261. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1262. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1263. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1264. retries = INIT_RETRIES;
  1265. gdth_delay(20);
  1266. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1267. if (--retries == 0) {
  1268. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1269. iounmap(ha->brd);
  1270. return 0;
  1271. }
  1272. gdth_delay(1);
  1273. }
  1274. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1275. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1276. if (prot_ver != PROTOCOL_VERSION) {
  1277. printk("GDT-PCI: Illegal protocol version\n");
  1278. iounmap(ha->brd);
  1279. return 0;
  1280. }
  1281. ha->type = GDT_PCIMPR;
  1282. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1283. /* special command to controller BIOS */
  1284. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1285. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1286. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1287. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1288. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1289. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1290. retries = INIT_RETRIES;
  1291. gdth_delay(20);
  1292. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1293. if (--retries == 0) {
  1294. printk("GDT-PCI: Initialization error\n");
  1295. iounmap(ha->brd);
  1296. return 0;
  1297. }
  1298. gdth_delay(1);
  1299. }
  1300. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1301. /* read FW version to detect 64-bit DMA support */
  1302. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1303. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1304. retries = INIT_RETRIES;
  1305. gdth_delay(20);
  1306. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1307. if (--retries == 0) {
  1308. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1309. iounmap(ha->brd);
  1310. return 0;
  1311. }
  1312. gdth_delay(1);
  1313. }
  1314. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1315. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1316. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1317. ha->dma64_support = 0;
  1318. else
  1319. ha->dma64_support = 1;
  1320. }
  1321. return 1;
  1322. }
  1323. /* controller protocol functions */
  1324. static void __init gdth_enable_int(int hanum)
  1325. {
  1326. gdth_ha_str *ha;
  1327. ulong flags;
  1328. gdt2_dpram_str __iomem *dp2_ptr;
  1329. gdt6_dpram_str __iomem *dp6_ptr;
  1330. gdt6m_dpram_str __iomem *dp6m_ptr;
  1331. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1332. ha = HADATA(gdth_ctr_tab[hanum]);
  1333. spin_lock_irqsave(&ha->smp_lock, flags);
  1334. if (ha->type == GDT_EISA) {
  1335. outb(0xff, ha->bmic + EDOORREG);
  1336. outb(0xff, ha->bmic + EDENABREG);
  1337. outb(0x01, ha->bmic + EINTENABREG);
  1338. } else if (ha->type == GDT_ISA) {
  1339. dp2_ptr = ha->brd;
  1340. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1341. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1342. gdth_writeb(1, &dp2_ptr->io.irqen);
  1343. } else if (ha->type == GDT_PCI) {
  1344. dp6_ptr = ha->brd;
  1345. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1346. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1347. gdth_writeb(1, &dp6_ptr->io.irqen);
  1348. } else if (ha->type == GDT_PCINEW) {
  1349. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1350. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1351. } else if (ha->type == GDT_PCIMPR) {
  1352. dp6m_ptr = ha->brd;
  1353. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1354. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1355. &dp6m_ptr->i960r.edoor_en_reg);
  1356. }
  1357. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1358. }
  1359. static int gdth_get_status(unchar *pIStatus,int irq)
  1360. {
  1361. register gdth_ha_str *ha;
  1362. int i;
  1363. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1364. irq,gdth_ctr_count));
  1365. *pIStatus = 0;
  1366. for (i=0; i<gdth_ctr_count; ++i) {
  1367. ha = HADATA(gdth_ctr_tab[i]);
  1368. if (ha->irq != (unchar)irq) /* check IRQ */
  1369. continue;
  1370. if (ha->type == GDT_EISA)
  1371. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1372. else if (ha->type == GDT_ISA)
  1373. *pIStatus =
  1374. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1375. else if (ha->type == GDT_PCI)
  1376. *pIStatus =
  1377. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1378. else if (ha->type == GDT_PCINEW)
  1379. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1380. else if (ha->type == GDT_PCIMPR)
  1381. *pIStatus =
  1382. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1383. if (*pIStatus)
  1384. return i; /* board found */
  1385. }
  1386. return -1;
  1387. }
  1388. static int gdth_test_busy(int hanum)
  1389. {
  1390. register gdth_ha_str *ha;
  1391. register int gdtsema0 = 0;
  1392. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1393. ha = HADATA(gdth_ctr_tab[hanum]);
  1394. if (ha->type == GDT_EISA)
  1395. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1396. else if (ha->type == GDT_ISA)
  1397. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1398. else if (ha->type == GDT_PCI)
  1399. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1400. else if (ha->type == GDT_PCINEW)
  1401. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1402. else if (ha->type == GDT_PCIMPR)
  1403. gdtsema0 =
  1404. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1405. return (gdtsema0 & 1);
  1406. }
  1407. static int gdth_get_cmd_index(int hanum)
  1408. {
  1409. register gdth_ha_str *ha;
  1410. int i;
  1411. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1412. ha = HADATA(gdth_ctr_tab[hanum]);
  1413. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1414. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1415. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1416. ha->cmd_tab[i].service = ha->pccb->Service;
  1417. ha->pccb->CommandIndex = (ulong32)i+2;
  1418. return (i+2);
  1419. }
  1420. }
  1421. return 0;
  1422. }
  1423. static void gdth_set_sema0(int hanum)
  1424. {
  1425. register gdth_ha_str *ha;
  1426. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1427. ha = HADATA(gdth_ctr_tab[hanum]);
  1428. if (ha->type == GDT_EISA) {
  1429. outb(1, ha->bmic + SEMA0REG);
  1430. } else if (ha->type == GDT_ISA) {
  1431. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1432. } else if (ha->type == GDT_PCI) {
  1433. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1434. } else if (ha->type == GDT_PCINEW) {
  1435. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1436. } else if (ha->type == GDT_PCIMPR) {
  1437. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1438. }
  1439. }
  1440. static void gdth_copy_command(int hanum)
  1441. {
  1442. register gdth_ha_str *ha;
  1443. register gdth_cmd_str *cmd_ptr;
  1444. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1445. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1446. gdt6_dpram_str __iomem *dp6_ptr;
  1447. gdt2_dpram_str __iomem *dp2_ptr;
  1448. ushort cp_count,dp_offset,cmd_no;
  1449. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1450. ha = HADATA(gdth_ctr_tab[hanum]);
  1451. cp_count = ha->cmd_len;
  1452. dp_offset= ha->cmd_offs_dpmem;
  1453. cmd_no = ha->cmd_cnt;
  1454. cmd_ptr = ha->pccb;
  1455. ++ha->cmd_cnt;
  1456. if (ha->type == GDT_EISA)
  1457. return; /* no DPMEM, no copy */
  1458. /* set cpcount dword aligned */
  1459. if (cp_count & 3)
  1460. cp_count += (4 - (cp_count & 3));
  1461. ha->cmd_offs_dpmem += cp_count;
  1462. /* set offset and service, copy command to DPMEM */
  1463. if (ha->type == GDT_ISA) {
  1464. dp2_ptr = ha->brd;
  1465. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1466. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1467. gdth_writew((ushort)cmd_ptr->Service,
  1468. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1469. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1470. } else if (ha->type == GDT_PCI) {
  1471. dp6_ptr = ha->brd;
  1472. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1473. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1474. gdth_writew((ushort)cmd_ptr->Service,
  1475. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1476. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1477. } else if (ha->type == GDT_PCINEW) {
  1478. dp6c_ptr = ha->brd;
  1479. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1480. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1481. gdth_writew((ushort)cmd_ptr->Service,
  1482. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1483. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1484. } else if (ha->type == GDT_PCIMPR) {
  1485. dp6m_ptr = ha->brd;
  1486. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1487. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1488. gdth_writew((ushort)cmd_ptr->Service,
  1489. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1490. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1491. }
  1492. }
  1493. static void gdth_release_event(int hanum)
  1494. {
  1495. register gdth_ha_str *ha;
  1496. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1497. ha = HADATA(gdth_ctr_tab[hanum]);
  1498. #ifdef GDTH_STATISTICS
  1499. {
  1500. ulong32 i,j;
  1501. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1502. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1503. ++i;
  1504. }
  1505. if (max_index < i) {
  1506. max_index = i;
  1507. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1508. }
  1509. }
  1510. #endif
  1511. if (ha->pccb->OpCode == GDT_INIT)
  1512. ha->pccb->Service |= 0x80;
  1513. if (ha->type == GDT_EISA) {
  1514. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1515. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1516. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1517. } else if (ha->type == GDT_ISA) {
  1518. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1519. } else if (ha->type == GDT_PCI) {
  1520. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1521. } else if (ha->type == GDT_PCINEW) {
  1522. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1523. } else if (ha->type == GDT_PCIMPR) {
  1524. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1525. }
  1526. }
  1527. static int gdth_wait(int hanum,int index,ulong32 time)
  1528. {
  1529. gdth_ha_str *ha;
  1530. int answer_found = FALSE;
  1531. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1532. ha = HADATA(gdth_ctr_tab[hanum]);
  1533. if (index == 0)
  1534. return 1; /* no wait required */
  1535. gdth_from_wait = TRUE;
  1536. do {
  1537. gdth_interrupt((int)ha->irq,ha,NULL);
  1538. if (wait_hanum==hanum && wait_index==index) {
  1539. answer_found = TRUE;
  1540. break;
  1541. }
  1542. gdth_delay(1);
  1543. } while (--time);
  1544. gdth_from_wait = FALSE;
  1545. while (gdth_test_busy(hanum))
  1546. gdth_delay(0);
  1547. return (answer_found);
  1548. }
  1549. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1550. ulong64 p2,ulong64 p3)
  1551. {
  1552. register gdth_ha_str *ha;
  1553. register gdth_cmd_str *cmd_ptr;
  1554. int retries,index;
  1555. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1556. ha = HADATA(gdth_ctr_tab[hanum]);
  1557. cmd_ptr = ha->pccb;
  1558. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1559. /* make command */
  1560. for (retries = INIT_RETRIES;;) {
  1561. cmd_ptr->Service = service;
  1562. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1563. if (!(index=gdth_get_cmd_index(hanum))) {
  1564. TRACE(("GDT: No free command index found\n"));
  1565. return 0;
  1566. }
  1567. gdth_set_sema0(hanum);
  1568. cmd_ptr->OpCode = opcode;
  1569. cmd_ptr->BoardNode = LOCALBOARD;
  1570. if (service == CACHESERVICE) {
  1571. if (opcode == GDT_IOCTL) {
  1572. cmd_ptr->u.ioctl.subfunc = p1;
  1573. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1574. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1575. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1576. } else {
  1577. if (ha->cache_feat & GDT_64BIT) {
  1578. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1579. cmd_ptr->u.cache64.BlockNo = p2;
  1580. } else {
  1581. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1582. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1583. }
  1584. }
  1585. } else if (service == SCSIRAWSERVICE) {
  1586. if (ha->raw_feat & GDT_64BIT) {
  1587. cmd_ptr->u.raw64.direction = p1;
  1588. cmd_ptr->u.raw64.bus = (unchar)p2;
  1589. cmd_ptr->u.raw64.target = (unchar)p3;
  1590. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1591. } else {
  1592. cmd_ptr->u.raw.direction = p1;
  1593. cmd_ptr->u.raw.bus = (unchar)p2;
  1594. cmd_ptr->u.raw.target = (unchar)p3;
  1595. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1596. }
  1597. } else if (service == SCREENSERVICE) {
  1598. if (opcode == GDT_REALTIME) {
  1599. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1600. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1601. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1602. }
  1603. }
  1604. ha->cmd_len = sizeof(gdth_cmd_str);
  1605. ha->cmd_offs_dpmem = 0;
  1606. ha->cmd_cnt = 0;
  1607. gdth_copy_command(hanum);
  1608. gdth_release_event(hanum);
  1609. gdth_delay(20);
  1610. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1611. printk("GDT: Initialization error (timeout service %d)\n",service);
  1612. return 0;
  1613. }
  1614. if (ha->status != S_BSY || --retries == 0)
  1615. break;
  1616. gdth_delay(1);
  1617. }
  1618. return (ha->status != S_OK ? 0:1);
  1619. }
  1620. /* search for devices */
  1621. static int __init gdth_search_drives(int hanum)
  1622. {
  1623. register gdth_ha_str *ha;
  1624. ushort cdev_cnt, i;
  1625. int ok;
  1626. ulong32 bus_no, drv_cnt, drv_no, j;
  1627. gdth_getch_str *chn;
  1628. gdth_drlist_str *drl;
  1629. gdth_iochan_str *ioc;
  1630. gdth_raw_iochan_str *iocr;
  1631. gdth_arcdl_str *alst;
  1632. gdth_alist_str *alst2;
  1633. gdth_oem_str_ioctl *oemstr;
  1634. #ifdef INT_COAL
  1635. gdth_perf_modes *pmod;
  1636. #endif
  1637. #ifdef GDTH_RTC
  1638. unchar rtc[12];
  1639. ulong flags;
  1640. #endif
  1641. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1642. ha = HADATA(gdth_ctr_tab[hanum]);
  1643. ok = 0;
  1644. /* initialize controller services, at first: screen service */
  1645. ha->screen_feat = 0;
  1646. if (!force_dma32) {
  1647. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1648. if (ok)
  1649. ha->screen_feat = GDT_64BIT;
  1650. }
  1651. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1652. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1653. if (!ok) {
  1654. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1655. hanum, ha->status);
  1656. return 0;
  1657. }
  1658. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1659. #ifdef GDTH_RTC
  1660. /* read realtime clock info, send to controller */
  1661. /* 1. wait for the falling edge of update flag */
  1662. spin_lock_irqsave(&rtc_lock, flags);
  1663. for (j = 0; j < 1000000; ++j)
  1664. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1665. break;
  1666. for (j = 0; j < 1000000; ++j)
  1667. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1668. break;
  1669. /* 2. read info */
  1670. do {
  1671. for (j = 0; j < 12; ++j)
  1672. rtc[j] = CMOS_READ(j);
  1673. } while (rtc[0] != CMOS_READ(0));
  1674. spin_lock_irqrestore(&rtc_lock, flags);
  1675. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1676. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1677. /* 3. send to controller firmware */
  1678. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1679. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1680. #endif
  1681. /* unfreeze all IOs */
  1682. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1683. /* initialize cache service */
  1684. ha->cache_feat = 0;
  1685. if (!force_dma32) {
  1686. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1687. if (ok)
  1688. ha->cache_feat = GDT_64BIT;
  1689. }
  1690. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1691. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1692. if (!ok) {
  1693. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1694. hanum, ha->status);
  1695. return 0;
  1696. }
  1697. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1698. cdev_cnt = (ushort)ha->info;
  1699. ha->fw_vers = ha->service;
  1700. #ifdef INT_COAL
  1701. if (ha->type == GDT_PCIMPR) {
  1702. /* set perf. modes */
  1703. pmod = (gdth_perf_modes *)ha->pscratch;
  1704. pmod->version = 1;
  1705. pmod->st_mode = 1; /* enable one status buffer */
  1706. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1707. pmod->st_buff_indx1 = COALINDEX;
  1708. pmod->st_buff_addr2 = 0;
  1709. pmod->st_buff_u_addr2 = 0;
  1710. pmod->st_buff_indx2 = 0;
  1711. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1712. pmod->cmd_mode = 0; // disable all cmd buffers
  1713. pmod->cmd_buff_addr1 = 0;
  1714. pmod->cmd_buff_u_addr1 = 0;
  1715. pmod->cmd_buff_indx1 = 0;
  1716. pmod->cmd_buff_addr2 = 0;
  1717. pmod->cmd_buff_u_addr2 = 0;
  1718. pmod->cmd_buff_indx2 = 0;
  1719. pmod->cmd_buff_size = 0;
  1720. pmod->reserved1 = 0;
  1721. pmod->reserved2 = 0;
  1722. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1723. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1724. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1725. }
  1726. }
  1727. #endif
  1728. /* detect number of buses - try new IOCTL */
  1729. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1730. iocr->hdr.version = 0xffffffff;
  1731. iocr->hdr.list_entries = MAXBUS;
  1732. iocr->hdr.first_chan = 0;
  1733. iocr->hdr.last_chan = MAXBUS-1;
  1734. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1735. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1736. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1737. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1738. ha->bus_cnt = iocr->hdr.chan_count;
  1739. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1740. if (iocr->list[bus_no].proc_id < MAXID)
  1741. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1742. else
  1743. ha->bus_id[bus_no] = 0xff;
  1744. }
  1745. } else {
  1746. /* old method */
  1747. chn = (gdth_getch_str *)ha->pscratch;
  1748. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1749. chn->channel_no = bus_no;
  1750. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1751. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1752. IO_CHANNEL | INVALID_CHANNEL,
  1753. sizeof(gdth_getch_str))) {
  1754. if (bus_no == 0) {
  1755. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1756. hanum, ha->status);
  1757. return 0;
  1758. }
  1759. break;
  1760. }
  1761. if (chn->siop_id < MAXID)
  1762. ha->bus_id[bus_no] = chn->siop_id;
  1763. else
  1764. ha->bus_id[bus_no] = 0xff;
  1765. }
  1766. ha->bus_cnt = (unchar)bus_no;
  1767. }
  1768. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1769. /* read cache configuration */
  1770. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1771. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1772. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1773. hanum, ha->status);
  1774. return 0;
  1775. }
  1776. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1777. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1778. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1779. ha->cpar.write_back,ha->cpar.block_size));
  1780. /* read board info and features */
  1781. ha->more_proc = FALSE;
  1782. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1783. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1784. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1785. sizeof(gdth_binfo_str));
  1786. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1787. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1788. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1789. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1790. ha->more_proc = TRUE;
  1791. }
  1792. } else {
  1793. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1794. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1795. }
  1796. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1797. /* read more informations */
  1798. if (ha->more_proc) {
  1799. /* physical drives, channel addresses */
  1800. ioc = (gdth_iochan_str *)ha->pscratch;
  1801. ioc->hdr.version = 0xffffffff;
  1802. ioc->hdr.list_entries = MAXBUS;
  1803. ioc->hdr.first_chan = 0;
  1804. ioc->hdr.last_chan = MAXBUS-1;
  1805. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1806. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1807. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1808. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1809. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1810. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1811. }
  1812. } else {
  1813. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1814. ha->raw[bus_no].address = IO_CHANNEL;
  1815. ha->raw[bus_no].local_no = bus_no;
  1816. }
  1817. }
  1818. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1819. chn = (gdth_getch_str *)ha->pscratch;
  1820. chn->channel_no = ha->raw[bus_no].local_no;
  1821. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1822. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1823. ha->raw[bus_no].address | INVALID_CHANNEL,
  1824. sizeof(gdth_getch_str))) {
  1825. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1826. TRACE2(("Channel %d: %d phys. drives\n",
  1827. bus_no,chn->drive_cnt));
  1828. }
  1829. if (ha->raw[bus_no].pdev_cnt > 0) {
  1830. drl = (gdth_drlist_str *)ha->pscratch;
  1831. drl->sc_no = ha->raw[bus_no].local_no;
  1832. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1833. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1834. SCSI_DR_LIST | L_CTRL_PATTERN,
  1835. ha->raw[bus_no].address | INVALID_CHANNEL,
  1836. sizeof(gdth_drlist_str))) {
  1837. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1838. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1839. } else {
  1840. ha->raw[bus_no].pdev_cnt = 0;
  1841. }
  1842. }
  1843. }
  1844. /* logical drives */
  1845. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1846. INVALID_CHANNEL,sizeof(ulong32))) {
  1847. drv_cnt = *(ulong32 *)ha->pscratch;
  1848. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1849. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1850. for (j = 0; j < drv_cnt; ++j) {
  1851. drv_no = ((ulong32 *)ha->pscratch)[j];
  1852. if (drv_no < MAX_LDRIVES) {
  1853. ha->hdr[drv_no].is_logdrv = TRUE;
  1854. TRACE2(("Drive %d is log. drive\n",drv_no));
  1855. }
  1856. }
  1857. }
  1858. alst = (gdth_arcdl_str *)ha->pscratch;
  1859. alst->entries_avail = MAX_LDRIVES;
  1860. alst->first_entry = 0;
  1861. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1862. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1863. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1864. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1865. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1866. for (j = 0; j < alst->entries_init; ++j) {
  1867. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1868. ha->hdr[j].is_master = alst->list[j].is_master;
  1869. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1870. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1871. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1872. }
  1873. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1874. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1875. 0, 35 * sizeof(gdth_alist_str))) {
  1876. for (j = 0; j < 35; ++j) {
  1877. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1878. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1879. ha->hdr[j].is_master = alst2->is_master;
  1880. ha->hdr[j].is_parity = alst2->is_parity;
  1881. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1882. ha->hdr[j].master_no = alst2->cd_handle;
  1883. }
  1884. }
  1885. }
  1886. }
  1887. /* initialize raw service */
  1888. ha->raw_feat = 0;
  1889. if (!force_dma32) {
  1890. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  1891. if (ok)
  1892. ha->raw_feat = GDT_64BIT;
  1893. }
  1894. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1895. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  1896. if (!ok) {
  1897. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1898. hanum, ha->status);
  1899. return 0;
  1900. }
  1901. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1902. /* set/get features raw service (scatter/gather) */
  1903. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  1904. 0,0)) {
  1905. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1906. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  1907. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1908. ha->info));
  1909. ha->raw_feat |= (ushort)ha->info;
  1910. }
  1911. }
  1912. /* set/get features cache service (equal to raw service) */
  1913. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  1914. SCATTER_GATHER,0)) {
  1915. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1916. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  1917. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1918. ha->info));
  1919. ha->cache_feat |= (ushort)ha->info;
  1920. }
  1921. }
  1922. /* reserve drives for raw service */
  1923. if (reserve_mode != 0) {
  1924. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  1925. reserve_mode == 1 ? 1 : 3, 0, 0);
  1926. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1927. ha->status));
  1928. }
  1929. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1930. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  1931. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1932. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1933. reserve_list[i], reserve_list[i+1],
  1934. reserve_list[i+2], reserve_list[i+3]));
  1935. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  1936. reserve_list[i+1], reserve_list[i+2] |
  1937. (reserve_list[i+3] << 8))) {
  1938. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1939. hanum, ha->status);
  1940. }
  1941. }
  1942. }
  1943. /* Determine OEM string using IOCTL */
  1944. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1945. oemstr->params.ctl_version = 0x01;
  1946. oemstr->params.buffer_size = sizeof(oemstr->text);
  1947. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1948. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1949. sizeof(gdth_oem_str_ioctl))) {
  1950. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1951. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1952. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  1953. /* Save the Host Drive inquiry data */
  1954. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  1955. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1956. sizeof(ha->oem_name));
  1957. #else
  1958. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  1959. ha->oem_name[7] = '\0';
  1960. #endif
  1961. } else {
  1962. /* Old method, based on PCI ID */
  1963. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1964. printk("GDT-HA %d: Name: %s\n",
  1965. hanum,ha->binfo.type_string);
  1966. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  1967. if (ha->oem_id == OEM_ID_INTEL)
  1968. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1969. else
  1970. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1971. #else
  1972. if (ha->oem_id == OEM_ID_INTEL)
  1973. strcpy(ha->oem_name,"Intel ");
  1974. else
  1975. strcpy(ha->oem_name,"ICP ");
  1976. #endif
  1977. }
  1978. /* scanning for host drives */
  1979. for (i = 0; i < cdev_cnt; ++i)
  1980. gdth_analyse_hdrive(hanum,i);
  1981. TRACE(("gdth_search_drives() OK\n"));
  1982. return 1;
  1983. }
  1984. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  1985. {
  1986. register gdth_ha_str *ha;
  1987. ulong32 drv_cyls;
  1988. int drv_hds, drv_secs;
  1989. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  1990. if (hdrive >= MAX_HDRIVES)
  1991. return 0;
  1992. ha = HADATA(gdth_ctr_tab[hanum]);
  1993. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  1994. return 0;
  1995. ha->hdr[hdrive].present = TRUE;
  1996. ha->hdr[hdrive].size = ha->info;
  1997. /* evaluate mapping (sectors per head, heads per cylinder) */
  1998. ha->hdr[hdrive].size &= ~SECS32;
  1999. if (ha->info2 == 0) {
  2000. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2001. } else {
  2002. drv_hds = ha->info2 & 0xff;
  2003. drv_secs = (ha->info2 >> 8) & 0xff;
  2004. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2005. }
  2006. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2007. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2008. /* round size */
  2009. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2010. if (ha->cache_feat & GDT_64BIT) {
  2011. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2012. && ha->info2 != 0) {
  2013. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2014. }
  2015. }
  2016. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2017. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2018. /* get informations about device */
  2019. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2020. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2021. hdrive,ha->info));
  2022. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2023. }
  2024. /* cluster info */
  2025. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2026. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2027. hdrive,ha->info));
  2028. if (!shared_access)
  2029. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2030. }
  2031. /* R/W attributes */
  2032. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2033. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2034. hdrive,ha->info));
  2035. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2036. }
  2037. return 1;
  2038. }
  2039. /* command queueing/sending functions */
  2040. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2041. {
  2042. register gdth_ha_str *ha;
  2043. register Scsi_Cmnd *pscp;
  2044. register Scsi_Cmnd *nscp;
  2045. ulong flags;
  2046. unchar b, t;
  2047. TRACE(("gdth_putq() priority %d\n",priority));
  2048. ha = HADATA(gdth_ctr_tab[hanum]);
  2049. spin_lock_irqsave(&ha->smp_lock, flags);
  2050. scp->SCp.this_residual = (int)priority;
  2051. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  2052. t = scp->device->id;
  2053. if (priority >= DEFAULT_PRI) {
  2054. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2055. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
  2056. TRACE2(("gdth_putq(): locked IO -> update_timeout()\n"));
  2057. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2058. }
  2059. }
  2060. if (ha->req_first==NULL) {
  2061. ha->req_first = scp; /* queue was empty */
  2062. scp->SCp.ptr = NULL;
  2063. } else { /* queue not empty */
  2064. pscp = ha->req_first;
  2065. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2066. /* priority: 0-highest,..,0xff-lowest */
  2067. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2068. pscp = nscp;
  2069. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2070. }
  2071. pscp->SCp.ptr = (char *)scp;
  2072. scp->SCp.ptr = (char *)nscp;
  2073. }
  2074. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2075. #ifdef GDTH_STATISTICS
  2076. flags = 0;
  2077. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2078. ++flags;
  2079. if (max_rq < flags) {
  2080. max_rq = flags;
  2081. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2082. }
  2083. #endif
  2084. }
  2085. static void gdth_next(int hanum)
  2086. {
  2087. register gdth_ha_str *ha;
  2088. register Scsi_Cmnd *pscp;
  2089. register Scsi_Cmnd *nscp;
  2090. unchar b, t, l, firsttime;
  2091. unchar this_cmd, next_cmd;
  2092. ulong flags = 0;
  2093. int cmd_index;
  2094. TRACE(("gdth_next() hanum %d\n",hanum));
  2095. ha = HADATA(gdth_ctr_tab[hanum]);
  2096. if (!gdth_polling)
  2097. spin_lock_irqsave(&ha->smp_lock, flags);
  2098. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2099. this_cmd = firsttime = TRUE;
  2100. next_cmd = gdth_polling ? FALSE:TRUE;
  2101. cmd_index = 0;
  2102. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2103. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2104. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2105. b = virt_ctr ? NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2106. t = nscp->device->id;
  2107. l = nscp->device->lun;
  2108. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2109. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2110. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2111. continue;
  2112. }
  2113. if (firsttime) {
  2114. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2115. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2116. if (!gdth_polling) {
  2117. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2118. return;
  2119. }
  2120. while (gdth_test_busy(hanum))
  2121. gdth_delay(1);
  2122. }
  2123. firsttime = FALSE;
  2124. }
  2125. if (nscp->done != gdth_scsi_done || nscp->cmnd[0] != 0xff) {
  2126. if (nscp->SCp.phase == -1) {
  2127. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2128. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2129. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2130. b, t, l));
  2131. /* TEST_UNIT_READY -> set scan mode */
  2132. if ((ha->scan_mode & 0x0f) == 0) {
  2133. if (b == 0 && t == 0 && l == 0) {
  2134. ha->scan_mode |= 1;
  2135. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2136. }
  2137. } else if ((ha->scan_mode & 0x0f) == 1) {
  2138. if (b == 0 && ((t == 0 && l == 1) ||
  2139. (t == 1 && l == 0))) {
  2140. nscp->SCp.sent_command = GDT_SCAN_START;
  2141. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2142. | SCSIRAWSERVICE;
  2143. ha->scan_mode = 0x12;
  2144. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2145. ha->scan_mode));
  2146. } else {
  2147. ha->scan_mode &= 0x10;
  2148. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2149. }
  2150. } else if (ha->scan_mode == 0x12) {
  2151. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2152. nscp->SCp.phase = SCSIRAWSERVICE;
  2153. nscp->SCp.sent_command = GDT_SCAN_END;
  2154. ha->scan_mode &= 0x10;
  2155. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2156. ha->scan_mode));
  2157. }
  2158. }
  2159. }
  2160. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2161. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2162. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2163. /* always GDT_CLUST_INFO! */
  2164. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2165. }
  2166. }
  2167. }
  2168. if (nscp->SCp.sent_command != -1) {
  2169. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2170. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2171. this_cmd = FALSE;
  2172. next_cmd = FALSE;
  2173. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2174. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2175. this_cmd = FALSE;
  2176. next_cmd = FALSE;
  2177. } else {
  2178. memset((char*)nscp->sense_buffer,0,16);
  2179. nscp->sense_buffer[0] = 0x70;
  2180. nscp->sense_buffer[2] = NOT_READY;
  2181. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2182. if (!nscp->SCp.have_data_in)
  2183. nscp->SCp.have_data_in++;
  2184. else
  2185. nscp->scsi_done(nscp);
  2186. }
  2187. } else if (nscp->done == gdth_scsi_done && nscp->cmnd[0] == 0xff) {
  2188. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2189. this_cmd = FALSE;
  2190. next_cmd = FALSE;
  2191. } else if (b != ha->virt_bus) {
  2192. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2193. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2194. this_cmd = FALSE;
  2195. else
  2196. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2197. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2198. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2199. nscp->cmnd[0], b, t, l));
  2200. nscp->result = DID_BAD_TARGET << 16;
  2201. if (!nscp->SCp.have_data_in)
  2202. nscp->SCp.have_data_in++;
  2203. else
  2204. nscp->scsi_done(nscp);
  2205. } else {
  2206. switch (nscp->cmnd[0]) {
  2207. case TEST_UNIT_READY:
  2208. case INQUIRY:
  2209. case REQUEST_SENSE:
  2210. case READ_CAPACITY:
  2211. case VERIFY:
  2212. case START_STOP:
  2213. case MODE_SENSE:
  2214. case SERVICE_ACTION_IN:
  2215. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2216. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2217. nscp->cmnd[4],nscp->cmnd[5]));
  2218. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2219. /* return UNIT_ATTENTION */
  2220. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2221. nscp->cmnd[0], t));
  2222. ha->hdr[t].media_changed = FALSE;
  2223. memset((char*)nscp->sense_buffer,0,16);
  2224. nscp->sense_buffer[0] = 0x70;
  2225. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2226. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2227. if (!nscp->SCp.have_data_in)
  2228. nscp->SCp.have_data_in++;
  2229. else
  2230. nscp->scsi_done(nscp);
  2231. } else if (gdth_internal_cache_cmd(hanum,nscp))
  2232. nscp->scsi_done(nscp);
  2233. break;
  2234. case ALLOW_MEDIUM_REMOVAL:
  2235. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2236. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2237. nscp->cmnd[4],nscp->cmnd[5]));
  2238. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2239. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2240. nscp->result = DID_OK << 16;
  2241. nscp->sense_buffer[0] = 0;
  2242. if (!nscp->SCp.have_data_in)
  2243. nscp->SCp.have_data_in++;
  2244. else
  2245. nscp->scsi_done(nscp);
  2246. } else {
  2247. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2248. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2249. nscp->cmnd[4],nscp->cmnd[3]));
  2250. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2251. this_cmd = FALSE;
  2252. }
  2253. break;
  2254. case RESERVE:
  2255. case RELEASE:
  2256. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2257. "RESERVE" : "RELEASE"));
  2258. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2259. this_cmd = FALSE;
  2260. break;
  2261. case READ_6:
  2262. case WRITE_6:
  2263. case READ_10:
  2264. case WRITE_10:
  2265. case READ_16:
  2266. case WRITE_16:
  2267. if (ha->hdr[t].media_changed) {
  2268. /* return UNIT_ATTENTION */
  2269. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2270. nscp->cmnd[0], t));
  2271. ha->hdr[t].media_changed = FALSE;
  2272. memset((char*)nscp->sense_buffer,0,16);
  2273. nscp->sense_buffer[0] = 0x70;
  2274. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2275. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2276. if (!nscp->SCp.have_data_in)
  2277. nscp->SCp.have_data_in++;
  2278. else
  2279. nscp->scsi_done(nscp);
  2280. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2281. this_cmd = FALSE;
  2282. break;
  2283. default:
  2284. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2285. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2286. nscp->cmnd[4],nscp->cmnd[5]));
  2287. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2288. hanum, nscp->cmnd[0]);
  2289. nscp->result = DID_ABORT << 16;
  2290. if (!nscp->SCp.have_data_in)
  2291. nscp->SCp.have_data_in++;
  2292. else
  2293. nscp->scsi_done(nscp);
  2294. break;
  2295. }
  2296. }
  2297. if (!this_cmd)
  2298. break;
  2299. if (nscp == ha->req_first)
  2300. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2301. else
  2302. pscp->SCp.ptr = nscp->SCp.ptr;
  2303. if (!next_cmd)
  2304. break;
  2305. }
  2306. if (ha->cmd_cnt > 0) {
  2307. gdth_release_event(hanum);
  2308. }
  2309. if (!gdth_polling)
  2310. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2311. if (gdth_polling && ha->cmd_cnt > 0) {
  2312. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2313. printk("GDT-HA %d: Command %d timed out !\n",
  2314. hanum,cmd_index);
  2315. }
  2316. }
  2317. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2318. char *buffer,ushort count)
  2319. {
  2320. ushort cpcount,i;
  2321. ushort cpsum,cpnow;
  2322. struct scatterlist *sl;
  2323. gdth_ha_str *ha;
  2324. char *address;
  2325. cpcount = count<=(ushort)scp->bufflen ? count:(ushort)scp->bufflen;
  2326. ha = HADATA(gdth_ctr_tab[hanum]);
  2327. if (scp->use_sg) {
  2328. sl = (struct scatterlist *)scp->request_buffer;
  2329. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2330. unsigned long flags;
  2331. cpnow = (ushort)sl->length;
  2332. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2333. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2334. if (cpsum+cpnow > cpcount)
  2335. cpnow = cpcount - cpsum;
  2336. cpsum += cpnow;
  2337. if (!sl->page) {
  2338. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2339. hanum);
  2340. return;
  2341. }
  2342. local_irq_save(flags);
  2343. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2344. memcpy(address,buffer,cpnow);
  2345. flush_dcache_page(sl->page);
  2346. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2347. local_irq_restore(flags);
  2348. if (cpsum == cpcount)
  2349. break;
  2350. buffer += cpnow;
  2351. }
  2352. } else {
  2353. TRACE(("copy_internal() count %d\n",cpcount));
  2354. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2355. }
  2356. }
  2357. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2358. {
  2359. register gdth_ha_str *ha;
  2360. unchar t;
  2361. gdth_inq_data inq;
  2362. gdth_rdcap_data rdc;
  2363. gdth_sense_data sd;
  2364. gdth_modep_data mpd;
  2365. ha = HADATA(gdth_ctr_tab[hanum]);
  2366. t = scp->device->id;
  2367. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2368. scp->cmnd[0],t));
  2369. scp->result = DID_OK << 16;
  2370. scp->sense_buffer[0] = 0;
  2371. switch (scp->cmnd[0]) {
  2372. case TEST_UNIT_READY:
  2373. case VERIFY:
  2374. case START_STOP:
  2375. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2376. break;
  2377. case INQUIRY:
  2378. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2379. t,ha->hdr[t].devtype));
  2380. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2381. /* you can here set all disks to removable, if you want to do
  2382. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2383. inq.modif_rmb = 0x00;
  2384. if ((ha->hdr[t].devtype & 1) ||
  2385. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2386. inq.modif_rmb = 0x80;
  2387. inq.version = 2;
  2388. inq.resp_aenc = 2;
  2389. inq.add_length= 32;
  2390. strcpy(inq.vendor,ha->oem_name);
  2391. sprintf(inq.product,"Host Drive #%02d",t);
  2392. strcpy(inq.revision," ");
  2393. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2394. break;
  2395. case REQUEST_SENSE:
  2396. TRACE2(("Request sense hdrive %d\n",t));
  2397. sd.errorcode = 0x70;
  2398. sd.segno = 0x00;
  2399. sd.key = NO_SENSE;
  2400. sd.info = 0;
  2401. sd.add_length= 0;
  2402. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2403. break;
  2404. case MODE_SENSE:
  2405. TRACE2(("Mode sense hdrive %d\n",t));
  2406. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2407. mpd.hd.data_length = sizeof(gdth_modep_data);
  2408. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2409. mpd.hd.bd_length = sizeof(mpd.bd);
  2410. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2411. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2412. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2413. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2414. break;
  2415. case READ_CAPACITY:
  2416. TRACE2(("Read capacity hdrive %d\n",t));
  2417. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2418. rdc.last_block_no = 0xffffffff;
  2419. else
  2420. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2421. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2422. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2423. break;
  2424. case SERVICE_ACTION_IN:
  2425. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2426. (ha->cache_feat & GDT_64BIT)) {
  2427. gdth_rdcap16_data rdc16;
  2428. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2429. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2430. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2431. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2432. } else {
  2433. scp->result = DID_ABORT << 16;
  2434. }
  2435. break;
  2436. default:
  2437. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2438. break;
  2439. }
  2440. if (!scp->SCp.have_data_in)
  2441. scp->SCp.have_data_in++;
  2442. else
  2443. return 1;
  2444. return 0;
  2445. }
  2446. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2447. {
  2448. register gdth_ha_str *ha;
  2449. register gdth_cmd_str *cmdp;
  2450. struct scatterlist *sl;
  2451. ulong32 cnt, blockcnt;
  2452. ulong64 no, blockno;
  2453. dma_addr_t phys_addr;
  2454. int i, cmd_index, read_write, sgcnt, mode64;
  2455. struct page *page;
  2456. ulong offset;
  2457. ha = HADATA(gdth_ctr_tab[hanum]);
  2458. cmdp = ha->pccb;
  2459. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2460. scp->cmnd[0],scp->cmd_len,hdrive));
  2461. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2462. return 0;
  2463. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2464. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2465. not required, should not occur due to error return on
  2466. READ_CAPACITY_16 */
  2467. cmdp->Service = CACHESERVICE;
  2468. cmdp->RequestBuffer = scp;
  2469. /* search free command index */
  2470. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2471. TRACE(("GDT: No free command index found\n"));
  2472. return 0;
  2473. }
  2474. /* if it's the first command, set command semaphore */
  2475. if (ha->cmd_cnt == 0)
  2476. gdth_set_sema0(hanum);
  2477. /* fill command */
  2478. read_write = 0;
  2479. if (scp->SCp.sent_command != -1)
  2480. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2481. else if (scp->cmnd[0] == RESERVE)
  2482. cmdp->OpCode = GDT_RESERVE_DRV;
  2483. else if (scp->cmnd[0] == RELEASE)
  2484. cmdp->OpCode = GDT_RELEASE_DRV;
  2485. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2486. if (scp->cmnd[4] & 1) /* prevent ? */
  2487. cmdp->OpCode = GDT_MOUNT;
  2488. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2489. cmdp->OpCode = GDT_UNMOUNT;
  2490. else
  2491. cmdp->OpCode = GDT_FLUSH;
  2492. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2493. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2494. ) {
  2495. read_write = 1;
  2496. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2497. (ha->cache_feat & GDT_WR_THROUGH)))
  2498. cmdp->OpCode = GDT_WRITE_THR;
  2499. else
  2500. cmdp->OpCode = GDT_WRITE;
  2501. } else {
  2502. read_write = 2;
  2503. cmdp->OpCode = GDT_READ;
  2504. }
  2505. cmdp->BoardNode = LOCALBOARD;
  2506. if (mode64) {
  2507. cmdp->u.cache64.DeviceNo = hdrive;
  2508. cmdp->u.cache64.BlockNo = 1;
  2509. cmdp->u.cache64.sg_canz = 0;
  2510. } else {
  2511. cmdp->u.cache.DeviceNo = hdrive;
  2512. cmdp->u.cache.BlockNo = 1;
  2513. cmdp->u.cache.sg_canz = 0;
  2514. }
  2515. if (read_write) {
  2516. if (scp->cmd_len == 16) {
  2517. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2518. blockno = be64_to_cpu(no);
  2519. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2520. blockcnt = be32_to_cpu(cnt);
  2521. } else if (scp->cmd_len == 10) {
  2522. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2523. blockno = be32_to_cpu(no);
  2524. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2525. blockcnt = be16_to_cpu(cnt);
  2526. } else {
  2527. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2528. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2529. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2530. }
  2531. if (mode64) {
  2532. cmdp->u.cache64.BlockNo = blockno;
  2533. cmdp->u.cache64.BlockCnt = blockcnt;
  2534. } else {
  2535. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2536. cmdp->u.cache.BlockCnt = blockcnt;
  2537. }
  2538. if (scp->use_sg) {
  2539. sl = (struct scatterlist *)scp->request_buffer;
  2540. sgcnt = scp->use_sg;
  2541. scp->SCp.Status = GDTH_MAP_SG;
  2542. scp->SCp.Message = (read_write == 1 ?
  2543. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2544. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2545. if (mode64) {
  2546. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2547. cmdp->u.cache64.sg_canz = sgcnt;
  2548. for (i=0; i<sgcnt; ++i,++sl) {
  2549. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2550. #ifdef GDTH_DMA_STATISTICS
  2551. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2552. ha->dma64_cnt++;
  2553. else
  2554. ha->dma32_cnt++;
  2555. #endif
  2556. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2557. }
  2558. } else {
  2559. cmdp->u.cache.DestAddr= 0xffffffff;
  2560. cmdp->u.cache.sg_canz = sgcnt;
  2561. for (i=0; i<sgcnt; ++i,++sl) {
  2562. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2563. #ifdef GDTH_DMA_STATISTICS
  2564. ha->dma32_cnt++;
  2565. #endif
  2566. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2567. }
  2568. }
  2569. #ifdef GDTH_STATISTICS
  2570. if (max_sg < (ulong32)sgcnt) {
  2571. max_sg = (ulong32)sgcnt;
  2572. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2573. }
  2574. #endif
  2575. } else {
  2576. scp->SCp.Status = GDTH_MAP_SINGLE;
  2577. scp->SCp.Message = (read_write == 1 ?
  2578. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2579. page = virt_to_page(scp->request_buffer);
  2580. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2581. phys_addr = pci_map_page(ha->pdev,page,offset,
  2582. scp->request_bufflen,scp->SCp.Message);
  2583. scp->SCp.dma_handle = phys_addr;
  2584. if (mode64) {
  2585. if (ha->cache_feat & SCATTER_GATHER) {
  2586. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2587. cmdp->u.cache64.sg_canz = 1;
  2588. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2589. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2590. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2591. } else {
  2592. cmdp->u.cache64.DestAddr = phys_addr;
  2593. cmdp->u.cache64.sg_canz= 0;
  2594. }
  2595. } else {
  2596. if (ha->cache_feat & SCATTER_GATHER) {
  2597. cmdp->u.cache.DestAddr = 0xffffffff;
  2598. cmdp->u.cache.sg_canz = 1;
  2599. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2600. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2601. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2602. } else {
  2603. cmdp->u.cache.DestAddr = phys_addr;
  2604. cmdp->u.cache.sg_canz= 0;
  2605. }
  2606. }
  2607. }
  2608. }
  2609. /* evaluate command size, check space */
  2610. if (mode64) {
  2611. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2612. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2613. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2614. cmdp->u.cache64.sg_lst[0].sg_len));
  2615. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2616. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2617. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2618. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2619. } else {
  2620. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2621. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2622. cmdp->u.cache.sg_lst[0].sg_ptr,
  2623. cmdp->u.cache.sg_lst[0].sg_len));
  2624. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2625. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2626. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2627. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2628. }
  2629. if (ha->cmd_len & 3)
  2630. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2631. if (ha->cmd_cnt > 0) {
  2632. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2633. ha->ic_all_size) {
  2634. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2635. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2636. return 0;
  2637. }
  2638. }
  2639. /* copy command */
  2640. gdth_copy_command(hanum);
  2641. return cmd_index;
  2642. }
  2643. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2644. {
  2645. register gdth_ha_str *ha;
  2646. register gdth_cmd_str *cmdp;
  2647. struct scatterlist *sl;
  2648. ushort i;
  2649. dma_addr_t phys_addr, sense_paddr;
  2650. int cmd_index, sgcnt, mode64;
  2651. unchar t,l;
  2652. struct page *page;
  2653. ulong offset;
  2654. ha = HADATA(gdth_ctr_tab[hanum]);
  2655. t = scp->device->id;
  2656. l = scp->device->lun;
  2657. cmdp = ha->pccb;
  2658. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2659. scp->cmnd[0],b,t,l));
  2660. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2661. return 0;
  2662. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2663. cmdp->Service = SCSIRAWSERVICE;
  2664. cmdp->RequestBuffer = scp;
  2665. /* search free command index */
  2666. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2667. TRACE(("GDT: No free command index found\n"));
  2668. return 0;
  2669. }
  2670. /* if it's the first command, set command semaphore */
  2671. if (ha->cmd_cnt == 0)
  2672. gdth_set_sema0(hanum);
  2673. /* fill command */
  2674. if (scp->SCp.sent_command != -1) {
  2675. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2676. cmdp->BoardNode = LOCALBOARD;
  2677. if (mode64) {
  2678. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2679. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2680. cmdp->OpCode, cmdp->u.raw64.direction));
  2681. /* evaluate command size */
  2682. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2683. } else {
  2684. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2685. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2686. cmdp->OpCode, cmdp->u.raw.direction));
  2687. /* evaluate command size */
  2688. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2689. }
  2690. } else {
  2691. page = virt_to_page(scp->sense_buffer);
  2692. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2693. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2694. 16,PCI_DMA_FROMDEVICE);
  2695. scp->SCp.buffer = (struct scatterlist *)((ulong32)sense_paddr);
  2696. /* high part, if 64bit */
  2697. scp->host_scribble = (char *)(ulong32)((ulong64)sense_paddr >> 32);
  2698. cmdp->OpCode = GDT_WRITE; /* always */
  2699. cmdp->BoardNode = LOCALBOARD;
  2700. if (mode64) {
  2701. cmdp->u.raw64.reserved = 0;
  2702. cmdp->u.raw64.mdisc_time = 0;
  2703. cmdp->u.raw64.mcon_time = 0;
  2704. cmdp->u.raw64.clen = scp->cmd_len;
  2705. cmdp->u.raw64.target = t;
  2706. cmdp->u.raw64.lun = l;
  2707. cmdp->u.raw64.bus = b;
  2708. cmdp->u.raw64.priority = 0;
  2709. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2710. cmdp->u.raw64.sense_len = 16;
  2711. cmdp->u.raw64.sense_data = sense_paddr;
  2712. cmdp->u.raw64.direction =
  2713. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2714. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2715. } else {
  2716. cmdp->u.raw.reserved = 0;
  2717. cmdp->u.raw.mdisc_time = 0;
  2718. cmdp->u.raw.mcon_time = 0;
  2719. cmdp->u.raw.clen = scp->cmd_len;
  2720. cmdp->u.raw.target = t;
  2721. cmdp->u.raw.lun = l;
  2722. cmdp->u.raw.bus = b;
  2723. cmdp->u.raw.priority = 0;
  2724. cmdp->u.raw.link_p = 0;
  2725. cmdp->u.raw.sdlen = scp->request_bufflen;
  2726. cmdp->u.raw.sense_len = 16;
  2727. cmdp->u.raw.sense_data = sense_paddr;
  2728. cmdp->u.raw.direction =
  2729. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2730. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2731. }
  2732. if (scp->use_sg) {
  2733. sl = (struct scatterlist *)scp->request_buffer;
  2734. sgcnt = scp->use_sg;
  2735. scp->SCp.Status = GDTH_MAP_SG;
  2736. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2737. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2738. if (mode64) {
  2739. cmdp->u.raw64.sdata = (ulong64)-1;
  2740. cmdp->u.raw64.sg_ranz = sgcnt;
  2741. for (i=0; i<sgcnt; ++i,++sl) {
  2742. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2743. #ifdef GDTH_DMA_STATISTICS
  2744. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2745. ha->dma64_cnt++;
  2746. else
  2747. ha->dma32_cnt++;
  2748. #endif
  2749. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2750. }
  2751. } else {
  2752. cmdp->u.raw.sdata = 0xffffffff;
  2753. cmdp->u.raw.sg_ranz = sgcnt;
  2754. for (i=0; i<sgcnt; ++i,++sl) {
  2755. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2756. #ifdef GDTH_DMA_STATISTICS
  2757. ha->dma32_cnt++;
  2758. #endif
  2759. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2760. }
  2761. }
  2762. #ifdef GDTH_STATISTICS
  2763. if (max_sg < sgcnt) {
  2764. max_sg = sgcnt;
  2765. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2766. }
  2767. #endif
  2768. } else {
  2769. scp->SCp.Status = GDTH_MAP_SINGLE;
  2770. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2771. page = virt_to_page(scp->request_buffer);
  2772. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2773. phys_addr = pci_map_page(ha->pdev,page,offset,
  2774. scp->request_bufflen,scp->SCp.Message);
  2775. scp->SCp.dma_handle = phys_addr;
  2776. if (mode64) {
  2777. if (ha->raw_feat & SCATTER_GATHER) {
  2778. cmdp->u.raw64.sdata = (ulong64)-1;
  2779. cmdp->u.raw64.sg_ranz= 1;
  2780. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2781. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2782. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2783. } else {
  2784. cmdp->u.raw64.sdata = phys_addr;
  2785. cmdp->u.raw64.sg_ranz= 0;
  2786. }
  2787. } else {
  2788. if (ha->raw_feat & SCATTER_GATHER) {
  2789. cmdp->u.raw.sdata = 0xffffffff;
  2790. cmdp->u.raw.sg_ranz= 1;
  2791. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2792. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2793. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2794. } else {
  2795. cmdp->u.raw.sdata = phys_addr;
  2796. cmdp->u.raw.sg_ranz= 0;
  2797. }
  2798. }
  2799. }
  2800. if (mode64) {
  2801. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2802. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2803. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2804. cmdp->u.raw64.sg_lst[0].sg_len));
  2805. /* evaluate command size */
  2806. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2807. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2808. } else {
  2809. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2810. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2811. cmdp->u.raw.sg_lst[0].sg_ptr,
  2812. cmdp->u.raw.sg_lst[0].sg_len));
  2813. /* evaluate command size */
  2814. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2815. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2816. }
  2817. }
  2818. /* check space */
  2819. if (ha->cmd_len & 3)
  2820. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2821. if (ha->cmd_cnt > 0) {
  2822. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2823. ha->ic_all_size) {
  2824. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2825. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2826. return 0;
  2827. }
  2828. }
  2829. /* copy command */
  2830. gdth_copy_command(hanum);
  2831. return cmd_index;
  2832. }
  2833. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2834. {
  2835. register gdth_ha_str *ha;
  2836. register gdth_cmd_str *cmdp;
  2837. int cmd_index;
  2838. ha = HADATA(gdth_ctr_tab[hanum]);
  2839. cmdp= ha->pccb;
  2840. TRACE2(("gdth_special_cmd(): "));
  2841. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2842. return 0;
  2843. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2844. cmdp->RequestBuffer = scp;
  2845. /* search free command index */
  2846. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2847. TRACE(("GDT: No free command index found\n"));
  2848. return 0;
  2849. }
  2850. /* if it's the first command, set command semaphore */
  2851. if (ha->cmd_cnt == 0)
  2852. gdth_set_sema0(hanum);
  2853. /* evaluate command size, check space */
  2854. if (cmdp->OpCode == GDT_IOCTL) {
  2855. TRACE2(("IOCTL\n"));
  2856. ha->cmd_len =
  2857. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2858. } else if (cmdp->Service == CACHESERVICE) {
  2859. TRACE2(("cache command %d\n",cmdp->OpCode));
  2860. if (ha->cache_feat & GDT_64BIT)
  2861. ha->cmd_len =
  2862. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2863. else
  2864. ha->cmd_len =
  2865. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2866. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2867. TRACE2(("raw command %d\n",cmdp->OpCode));
  2868. if (ha->raw_feat & GDT_64BIT)
  2869. ha->cmd_len =
  2870. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2871. else
  2872. ha->cmd_len =
  2873. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2874. }
  2875. if (ha->cmd_len & 3)
  2876. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2877. if (ha->cmd_cnt > 0) {
  2878. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2879. ha->ic_all_size) {
  2880. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2881. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2882. return 0;
  2883. }
  2884. }
  2885. /* copy command */
  2886. gdth_copy_command(hanum);
  2887. return cmd_index;
  2888. }
  2889. /* Controller event handling functions */
  2890. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2891. ushort idx, gdth_evt_data *evt)
  2892. {
  2893. gdth_evt_str *e;
  2894. struct timeval tv;
  2895. /* no GDTH_LOCK_HA() ! */
  2896. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2897. if (source == 0) /* no source -> no event */
  2898. return NULL;
  2899. if (ebuffer[elastidx].event_source == source &&
  2900. ebuffer[elastidx].event_idx == idx &&
  2901. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2902. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2903. (char *)&evt->eu, evt->size)) ||
  2904. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2905. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2906. (char *)&evt->event_string)))) {
  2907. e = &ebuffer[elastidx];
  2908. do_gettimeofday(&tv);
  2909. e->last_stamp = tv.tv_sec;
  2910. ++e->same_count;
  2911. } else {
  2912. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2913. ++elastidx;
  2914. if (elastidx == MAX_EVENTS)
  2915. elastidx = 0;
  2916. if (elastidx == eoldidx) { /* reached mark ? */
  2917. ++eoldidx;
  2918. if (eoldidx == MAX_EVENTS)
  2919. eoldidx = 0;
  2920. }
  2921. }
  2922. e = &ebuffer[elastidx];
  2923. e->event_source = source;
  2924. e->event_idx = idx;
  2925. do_gettimeofday(&tv);
  2926. e->first_stamp = e->last_stamp = tv.tv_sec;
  2927. e->same_count = 1;
  2928. e->event_data = *evt;
  2929. e->application = 0;
  2930. }
  2931. return e;
  2932. }
  2933. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2934. {
  2935. gdth_evt_str *e;
  2936. int eindex;
  2937. ulong flags;
  2938. TRACE2(("gdth_read_event() handle %d\n", handle));
  2939. spin_lock_irqsave(&ha->smp_lock, flags);
  2940. if (handle == -1)
  2941. eindex = eoldidx;
  2942. else
  2943. eindex = handle;
  2944. estr->event_source = 0;
  2945. if (eindex >= MAX_EVENTS) {
  2946. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2947. return eindex;
  2948. }
  2949. e = &ebuffer[eindex];
  2950. if (e->event_source != 0) {
  2951. if (eindex != elastidx) {
  2952. if (++eindex == MAX_EVENTS)
  2953. eindex = 0;
  2954. } else {
  2955. eindex = -1;
  2956. }
  2957. memcpy(estr, e, sizeof(gdth_evt_str));
  2958. }
  2959. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2960. return eindex;
  2961. }
  2962. static void gdth_readapp_event(gdth_ha_str *ha,
  2963. unchar application, gdth_evt_str *estr)
  2964. {
  2965. gdth_evt_str *e;
  2966. int eindex;
  2967. ulong flags;
  2968. unchar found = FALSE;
  2969. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2970. spin_lock_irqsave(&ha->smp_lock, flags);
  2971. eindex = eoldidx;
  2972. for (;;) {
  2973. e = &ebuffer[eindex];
  2974. if (e->event_source == 0)
  2975. break;
  2976. if ((e->application & application) == 0) {
  2977. e->application |= application;
  2978. found = TRUE;
  2979. break;
  2980. }
  2981. if (eindex == elastidx)
  2982. break;
  2983. if (++eindex == MAX_EVENTS)
  2984. eindex = 0;
  2985. }
  2986. if (found)
  2987. memcpy(estr, e, sizeof(gdth_evt_str));
  2988. else
  2989. estr->event_source = 0;
  2990. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2991. }
  2992. static void gdth_clear_events(void)
  2993. {
  2994. TRACE(("gdth_clear_events()"));
  2995. eoldidx = elastidx = 0;
  2996. ebuffer[0].event_source = 0;
  2997. }
  2998. /* SCSI interface functions */
  2999. static irqreturn_t gdth_interrupt(int irq,void *dev_id,struct pt_regs *regs)
  3000. {
  3001. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3002. register gdth_ha_str *ha;
  3003. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3004. gdt6_dpram_str __iomem *dp6_ptr;
  3005. gdt2_dpram_str __iomem *dp2_ptr;
  3006. Scsi_Cmnd *scp;
  3007. int hanum, rval, i;
  3008. unchar IStatus;
  3009. ushort Service;
  3010. ulong flags = 0;
  3011. #ifdef INT_COAL
  3012. int coalesced = FALSE;
  3013. int next = FALSE;
  3014. gdth_coal_status *pcs = NULL;
  3015. int act_int_coal = 0;
  3016. #endif
  3017. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3018. /* if polling and not from gdth_wait() -> return */
  3019. if (gdth_polling) {
  3020. if (!gdth_from_wait) {
  3021. return IRQ_HANDLED;
  3022. }
  3023. }
  3024. if (!gdth_polling)
  3025. spin_lock_irqsave(&ha2->smp_lock, flags);
  3026. wait_index = 0;
  3027. /* search controller */
  3028. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3029. /* spurious interrupt */
  3030. if (!gdth_polling)
  3031. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3032. return IRQ_HANDLED;
  3033. }
  3034. ha = HADATA(gdth_ctr_tab[hanum]);
  3035. #ifdef GDTH_STATISTICS
  3036. ++act_ints;
  3037. #endif
  3038. #ifdef INT_COAL
  3039. /* See if the fw is returning coalesced status */
  3040. if (IStatus == COALINDEX) {
  3041. /* Coalesced status. Setup the initial status
  3042. buffer pointer and flags */
  3043. pcs = ha->coal_stat;
  3044. coalesced = TRUE;
  3045. next = TRUE;
  3046. }
  3047. do {
  3048. if (coalesced) {
  3049. /* For coalesced requests all status
  3050. information is found in the status buffer */
  3051. IStatus = (unchar)(pcs->status & 0xff);
  3052. }
  3053. #endif
  3054. if (ha->type == GDT_EISA) {
  3055. if (IStatus & 0x80) { /* error flag */
  3056. IStatus &= ~0x80;
  3057. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3058. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3059. } else /* no error */
  3060. ha->status = S_OK;
  3061. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3062. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3063. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3064. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3065. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3066. } else if (ha->type == GDT_ISA) {
  3067. dp2_ptr = ha->brd;
  3068. if (IStatus & 0x80) { /* error flag */
  3069. IStatus &= ~0x80;
  3070. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3071. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3072. } else /* no error */
  3073. ha->status = S_OK;
  3074. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3075. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3076. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3077. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3078. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3079. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3080. } else if (ha->type == GDT_PCI) {
  3081. dp6_ptr = ha->brd;
  3082. if (IStatus & 0x80) { /* error flag */
  3083. IStatus &= ~0x80;
  3084. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3085. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3086. } else /* no error */
  3087. ha->status = S_OK;
  3088. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3089. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3090. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3091. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3092. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3093. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3094. } else if (ha->type == GDT_PCINEW) {
  3095. if (IStatus & 0x80) { /* error flag */
  3096. IStatus &= ~0x80;
  3097. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3098. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3099. } else
  3100. ha->status = S_OK;
  3101. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3102. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3103. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3104. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3105. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3106. } else if (ha->type == GDT_PCIMPR) {
  3107. dp6m_ptr = ha->brd;
  3108. if (IStatus & 0x80) { /* error flag */
  3109. IStatus &= ~0x80;
  3110. #ifdef INT_COAL
  3111. if (coalesced)
  3112. ha->status = pcs->ext_status && 0xffff;
  3113. else
  3114. #endif
  3115. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3116. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3117. } else /* no error */
  3118. ha->status = S_OK;
  3119. #ifdef INT_COAL
  3120. /* get information */
  3121. if (coalesced) {
  3122. ha->info = pcs->info0;
  3123. ha->info2 = pcs->info1;
  3124. ha->service = (pcs->ext_status >> 16) && 0xffff;
  3125. } else
  3126. #endif
  3127. {
  3128. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3129. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3130. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3131. }
  3132. /* event string */
  3133. if (IStatus == ASYNCINDEX) {
  3134. if (ha->service != SCREENSERVICE &&
  3135. (ha->fw_vers & 0xff) >= 0x1a) {
  3136. ha->dvr.severity = gdth_readb
  3137. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3138. for (i = 0; i < 256; ++i) {
  3139. ha->dvr.event_string[i] = gdth_readb
  3140. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3141. if (ha->dvr.event_string[i] == 0)
  3142. break;
  3143. }
  3144. }
  3145. }
  3146. #ifdef INT_COAL
  3147. /* Make sure that non coalesced interrupts get cleared
  3148. before being handled by gdth_async_event/gdth_sync_event */
  3149. if (!coalesced)
  3150. #endif
  3151. {
  3152. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3153. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3154. }
  3155. } else {
  3156. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3157. if (!gdth_polling)
  3158. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3159. return IRQ_HANDLED;
  3160. }
  3161. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3162. IStatus,ha->status,ha->info));
  3163. if (gdth_from_wait) {
  3164. wait_hanum = hanum;
  3165. wait_index = (int)IStatus;
  3166. }
  3167. if (IStatus == ASYNCINDEX) {
  3168. TRACE2(("gdth_interrupt() async. event\n"));
  3169. gdth_async_event(hanum);
  3170. if (!gdth_polling)
  3171. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3172. gdth_next(hanum);
  3173. return IRQ_HANDLED;
  3174. }
  3175. if (IStatus == SPEZINDEX) {
  3176. TRACE2(("Service unknown or not initialized !\n"));
  3177. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3178. ha->dvr.eu.driver.ionode = hanum;
  3179. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3180. if (!gdth_polling)
  3181. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3182. return IRQ_HANDLED;
  3183. }
  3184. scp = ha->cmd_tab[IStatus-2].cmnd;
  3185. Service = ha->cmd_tab[IStatus-2].service;
  3186. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3187. if (scp == UNUSED_CMND) {
  3188. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3189. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3190. ha->dvr.eu.driver.ionode = hanum;
  3191. ha->dvr.eu.driver.index = IStatus;
  3192. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3193. if (!gdth_polling)
  3194. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3195. return IRQ_HANDLED;
  3196. }
  3197. if (scp == INTERNAL_CMND) {
  3198. TRACE(("gdth_interrupt() answer to internal command\n"));
  3199. if (!gdth_polling)
  3200. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3201. return IRQ_HANDLED;
  3202. }
  3203. TRACE(("gdth_interrupt() sync. status\n"));
  3204. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3205. if (!gdth_polling)
  3206. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3207. if (rval == 2) {
  3208. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3209. } else if (rval == 1) {
  3210. scp->scsi_done(scp);
  3211. }
  3212. #ifdef INT_COAL
  3213. if (coalesced) {
  3214. /* go to the next status in the status buffer */
  3215. ++pcs;
  3216. #ifdef GDTH_STATISTICS
  3217. ++act_int_coal;
  3218. if (act_int_coal > max_int_coal) {
  3219. max_int_coal = act_int_coal;
  3220. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3221. }
  3222. #endif
  3223. /* see if there is another status */
  3224. if (pcs->status == 0)
  3225. /* Stop the coalesce loop */
  3226. next = FALSE;
  3227. }
  3228. } while (next);
  3229. /* coalescing only for new GDT_PCIMPR controllers available */
  3230. if (ha->type == GDT_PCIMPR && coalesced) {
  3231. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3232. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3233. }
  3234. #endif
  3235. gdth_next(hanum);
  3236. return IRQ_HANDLED;
  3237. }
  3238. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3239. {
  3240. register gdth_ha_str *ha;
  3241. gdth_msg_str *msg;
  3242. gdth_cmd_str *cmdp;
  3243. unchar b, t;
  3244. ha = HADATA(gdth_ctr_tab[hanum]);
  3245. cmdp = ha->pccb;
  3246. TRACE(("gdth_sync_event() serv %d status %d\n",
  3247. service,ha->status));
  3248. if (service == SCREENSERVICE) {
  3249. msg = ha->pmsg;
  3250. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3251. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3252. if (msg->msg_len > MSGLEN+1)
  3253. msg->msg_len = MSGLEN+1;
  3254. if (msg->msg_len)
  3255. if (!(msg->msg_answer && msg->msg_ext)) {
  3256. msg->msg_text[msg->msg_len] = '\0';
  3257. printk("%s",msg->msg_text);
  3258. }
  3259. if (msg->msg_ext && !msg->msg_answer) {
  3260. while (gdth_test_busy(hanum))
  3261. gdth_delay(0);
  3262. cmdp->Service = SCREENSERVICE;
  3263. cmdp->RequestBuffer = SCREEN_CMND;
  3264. gdth_get_cmd_index(hanum);
  3265. gdth_set_sema0(hanum);
  3266. cmdp->OpCode = GDT_READ;
  3267. cmdp->BoardNode = LOCALBOARD;
  3268. cmdp->u.screen.reserved = 0;
  3269. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3270. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3271. ha->cmd_offs_dpmem = 0;
  3272. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3273. + sizeof(ulong64);
  3274. ha->cmd_cnt = 0;
  3275. gdth_copy_command(hanum);
  3276. gdth_release_event(hanum);
  3277. return 0;
  3278. }
  3279. if (msg->msg_answer && msg->msg_alen) {
  3280. /* default answers (getchar() not possible) */
  3281. if (msg->msg_alen == 1) {
  3282. msg->msg_alen = 0;
  3283. msg->msg_len = 1;
  3284. msg->msg_text[0] = 0;
  3285. } else {
  3286. msg->msg_alen -= 2;
  3287. msg->msg_len = 2;
  3288. msg->msg_text[0] = 1;
  3289. msg->msg_text[1] = 0;
  3290. }
  3291. msg->msg_ext = 0;
  3292. msg->msg_answer = 0;
  3293. while (gdth_test_busy(hanum))
  3294. gdth_delay(0);
  3295. cmdp->Service = SCREENSERVICE;
  3296. cmdp->RequestBuffer = SCREEN_CMND;
  3297. gdth_get_cmd_index(hanum);
  3298. gdth_set_sema0(hanum);
  3299. cmdp->OpCode = GDT_WRITE;
  3300. cmdp->BoardNode = LOCALBOARD;
  3301. cmdp->u.screen.reserved = 0;
  3302. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3303. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3304. ha->cmd_offs_dpmem = 0;
  3305. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3306. + sizeof(ulong64);
  3307. ha->cmd_cnt = 0;
  3308. gdth_copy_command(hanum);
  3309. gdth_release_event(hanum);
  3310. return 0;
  3311. }
  3312. printk("\n");
  3313. } else {
  3314. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3315. t = scp->device->id;
  3316. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3317. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3318. }
  3319. /* cache or raw service */
  3320. if (ha->status == S_BSY) {
  3321. TRACE2(("Controller busy -> retry !\n"));
  3322. if (scp->SCp.sent_command == GDT_MOUNT)
  3323. scp->SCp.sent_command = GDT_CLUST_INFO;
  3324. /* retry */
  3325. return 2;
  3326. }
  3327. if (scp->SCp.Status == GDTH_MAP_SG)
  3328. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3329. scp->use_sg,scp->SCp.Message);
  3330. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3331. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3332. scp->request_bufflen,scp->SCp.Message);
  3333. if (scp->SCp.buffer) {
  3334. dma_addr_t addr;
  3335. addr = (dma_addr_t)(ulong32)scp->SCp.buffer;
  3336. if (scp->host_scribble)
  3337. addr += (dma_addr_t)((ulong64)(ulong32)scp->host_scribble << 32);
  3338. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3339. }
  3340. if (ha->status == S_OK) {
  3341. scp->SCp.Status = S_OK;
  3342. scp->SCp.Message = ha->info;
  3343. if (scp->SCp.sent_command != -1) {
  3344. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3345. scp->SCp.sent_command));
  3346. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3347. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3348. ha->hdr[t].cluster_type = (unchar)ha->info;
  3349. if (!(ha->hdr[t].cluster_type &
  3350. CLUSTER_MOUNTED)) {
  3351. /* NOT MOUNTED -> MOUNT */
  3352. scp->SCp.sent_command = GDT_MOUNT;
  3353. if (ha->hdr[t].cluster_type &
  3354. CLUSTER_RESERVED) {
  3355. /* cluster drive RESERVED (on the other node) */
  3356. scp->SCp.phase = -2; /* reservation conflict */
  3357. }
  3358. } else {
  3359. scp->SCp.sent_command = -1;
  3360. }
  3361. } else {
  3362. if (scp->SCp.sent_command == GDT_MOUNT) {
  3363. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3364. ha->hdr[t].media_changed = TRUE;
  3365. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3366. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3367. ha->hdr[t].media_changed = TRUE;
  3368. }
  3369. scp->SCp.sent_command = -1;
  3370. }
  3371. /* retry */
  3372. scp->SCp.this_residual = HIGH_PRI;
  3373. return 2;
  3374. } else {
  3375. /* RESERVE/RELEASE ? */
  3376. if (scp->cmnd[0] == RESERVE) {
  3377. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3378. } else if (scp->cmnd[0] == RELEASE) {
  3379. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3380. }
  3381. scp->result = DID_OK << 16;
  3382. scp->sense_buffer[0] = 0;
  3383. }
  3384. } else {
  3385. scp->SCp.Status = ha->status;
  3386. scp->SCp.Message = ha->info;
  3387. if (scp->SCp.sent_command != -1) {
  3388. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3389. scp->SCp.sent_command, ha->status));
  3390. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3391. scp->SCp.sent_command == GDT_SCAN_END) {
  3392. scp->SCp.sent_command = -1;
  3393. /* retry */
  3394. scp->SCp.this_residual = HIGH_PRI;
  3395. return 2;
  3396. }
  3397. memset((char*)scp->sense_buffer,0,16);
  3398. scp->sense_buffer[0] = 0x70;
  3399. scp->sense_buffer[2] = NOT_READY;
  3400. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3401. } else if (service == CACHESERVICE) {
  3402. if (ha->status == S_CACHE_UNKNOWN &&
  3403. (ha->hdr[t].cluster_type &
  3404. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3405. /* bus reset -> force GDT_CLUST_INFO */
  3406. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3407. }
  3408. memset((char*)scp->sense_buffer,0,16);
  3409. if (ha->status == (ushort)S_CACHE_RESERV) {
  3410. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3411. } else {
  3412. scp->sense_buffer[0] = 0x70;
  3413. scp->sense_buffer[2] = NOT_READY;
  3414. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3415. }
  3416. if (scp->done != gdth_scsi_done) {
  3417. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3418. ha->dvr.eu.sync.ionode = hanum;
  3419. ha->dvr.eu.sync.service = service;
  3420. ha->dvr.eu.sync.status = ha->status;
  3421. ha->dvr.eu.sync.info = ha->info;
  3422. ha->dvr.eu.sync.hostdrive = t;
  3423. if (ha->status >= 0x8000)
  3424. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3425. else
  3426. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3427. }
  3428. } else {
  3429. /* sense buffer filled from controller firmware (DMA) */
  3430. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3431. scp->result = DID_BAD_TARGET << 16;
  3432. } else {
  3433. scp->result = (DID_OK << 16) | ha->info;
  3434. }
  3435. }
  3436. }
  3437. if (!scp->SCp.have_data_in)
  3438. scp->SCp.have_data_in++;
  3439. else
  3440. return 1;
  3441. }
  3442. return 0;
  3443. }
  3444. static char *async_cache_tab[] = {
  3445. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3446. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3447. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3448. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3449. /* 2*/ "\005\000\002\006\004"
  3450. "GDT HA %u, Host Drive %lu not ready",
  3451. /* 3*/ "\005\000\002\006\004"
  3452. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3453. /* 4*/ "\005\000\002\006\004"
  3454. "GDT HA %u, mirror update on Host Drive %lu failed",
  3455. /* 5*/ "\005\000\002\006\004"
  3456. "GDT HA %u, Mirror Drive %lu failed",
  3457. /* 6*/ "\005\000\002\006\004"
  3458. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3459. /* 7*/ "\005\000\002\006\004"
  3460. "GDT HA %u, Host Drive %lu write protected",
  3461. /* 8*/ "\005\000\002\006\004"
  3462. "GDT HA %u, media changed in Host Drive %lu",
  3463. /* 9*/ "\005\000\002\006\004"
  3464. "GDT HA %u, Host Drive %lu is offline",
  3465. /*10*/ "\005\000\002\006\004"
  3466. "GDT HA %u, media change of Mirror Drive %lu",
  3467. /*11*/ "\005\000\002\006\004"
  3468. "GDT HA %u, Mirror Drive %lu is write protected",
  3469. /*12*/ "\005\000\002\006\004"
  3470. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3471. /*13*/ "\007\000\002\006\002\010\002"
  3472. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3473. /*14*/ "\005\000\002\006\002"
  3474. "GDT HA %u, Array Drive %u: FAIL state entered",
  3475. /*15*/ "\005\000\002\006\002"
  3476. "GDT HA %u, Array Drive %u: error",
  3477. /*16*/ "\007\000\002\006\002\010\002"
  3478. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3479. /*17*/ "\005\000\002\006\002"
  3480. "GDT HA %u, Array Drive %u: parity build failed",
  3481. /*18*/ "\005\000\002\006\002"
  3482. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3483. /*19*/ "\005\000\002\010\002"
  3484. "GDT HA %u, Test of Hot Fix %u failed",
  3485. /*20*/ "\005\000\002\006\002"
  3486. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3487. /*21*/ "\005\000\002\006\002"
  3488. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3489. /*22*/ "\007\000\002\006\002\010\002"
  3490. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3491. /*23*/ "\005\000\002\006\002"
  3492. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3493. /*24*/ "\005\000\002\010\002"
  3494. "GDT HA %u, mirror update on Cache Drive %u completed",
  3495. /*25*/ "\005\000\002\010\002"
  3496. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3497. /*26*/ "\005\000\002\006\002"
  3498. "GDT HA %u, Array Drive %u: drive rebuild started",
  3499. /*27*/ "\005\000\002\012\001"
  3500. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3501. /*28*/ "\005\000\002\012\001"
  3502. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3503. /*29*/ "\007\000\002\012\001\013\001"
  3504. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3505. /*30*/ "\007\000\002\012\001\013\001"
  3506. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3507. /*31*/ "\007\000\002\012\001\013\001"
  3508. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3509. /*32*/ "\007\000\002\012\001\013\001"
  3510. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3511. /*33*/ "\007\000\002\012\001\013\001"
  3512. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3513. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3514. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3515. /*35*/ "\007\000\002\012\001\013\001"
  3516. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3517. /*36*/ "\007\000\002\012\001\013\001"
  3518. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3519. /*37*/ "\007\000\002\012\001\006\004"
  3520. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3521. /*38*/ "\007\000\002\012\001\013\001"
  3522. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3523. /*39*/ "\007\000\002\012\001\013\001"
  3524. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3525. /*40*/ "\007\000\002\012\001\013\001"
  3526. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3527. /*41*/ "\007\000\002\012\001\013\001"
  3528. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3529. /*42*/ "\005\000\002\006\002"
  3530. "GDT HA %u, Array Drive %u: drive build started",
  3531. /*43*/ "\003\000\002"
  3532. "GDT HA %u, DRAM parity error detected",
  3533. /*44*/ "\005\000\002\006\002"
  3534. "GDT HA %u, Mirror Drive %u: update started",
  3535. /*45*/ "\007\000\002\006\002\010\002"
  3536. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3537. /*46*/ "\005\000\002\006\002"
  3538. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3539. /*47*/ "\005\000\002\006\002"
  3540. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3541. /*48*/ "\005\000\002\006\002"
  3542. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3543. /*49*/ "\005\000\002\006\002"
  3544. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3545. /*50*/ "\007\000\002\012\001\013\001"
  3546. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3547. /*51*/ "\005\000\002\006\002"
  3548. "GDT HA %u, Array Drive %u: expand started",
  3549. /*52*/ "\005\000\002\006\002"
  3550. "GDT HA %u, Array Drive %u: expand finished successfully",
  3551. /*53*/ "\005\000\002\006\002"
  3552. "GDT HA %u, Array Drive %u: expand failed",
  3553. /*54*/ "\003\000\002"
  3554. "GDT HA %u, CPU temperature critical",
  3555. /*55*/ "\003\000\002"
  3556. "GDT HA %u, CPU temperature OK",
  3557. /*56*/ "\005\000\002\006\004"
  3558. "GDT HA %u, Host drive %lu created",
  3559. /*57*/ "\005\000\002\006\002"
  3560. "GDT HA %u, Array Drive %u: expand restarted",
  3561. /*58*/ "\005\000\002\006\002"
  3562. "GDT HA %u, Array Drive %u: expand stopped",
  3563. /*59*/ "\005\000\002\010\002"
  3564. "GDT HA %u, Mirror Drive %u: drive build quited",
  3565. /*60*/ "\005\000\002\006\002"
  3566. "GDT HA %u, Array Drive %u: parity build quited",
  3567. /*61*/ "\005\000\002\006\002"
  3568. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3569. /*62*/ "\005\000\002\006\002"
  3570. "GDT HA %u, Array Drive %u: parity verify started",
  3571. /*63*/ "\005\000\002\006\002"
  3572. "GDT HA %u, Array Drive %u: parity verify done",
  3573. /*64*/ "\005\000\002\006\002"
  3574. "GDT HA %u, Array Drive %u: parity verify failed",
  3575. /*65*/ "\005\000\002\006\002"
  3576. "GDT HA %u, Array Drive %u: parity error detected",
  3577. /*66*/ "\005\000\002\006\002"
  3578. "GDT HA %u, Array Drive %u: parity verify quited",
  3579. /*67*/ "\005\000\002\006\002"
  3580. "GDT HA %u, Host Drive %u reserved",
  3581. /*68*/ "\005\000\002\006\002"
  3582. "GDT HA %u, Host Drive %u mounted and released",
  3583. /*69*/ "\005\000\002\006\002"
  3584. "GDT HA %u, Host Drive %u released",
  3585. /*70*/ "\003\000\002"
  3586. "GDT HA %u, DRAM error detected and corrected with ECC",
  3587. /*71*/ "\003\000\002"
  3588. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3589. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3590. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3591. /*73*/ "\005\000\002\006\002"
  3592. "GDT HA %u, Host drive %u resetted locally",
  3593. /*74*/ "\005\000\002\006\002"
  3594. "GDT HA %u, Host drive %u resetted remotely",
  3595. /*75*/ "\003\000\002"
  3596. "GDT HA %u, async. status 75 unknown",
  3597. };
  3598. static int gdth_async_event(int hanum)
  3599. {
  3600. gdth_ha_str *ha;
  3601. gdth_cmd_str *cmdp;
  3602. int cmd_index;
  3603. ha = HADATA(gdth_ctr_tab[hanum]);
  3604. cmdp= ha->pccb;
  3605. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3606. hanum,ha->service));
  3607. if (ha->service == SCREENSERVICE) {
  3608. if (ha->status == MSG_REQUEST) {
  3609. while (gdth_test_busy(hanum))
  3610. gdth_delay(0);
  3611. cmdp->Service = SCREENSERVICE;
  3612. cmdp->RequestBuffer = SCREEN_CMND;
  3613. cmd_index = gdth_get_cmd_index(hanum);
  3614. gdth_set_sema0(hanum);
  3615. cmdp->OpCode = GDT_READ;
  3616. cmdp->BoardNode = LOCALBOARD;
  3617. cmdp->u.screen.reserved = 0;
  3618. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3619. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3620. ha->cmd_offs_dpmem = 0;
  3621. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3622. + sizeof(ulong64);
  3623. ha->cmd_cnt = 0;
  3624. gdth_copy_command(hanum);
  3625. if (ha->type == GDT_EISA)
  3626. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3627. else if (ha->type == GDT_ISA)
  3628. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3629. else
  3630. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3631. (ushort)((ha->brd_phys>>3)&0x1f));
  3632. gdth_release_event(hanum);
  3633. }
  3634. } else {
  3635. if (ha->type == GDT_PCIMPR &&
  3636. (ha->fw_vers & 0xff) >= 0x1a) {
  3637. ha->dvr.size = 0;
  3638. ha->dvr.eu.async.ionode = hanum;
  3639. ha->dvr.eu.async.status = ha->status;
  3640. /* severity and event_string already set! */
  3641. } else {
  3642. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3643. ha->dvr.eu.async.ionode = hanum;
  3644. ha->dvr.eu.async.service = ha->service;
  3645. ha->dvr.eu.async.status = ha->status;
  3646. ha->dvr.eu.async.info = ha->info;
  3647. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3648. }
  3649. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3650. gdth_log_event( &ha->dvr, NULL );
  3651. /* new host drive from expand? */
  3652. if (ha->service == CACHESERVICE && ha->status == 56) {
  3653. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3654. (ushort)ha->info));
  3655. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3656. }
  3657. }
  3658. return 1;
  3659. }
  3660. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3661. {
  3662. gdth_stackframe stack;
  3663. char *f = NULL;
  3664. int i,j;
  3665. TRACE2(("gdth_log_event()\n"));
  3666. if (dvr->size == 0) {
  3667. if (buffer == NULL) {
  3668. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3669. } else {
  3670. sprintf(buffer,"Adapter %d: %s\n",
  3671. dvr->eu.async.ionode,dvr->event_string);
  3672. }
  3673. } else if (dvr->eu.async.service == CACHESERVICE &&
  3674. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3675. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3676. dvr->eu.async.status));
  3677. f = async_cache_tab[dvr->eu.async.status];
  3678. /* i: parameter to push, j: stack element to fill */
  3679. for (j=0,i=1; i < f[0]; i+=2) {
  3680. switch (f[i+1]) {
  3681. case 4:
  3682. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3683. break;
  3684. case 2:
  3685. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3686. break;
  3687. case 1:
  3688. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3689. break;
  3690. default:
  3691. break;
  3692. }
  3693. }
  3694. if (buffer == NULL) {
  3695. printk(&f[(int)f[0]],stack);
  3696. printk("\n");
  3697. } else {
  3698. sprintf(buffer,&f[(int)f[0]],stack);
  3699. }
  3700. } else {
  3701. if (buffer == NULL) {
  3702. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3703. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3704. } else {
  3705. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3706. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3707. }
  3708. }
  3709. }
  3710. #ifdef GDTH_STATISTICS
  3711. static void gdth_timeout(ulong data)
  3712. {
  3713. ulong32 i;
  3714. Scsi_Cmnd *nscp;
  3715. gdth_ha_str *ha;
  3716. ulong flags;
  3717. int hanum = 0;
  3718. ha = HADATA(gdth_ctr_tab[hanum]);
  3719. spin_lock_irqsave(&ha->smp_lock, flags);
  3720. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3721. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3722. ++act_stats;
  3723. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3724. ++act_rq;
  3725. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3726. act_ints, act_ios, act_stats, act_rq));
  3727. act_ints = act_ios = 0;
  3728. gdth_timer.expires = jiffies + 30 * HZ;
  3729. add_timer(&gdth_timer);
  3730. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3731. }
  3732. #endif
  3733. static void __init internal_setup(char *str,int *ints)
  3734. {
  3735. int i, argc;
  3736. char *cur_str, *argv;
  3737. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3738. str ? str:"NULL", ints ? ints[0]:0));
  3739. /* read irq[] from ints[] */
  3740. if (ints) {
  3741. argc = ints[0];
  3742. if (argc > 0) {
  3743. if (argc > MAXHA)
  3744. argc = MAXHA;
  3745. for (i = 0; i < argc; ++i)
  3746. irq[i] = ints[i+1];
  3747. }
  3748. }
  3749. /* analyse string */
  3750. argv = str;
  3751. while (argv && (cur_str = strchr(argv, ':'))) {
  3752. int val = 0, c = *++cur_str;
  3753. if (c == 'n' || c == 'N')
  3754. val = 0;
  3755. else if (c == 'y' || c == 'Y')
  3756. val = 1;
  3757. else
  3758. val = (int)simple_strtoul(cur_str, NULL, 0);
  3759. if (!strncmp(argv, "disable:", 8))
  3760. disable = val;
  3761. else if (!strncmp(argv, "reserve_mode:", 13))
  3762. reserve_mode = val;
  3763. else if (!strncmp(argv, "reverse_scan:", 13))
  3764. reverse_scan = val;
  3765. else if (!strncmp(argv, "hdr_channel:", 12))
  3766. hdr_channel = val;
  3767. else if (!strncmp(argv, "max_ids:", 8))
  3768. max_ids = val;
  3769. else if (!strncmp(argv, "rescan:", 7))
  3770. rescan = val;
  3771. else if (!strncmp(argv, "virt_ctr:", 9))
  3772. virt_ctr = val;
  3773. else if (!strncmp(argv, "shared_access:", 14))
  3774. shared_access = val;
  3775. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3776. probe_eisa_isa = val;
  3777. else if (!strncmp(argv, "reserve_list:", 13)) {
  3778. reserve_list[0] = val;
  3779. for (i = 1; i < MAX_RES_ARGS; i++) {
  3780. cur_str = strchr(cur_str, ',');
  3781. if (!cur_str)
  3782. break;
  3783. if (!isdigit((int)*++cur_str)) {
  3784. --cur_str;
  3785. break;
  3786. }
  3787. reserve_list[i] =
  3788. (int)simple_strtoul(cur_str, NULL, 0);
  3789. }
  3790. if (!cur_str)
  3791. break;
  3792. argv = ++cur_str;
  3793. continue;
  3794. }
  3795. if ((argv = strchr(argv, ',')))
  3796. ++argv;
  3797. }
  3798. }
  3799. int __init option_setup(char *str)
  3800. {
  3801. int ints[MAXHA];
  3802. char *cur = str;
  3803. int i = 1;
  3804. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3805. while (cur && isdigit(*cur) && i <= MAXHA) {
  3806. ints[i++] = simple_strtoul(cur, NULL, 0);
  3807. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3808. }
  3809. ints[0] = i - 1;
  3810. internal_setup(cur, ints);
  3811. return 1;
  3812. }
  3813. static int __init gdth_detect(Scsi_Host_Template *shtp)
  3814. {
  3815. struct Scsi_Host *shp;
  3816. gdth_pci_str pcistr[MAXHA];
  3817. gdth_ha_str *ha;
  3818. ulong32 isa_bios;
  3819. ushort eisa_slot;
  3820. int i,hanum,cnt,ctr,err;
  3821. unchar b;
  3822. #ifdef DEBUG_GDTH
  3823. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3824. DebugState);
  3825. printk(" Destination of debugging information: ");
  3826. #ifdef __SERIAL__
  3827. #ifdef __COM2__
  3828. printk("Serial port COM2\n");
  3829. #else
  3830. printk("Serial port COM1\n");
  3831. #endif
  3832. #else
  3833. printk("Console\n");
  3834. #endif
  3835. gdth_delay(3000);
  3836. #endif
  3837. TRACE(("gdth_detect()\n"));
  3838. if (disable) {
  3839. printk("GDT-HA: Controller driver disabled from command line !\n");
  3840. return 0;
  3841. }
  3842. printk("GDT-HA: Storage RAID Controller Driver. Version: %s \n",GDTH_VERSION_STR);
  3843. /* initializations */
  3844. gdth_polling = TRUE; b = 0;
  3845. gdth_clear_events();
  3846. /* As default we do not probe for EISA or ISA controllers */
  3847. if (probe_eisa_isa) {
  3848. /* scanning for controllers, at first: ISA controller */
  3849. for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
  3850. dma_addr_t scratch_dma_handle;
  3851. scratch_dma_handle = 0;
  3852. if (gdth_ctr_count >= MAXHA)
  3853. break;
  3854. if (gdth_search_isa(isa_bios)) { /* controller found */
  3855. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3856. if (shp == NULL)
  3857. continue;
  3858. ha = HADATA(shp);
  3859. if (!gdth_init_isa(isa_bios,ha)) {
  3860. scsi_unregister(shp);
  3861. continue;
  3862. }
  3863. #ifdef __ia64__
  3864. break;
  3865. #else
  3866. /* controller found and initialized */
  3867. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  3868. isa_bios,ha->irq,ha->drq);
  3869. if (request_irq(ha->irq,gdth_interrupt,SA_INTERRUPT,"gdth",ha)) {
  3870. printk("GDT-ISA: Unable to allocate IRQ\n");
  3871. scsi_unregister(shp);
  3872. continue;
  3873. }
  3874. if (request_dma(ha->drq,"gdth")) {
  3875. printk("GDT-ISA: Unable to allocate DMA channel\n");
  3876. free_irq(ha->irq,ha);
  3877. scsi_unregister(shp);
  3878. continue;
  3879. }
  3880. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  3881. enable_dma(ha->drq);
  3882. shp->unchecked_isa_dma = 1;
  3883. shp->irq = ha->irq;
  3884. shp->dma_channel = ha->drq;
  3885. hanum = gdth_ctr_count;
  3886. gdth_ctr_tab[gdth_ctr_count++] = shp;
  3887. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3888. NUMDATA(shp)->hanum = (ushort)hanum;
  3889. NUMDATA(shp)->busnum= 0;
  3890. ha->pccb = CMDDATA(shp);
  3891. ha->ccb_phys = 0L;
  3892. ha->pdev = NULL;
  3893. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  3894. &scratch_dma_handle);
  3895. ha->scratch_phys = scratch_dma_handle;
  3896. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  3897. &scratch_dma_handle);
  3898. ha->msg_phys = scratch_dma_handle;
  3899. #ifdef INT_COAL
  3900. ha->coal_stat = (gdth_coal_status *)
  3901. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  3902. MAXOFFSETS, &scratch_dma_handle);
  3903. ha->coal_stat_phys = scratch_dma_handle;
  3904. #endif
  3905. ha->scratch_busy = FALSE;
  3906. ha->req_first = NULL;
  3907. ha->tid_cnt = MAX_HDRIVES;
  3908. if (max_ids > 0 && max_ids < ha->tid_cnt)
  3909. ha->tid_cnt = max_ids;
  3910. for (i=0; i<GDTH_MAXCMDS; ++i)
  3911. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3912. ha->scan_mode = rescan ? 0x10 : 0;
  3913. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  3914. !gdth_search_drives(hanum)) {
  3915. printk("GDT-ISA: Error during device scan\n");
  3916. --gdth_ctr_count;
  3917. --gdth_ctr_vcount;
  3918. #ifdef INT_COAL
  3919. if (ha->coal_stat)
  3920. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  3921. MAXOFFSETS, ha->coal_stat,
  3922. ha->coal_stat_phys);
  3923. #endif
  3924. if (ha->pscratch)
  3925. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  3926. ha->pscratch, ha->scratch_phys);
  3927. if (ha->pmsg)
  3928. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  3929. ha->pmsg, ha->msg_phys);
  3930. free_irq(ha->irq,ha);
  3931. scsi_unregister(shp);
  3932. continue;
  3933. }
  3934. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  3935. hdr_channel = ha->bus_cnt;
  3936. ha->virt_bus = hdr_channel;
  3937. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  3938. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  3939. shp->highmem_io = 0;
  3940. #endif
  3941. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  3942. shp->max_cmd_len = 16;
  3943. shp->max_id = ha->tid_cnt;
  3944. shp->max_lun = MAXLUN;
  3945. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  3946. if (virt_ctr) {
  3947. virt_ctr = 1;
  3948. /* register addit. SCSI channels as virtual controllers */
  3949. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  3950. shp = scsi_register(shtp,sizeof(gdth_num_str));
  3951. shp->unchecked_isa_dma = 1;
  3952. shp->irq = ha->irq;
  3953. shp->dma_channel = ha->drq;
  3954. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3955. NUMDATA(shp)->hanum = (ushort)hanum;
  3956. NUMDATA(shp)->busnum = b;
  3957. }
  3958. }
  3959. spin_lock_init(&ha->smp_lock);
  3960. gdth_enable_int(hanum);
  3961. #endif /* !__ia64__ */
  3962. }
  3963. }
  3964. /* scanning for EISA controllers */
  3965. for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
  3966. dma_addr_t scratch_dma_handle;
  3967. scratch_dma_handle = 0;
  3968. if (gdth_ctr_count >= MAXHA)
  3969. break;
  3970. if (gdth_search_eisa(eisa_slot)) { /* controller found */
  3971. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3972. if (shp == NULL)
  3973. continue;
  3974. ha = HADATA(shp);
  3975. if (!gdth_init_eisa(eisa_slot,ha)) {
  3976. scsi_unregister(shp);
  3977. continue;
  3978. }
  3979. /* controller found and initialized */
  3980. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  3981. eisa_slot>>12,ha->irq);
  3982. if (request_irq(ha->irq,gdth_interrupt,SA_INTERRUPT,"gdth",ha)) {
  3983. printk("GDT-EISA: Unable to allocate IRQ\n");
  3984. scsi_unregister(shp);
  3985. continue;
  3986. }
  3987. shp->unchecked_isa_dma = 0;
  3988. shp->irq = ha->irq;
  3989. shp->dma_channel = 0xff;
  3990. hanum = gdth_ctr_count;
  3991. gdth_ctr_tab[gdth_ctr_count++] = shp;
  3992. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3993. NUMDATA(shp)->hanum = (ushort)hanum;
  3994. NUMDATA(shp)->busnum= 0;
  3995. TRACE2(("EISA detect Bus 0: hanum %d\n",
  3996. NUMDATA(shp)->hanum));
  3997. ha->pccb = CMDDATA(shp);
  3998. ha->ccb_phys = 0L;
  3999. ha->pdev = NULL;
  4000. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4001. &scratch_dma_handle);
  4002. ha->scratch_phys = scratch_dma_handle;
  4003. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4004. &scratch_dma_handle);
  4005. ha->msg_phys = scratch_dma_handle;
  4006. #ifdef INT_COAL
  4007. ha->coal_stat = (gdth_coal_status *)
  4008. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4009. MAXOFFSETS, &scratch_dma_handle);
  4010. ha->coal_stat_phys = scratch_dma_handle;
  4011. #endif
  4012. ha->ccb_phys =
  4013. pci_map_single(ha->pdev,ha->pccb,
  4014. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4015. ha->scratch_busy = FALSE;
  4016. ha->req_first = NULL;
  4017. ha->tid_cnt = MAX_HDRIVES;
  4018. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4019. ha->tid_cnt = max_ids;
  4020. for (i=0; i<GDTH_MAXCMDS; ++i)
  4021. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4022. ha->scan_mode = rescan ? 0x10 : 0;
  4023. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4024. !gdth_search_drives(hanum)) {
  4025. printk("GDT-EISA: Error during device scan\n");
  4026. --gdth_ctr_count;
  4027. --gdth_ctr_vcount;
  4028. #ifdef INT_COAL
  4029. if (ha->coal_stat)
  4030. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4031. MAXOFFSETS, ha->coal_stat,
  4032. ha->coal_stat_phys);
  4033. #endif
  4034. if (ha->pscratch)
  4035. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4036. ha->pscratch, ha->scratch_phys);
  4037. if (ha->pmsg)
  4038. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4039. ha->pmsg, ha->msg_phys);
  4040. if (ha->ccb_phys)
  4041. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4042. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4043. free_irq(ha->irq,ha);
  4044. scsi_unregister(shp);
  4045. continue;
  4046. }
  4047. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4048. hdr_channel = ha->bus_cnt;
  4049. ha->virt_bus = hdr_channel;
  4050. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4051. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4052. shp->highmem_io = 0;
  4053. #endif
  4054. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4055. shp->max_cmd_len = 16;
  4056. shp->max_id = ha->tid_cnt;
  4057. shp->max_lun = MAXLUN;
  4058. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4059. if (virt_ctr) {
  4060. virt_ctr = 1;
  4061. /* register addit. SCSI channels as virtual controllers */
  4062. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4063. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4064. shp->unchecked_isa_dma = 0;
  4065. shp->irq = ha->irq;
  4066. shp->dma_channel = 0xff;
  4067. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4068. NUMDATA(shp)->hanum = (ushort)hanum;
  4069. NUMDATA(shp)->busnum = b;
  4070. }
  4071. }
  4072. spin_lock_init(&ha->smp_lock);
  4073. gdth_enable_int(hanum);
  4074. }
  4075. }
  4076. }
  4077. /* scanning for PCI controllers */
  4078. cnt = gdth_search_pci(pcistr);
  4079. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4080. gdth_sort_pci(pcistr,cnt);
  4081. for (ctr = 0; ctr < cnt; ++ctr) {
  4082. dma_addr_t scratch_dma_handle;
  4083. scratch_dma_handle = 0;
  4084. if (gdth_ctr_count >= MAXHA)
  4085. break;
  4086. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4087. if (shp == NULL)
  4088. continue;
  4089. ha = HADATA(shp);
  4090. if (!gdth_init_pci(&pcistr[ctr],ha)) {
  4091. scsi_unregister(shp);
  4092. continue;
  4093. }
  4094. /* controller found and initialized */
  4095. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4096. pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
  4097. if (request_irq(ha->irq, gdth_interrupt,
  4098. SA_INTERRUPT|SA_SHIRQ, "gdth", ha))
  4099. {
  4100. printk("GDT-PCI: Unable to allocate IRQ\n");
  4101. scsi_unregister(shp);
  4102. continue;
  4103. }
  4104. shp->unchecked_isa_dma = 0;
  4105. shp->irq = ha->irq;
  4106. shp->dma_channel = 0xff;
  4107. hanum = gdth_ctr_count;
  4108. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4109. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4110. NUMDATA(shp)->hanum = (ushort)hanum;
  4111. NUMDATA(shp)->busnum= 0;
  4112. ha->pccb = CMDDATA(shp);
  4113. ha->ccb_phys = 0L;
  4114. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4115. &scratch_dma_handle);
  4116. ha->scratch_phys = scratch_dma_handle;
  4117. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4118. &scratch_dma_handle);
  4119. ha->msg_phys = scratch_dma_handle;
  4120. #ifdef INT_COAL
  4121. ha->coal_stat = (gdth_coal_status *)
  4122. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4123. MAXOFFSETS, &scratch_dma_handle);
  4124. ha->coal_stat_phys = scratch_dma_handle;
  4125. #endif
  4126. ha->scratch_busy = FALSE;
  4127. ha->req_first = NULL;
  4128. ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
  4129. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4130. ha->tid_cnt = max_ids;
  4131. for (i=0; i<GDTH_MAXCMDS; ++i)
  4132. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4133. ha->scan_mode = rescan ? 0x10 : 0;
  4134. err = FALSE;
  4135. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4136. !gdth_search_drives(hanum)) {
  4137. err = TRUE;
  4138. } else {
  4139. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4140. hdr_channel = ha->bus_cnt;
  4141. ha->virt_bus = hdr_channel;
  4142. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4143. scsi_set_pci_device(shp, pcistr[ctr].pdev);
  4144. #endif
  4145. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
  4146. /* 64-bit DMA only supported from FW >= x.43 */
  4147. (!ha->dma64_support)) {
  4148. if (pci_set_dma_mask(pcistr[ctr].pdev, 0xffffffff)) {
  4149. printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
  4150. err = TRUE;
  4151. }
  4152. } else {
  4153. shp->max_cmd_len = 16;
  4154. if (!pci_set_dma_mask(pcistr[ctr].pdev, 0xffffffffffffffffULL)) {
  4155. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4156. } else if (pci_set_dma_mask(pcistr[ctr].pdev, 0xffffffff)) {
  4157. printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
  4158. err = TRUE;
  4159. }
  4160. }
  4161. }
  4162. if (err) {
  4163. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4164. --gdth_ctr_count;
  4165. --gdth_ctr_vcount;
  4166. #ifdef INT_COAL
  4167. if (ha->coal_stat)
  4168. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4169. MAXOFFSETS, ha->coal_stat,
  4170. ha->coal_stat_phys);
  4171. #endif
  4172. if (ha->pscratch)
  4173. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4174. ha->pscratch, ha->scratch_phys);
  4175. if (ha->pmsg)
  4176. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4177. ha->pmsg, ha->msg_phys);
  4178. free_irq(ha->irq,ha);
  4179. scsi_unregister(shp);
  4180. continue;
  4181. }
  4182. shp->max_id = ha->tid_cnt;
  4183. shp->max_lun = MAXLUN;
  4184. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4185. if (virt_ctr) {
  4186. virt_ctr = 1;
  4187. /* register addit. SCSI channels as virtual controllers */
  4188. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4189. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4190. shp->unchecked_isa_dma = 0;
  4191. shp->irq = ha->irq;
  4192. shp->dma_channel = 0xff;
  4193. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4194. NUMDATA(shp)->hanum = (ushort)hanum;
  4195. NUMDATA(shp)->busnum = b;
  4196. }
  4197. }
  4198. spin_lock_init(&ha->smp_lock);
  4199. gdth_enable_int(hanum);
  4200. }
  4201. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4202. if (gdth_ctr_count > 0) {
  4203. #ifdef GDTH_STATISTICS
  4204. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4205. init_timer(&gdth_timer);
  4206. gdth_timer.expires = jiffies + HZ;
  4207. gdth_timer.data = 0L;
  4208. gdth_timer.function = gdth_timeout;
  4209. add_timer(&gdth_timer);
  4210. #endif
  4211. major = register_chrdev(0,"gdth",&gdth_fops);
  4212. register_reboot_notifier(&gdth_notifier);
  4213. }
  4214. gdth_polling = FALSE;
  4215. return gdth_ctr_vcount;
  4216. }
  4217. static int gdth_release(struct Scsi_Host *shp)
  4218. {
  4219. int hanum;
  4220. gdth_ha_str *ha;
  4221. TRACE2(("gdth_release()\n"));
  4222. if (NUMDATA(shp)->busnum == 0) {
  4223. hanum = NUMDATA(shp)->hanum;
  4224. ha = HADATA(gdth_ctr_tab[hanum]);
  4225. if (ha->sdev) {
  4226. scsi_free_host_dev(ha->sdev);
  4227. ha->sdev = NULL;
  4228. }
  4229. gdth_flush(hanum);
  4230. if (shp->irq) {
  4231. free_irq(shp->irq,ha);
  4232. }
  4233. #ifndef __ia64__
  4234. if (shp->dma_channel != 0xff) {
  4235. free_dma(shp->dma_channel);
  4236. }
  4237. #endif
  4238. #ifdef INT_COAL
  4239. if (ha->coal_stat)
  4240. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4241. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4242. #endif
  4243. if (ha->pscratch)
  4244. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4245. ha->pscratch, ha->scratch_phys);
  4246. if (ha->pmsg)
  4247. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4248. ha->pmsg, ha->msg_phys);
  4249. if (ha->ccb_phys)
  4250. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4251. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4252. gdth_ctr_released++;
  4253. TRACE2(("gdth_release(): HA %d of %d\n",
  4254. gdth_ctr_released, gdth_ctr_count));
  4255. if (gdth_ctr_released == gdth_ctr_count) {
  4256. #ifdef GDTH_STATISTICS
  4257. del_timer(&gdth_timer);
  4258. #endif
  4259. unregister_chrdev(major,"gdth");
  4260. unregister_reboot_notifier(&gdth_notifier);
  4261. }
  4262. }
  4263. scsi_unregister(shp);
  4264. return 0;
  4265. }
  4266. static const char *gdth_ctr_name(int hanum)
  4267. {
  4268. gdth_ha_str *ha;
  4269. TRACE2(("gdth_ctr_name()\n"));
  4270. ha = HADATA(gdth_ctr_tab[hanum]);
  4271. if (ha->type == GDT_EISA) {
  4272. switch (ha->stype) {
  4273. case GDT3_ID:
  4274. return("GDT3000/3020");
  4275. case GDT3A_ID:
  4276. return("GDT3000A/3020A/3050A");
  4277. case GDT3B_ID:
  4278. return("GDT3000B/3010A");
  4279. }
  4280. } else if (ha->type == GDT_ISA) {
  4281. return("GDT2000/2020");
  4282. } else if (ha->type == GDT_PCI) {
  4283. switch (ha->stype) {
  4284. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4285. return("GDT6000/6020/6050");
  4286. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4287. return("GDT6000B/6010");
  4288. }
  4289. }
  4290. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4291. return("");
  4292. }
  4293. static const char *gdth_info(struct Scsi_Host *shp)
  4294. {
  4295. int hanum;
  4296. gdth_ha_str *ha;
  4297. TRACE2(("gdth_info()\n"));
  4298. hanum = NUMDATA(shp)->hanum;
  4299. ha = HADATA(gdth_ctr_tab[hanum]);
  4300. return ((const char *)ha->binfo.type_string);
  4301. }
  4302. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4303. {
  4304. int i, hanum;
  4305. gdth_ha_str *ha;
  4306. ulong flags;
  4307. Scsi_Cmnd *cmnd;
  4308. unchar b;
  4309. TRACE2(("gdth_eh_bus_reset()\n"));
  4310. hanum = NUMDATA(scp->device->host)->hanum;
  4311. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4312. ha = HADATA(gdth_ctr_tab[hanum]);
  4313. /* clear command tab */
  4314. spin_lock_irqsave(&ha->smp_lock, flags);
  4315. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4316. cmnd = ha->cmd_tab[i].cmnd;
  4317. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4318. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4319. }
  4320. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4321. if (b == ha->virt_bus) {
  4322. /* host drives */
  4323. for (i = 0; i < MAX_HDRIVES; ++i) {
  4324. if (ha->hdr[i].present) {
  4325. spin_lock_irqsave(&ha->smp_lock, flags);
  4326. gdth_polling = TRUE;
  4327. while (gdth_test_busy(hanum))
  4328. gdth_delay(0);
  4329. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4330. GDT_CLUST_RESET, i, 0, 0))
  4331. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4332. gdth_polling = FALSE;
  4333. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4334. }
  4335. }
  4336. } else {
  4337. /* raw devices */
  4338. spin_lock_irqsave(&ha->smp_lock, flags);
  4339. for (i = 0; i < MAXID; ++i)
  4340. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4341. gdth_polling = TRUE;
  4342. while (gdth_test_busy(hanum))
  4343. gdth_delay(0);
  4344. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4345. BUS_L2P(ha,b), 0, 0);
  4346. gdth_polling = FALSE;
  4347. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4348. }
  4349. return SUCCESS;
  4350. }
  4351. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4352. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4353. #else
  4354. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4355. #endif
  4356. {
  4357. unchar b, t;
  4358. int hanum;
  4359. gdth_ha_str *ha;
  4360. struct scsi_device *sd;
  4361. unsigned capacity;
  4362. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4363. sd = sdev;
  4364. capacity = cap;
  4365. #else
  4366. sd = disk->device;
  4367. capacity = disk->capacity;
  4368. #endif
  4369. hanum = NUMDATA(sd->host)->hanum;
  4370. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4371. t = sd->id;
  4372. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4373. ha = HADATA(gdth_ctr_tab[hanum]);
  4374. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4375. /* raw device or host drive without mapping information */
  4376. TRACE2(("Evaluate mapping\n"));
  4377. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4378. } else {
  4379. ip[0] = ha->hdr[t].heads;
  4380. ip[1] = ha->hdr[t].secs;
  4381. ip[2] = capacity / ip[0] / ip[1];
  4382. }
  4383. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4384. ip[0],ip[1],ip[2]));
  4385. return 0;
  4386. }
  4387. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
  4388. {
  4389. int hanum;
  4390. int priority;
  4391. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4392. scp->scsi_done = (void *)done;
  4393. scp->SCp.have_data_in = 1;
  4394. scp->SCp.phase = -1;
  4395. scp->SCp.sent_command = -1;
  4396. scp->SCp.Status = GDTH_MAP_NONE;
  4397. scp->SCp.buffer = (struct scatterlist *)NULL;
  4398. hanum = NUMDATA(scp->device->host)->hanum;
  4399. #ifdef GDTH_STATISTICS
  4400. ++act_ios;
  4401. #endif
  4402. priority = DEFAULT_PRI;
  4403. if (scp->done == gdth_scsi_done)
  4404. priority = scp->SCp.this_residual;
  4405. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4406. gdth_putq( hanum, scp, priority );
  4407. gdth_next( hanum );
  4408. return 0;
  4409. }
  4410. static int gdth_open(struct inode *inode, struct file *filep)
  4411. {
  4412. gdth_ha_str *ha;
  4413. int i;
  4414. for (i = 0; i < gdth_ctr_count; i++) {
  4415. ha = HADATA(gdth_ctr_tab[i]);
  4416. if (!ha->sdev)
  4417. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4418. }
  4419. TRACE(("gdth_open()\n"));
  4420. return 0;
  4421. }
  4422. static int gdth_close(struct inode *inode, struct file *filep)
  4423. {
  4424. TRACE(("gdth_close()\n"));
  4425. return 0;
  4426. }
  4427. static int ioc_event(void __user *arg)
  4428. {
  4429. gdth_ioctl_event evt;
  4430. gdth_ha_str *ha;
  4431. ulong flags;
  4432. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4433. evt.ionode >= gdth_ctr_count)
  4434. return -EFAULT;
  4435. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4436. if (evt.erase == 0xff) {
  4437. if (evt.event.event_source == ES_TEST)
  4438. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4439. else if (evt.event.event_source == ES_DRIVER)
  4440. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4441. else if (evt.event.event_source == ES_SYNC)
  4442. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4443. else
  4444. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4445. spin_lock_irqsave(&ha->smp_lock, flags);
  4446. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4447. &evt.event.event_data);
  4448. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4449. } else if (evt.erase == 0xfe) {
  4450. gdth_clear_events();
  4451. } else if (evt.erase == 0) {
  4452. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4453. } else {
  4454. gdth_readapp_event(ha, evt.erase, &evt.event);
  4455. }
  4456. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4457. return -EFAULT;
  4458. return 0;
  4459. }
  4460. static int ioc_lockdrv(void __user *arg)
  4461. {
  4462. gdth_ioctl_lockdrv ldrv;
  4463. unchar i, j;
  4464. ulong flags;
  4465. gdth_ha_str *ha;
  4466. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4467. ldrv.ionode >= gdth_ctr_count)
  4468. return -EFAULT;
  4469. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4470. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4471. j = ldrv.drives[i];
  4472. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4473. continue;
  4474. if (ldrv.lock) {
  4475. spin_lock_irqsave(&ha->smp_lock, flags);
  4476. ha->hdr[j].lock = 1;
  4477. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4478. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4479. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4480. } else {
  4481. spin_lock_irqsave(&ha->smp_lock, flags);
  4482. ha->hdr[j].lock = 0;
  4483. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4484. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4485. gdth_next(ldrv.ionode);
  4486. }
  4487. }
  4488. return 0;
  4489. }
  4490. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4491. {
  4492. gdth_ioctl_reset res;
  4493. gdth_cmd_str cmd;
  4494. int hanum;
  4495. gdth_ha_str *ha;
  4496. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4497. Scsi_Request *srp;
  4498. #else
  4499. Scsi_Cmnd *scp;
  4500. #endif
  4501. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4502. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4503. return -EFAULT;
  4504. hanum = res.ionode;
  4505. ha = HADATA(gdth_ctr_tab[hanum]);
  4506. if (!ha->hdr[res.number].present)
  4507. return 0;
  4508. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4509. cmd.Service = CACHESERVICE;
  4510. cmd.OpCode = GDT_CLUST_RESET;
  4511. if (ha->cache_feat & GDT_64BIT)
  4512. cmd.u.cache64.DeviceNo = res.number;
  4513. else
  4514. cmd.u.cache.DeviceNo = res.number;
  4515. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4516. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4517. if (!srp)
  4518. return -ENOMEM;
  4519. srp->sr_cmd_len = 12;
  4520. srp->sr_use_sg = 0;
  4521. gdth_do_req(srp, &cmd, cmnd, 30);
  4522. res.status = (ushort)srp->sr_command->SCp.Status;
  4523. scsi_release_request(srp);
  4524. #else
  4525. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4526. if (!scp)
  4527. return -ENOMEM;
  4528. scp->cmd_len = 12;
  4529. scp->use_sg = 0;
  4530. gdth_do_cmd(scp, &cmd, cmnd, 30);
  4531. res.status = (ushort)scp->SCp.Status;
  4532. scsi_release_command(scp);
  4533. #endif
  4534. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4535. return -EFAULT;
  4536. return 0;
  4537. }
  4538. static int ioc_general(void __user *arg, char *cmnd)
  4539. {
  4540. gdth_ioctl_general gen;
  4541. char *buf = NULL;
  4542. ulong64 paddr;
  4543. int hanum;
  4544. gdth_ha_str *ha;
  4545. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4546. Scsi_Request *srp;
  4547. #else
  4548. Scsi_Cmnd *scp;
  4549. #endif
  4550. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4551. gen.ionode >= gdth_ctr_count)
  4552. return -EFAULT;
  4553. hanum = gen.ionode;
  4554. ha = HADATA(gdth_ctr_tab[hanum]);
  4555. if (gen.data_len + gen.sense_len != 0) {
  4556. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4557. FALSE, &paddr)))
  4558. return -EFAULT;
  4559. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4560. gen.data_len + gen.sense_len)) {
  4561. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4562. return -EFAULT;
  4563. }
  4564. if (gen.command.OpCode == GDT_IOCTL) {
  4565. gen.command.u.ioctl.p_param = paddr;
  4566. } else if (gen.command.Service == CACHESERVICE) {
  4567. if (ha->cache_feat & GDT_64BIT) {
  4568. /* copy elements from 32-bit IOCTL structure */
  4569. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4570. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4571. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4572. /* addresses */
  4573. if (ha->cache_feat & SCATTER_GATHER) {
  4574. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4575. gen.command.u.cache64.sg_canz = 1;
  4576. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4577. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4578. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4579. } else {
  4580. gen.command.u.cache64.DestAddr = paddr;
  4581. gen.command.u.cache64.sg_canz = 0;
  4582. }
  4583. } else {
  4584. if (ha->cache_feat & SCATTER_GATHER) {
  4585. gen.command.u.cache.DestAddr = 0xffffffff;
  4586. gen.command.u.cache.sg_canz = 1;
  4587. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4588. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4589. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4590. } else {
  4591. gen.command.u.cache.DestAddr = paddr;
  4592. gen.command.u.cache.sg_canz = 0;
  4593. }
  4594. }
  4595. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4596. if (ha->raw_feat & GDT_64BIT) {
  4597. /* copy elements from 32-bit IOCTL structure */
  4598. char cmd[16];
  4599. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4600. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4601. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4602. gen.command.u.raw64.target = gen.command.u.raw.target;
  4603. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4604. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4605. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4606. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4607. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4608. /* addresses */
  4609. if (ha->raw_feat & SCATTER_GATHER) {
  4610. gen.command.u.raw64.sdata = (ulong64)-1;
  4611. gen.command.u.raw64.sg_ranz = 1;
  4612. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4613. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4614. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4615. } else {
  4616. gen.command.u.raw64.sdata = paddr;
  4617. gen.command.u.raw64.sg_ranz = 0;
  4618. }
  4619. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4620. } else {
  4621. if (ha->raw_feat & SCATTER_GATHER) {
  4622. gen.command.u.raw.sdata = 0xffffffff;
  4623. gen.command.u.raw.sg_ranz = 1;
  4624. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4625. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4626. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4627. } else {
  4628. gen.command.u.raw.sdata = paddr;
  4629. gen.command.u.raw.sg_ranz = 0;
  4630. }
  4631. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4632. }
  4633. } else {
  4634. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4635. return -EFAULT;
  4636. }
  4637. }
  4638. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4639. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4640. if (!srp)
  4641. return -ENOMEM;
  4642. srp->sr_cmd_len = 12;
  4643. srp->sr_use_sg = 0;
  4644. gdth_do_req(srp, &gen.command, cmnd, gen.timeout);
  4645. gen.status = srp->sr_command->SCp.Status;
  4646. gen.info = srp->sr_command->SCp.Message;
  4647. scsi_release_request(srp);
  4648. #else
  4649. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4650. if (!scp)
  4651. return -ENOMEM;
  4652. scp->cmd_len = 12;
  4653. scp->use_sg = 0;
  4654. gdth_do_cmd(scp, &gen.command, cmnd, gen.timeout);
  4655. gen.status = scp->SCp.Status;
  4656. gen.info = scp->SCp.Message;
  4657. scsi_release_command(scp);
  4658. #endif
  4659. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4660. gen.data_len + gen.sense_len)) {
  4661. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4662. return -EFAULT;
  4663. }
  4664. if (copy_to_user(arg, &gen,
  4665. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4666. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4667. return -EFAULT;
  4668. }
  4669. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4670. return 0;
  4671. }
  4672. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4673. {
  4674. gdth_ioctl_rescan *rsc;
  4675. gdth_cmd_str *cmd;
  4676. gdth_ha_str *ha;
  4677. unchar i;
  4678. int hanum, rc = -ENOMEM;
  4679. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4680. Scsi_Request *srp;
  4681. #else
  4682. Scsi_Cmnd *scp;
  4683. #endif
  4684. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4685. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4686. if (!rsc || !cmd)
  4687. goto free_fail;
  4688. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4689. rsc->ionode >= gdth_ctr_count) {
  4690. rc = -EFAULT;
  4691. goto free_fail;
  4692. }
  4693. hanum = rsc->ionode;
  4694. ha = HADATA(gdth_ctr_tab[hanum]);
  4695. memset(cmd, 0, sizeof(gdth_cmd_str));
  4696. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4697. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4698. if (!srp)
  4699. goto free_fail;
  4700. srp->sr_cmd_len = 12;
  4701. srp->sr_use_sg = 0;
  4702. #else
  4703. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4704. if (!scp)
  4705. goto free_fail;
  4706. scp->cmd_len = 12;
  4707. scp->use_sg = 0;
  4708. #endif
  4709. for (i = 0; i < MAX_HDRIVES; ++i) {
  4710. if (!ha->hdr[i].present) {
  4711. rsc->hdr_list[i].bus = 0xff;
  4712. continue;
  4713. }
  4714. rsc->hdr_list[i].bus = ha->virt_bus;
  4715. rsc->hdr_list[i].target = i;
  4716. rsc->hdr_list[i].lun = 0;
  4717. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4718. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4719. cmd->Service = CACHESERVICE;
  4720. cmd->OpCode = GDT_CLUST_INFO;
  4721. if (ha->cache_feat & GDT_64BIT)
  4722. cmd->u.cache64.DeviceNo = i;
  4723. else
  4724. cmd->u.cache.DeviceNo = i;
  4725. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4726. gdth_do_req(srp, cmd, cmnd, 30);
  4727. if (srp->sr_command->SCp.Status == S_OK)
  4728. rsc->hdr_list[i].cluster_type = srp->sr_command->SCp.Message;
  4729. #else
  4730. gdth_do_cmd(scp, cmd, cmnd, 30);
  4731. if (scp->SCp.Status == S_OK)
  4732. rsc->hdr_list[i].cluster_type = scp->SCp.Message;
  4733. #endif
  4734. }
  4735. }
  4736. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4737. scsi_release_request(srp);
  4738. #else
  4739. scsi_release_command(scp);
  4740. #endif
  4741. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4742. rc = -EFAULT;
  4743. else
  4744. rc = 0;
  4745. free_fail:
  4746. kfree(rsc);
  4747. kfree(cmd);
  4748. return rc;
  4749. }
  4750. static int ioc_rescan(void __user *arg, char *cmnd)
  4751. {
  4752. gdth_ioctl_rescan *rsc;
  4753. gdth_cmd_str *cmd;
  4754. ushort i, status, hdr_cnt;
  4755. ulong32 info;
  4756. int hanum, cyls, hds, secs;
  4757. int rc = -ENOMEM;
  4758. ulong flags;
  4759. gdth_ha_str *ha;
  4760. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4761. Scsi_Request *srp;
  4762. #else
  4763. Scsi_Cmnd *scp;
  4764. #endif
  4765. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4766. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4767. if (!cmd || !rsc)
  4768. goto free_fail;
  4769. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4770. rsc->ionode >= gdth_ctr_count) {
  4771. rc = -EFAULT;
  4772. goto free_fail;
  4773. }
  4774. hanum = rsc->ionode;
  4775. ha = HADATA(gdth_ctr_tab[hanum]);
  4776. memset(cmd, 0, sizeof(gdth_cmd_str));
  4777. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4778. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4779. if (!srp)
  4780. goto free_fail;
  4781. srp->sr_cmd_len = 12;
  4782. srp->sr_use_sg = 0;
  4783. #else
  4784. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4785. if (!scp)
  4786. goto free_fail;
  4787. scp->cmd_len = 12;
  4788. scp->use_sg = 0;
  4789. #endif
  4790. if (rsc->flag == 0) {
  4791. /* old method: re-init. cache service */
  4792. cmd->Service = CACHESERVICE;
  4793. if (ha->cache_feat & GDT_64BIT) {
  4794. cmd->OpCode = GDT_X_INIT_HOST;
  4795. cmd->u.cache64.DeviceNo = LINUX_OS;
  4796. } else {
  4797. cmd->OpCode = GDT_INIT;
  4798. cmd->u.cache.DeviceNo = LINUX_OS;
  4799. }
  4800. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4801. gdth_do_req(srp, cmd, cmnd, 30);
  4802. status = (ushort)srp->sr_command->SCp.Status;
  4803. info = (ulong32)srp->sr_command->SCp.Message;
  4804. #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
  4805. gdth_do_cmd(scp, cmd, cmnd, 30);
  4806. status = (ushort)scp->SCp.Status;
  4807. info = (ulong32)scp->SCp.Message;
  4808. #else
  4809. gdth_do_cmd(&scp, cmd, cmnd, 30);
  4810. status = (ushort)scp.SCp.Status;
  4811. info = (ulong32)scp.SCp.Message;
  4812. #endif
  4813. i = 0;
  4814. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4815. } else {
  4816. i = rsc->hdr_no;
  4817. hdr_cnt = i + 1;
  4818. }
  4819. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4820. cmd->Service = CACHESERVICE;
  4821. cmd->OpCode = GDT_INFO;
  4822. if (ha->cache_feat & GDT_64BIT)
  4823. cmd->u.cache64.DeviceNo = i;
  4824. else
  4825. cmd->u.cache.DeviceNo = i;
  4826. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4827. gdth_do_req(srp, cmd, cmnd, 30);
  4828. status = (ushort)srp->sr_command->SCp.Status;
  4829. info = (ulong32)srp->sr_command->SCp.Message;
  4830. #else
  4831. gdth_do_cmd(scp, cmd, cmnd, 30);
  4832. status = (ushort)scp->SCp.Status;
  4833. info = (ulong32)scp->SCp.Message;
  4834. #endif
  4835. spin_lock_irqsave(&ha->smp_lock, flags);
  4836. rsc->hdr_list[i].bus = ha->virt_bus;
  4837. rsc->hdr_list[i].target = i;
  4838. rsc->hdr_list[i].lun = 0;
  4839. if (status != S_OK) {
  4840. ha->hdr[i].present = FALSE;
  4841. } else {
  4842. ha->hdr[i].present = TRUE;
  4843. ha->hdr[i].size = info;
  4844. /* evaluate mapping */
  4845. ha->hdr[i].size &= ~SECS32;
  4846. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4847. ha->hdr[i].heads = hds;
  4848. ha->hdr[i].secs = secs;
  4849. /* round size */
  4850. ha->hdr[i].size = cyls * hds * secs;
  4851. }
  4852. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4853. if (status != S_OK)
  4854. continue;
  4855. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4856. /* but we need ha->info2, not yet stored in scp->SCp */
  4857. /* devtype, cluster info, R/W attribs */
  4858. cmd->Service = CACHESERVICE;
  4859. cmd->OpCode = GDT_DEVTYPE;
  4860. if (ha->cache_feat & GDT_64BIT)
  4861. cmd->u.cache64.DeviceNo = i;
  4862. else
  4863. cmd->u.cache.DeviceNo = i;
  4864. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4865. gdth_do_req(srp, cmd, cmnd, 30);
  4866. status = (ushort)srp->sr_command->SCp.Status;
  4867. info = (ulong32)srp->sr_command->SCp.Message;
  4868. #else
  4869. gdth_do_cmd(scp, cmd, cmnd, 30);
  4870. status = (ushort)scp->SCp.Status;
  4871. info = (ulong32)scp->SCp.Message;
  4872. #endif
  4873. spin_lock_irqsave(&ha->smp_lock, flags);
  4874. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4875. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4876. cmd->Service = CACHESERVICE;
  4877. cmd->OpCode = GDT_CLUST_INFO;
  4878. if (ha->cache_feat & GDT_64BIT)
  4879. cmd->u.cache64.DeviceNo = i;
  4880. else
  4881. cmd->u.cache.DeviceNo = i;
  4882. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4883. gdth_do_req(srp, cmd, cmnd, 30);
  4884. status = (ushort)srp->sr_command->SCp.Status;
  4885. info = (ulong32)srp->sr_command->SCp.Message;
  4886. #else
  4887. gdth_do_cmd(scp, cmd, cmnd, 30);
  4888. status = (ushort)scp->SCp.Status;
  4889. info = (ulong32)scp->SCp.Message;
  4890. #endif
  4891. spin_lock_irqsave(&ha->smp_lock, flags);
  4892. ha->hdr[i].cluster_type =
  4893. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4894. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4895. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4896. cmd->Service = CACHESERVICE;
  4897. cmd->OpCode = GDT_RW_ATTRIBS;
  4898. if (ha->cache_feat & GDT_64BIT)
  4899. cmd->u.cache64.DeviceNo = i;
  4900. else
  4901. cmd->u.cache.DeviceNo = i;
  4902. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4903. gdth_do_req(srp, cmd, cmnd, 30);
  4904. status = (ushort)srp->sr_command->SCp.Status;
  4905. info = (ulong32)srp->sr_command->SCp.Message;
  4906. #else
  4907. gdth_do_cmd(scp, cmd, cmnd, 30);
  4908. status = (ushort)scp->SCp.Status;
  4909. info = (ulong32)scp->SCp.Message;
  4910. #endif
  4911. spin_lock_irqsave(&ha->smp_lock, flags);
  4912. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4913. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4914. }
  4915. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4916. scsi_release_request(srp);
  4917. #else
  4918. scsi_release_command(scp);
  4919. #endif
  4920. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4921. rc = -EFAULT;
  4922. else
  4923. rc = 0;
  4924. free_fail:
  4925. kfree(rsc);
  4926. kfree(cmd);
  4927. return rc;
  4928. }
  4929. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4930. unsigned int cmd, unsigned long arg)
  4931. {
  4932. gdth_ha_str *ha;
  4933. Scsi_Cmnd *scp;
  4934. ulong flags;
  4935. char cmnd[MAX_COMMAND_SIZE];
  4936. void __user *argp = (void __user *)arg;
  4937. memset(cmnd, 0xff, 12);
  4938. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4939. switch (cmd) {
  4940. case GDTIOCTL_CTRCNT:
  4941. {
  4942. int cnt = gdth_ctr_count;
  4943. if (put_user(cnt, (int __user *)argp))
  4944. return -EFAULT;
  4945. break;
  4946. }
  4947. case GDTIOCTL_DRVERS:
  4948. {
  4949. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4950. if (put_user(ver, (int __user *)argp))
  4951. return -EFAULT;
  4952. break;
  4953. }
  4954. case GDTIOCTL_OSVERS:
  4955. {
  4956. gdth_ioctl_osvers osv;
  4957. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4958. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4959. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4960. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4961. return -EFAULT;
  4962. break;
  4963. }
  4964. case GDTIOCTL_CTRTYPE:
  4965. {
  4966. gdth_ioctl_ctrtype ctrt;
  4967. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4968. ctrt.ionode >= gdth_ctr_count)
  4969. return -EFAULT;
  4970. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4971. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4972. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4973. } else {
  4974. if (ha->type != GDT_PCIMPR) {
  4975. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4976. } else {
  4977. ctrt.type =
  4978. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4979. if (ha->stype >= 0x300)
  4980. ctrt.ext_type = 0x6000 | ha->subdevice_id;
  4981. else
  4982. ctrt.ext_type = 0x6000 | ha->stype;
  4983. }
  4984. ctrt.device_id = ha->stype;
  4985. ctrt.sub_device_id = ha->subdevice_id;
  4986. }
  4987. ctrt.info = ha->brd_phys;
  4988. ctrt.oem_id = ha->oem_id;
  4989. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4990. return -EFAULT;
  4991. break;
  4992. }
  4993. case GDTIOCTL_GENERAL:
  4994. return ioc_general(argp, cmnd);
  4995. case GDTIOCTL_EVENT:
  4996. return ioc_event(argp);
  4997. case GDTIOCTL_LOCKDRV:
  4998. return ioc_lockdrv(argp);
  4999. case GDTIOCTL_LOCKCHN:
  5000. {
  5001. gdth_ioctl_lockchn lchn;
  5002. unchar i, j;
  5003. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  5004. lchn.ionode >= gdth_ctr_count)
  5005. return -EFAULT;
  5006. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  5007. i = lchn.channel;
  5008. if (i < ha->bus_cnt) {
  5009. if (lchn.lock) {
  5010. spin_lock_irqsave(&ha->smp_lock, flags);
  5011. ha->raw[i].lock = 1;
  5012. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5013. for (j = 0; j < ha->tid_cnt; ++j) {
  5014. gdth_wait_completion(lchn.ionode, i, j);
  5015. gdth_stop_timeout(lchn.ionode, i, j);
  5016. }
  5017. } else {
  5018. spin_lock_irqsave(&ha->smp_lock, flags);
  5019. ha->raw[i].lock = 0;
  5020. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5021. for (j = 0; j < ha->tid_cnt; ++j) {
  5022. gdth_start_timeout(lchn.ionode, i, j);
  5023. gdth_next(lchn.ionode);
  5024. }
  5025. }
  5026. }
  5027. break;
  5028. }
  5029. case GDTIOCTL_RESCAN:
  5030. return ioc_rescan(argp, cmnd);
  5031. case GDTIOCTL_HDRLIST:
  5032. return ioc_hdrlist(argp, cmnd);
  5033. case GDTIOCTL_RESET_BUS:
  5034. {
  5035. gdth_ioctl_reset res;
  5036. int hanum, rval;
  5037. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  5038. res.ionode >= gdth_ctr_count)
  5039. return -EFAULT;
  5040. hanum = res.ionode;
  5041. ha = HADATA(gdth_ctr_tab[hanum]);
  5042. /* Because we need a Scsi_Cmnd struct., we make a scsi_allocate device also for kernels >=2.6.x */
  5043. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5044. scp = scsi_get_command(ha->sdev, GFP_KERNEL);
  5045. if (!scp)
  5046. return -ENOMEM;
  5047. scp->cmd_len = 12;
  5048. scp->use_sg = 0;
  5049. scp->device->channel = virt_ctr ? 0 : res.number;
  5050. rval = gdth_eh_bus_reset(scp);
  5051. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5052. scsi_put_command(scp);
  5053. #else
  5054. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  5055. if (!scp)
  5056. return -ENOMEM;
  5057. scp->cmd_len = 12;
  5058. scp->use_sg = 0;
  5059. scp->channel = virt_ctr ? 0 : res.number;
  5060. rval = gdth_eh_bus_reset(scp);
  5061. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5062. scsi_release_command(scp);
  5063. #endif
  5064. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  5065. return -EFAULT;
  5066. break;
  5067. }
  5068. case GDTIOCTL_RESET_DRV:
  5069. return ioc_resetdrv(argp, cmnd);
  5070. default:
  5071. break;
  5072. }
  5073. return 0;
  5074. }
  5075. /* flush routine */
  5076. static void gdth_flush(int hanum)
  5077. {
  5078. int i;
  5079. gdth_ha_str *ha;
  5080. gdth_cmd_str gdtcmd;
  5081. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5082. Scsi_Request *srp;
  5083. #else
  5084. Scsi_Cmnd *scp;
  5085. #endif
  5086. Scsi_Device *sdev;
  5087. char cmnd[MAX_COMMAND_SIZE];
  5088. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5089. TRACE2(("gdth_flush() hanum %d\n",hanum));
  5090. ha = HADATA(gdth_ctr_tab[hanum]);
  5091. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5092. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5093. srp = scsi_allocate_request(sdev, GFP_KERNEL);
  5094. if (!srp)
  5095. return;
  5096. srp->sr_cmd_len = 12;
  5097. srp->sr_use_sg = 0;
  5098. #else
  5099. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5100. scp = scsi_allocate_device(sdev, 1, FALSE);
  5101. if (!scp)
  5102. return;
  5103. scp->cmd_len = 12;
  5104. scp->use_sg = 0;
  5105. #endif
  5106. for (i = 0; i < MAX_HDRIVES; ++i) {
  5107. if (ha->hdr[i].present) {
  5108. gdtcmd.BoardNode = LOCALBOARD;
  5109. gdtcmd.Service = CACHESERVICE;
  5110. gdtcmd.OpCode = GDT_FLUSH;
  5111. if (ha->cache_feat & GDT_64BIT) {
  5112. gdtcmd.u.cache64.DeviceNo = i;
  5113. gdtcmd.u.cache64.BlockNo = 1;
  5114. gdtcmd.u.cache64.sg_canz = 0;
  5115. } else {
  5116. gdtcmd.u.cache.DeviceNo = i;
  5117. gdtcmd.u.cache.BlockNo = 1;
  5118. gdtcmd.u.cache.sg_canz = 0;
  5119. }
  5120. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  5121. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5122. gdth_do_req(srp, &gdtcmd, cmnd, 30);
  5123. #else
  5124. gdth_do_cmd(scp, &gdtcmd, cmnd, 30);
  5125. #endif
  5126. }
  5127. }
  5128. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5129. scsi_release_request(srp);
  5130. scsi_free_host_dev(sdev);
  5131. #else
  5132. scsi_release_command(scp);
  5133. scsi_free_host_dev(sdev);
  5134. #endif
  5135. }
  5136. /* shutdown routine */
  5137. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  5138. {
  5139. int hanum;
  5140. #ifndef __alpha__
  5141. gdth_cmd_str gdtcmd;
  5142. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5143. Scsi_Request *srp;
  5144. Scsi_Device *sdev;
  5145. #else
  5146. Scsi_Cmnd *scp;
  5147. Scsi_Device *sdev;
  5148. #endif
  5149. char cmnd[MAX_COMMAND_SIZE];
  5150. #endif
  5151. TRACE2(("gdth_halt() event %d\n",(int)event));
  5152. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  5153. return NOTIFY_DONE;
  5154. printk("GDT-HA: Flushing all host drives .. ");
  5155. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  5156. gdth_flush(hanum);
  5157. #ifndef __alpha__
  5158. /* controller reset */
  5159. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5160. gdtcmd.BoardNode = LOCALBOARD;
  5161. gdtcmd.Service = CACHESERVICE;
  5162. gdtcmd.OpCode = GDT_RESET;
  5163. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  5164. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5165. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5166. srp = scsi_allocate_request(sdev, GFP_KERNEL);
  5167. if (!srp) {
  5168. unregister_reboot_notifier(&gdth_notifier);
  5169. return NOTIFY_OK;
  5170. }
  5171. srp->sr_cmd_len = 12;
  5172. srp->sr_use_sg = 0;
  5173. gdth_do_req(srp, &gdtcmd, cmnd, 10);
  5174. scsi_release_request(srp);
  5175. scsi_free_host_dev(sdev);
  5176. #else
  5177. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5178. scp = scsi_allocate_device(sdev, 1, FALSE);
  5179. if (!scp) {
  5180. unregister_reboot_notifier(&gdth_notifier);
  5181. return NOTIFY_OK;
  5182. }
  5183. scp->cmd_len = 12;
  5184. scp->use_sg = 0;
  5185. gdth_do_cmd(scp, &gdtcmd, cmnd, 10);
  5186. scsi_release_command(scp);
  5187. scsi_free_host_dev(sdev);
  5188. #endif
  5189. #endif
  5190. }
  5191. printk("Done.\n");
  5192. #ifdef GDTH_STATISTICS
  5193. del_timer(&gdth_timer);
  5194. #endif
  5195. unregister_reboot_notifier(&gdth_notifier);
  5196. return NOTIFY_OK;
  5197. }
  5198. static Scsi_Host_Template driver_template = {
  5199. .proc_name = "gdth",
  5200. .proc_info = gdth_proc_info,
  5201. .name = "GDT SCSI Disk Array Controller",
  5202. .detect = gdth_detect,
  5203. .release = gdth_release,
  5204. .info = gdth_info,
  5205. .queuecommand = gdth_queuecommand,
  5206. .eh_bus_reset_handler = gdth_eh_bus_reset,
  5207. .bios_param = gdth_bios_param,
  5208. .can_queue = GDTH_MAXCMDS,
  5209. .this_id = -1,
  5210. .sg_tablesize = GDTH_MAXSG,
  5211. .cmd_per_lun = GDTH_MAXC_P_L,
  5212. .unchecked_isa_dma = 1,
  5213. .use_clustering = ENABLE_CLUSTERING,
  5214. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  5215. .use_new_eh_code = 1,
  5216. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  5217. .highmem_io = 1,
  5218. #endif
  5219. #endif
  5220. };
  5221. #include "scsi_module.c"
  5222. #ifndef MODULE
  5223. __setup("gdth=", option_setup);
  5224. #endif