aic7xxx_reg_print.c_shipped 41 KB

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  1. /*
  2. * DO NOT EDIT - This file is automatically generated
  3. * from the following source files:
  4. *
  5. * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
  6. * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
  7. */
  8. #include "aic7xxx_osm.h"
  9. static ahc_reg_parse_entry_t SCSISEQ_parse_table[] = {
  10. { "SCSIRSTO", 0x01, 0x01 },
  11. { "ENAUTOATNP", 0x02, 0x02 },
  12. { "ENAUTOATNI", 0x04, 0x04 },
  13. { "ENAUTOATNO", 0x08, 0x08 },
  14. { "ENRSELI", 0x10, 0x10 },
  15. { "ENSELI", 0x20, 0x20 },
  16. { "ENSELO", 0x40, 0x40 },
  17. { "TEMODE", 0x80, 0x80 }
  18. };
  19. int
  20. ahc_scsiseq_print(u_int regvalue, u_int *cur_col, u_int wrap)
  21. {
  22. return (ahc_print_register(SCSISEQ_parse_table, 8, "SCSISEQ",
  23. 0x00, regvalue, cur_col, wrap));
  24. }
  25. static ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = {
  26. { "CLRCHN", 0x02, 0x02 },
  27. { "SCAMEN", 0x04, 0x04 },
  28. { "SPIOEN", 0x08, 0x08 },
  29. { "CLRSTCNT", 0x10, 0x10 },
  30. { "FAST20", 0x20, 0x20 },
  31. { "DFPEXP", 0x40, 0x40 },
  32. { "DFON", 0x80, 0x80 }
  33. };
  34. int
  35. ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  36. {
  37. return (ahc_print_register(SXFRCTL0_parse_table, 7, "SXFRCTL0",
  38. 0x01, regvalue, cur_col, wrap));
  39. }
  40. static ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = {
  41. { "STPWEN", 0x01, 0x01 },
  42. { "ACTNEGEN", 0x02, 0x02 },
  43. { "ENSTIMER", 0x04, 0x04 },
  44. { "ENSPCHK", 0x20, 0x20 },
  45. { "SWRAPEN", 0x40, 0x40 },
  46. { "BITBUCKET", 0x80, 0x80 },
  47. { "STIMESEL", 0x18, 0x18 }
  48. };
  49. int
  50. ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  51. {
  52. return (ahc_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1",
  53. 0x02, regvalue, cur_col, wrap));
  54. }
  55. static ahc_reg_parse_entry_t SCSISIGO_parse_table[] = {
  56. { "ACKO", 0x01, 0x01 },
  57. { "REQO", 0x02, 0x02 },
  58. { "BSYO", 0x04, 0x04 },
  59. { "SELO", 0x08, 0x08 },
  60. { "ATNO", 0x10, 0x10 },
  61. { "MSGO", 0x20, 0x20 },
  62. { "IOO", 0x40, 0x40 },
  63. { "CDO", 0x80, 0x80 },
  64. { "P_DATAOUT", 0x00, 0x00 },
  65. { "P_DATAIN", 0x40, 0x40 },
  66. { "P_COMMAND", 0x80, 0x80 },
  67. { "P_MESGOUT", 0xa0, 0xa0 },
  68. { "P_STATUS", 0xc0, 0xc0 },
  69. { "PHASE_MASK", 0xe0, 0xe0 },
  70. { "P_MESGIN", 0xe0, 0xe0 }
  71. };
  72. int
  73. ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
  74. {
  75. return (ahc_print_register(SCSISIGO_parse_table, 15, "SCSISIGO",
  76. 0x03, regvalue, cur_col, wrap));
  77. }
  78. static ahc_reg_parse_entry_t SCSISIGI_parse_table[] = {
  79. { "ACKI", 0x01, 0x01 },
  80. { "REQI", 0x02, 0x02 },
  81. { "BSYI", 0x04, 0x04 },
  82. { "SELI", 0x08, 0x08 },
  83. { "ATNI", 0x10, 0x10 },
  84. { "MSGI", 0x20, 0x20 },
  85. { "IOI", 0x40, 0x40 },
  86. { "CDI", 0x80, 0x80 },
  87. { "P_DATAOUT", 0x00, 0x00 },
  88. { "P_DATAOUT_DT", 0x20, 0x20 },
  89. { "P_DATAIN", 0x40, 0x40 },
  90. { "P_DATAIN_DT", 0x60, 0x60 },
  91. { "P_COMMAND", 0x80, 0x80 },
  92. { "P_MESGOUT", 0xa0, 0xa0 },
  93. { "P_STATUS", 0xc0, 0xc0 },
  94. { "PHASE_MASK", 0xe0, 0xe0 },
  95. { "P_MESGIN", 0xe0, 0xe0 }
  96. };
  97. int
  98. ahc_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
  99. {
  100. return (ahc_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
  101. 0x03, regvalue, cur_col, wrap));
  102. }
  103. static ahc_reg_parse_entry_t SCSIRATE_parse_table[] = {
  104. { "SINGLE_EDGE", 0x10, 0x10 },
  105. { "ENABLE_CRC", 0x40, 0x40 },
  106. { "WIDEXFER", 0x80, 0x80 },
  107. { "SXFR_ULTRA2", 0x0f, 0x0f },
  108. { "SOFS", 0x0f, 0x0f },
  109. { "SXFR", 0x70, 0x70 }
  110. };
  111. int
  112. ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
  113. {
  114. return (ahc_print_register(SCSIRATE_parse_table, 6, "SCSIRATE",
  115. 0x04, regvalue, cur_col, wrap));
  116. }
  117. static ahc_reg_parse_entry_t SCSIID_parse_table[] = {
  118. { "TWIN_CHNLB", 0x80, 0x80 },
  119. { "OID", 0x0f, 0x0f },
  120. { "TWIN_TID", 0x70, 0x70 },
  121. { "SOFS_ULTRA2", 0x7f, 0x7f },
  122. { "TID", 0xf0, 0xf0 }
  123. };
  124. int
  125. ahc_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  126. {
  127. return (ahc_print_register(SCSIID_parse_table, 5, "SCSIID",
  128. 0x05, regvalue, cur_col, wrap));
  129. }
  130. int
  131. ahc_scsidatl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  132. {
  133. return (ahc_print_register(NULL, 0, "SCSIDATL",
  134. 0x06, regvalue, cur_col, wrap));
  135. }
  136. int
  137. ahc_scsidath_print(u_int regvalue, u_int *cur_col, u_int wrap)
  138. {
  139. return (ahc_print_register(NULL, 0, "SCSIDATH",
  140. 0x07, regvalue, cur_col, wrap));
  141. }
  142. int
  143. ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  144. {
  145. return (ahc_print_register(NULL, 0, "STCNT",
  146. 0x08, regvalue, cur_col, wrap));
  147. }
  148. static ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = {
  149. { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 },
  150. { "AUTO_MSGOUT_DE", 0x02, 0x02 },
  151. { "SCSIDATL_IMGEN", 0x04, 0x04 },
  152. { "EXPPHASEDIS", 0x08, 0x08 },
  153. { "BUSFREEREV", 0x10, 0x10 },
  154. { "ATNMGMNTEN", 0x20, 0x20 },
  155. { "AUTOACKEN", 0x40, 0x40 },
  156. { "AUTORATEEN", 0x80, 0x80 },
  157. { "OPTIONMODE_DEFAULTS",0x03, 0x03 }
  158. };
  159. int
  160. ahc_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
  161. {
  162. return (ahc_print_register(OPTIONMODE_parse_table, 9, "OPTIONMODE",
  163. 0x08, regvalue, cur_col, wrap));
  164. }
  165. int
  166. ahc_targcrccnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  167. {
  168. return (ahc_print_register(NULL, 0, "TARGCRCCNT",
  169. 0x0a, regvalue, cur_col, wrap));
  170. }
  171. static ahc_reg_parse_entry_t CLRSINT0_parse_table[] = {
  172. { "CLRSPIORDY", 0x02, 0x02 },
  173. { "CLRSWRAP", 0x08, 0x08 },
  174. { "CLRIOERR", 0x08, 0x08 },
  175. { "CLRSELINGO", 0x10, 0x10 },
  176. { "CLRSELDI", 0x20, 0x20 },
  177. { "CLRSELDO", 0x40, 0x40 }
  178. };
  179. int
  180. ahc_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  181. {
  182. return (ahc_print_register(CLRSINT0_parse_table, 6, "CLRSINT0",
  183. 0x0b, regvalue, cur_col, wrap));
  184. }
  185. static ahc_reg_parse_entry_t SSTAT0_parse_table[] = {
  186. { "DMADONE", 0x01, 0x01 },
  187. { "SPIORDY", 0x02, 0x02 },
  188. { "SDONE", 0x04, 0x04 },
  189. { "SWRAP", 0x08, 0x08 },
  190. { "IOERR", 0x08, 0x08 },
  191. { "SELINGO", 0x10, 0x10 },
  192. { "SELDI", 0x20, 0x20 },
  193. { "SELDO", 0x40, 0x40 },
  194. { "TARGET", 0x80, 0x80 }
  195. };
  196. int
  197. ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  198. {
  199. return (ahc_print_register(SSTAT0_parse_table, 9, "SSTAT0",
  200. 0x0b, regvalue, cur_col, wrap));
  201. }
  202. static ahc_reg_parse_entry_t CLRSINT1_parse_table[] = {
  203. { "CLRREQINIT", 0x01, 0x01 },
  204. { "CLRPHASECHG", 0x02, 0x02 },
  205. { "CLRSCSIPERR", 0x04, 0x04 },
  206. { "CLRBUSFREE", 0x08, 0x08 },
  207. { "CLRSCSIRSTI", 0x20, 0x20 },
  208. { "CLRATNO", 0x40, 0x40 },
  209. { "CLRSELTIMEO", 0x80, 0x80 }
  210. };
  211. int
  212. ahc_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  213. {
  214. return (ahc_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
  215. 0x0c, regvalue, cur_col, wrap));
  216. }
  217. static ahc_reg_parse_entry_t SSTAT1_parse_table[] = {
  218. { "REQINIT", 0x01, 0x01 },
  219. { "PHASECHG", 0x02, 0x02 },
  220. { "SCSIPERR", 0x04, 0x04 },
  221. { "BUSFREE", 0x08, 0x08 },
  222. { "PHASEMIS", 0x10, 0x10 },
  223. { "SCSIRSTI", 0x20, 0x20 },
  224. { "ATNTARG", 0x40, 0x40 },
  225. { "SELTO", 0x80, 0x80 }
  226. };
  227. int
  228. ahc_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  229. {
  230. return (ahc_print_register(SSTAT1_parse_table, 8, "SSTAT1",
  231. 0x0c, regvalue, cur_col, wrap));
  232. }
  233. static ahc_reg_parse_entry_t SSTAT2_parse_table[] = {
  234. { "DUAL_EDGE_ERR", 0x01, 0x01 },
  235. { "CRCREQERR", 0x02, 0x02 },
  236. { "CRCENDERR", 0x04, 0x04 },
  237. { "CRCVALERR", 0x08, 0x08 },
  238. { "EXP_ACTIVE", 0x10, 0x10 },
  239. { "SHVALID", 0x40, 0x40 },
  240. { "OVERRUN", 0x80, 0x80 },
  241. { "SFCNT", 0x1f, 0x1f }
  242. };
  243. int
  244. ahc_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  245. {
  246. return (ahc_print_register(SSTAT2_parse_table, 8, "SSTAT2",
  247. 0x0d, regvalue, cur_col, wrap));
  248. }
  249. static ahc_reg_parse_entry_t SSTAT3_parse_table[] = {
  250. { "OFFCNT", 0x0f, 0x0f },
  251. { "U2OFFCNT", 0x7f, 0x7f },
  252. { "SCSICNT", 0xf0, 0xf0 }
  253. };
  254. int
  255. ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
  256. {
  257. return (ahc_print_register(SSTAT3_parse_table, 3, "SSTAT3",
  258. 0x0e, regvalue, cur_col, wrap));
  259. }
  260. static ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = {
  261. { "OID", 0x0f, 0x0f },
  262. { "TID", 0xf0, 0xf0 }
  263. };
  264. int
  265. ahc_scsiid_ultra2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  266. {
  267. return (ahc_print_register(SCSIID_ULTRA2_parse_table, 2, "SCSIID_ULTRA2",
  268. 0x0f, regvalue, cur_col, wrap));
  269. }
  270. static ahc_reg_parse_entry_t SIMODE0_parse_table[] = {
  271. { "ENDMADONE", 0x01, 0x01 },
  272. { "ENSPIORDY", 0x02, 0x02 },
  273. { "ENSDONE", 0x04, 0x04 },
  274. { "ENSWRAP", 0x08, 0x08 },
  275. { "ENIOERR", 0x08, 0x08 },
  276. { "ENSELINGO", 0x10, 0x10 },
  277. { "ENSELDI", 0x20, 0x20 },
  278. { "ENSELDO", 0x40, 0x40 }
  279. };
  280. int
  281. ahc_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  282. {
  283. return (ahc_print_register(SIMODE0_parse_table, 8, "SIMODE0",
  284. 0x10, regvalue, cur_col, wrap));
  285. }
  286. static ahc_reg_parse_entry_t SIMODE1_parse_table[] = {
  287. { "ENREQINIT", 0x01, 0x01 },
  288. { "ENPHASECHG", 0x02, 0x02 },
  289. { "ENSCSIPERR", 0x04, 0x04 },
  290. { "ENBUSFREE", 0x08, 0x08 },
  291. { "ENPHASEMIS", 0x10, 0x10 },
  292. { "ENSCSIRST", 0x20, 0x20 },
  293. { "ENATNTARG", 0x40, 0x40 },
  294. { "ENSELTIMO", 0x80, 0x80 }
  295. };
  296. int
  297. ahc_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  298. {
  299. return (ahc_print_register(SIMODE1_parse_table, 8, "SIMODE1",
  300. 0x11, regvalue, cur_col, wrap));
  301. }
  302. int
  303. ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  304. {
  305. return (ahc_print_register(NULL, 0, "SCSIBUSL",
  306. 0x12, regvalue, cur_col, wrap));
  307. }
  308. int
  309. ahc_scsibush_print(u_int regvalue, u_int *cur_col, u_int wrap)
  310. {
  311. return (ahc_print_register(NULL, 0, "SCSIBUSH",
  312. 0x13, regvalue, cur_col, wrap));
  313. }
  314. static ahc_reg_parse_entry_t SXFRCTL2_parse_table[] = {
  315. { "CMDDMAEN", 0x08, 0x08 },
  316. { "AUTORSTDIS", 0x10, 0x10 },
  317. { "ASYNC_SETUP", 0x07, 0x07 }
  318. };
  319. int
  320. ahc_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  321. {
  322. return (ahc_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2",
  323. 0x13, regvalue, cur_col, wrap));
  324. }
  325. int
  326. ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  327. {
  328. return (ahc_print_register(NULL, 0, "SHADDR",
  329. 0x14, regvalue, cur_col, wrap));
  330. }
  331. static ahc_reg_parse_entry_t SELTIMER_parse_table[] = {
  332. { "STAGE1", 0x01, 0x01 },
  333. { "STAGE2", 0x02, 0x02 },
  334. { "STAGE3", 0x04, 0x04 },
  335. { "STAGE4", 0x08, 0x08 },
  336. { "STAGE5", 0x10, 0x10 },
  337. { "STAGE6", 0x20, 0x20 }
  338. };
  339. int
  340. ahc_seltimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
  341. {
  342. return (ahc_print_register(SELTIMER_parse_table, 6, "SELTIMER",
  343. 0x18, regvalue, cur_col, wrap));
  344. }
  345. static ahc_reg_parse_entry_t SELID_parse_table[] = {
  346. { "ONEBIT", 0x08, 0x08 },
  347. { "SELID_MASK", 0xf0, 0xf0 }
  348. };
  349. int
  350. ahc_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  351. {
  352. return (ahc_print_register(SELID_parse_table, 2, "SELID",
  353. 0x19, regvalue, cur_col, wrap));
  354. }
  355. static ahc_reg_parse_entry_t SCAMCTL_parse_table[] = {
  356. { "DFLTTID", 0x10, 0x10 },
  357. { "ALTSTIM", 0x20, 0x20 },
  358. { "CLRSCAMSELID", 0x40, 0x40 },
  359. { "ENSCAMSELO", 0x80, 0x80 },
  360. { "SCAMLVL", 0x03, 0x03 }
  361. };
  362. int
  363. ahc_scamctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  364. {
  365. return (ahc_print_register(SCAMCTL_parse_table, 5, "SCAMCTL",
  366. 0x1a, regvalue, cur_col, wrap));
  367. }
  368. int
  369. ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  370. {
  371. return (ahc_print_register(NULL, 0, "TARGID",
  372. 0x1b, regvalue, cur_col, wrap));
  373. }
  374. static ahc_reg_parse_entry_t SPIOCAP_parse_table[] = {
  375. { "SSPIOCPS", 0x01, 0x01 },
  376. { "ROM", 0x02, 0x02 },
  377. { "EEPROM", 0x04, 0x04 },
  378. { "SEEPROM", 0x08, 0x08 },
  379. { "EXT_BRDCTL", 0x10, 0x10 },
  380. { "SOFTCMDEN", 0x20, 0x20 },
  381. { "SOFT0", 0x40, 0x40 },
  382. { "SOFT1", 0x80, 0x80 }
  383. };
  384. int
  385. ahc_spiocap_print(u_int regvalue, u_int *cur_col, u_int wrap)
  386. {
  387. return (ahc_print_register(SPIOCAP_parse_table, 8, "SPIOCAP",
  388. 0x1b, regvalue, cur_col, wrap));
  389. }
  390. static ahc_reg_parse_entry_t BRDCTL_parse_table[] = {
  391. { "BRDCTL0", 0x01, 0x01 },
  392. { "BRDSTB_ULTRA2", 0x01, 0x01 },
  393. { "BRDCTL1", 0x02, 0x02 },
  394. { "BRDRW_ULTRA2", 0x02, 0x02 },
  395. { "BRDRW", 0x04, 0x04 },
  396. { "BRDDAT2", 0x04, 0x04 },
  397. { "BRDCS", 0x08, 0x08 },
  398. { "BRDDAT3", 0x08, 0x08 },
  399. { "BRDSTB", 0x10, 0x10 },
  400. { "BRDDAT4", 0x10, 0x10 },
  401. { "BRDDAT5", 0x20, 0x20 },
  402. { "BRDDAT6", 0x40, 0x40 },
  403. { "BRDDAT7", 0x80, 0x80 }
  404. };
  405. int
  406. ahc_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  407. {
  408. return (ahc_print_register(BRDCTL_parse_table, 13, "BRDCTL",
  409. 0x1d, regvalue, cur_col, wrap));
  410. }
  411. static ahc_reg_parse_entry_t SEECTL_parse_table[] = {
  412. { "SEEDI", 0x01, 0x01 },
  413. { "SEEDO", 0x02, 0x02 },
  414. { "SEECK", 0x04, 0x04 },
  415. { "SEECS", 0x08, 0x08 },
  416. { "SEERDY", 0x10, 0x10 },
  417. { "SEEMS", 0x20, 0x20 },
  418. { "EXTARBREQ", 0x40, 0x40 },
  419. { "EXTARBACK", 0x80, 0x80 }
  420. };
  421. int
  422. ahc_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  423. {
  424. return (ahc_print_register(SEECTL_parse_table, 8, "SEECTL",
  425. 0x1e, regvalue, cur_col, wrap));
  426. }
  427. static ahc_reg_parse_entry_t SBLKCTL_parse_table[] = {
  428. { "XCVR", 0x01, 0x01 },
  429. { "SELWIDE", 0x02, 0x02 },
  430. { "ENAB20", 0x04, 0x04 },
  431. { "SELBUSB", 0x08, 0x08 },
  432. { "ENAB40", 0x08, 0x08 },
  433. { "AUTOFLUSHDIS", 0x20, 0x20 },
  434. { "DIAGLEDON", 0x40, 0x40 },
  435. { "DIAGLEDEN", 0x80, 0x80 }
  436. };
  437. int
  438. ahc_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  439. {
  440. return (ahc_print_register(SBLKCTL_parse_table, 8, "SBLKCTL",
  441. 0x1f, regvalue, cur_col, wrap));
  442. }
  443. int
  444. ahc_busy_targets_print(u_int regvalue, u_int *cur_col, u_int wrap)
  445. {
  446. return (ahc_print_register(NULL, 0, "BUSY_TARGETS",
  447. 0x20, regvalue, cur_col, wrap));
  448. }
  449. int
  450. ahc_ultra_enb_print(u_int regvalue, u_int *cur_col, u_int wrap)
  451. {
  452. return (ahc_print_register(NULL, 0, "ULTRA_ENB",
  453. 0x30, regvalue, cur_col, wrap));
  454. }
  455. int
  456. ahc_disc_dsb_print(u_int regvalue, u_int *cur_col, u_int wrap)
  457. {
  458. return (ahc_print_register(NULL, 0, "DISC_DSB",
  459. 0x32, regvalue, cur_col, wrap));
  460. }
  461. int
  462. ahc_cmdsize_table_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
  463. {
  464. return (ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL",
  465. 0x34, regvalue, cur_col, wrap));
  466. }
  467. int
  468. ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap)
  469. {
  470. return (ahc_print_register(NULL, 0, "MWI_RESIDUAL",
  471. 0x38, regvalue, cur_col, wrap));
  472. }
  473. int
  474. ahc_next_queued_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
  475. {
  476. return (ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB",
  477. 0x39, regvalue, cur_col, wrap));
  478. }
  479. int
  480. ahc_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
  481. {
  482. return (ahc_print_register(NULL, 0, "MSG_OUT",
  483. 0x3a, regvalue, cur_col, wrap));
  484. }
  485. static ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = {
  486. { "FIFORESET", 0x01, 0x01 },
  487. { "FIFOFLUSH", 0x02, 0x02 },
  488. { "DIRECTION", 0x04, 0x04 },
  489. { "HDMAEN", 0x08, 0x08 },
  490. { "HDMAENACK", 0x08, 0x08 },
  491. { "SDMAEN", 0x10, 0x10 },
  492. { "SDMAENACK", 0x10, 0x10 },
  493. { "SCSIEN", 0x20, 0x20 },
  494. { "WIDEODD", 0x40, 0x40 },
  495. { "PRELOADEN", 0x80, 0x80 }
  496. };
  497. int
  498. ahc_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
  499. {
  500. return (ahc_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
  501. 0x3b, regvalue, cur_col, wrap));
  502. }
  503. static ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
  504. { "NO_DISCONNECT", 0x01, 0x01 },
  505. { "SPHASE_PENDING", 0x02, 0x02 },
  506. { "DPHASE_PENDING", 0x04, 0x04 },
  507. { "CMDPHASE_PENDING", 0x08, 0x08 },
  508. { "TARG_CMD_PENDING", 0x10, 0x10 },
  509. { "DPHASE", 0x20, 0x20 },
  510. { "NO_CDB_SENT", 0x40, 0x40 },
  511. { "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
  512. { "NOT_IDENTIFIED", 0x80, 0x80 }
  513. };
  514. int
  515. ahc_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
  516. {
  517. return (ahc_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
  518. 0x3c, regvalue, cur_col, wrap));
  519. }
  520. int
  521. ahc_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  522. {
  523. return (ahc_print_register(NULL, 0, "SAVED_SCSIID",
  524. 0x3d, regvalue, cur_col, wrap));
  525. }
  526. int
  527. ahc_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
  528. {
  529. return (ahc_print_register(NULL, 0, "SAVED_LUN",
  530. 0x3e, regvalue, cur_col, wrap));
  531. }
  532. static ahc_reg_parse_entry_t LASTPHASE_parse_table[] = {
  533. { "MSGI", 0x20, 0x20 },
  534. { "IOI", 0x40, 0x40 },
  535. { "CDI", 0x80, 0x80 },
  536. { "P_DATAOUT", 0x00, 0x00 },
  537. { "P_BUSFREE", 0x01, 0x01 },
  538. { "P_DATAIN", 0x40, 0x40 },
  539. { "P_COMMAND", 0x80, 0x80 },
  540. { "P_MESGOUT", 0xa0, 0xa0 },
  541. { "P_STATUS", 0xc0, 0xc0 },
  542. { "PHASE_MASK", 0xe0, 0xe0 },
  543. { "P_MESGIN", 0xe0, 0xe0 }
  544. };
  545. int
  546. ahc_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
  547. {
  548. return (ahc_print_register(LASTPHASE_parse_table, 11, "LASTPHASE",
  549. 0x3f, regvalue, cur_col, wrap));
  550. }
  551. int
  552. ahc_waiting_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
  553. {
  554. return (ahc_print_register(NULL, 0, "WAITING_SCBH",
  555. 0x40, regvalue, cur_col, wrap));
  556. }
  557. int
  558. ahc_disconnected_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
  559. {
  560. return (ahc_print_register(NULL, 0, "DISCONNECTED_SCBH",
  561. 0x41, regvalue, cur_col, wrap));
  562. }
  563. int
  564. ahc_free_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
  565. {
  566. return (ahc_print_register(NULL, 0, "FREE_SCBH",
  567. 0x42, regvalue, cur_col, wrap));
  568. }
  569. int
  570. ahc_complete_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
  571. {
  572. return (ahc_print_register(NULL, 0, "COMPLETE_SCBH",
  573. 0x43, regvalue, cur_col, wrap));
  574. }
  575. int
  576. ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  577. {
  578. return (ahc_print_register(NULL, 0, "HSCB_ADDR",
  579. 0x44, regvalue, cur_col, wrap));
  580. }
  581. int
  582. ahc_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  583. {
  584. return (ahc_print_register(NULL, 0, "SHARED_DATA_ADDR",
  585. 0x48, regvalue, cur_col, wrap));
  586. }
  587. int
  588. ahc_kernel_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
  589. {
  590. return (ahc_print_register(NULL, 0, "KERNEL_QINPOS",
  591. 0x4c, regvalue, cur_col, wrap));
  592. }
  593. int
  594. ahc_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
  595. {
  596. return (ahc_print_register(NULL, 0, "QINPOS",
  597. 0x4d, regvalue, cur_col, wrap));
  598. }
  599. int
  600. ahc_qoutpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
  601. {
  602. return (ahc_print_register(NULL, 0, "QOUTPOS",
  603. 0x4e, regvalue, cur_col, wrap));
  604. }
  605. int
  606. ahc_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
  607. {
  608. return (ahc_print_register(NULL, 0, "KERNEL_TQINPOS",
  609. 0x4f, regvalue, cur_col, wrap));
  610. }
  611. int
  612. ahc_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
  613. {
  614. return (ahc_print_register(NULL, 0, "TQINPOS",
  615. 0x50, regvalue, cur_col, wrap));
  616. }
  617. static ahc_reg_parse_entry_t ARG_1_parse_table[] = {
  618. { "CONT_TARG_SESSION", 0x02, 0x02 },
  619. { "CONT_MSG_LOOP", 0x04, 0x04 },
  620. { "EXIT_MSG_LOOP", 0x08, 0x08 },
  621. { "MSGOUT_PHASEMIS", 0x10, 0x10 },
  622. { "SEND_REJ", 0x20, 0x20 },
  623. { "SEND_SENSE", 0x40, 0x40 },
  624. { "SEND_MSG", 0x80, 0x80 }
  625. };
  626. int
  627. ahc_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  628. {
  629. return (ahc_print_register(ARG_1_parse_table, 7, "ARG_1",
  630. 0x51, regvalue, cur_col, wrap));
  631. }
  632. int
  633. ahc_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  634. {
  635. return (ahc_print_register(NULL, 0, "ARG_2",
  636. 0x52, regvalue, cur_col, wrap));
  637. }
  638. int
  639. ahc_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
  640. {
  641. return (ahc_print_register(NULL, 0, "LAST_MSG",
  642. 0x53, regvalue, cur_col, wrap));
  643. }
  644. static ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
  645. { "ENAUTOATNP", 0x02, 0x02 },
  646. { "ENAUTOATNI", 0x04, 0x04 },
  647. { "ENAUTOATNO", 0x08, 0x08 },
  648. { "ENRSELI", 0x10, 0x10 },
  649. { "ENSELI", 0x20, 0x20 },
  650. { "ENSELO", 0x40, 0x40 }
  651. };
  652. int
  653. ahc_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
  654. {
  655. return (ahc_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
  656. 0x54, regvalue, cur_col, wrap));
  657. }
  658. static ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = {
  659. { "HA_274_EXTENDED_TRANS",0x01, 0x01 }
  660. };
  661. int
  662. ahc_ha_274_biosglobal_print(u_int regvalue, u_int *cur_col, u_int wrap)
  663. {
  664. return (ahc_print_register(HA_274_BIOSGLOBAL_parse_table, 1, "HA_274_BIOSGLOBAL",
  665. 0x56, regvalue, cur_col, wrap));
  666. }
  667. static ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
  668. { "SCB_DMA", 0x01, 0x01 },
  669. { "TARGET_MSG_PENDING", 0x02, 0x02 }
  670. };
  671. int
  672. ahc_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  673. {
  674. return (ahc_print_register(SEQ_FLAGS2_parse_table, 2, "SEQ_FLAGS2",
  675. 0x57, regvalue, cur_col, wrap));
  676. }
  677. static ahc_reg_parse_entry_t SCSICONF_parse_table[] = {
  678. { "ENSPCHK", 0x20, 0x20 },
  679. { "RESET_SCSI", 0x40, 0x40 },
  680. { "TERM_ENB", 0x80, 0x80 },
  681. { "HSCSIID", 0x07, 0x07 },
  682. { "HWSCSIID", 0x0f, 0x0f }
  683. };
  684. int
  685. ahc_scsiconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
  686. {
  687. return (ahc_print_register(SCSICONF_parse_table, 5, "SCSICONF",
  688. 0x5a, regvalue, cur_col, wrap));
  689. }
  690. static ahc_reg_parse_entry_t INTDEF_parse_table[] = {
  691. { "EDGE_TRIG", 0x80, 0x80 },
  692. { "VECTOR", 0x0f, 0x0f }
  693. };
  694. int
  695. ahc_intdef_print(u_int regvalue, u_int *cur_col, u_int wrap)
  696. {
  697. return (ahc_print_register(INTDEF_parse_table, 2, "INTDEF",
  698. 0x5c, regvalue, cur_col, wrap));
  699. }
  700. int
  701. ahc_hostconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
  702. {
  703. return (ahc_print_register(NULL, 0, "HOSTCONF",
  704. 0x5d, regvalue, cur_col, wrap));
  705. }
  706. static ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = {
  707. { "CHANNEL_B_PRIMARY", 0x08, 0x08 },
  708. { "BIOSMODE", 0x30, 0x30 },
  709. { "BIOSDISABLED", 0x30, 0x30 }
  710. };
  711. int
  712. ahc_ha_274_biosctrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  713. {
  714. return (ahc_print_register(HA_274_BIOSCTRL_parse_table, 3, "HA_274_BIOSCTRL",
  715. 0x5f, regvalue, cur_col, wrap));
  716. }
  717. static ahc_reg_parse_entry_t SEQCTL_parse_table[] = {
  718. { "LOADRAM", 0x01, 0x01 },
  719. { "SEQRESET", 0x02, 0x02 },
  720. { "STEP", 0x04, 0x04 },
  721. { "BRKADRINTEN", 0x08, 0x08 },
  722. { "FASTMODE", 0x10, 0x10 },
  723. { "FAILDIS", 0x20, 0x20 },
  724. { "PAUSEDIS", 0x40, 0x40 },
  725. { "PERRORDIS", 0x80, 0x80 }
  726. };
  727. int
  728. ahc_seqctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  729. {
  730. return (ahc_print_register(SEQCTL_parse_table, 8, "SEQCTL",
  731. 0x60, regvalue, cur_col, wrap));
  732. }
  733. int
  734. ahc_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap)
  735. {
  736. return (ahc_print_register(NULL, 0, "SEQRAM",
  737. 0x61, regvalue, cur_col, wrap));
  738. }
  739. int
  740. ahc_seqaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  741. {
  742. return (ahc_print_register(NULL, 0, "SEQADDR0",
  743. 0x62, regvalue, cur_col, wrap));
  744. }
  745. static ahc_reg_parse_entry_t SEQADDR1_parse_table[] = {
  746. { "SEQADDR1_MASK", 0x01, 0x01 }
  747. };
  748. int
  749. ahc_seqaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  750. {
  751. return (ahc_print_register(SEQADDR1_parse_table, 1, "SEQADDR1",
  752. 0x63, regvalue, cur_col, wrap));
  753. }
  754. int
  755. ahc_accum_print(u_int regvalue, u_int *cur_col, u_int wrap)
  756. {
  757. return (ahc_print_register(NULL, 0, "ACCUM",
  758. 0x64, regvalue, cur_col, wrap));
  759. }
  760. int
  761. ahc_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
  762. {
  763. return (ahc_print_register(NULL, 0, "SINDEX",
  764. 0x65, regvalue, cur_col, wrap));
  765. }
  766. int
  767. ahc_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
  768. {
  769. return (ahc_print_register(NULL, 0, "DINDEX",
  770. 0x66, regvalue, cur_col, wrap));
  771. }
  772. int
  773. ahc_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
  774. {
  775. return (ahc_print_register(NULL, 0, "ALLONES",
  776. 0x69, regvalue, cur_col, wrap));
  777. }
  778. int
  779. ahc_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap)
  780. {
  781. return (ahc_print_register(NULL, 0, "ALLZEROS",
  782. 0x6a, regvalue, cur_col, wrap));
  783. }
  784. int
  785. ahc_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
  786. {
  787. return (ahc_print_register(NULL, 0, "NONE",
  788. 0x6a, regvalue, cur_col, wrap));
  789. }
  790. static ahc_reg_parse_entry_t FLAGS_parse_table[] = {
  791. { "CARRY", 0x01, 0x01 },
  792. { "ZERO", 0x02, 0x02 }
  793. };
  794. int
  795. ahc_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
  796. {
  797. return (ahc_print_register(FLAGS_parse_table, 2, "FLAGS",
  798. 0x6b, regvalue, cur_col, wrap));
  799. }
  800. int
  801. ahc_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
  802. {
  803. return (ahc_print_register(NULL, 0, "SINDIR",
  804. 0x6c, regvalue, cur_col, wrap));
  805. }
  806. int
  807. ahc_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
  808. {
  809. return (ahc_print_register(NULL, 0, "DINDIR",
  810. 0x6d, regvalue, cur_col, wrap));
  811. }
  812. int
  813. ahc_function1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  814. {
  815. return (ahc_print_register(NULL, 0, "FUNCTION1",
  816. 0x6e, regvalue, cur_col, wrap));
  817. }
  818. int
  819. ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
  820. {
  821. return (ahc_print_register(NULL, 0, "STACK",
  822. 0x6f, regvalue, cur_col, wrap));
  823. }
  824. int
  825. ahc_targ_offset_print(u_int regvalue, u_int *cur_col, u_int wrap)
  826. {
  827. return (ahc_print_register(NULL, 0, "TARG_OFFSET",
  828. 0x70, regvalue, cur_col, wrap));
  829. }
  830. int
  831. ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
  832. {
  833. return (ahc_print_register(NULL, 0, "SRAM_BASE",
  834. 0x70, regvalue, cur_col, wrap));
  835. }
  836. static ahc_reg_parse_entry_t BCTL_parse_table[] = {
  837. { "ENABLE", 0x01, 0x01 },
  838. { "ACE", 0x08, 0x08 }
  839. };
  840. int
  841. ahc_bctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  842. {
  843. return (ahc_print_register(BCTL_parse_table, 2, "BCTL",
  844. 0x84, regvalue, cur_col, wrap));
  845. }
  846. static ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
  847. { "CIOPARCKEN", 0x01, 0x01 },
  848. { "USCBSIZE32", 0x02, 0x02 },
  849. { "RAMPS", 0x04, 0x04 },
  850. { "INTSCBRAMSEL", 0x08, 0x08 },
  851. { "EXTREQLCK", 0x10, 0x10 },
  852. { "MPARCKEN", 0x20, 0x20 },
  853. { "DPARCKEN", 0x40, 0x40 },
  854. { "CACHETHEN", 0x80, 0x80 }
  855. };
  856. int
  857. ahc_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  858. {
  859. return (ahc_print_register(DSCOMMAND0_parse_table, 8, "DSCOMMAND0",
  860. 0x84, regvalue, cur_col, wrap));
  861. }
  862. static ahc_reg_parse_entry_t BUSTIME_parse_table[] = {
  863. { "BON", 0x0f, 0x0f },
  864. { "BOFF", 0xf0, 0xf0 }
  865. };
  866. int
  867. ahc_bustime_print(u_int regvalue, u_int *cur_col, u_int wrap)
  868. {
  869. return (ahc_print_register(BUSTIME_parse_table, 2, "BUSTIME",
  870. 0x85, regvalue, cur_col, wrap));
  871. }
  872. static ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = {
  873. { "HADDLDSEL0", 0x01, 0x01 },
  874. { "HADDLDSEL1", 0x02, 0x02 },
  875. { "DSLATT", 0xfc, 0xfc }
  876. };
  877. int
  878. ahc_dscommand1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  879. {
  880. return (ahc_print_register(DSCOMMAND1_parse_table, 3, "DSCOMMAND1",
  881. 0x85, regvalue, cur_col, wrap));
  882. }
  883. static ahc_reg_parse_entry_t BUSSPD_parse_table[] = {
  884. { "STBON", 0x07, 0x07 },
  885. { "STBOFF", 0x38, 0x38 },
  886. { "DFTHRSH_75", 0x80, 0x80 },
  887. { "DFTHRSH", 0xc0, 0xc0 },
  888. { "DFTHRSH_100", 0xc0, 0xc0 }
  889. };
  890. int
  891. ahc_busspd_print(u_int regvalue, u_int *cur_col, u_int wrap)
  892. {
  893. return (ahc_print_register(BUSSPD_parse_table, 5, "BUSSPD",
  894. 0x86, regvalue, cur_col, wrap));
  895. }
  896. static ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
  897. { "SEQ_MAILBOX", 0x0f, 0x0f },
  898. { "HOST_TQINPOS", 0x80, 0x80 },
  899. { "HOST_MAILBOX", 0xf0, 0xf0 }
  900. };
  901. int
  902. ahc_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
  903. {
  904. return (ahc_print_register(HS_MAILBOX_parse_table, 3, "HS_MAILBOX",
  905. 0x86, regvalue, cur_col, wrap));
  906. }
  907. static ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = {
  908. { "DFTHRSH_100", 0xc0, 0xc0 }
  909. };
  910. int
  911. ahc_dspcistatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
  912. {
  913. return (ahc_print_register(DSPCISTATUS_parse_table, 1, "DSPCISTATUS",
  914. 0x86, regvalue, cur_col, wrap));
  915. }
  916. static ahc_reg_parse_entry_t HCNTRL_parse_table[] = {
  917. { "CHIPRST", 0x01, 0x01 },
  918. { "CHIPRSTACK", 0x01, 0x01 },
  919. { "INTEN", 0x02, 0x02 },
  920. { "PAUSE", 0x04, 0x04 },
  921. { "IRQMS", 0x08, 0x08 },
  922. { "SWINT", 0x10, 0x10 },
  923. { "POWRDN", 0x40, 0x40 }
  924. };
  925. int
  926. ahc_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  927. {
  928. return (ahc_print_register(HCNTRL_parse_table, 7, "HCNTRL",
  929. 0x87, regvalue, cur_col, wrap));
  930. }
  931. int
  932. ahc_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  933. {
  934. return (ahc_print_register(NULL, 0, "HADDR",
  935. 0x88, regvalue, cur_col, wrap));
  936. }
  937. int
  938. ahc_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  939. {
  940. return (ahc_print_register(NULL, 0, "HCNT",
  941. 0x8c, regvalue, cur_col, wrap));
  942. }
  943. int
  944. ahc_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  945. {
  946. return (ahc_print_register(NULL, 0, "SCBPTR",
  947. 0x90, regvalue, cur_col, wrap));
  948. }
  949. static ahc_reg_parse_entry_t INTSTAT_parse_table[] = {
  950. { "SEQINT", 0x01, 0x01 },
  951. { "CMDCMPLT", 0x02, 0x02 },
  952. { "SCSIINT", 0x04, 0x04 },
  953. { "BRKADRINT", 0x08, 0x08 },
  954. { "BAD_PHASE", 0x01, 0x01 },
  955. { "INT_PEND", 0x0f, 0x0f },
  956. { "SEND_REJECT", 0x11, 0x11 },
  957. { "PROTO_VIOLATION", 0x21, 0x21 },
  958. { "NO_MATCH", 0x31, 0x31 },
  959. { "IGN_WIDE_RES", 0x41, 0x41 },
  960. { "PDATA_REINIT", 0x51, 0x51 },
  961. { "HOST_MSG_LOOP", 0x61, 0x61 },
  962. { "BAD_STATUS", 0x71, 0x71 },
  963. { "PERR_DETECTED", 0x81, 0x81 },
  964. { "DATA_OVERRUN", 0x91, 0x91 },
  965. { "MKMSG_FAILED", 0xa1, 0xa1 },
  966. { "MISSED_BUSFREE", 0xb1, 0xb1 },
  967. { "SCB_MISMATCH", 0xc1, 0xc1 },
  968. { "NO_FREE_SCB", 0xd1, 0xd1 },
  969. { "OUT_OF_RANGE", 0xe1, 0xe1 },
  970. { "SEQINT_MASK", 0xf1, 0xf1 }
  971. };
  972. int
  973. ahc_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  974. {
  975. return (ahc_print_register(INTSTAT_parse_table, 21, "INTSTAT",
  976. 0x91, regvalue, cur_col, wrap));
  977. }
  978. static ahc_reg_parse_entry_t CLRINT_parse_table[] = {
  979. { "CLRSEQINT", 0x01, 0x01 },
  980. { "CLRCMDINT", 0x02, 0x02 },
  981. { "CLRSCSIINT", 0x04, 0x04 },
  982. { "CLRBRKADRINT", 0x08, 0x08 },
  983. { "CLRPARERR", 0x10, 0x10 }
  984. };
  985. int
  986. ahc_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
  987. {
  988. return (ahc_print_register(CLRINT_parse_table, 5, "CLRINT",
  989. 0x92, regvalue, cur_col, wrap));
  990. }
  991. static ahc_reg_parse_entry_t ERROR_parse_table[] = {
  992. { "ILLHADDR", 0x01, 0x01 },
  993. { "ILLSADDR", 0x02, 0x02 },
  994. { "ILLOPCODE", 0x04, 0x04 },
  995. { "SQPARERR", 0x08, 0x08 },
  996. { "DPARERR", 0x10, 0x10 },
  997. { "MPARERR", 0x20, 0x20 },
  998. { "PCIERRSTAT", 0x40, 0x40 },
  999. { "CIOPARERR", 0x80, 0x80 }
  1000. };
  1001. int
  1002. ahc_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1003. {
  1004. return (ahc_print_register(ERROR_parse_table, 8, "ERROR",
  1005. 0x92, regvalue, cur_col, wrap));
  1006. }
  1007. static ahc_reg_parse_entry_t DFCNTRL_parse_table[] = {
  1008. { "FIFORESET", 0x01, 0x01 },
  1009. { "FIFOFLUSH", 0x02, 0x02 },
  1010. { "DIRECTION", 0x04, 0x04 },
  1011. { "HDMAEN", 0x08, 0x08 },
  1012. { "HDMAENACK", 0x08, 0x08 },
  1013. { "SDMAEN", 0x10, 0x10 },
  1014. { "SDMAENACK", 0x10, 0x10 },
  1015. { "SCSIEN", 0x20, 0x20 },
  1016. { "WIDEODD", 0x40, 0x40 },
  1017. { "PRELOADEN", 0x80, 0x80 }
  1018. };
  1019. int
  1020. ahc_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1021. {
  1022. return (ahc_print_register(DFCNTRL_parse_table, 10, "DFCNTRL",
  1023. 0x93, regvalue, cur_col, wrap));
  1024. }
  1025. static ahc_reg_parse_entry_t DFSTATUS_parse_table[] = {
  1026. { "FIFOEMP", 0x01, 0x01 },
  1027. { "FIFOFULL", 0x02, 0x02 },
  1028. { "DFTHRESH", 0x04, 0x04 },
  1029. { "HDONE", 0x08, 0x08 },
  1030. { "MREQPEND", 0x10, 0x10 },
  1031. { "FIFOQWDEMP", 0x20, 0x20 },
  1032. { "DFCACHETH", 0x40, 0x40 },
  1033. { "PRELOAD_AVAIL", 0x80, 0x80 }
  1034. };
  1035. int
  1036. ahc_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1037. {
  1038. return (ahc_print_register(DFSTATUS_parse_table, 8, "DFSTATUS",
  1039. 0x94, regvalue, cur_col, wrap));
  1040. }
  1041. int
  1042. ahc_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1043. {
  1044. return (ahc_print_register(NULL, 0, "DFWADDR",
  1045. 0x95, regvalue, cur_col, wrap));
  1046. }
  1047. int
  1048. ahc_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1049. {
  1050. return (ahc_print_register(NULL, 0, "DFRADDR",
  1051. 0x97, regvalue, cur_col, wrap));
  1052. }
  1053. int
  1054. ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1055. {
  1056. return (ahc_print_register(NULL, 0, "DFDAT",
  1057. 0x99, regvalue, cur_col, wrap));
  1058. }
  1059. static ahc_reg_parse_entry_t SCBCNT_parse_table[] = {
  1060. { "SCBAUTO", 0x80, 0x80 },
  1061. { "SCBCNT_MASK", 0x1f, 0x1f }
  1062. };
  1063. int
  1064. ahc_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1065. {
  1066. return (ahc_print_register(SCBCNT_parse_table, 2, "SCBCNT",
  1067. 0x9a, regvalue, cur_col, wrap));
  1068. }
  1069. int
  1070. ahc_qinfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1071. {
  1072. return (ahc_print_register(NULL, 0, "QINFIFO",
  1073. 0x9b, regvalue, cur_col, wrap));
  1074. }
  1075. int
  1076. ahc_qincnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1077. {
  1078. return (ahc_print_register(NULL, 0, "QINCNT",
  1079. 0x9c, regvalue, cur_col, wrap));
  1080. }
  1081. int
  1082. ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1083. {
  1084. return (ahc_print_register(NULL, 0, "QOUTFIFO",
  1085. 0x9d, regvalue, cur_col, wrap));
  1086. }
  1087. static ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = {
  1088. { "TARGCRCCNTEN", 0x04, 0x04 },
  1089. { "TARGCRCENDEN", 0x08, 0x08 },
  1090. { "CRCREQCHKEN", 0x10, 0x10 },
  1091. { "CRCENDCHKEN", 0x20, 0x20 },
  1092. { "CRCVALCHKEN", 0x40, 0x40 },
  1093. { "CRCONSEEN", 0x80, 0x80 }
  1094. };
  1095. int
  1096. ahc_crccontrol1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1097. {
  1098. return (ahc_print_register(CRCCONTROL1_parse_table, 6, "CRCCONTROL1",
  1099. 0x9d, regvalue, cur_col, wrap));
  1100. }
  1101. int
  1102. ahc_qoutcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1103. {
  1104. return (ahc_print_register(NULL, 0, "QOUTCNT",
  1105. 0x9e, regvalue, cur_col, wrap));
  1106. }
  1107. static ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
  1108. { "DATA_OUT_PHASE", 0x01, 0x01 },
  1109. { "DATA_IN_PHASE", 0x02, 0x02 },
  1110. { "MSG_OUT_PHASE", 0x04, 0x04 },
  1111. { "MSG_IN_PHASE", 0x08, 0x08 },
  1112. { "COMMAND_PHASE", 0x10, 0x10 },
  1113. { "STATUS_PHASE", 0x20, 0x20 },
  1114. { "DATA_PHASE_MASK", 0x03, 0x03 }
  1115. };
  1116. int
  1117. ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1118. {
  1119. return (ahc_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
  1120. 0x9e, regvalue, cur_col, wrap));
  1121. }
  1122. static ahc_reg_parse_entry_t SFUNCT_parse_table[] = {
  1123. { "ALT_MODE", 0x80, 0x80 }
  1124. };
  1125. int
  1126. ahc_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1127. {
  1128. return (ahc_print_register(SFUNCT_parse_table, 1, "SFUNCT",
  1129. 0x9f, regvalue, cur_col, wrap));
  1130. }
  1131. int
  1132. ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1133. {
  1134. return (ahc_print_register(NULL, 0, "SCB_BASE",
  1135. 0xa0, regvalue, cur_col, wrap));
  1136. }
  1137. int
  1138. ahc_scb_cdb_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1139. {
  1140. return (ahc_print_register(NULL, 0, "SCB_CDB_PTR",
  1141. 0xa0, regvalue, cur_col, wrap));
  1142. }
  1143. int
  1144. ahc_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1145. {
  1146. return (ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR",
  1147. 0xa4, regvalue, cur_col, wrap));
  1148. }
  1149. int
  1150. ahc_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1151. {
  1152. return (ahc_print_register(NULL, 0, "SCB_SCSI_STATUS",
  1153. 0xa8, regvalue, cur_col, wrap));
  1154. }
  1155. int
  1156. ahc_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1157. {
  1158. return (ahc_print_register(NULL, 0, "SCB_TARGET_PHASES",
  1159. 0xa9, regvalue, cur_col, wrap));
  1160. }
  1161. int
  1162. ahc_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1163. {
  1164. return (ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR",
  1165. 0xaa, regvalue, cur_col, wrap));
  1166. }
  1167. int
  1168. ahc_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1169. {
  1170. return (ahc_print_register(NULL, 0, "SCB_TARGET_ITAG",
  1171. 0xab, regvalue, cur_col, wrap));
  1172. }
  1173. int
  1174. ahc_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1175. {
  1176. return (ahc_print_register(NULL, 0, "SCB_DATAPTR",
  1177. 0xac, regvalue, cur_col, wrap));
  1178. }
  1179. static ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
  1180. { "SG_LAST_SEG", 0x80, 0x80 },
  1181. { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }
  1182. };
  1183. int
  1184. ahc_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1185. {
  1186. return (ahc_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT",
  1187. 0xb0, regvalue, cur_col, wrap));
  1188. }
  1189. static ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
  1190. { "SG_LIST_NULL", 0x01, 0x01 },
  1191. { "SG_FULL_RESID", 0x02, 0x02 },
  1192. { "SG_RESID_VALID", 0x04, 0x04 }
  1193. };
  1194. int
  1195. ahc_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1196. {
  1197. return (ahc_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR",
  1198. 0xb4, regvalue, cur_col, wrap));
  1199. }
  1200. static ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
  1201. { "DISCONNECTED", 0x04, 0x04 },
  1202. { "ULTRAENB", 0x08, 0x08 },
  1203. { "MK_MESSAGE", 0x10, 0x10 },
  1204. { "TAG_ENB", 0x20, 0x20 },
  1205. { "DISCENB", 0x40, 0x40 },
  1206. { "TARGET_SCB", 0x80, 0x80 },
  1207. { "STATUS_RCVD", 0x80, 0x80 },
  1208. { "SCB_TAG_TYPE", 0x03, 0x03 }
  1209. };
  1210. int
  1211. ahc_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1212. {
  1213. return (ahc_print_register(SCB_CONTROL_parse_table, 8, "SCB_CONTROL",
  1214. 0xb8, regvalue, cur_col, wrap));
  1215. }
  1216. static ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
  1217. { "TWIN_CHNLB", 0x80, 0x80 },
  1218. { "OID", 0x0f, 0x0f },
  1219. { "TWIN_TID", 0x70, 0x70 },
  1220. { "TID", 0xf0, 0xf0 }
  1221. };
  1222. int
  1223. ahc_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1224. {
  1225. return (ahc_print_register(SCB_SCSIID_parse_table, 4, "SCB_SCSIID",
  1226. 0xb9, regvalue, cur_col, wrap));
  1227. }
  1228. static ahc_reg_parse_entry_t SCB_LUN_parse_table[] = {
  1229. { "SCB_XFERLEN_ODD", 0x80, 0x80 },
  1230. { "LID", 0x3f, 0x3f }
  1231. };
  1232. int
  1233. ahc_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1234. {
  1235. return (ahc_print_register(SCB_LUN_parse_table, 2, "SCB_LUN",
  1236. 0xba, regvalue, cur_col, wrap));
  1237. }
  1238. int
  1239. ahc_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1240. {
  1241. return (ahc_print_register(NULL, 0, "SCB_TAG",
  1242. 0xbb, regvalue, cur_col, wrap));
  1243. }
  1244. int
  1245. ahc_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1246. {
  1247. return (ahc_print_register(NULL, 0, "SCB_CDB_LEN",
  1248. 0xbc, regvalue, cur_col, wrap));
  1249. }
  1250. int
  1251. ahc_scb_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1252. {
  1253. return (ahc_print_register(NULL, 0, "SCB_SCSIRATE",
  1254. 0xbd, regvalue, cur_col, wrap));
  1255. }
  1256. int
  1257. ahc_scb_scsioffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1258. {
  1259. return (ahc_print_register(NULL, 0, "SCB_SCSIOFFSET",
  1260. 0xbe, regvalue, cur_col, wrap));
  1261. }
  1262. int
  1263. ahc_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1264. {
  1265. return (ahc_print_register(NULL, 0, "SCB_NEXT",
  1266. 0xbf, regvalue, cur_col, wrap));
  1267. }
  1268. int
  1269. ahc_scb_64_spare_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1270. {
  1271. return (ahc_print_register(NULL, 0, "SCB_64_SPARE",
  1272. 0xc0, regvalue, cur_col, wrap));
  1273. }
  1274. static ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = {
  1275. { "DO_2840", 0x01, 0x01 },
  1276. { "CK_2840", 0x02, 0x02 },
  1277. { "CS_2840", 0x04, 0x04 }
  1278. };
  1279. int
  1280. ahc_seectl_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1281. {
  1282. return (ahc_print_register(SEECTL_2840_parse_table, 3, "SEECTL_2840",
  1283. 0xc0, regvalue, cur_col, wrap));
  1284. }
  1285. static ahc_reg_parse_entry_t STATUS_2840_parse_table[] = {
  1286. { "DI_2840", 0x01, 0x01 },
  1287. { "EEPROM_TF", 0x80, 0x80 },
  1288. { "ADSEL", 0x1e, 0x1e },
  1289. { "BIOS_SEL", 0x60, 0x60 }
  1290. };
  1291. int
  1292. ahc_status_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1293. {
  1294. return (ahc_print_register(STATUS_2840_parse_table, 4, "STATUS_2840",
  1295. 0xc1, regvalue, cur_col, wrap));
  1296. }
  1297. int
  1298. ahc_scb_64_btt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1299. {
  1300. return (ahc_print_register(NULL, 0, "SCB_64_BTT",
  1301. 0xd0, regvalue, cur_col, wrap));
  1302. }
  1303. int
  1304. ahc_cchaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1305. {
  1306. return (ahc_print_register(NULL, 0, "CCHADDR",
  1307. 0xe0, regvalue, cur_col, wrap));
  1308. }
  1309. int
  1310. ahc_cchcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1311. {
  1312. return (ahc_print_register(NULL, 0, "CCHCNT",
  1313. 0xe8, regvalue, cur_col, wrap));
  1314. }
  1315. int
  1316. ahc_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1317. {
  1318. return (ahc_print_register(NULL, 0, "CCSGRAM",
  1319. 0xe9, regvalue, cur_col, wrap));
  1320. }
  1321. int
  1322. ahc_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1323. {
  1324. return (ahc_print_register(NULL, 0, "CCSGADDR",
  1325. 0xea, regvalue, cur_col, wrap));
  1326. }
  1327. static ahc_reg_parse_entry_t CCSGCTL_parse_table[] = {
  1328. { "CCSGRESET", 0x01, 0x01 },
  1329. { "SG_FETCH_NEEDED", 0x02, 0x02 },
  1330. { "CCSGEN", 0x08, 0x08 },
  1331. { "CCSGDONE", 0x80, 0x80 }
  1332. };
  1333. int
  1334. ahc_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1335. {
  1336. return (ahc_print_register(CCSGCTL_parse_table, 4, "CCSGCTL",
  1337. 0xeb, regvalue, cur_col, wrap));
  1338. }
  1339. int
  1340. ahc_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1341. {
  1342. return (ahc_print_register(NULL, 0, "CCSCBRAM",
  1343. 0xec, regvalue, cur_col, wrap));
  1344. }
  1345. int
  1346. ahc_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1347. {
  1348. return (ahc_print_register(NULL, 0, "CCSCBADDR",
  1349. 0xed, regvalue, cur_col, wrap));
  1350. }
  1351. static ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = {
  1352. { "CCSCBRESET", 0x01, 0x01 },
  1353. { "CCSCBDIR", 0x04, 0x04 },
  1354. { "CCSCBEN", 0x08, 0x08 },
  1355. { "CCARREN", 0x10, 0x10 },
  1356. { "ARRDONE", 0x40, 0x40 },
  1357. { "CCSCBDONE", 0x80, 0x80 }
  1358. };
  1359. int
  1360. ahc_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1361. {
  1362. return (ahc_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
  1363. 0xee, regvalue, cur_col, wrap));
  1364. }
  1365. int
  1366. ahc_ccscbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1367. {
  1368. return (ahc_print_register(NULL, 0, "CCSCBCNT",
  1369. 0xef, regvalue, cur_col, wrap));
  1370. }
  1371. int
  1372. ahc_scbbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1373. {
  1374. return (ahc_print_register(NULL, 0, "SCBBADDR",
  1375. 0xf0, regvalue, cur_col, wrap));
  1376. }
  1377. int
  1378. ahc_ccscbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1379. {
  1380. return (ahc_print_register(NULL, 0, "CCSCBPTR",
  1381. 0xf1, regvalue, cur_col, wrap));
  1382. }
  1383. int
  1384. ahc_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1385. {
  1386. return (ahc_print_register(NULL, 0, "HNSCB_QOFF",
  1387. 0xf4, regvalue, cur_col, wrap));
  1388. }
  1389. int
  1390. ahc_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1391. {
  1392. return (ahc_print_register(NULL, 0, "SNSCB_QOFF",
  1393. 0xf6, regvalue, cur_col, wrap));
  1394. }
  1395. int
  1396. ahc_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1397. {
  1398. return (ahc_print_register(NULL, 0, "SDSCB_QOFF",
  1399. 0xf8, regvalue, cur_col, wrap));
  1400. }
  1401. static ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
  1402. { "SDSCB_ROLLOVER", 0x10, 0x10 },
  1403. { "SNSCB_ROLLOVER", 0x20, 0x20 },
  1404. { "SCB_AVAIL", 0x40, 0x40 },
  1405. { "SCB_QSIZE_256", 0x06, 0x06 },
  1406. { "SCB_QSIZE", 0x07, 0x07 }
  1407. };
  1408. int
  1409. ahc_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1410. {
  1411. return (ahc_print_register(QOFF_CTLSTA_parse_table, 5, "QOFF_CTLSTA",
  1412. 0xfa, regvalue, cur_col, wrap));
  1413. }
  1414. static ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = {
  1415. { "RD_DFTHRSH_MIN", 0x00, 0x00 },
  1416. { "WR_DFTHRSH_MIN", 0x00, 0x00 },
  1417. { "RD_DFTHRSH_25", 0x01, 0x01 },
  1418. { "RD_DFTHRSH_50", 0x02, 0x02 },
  1419. { "RD_DFTHRSH_63", 0x03, 0x03 },
  1420. { "RD_DFTHRSH_75", 0x04, 0x04 },
  1421. { "RD_DFTHRSH_85", 0x05, 0x05 },
  1422. { "RD_DFTHRSH_90", 0x06, 0x06 },
  1423. { "RD_DFTHRSH", 0x07, 0x07 },
  1424. { "RD_DFTHRSH_MAX", 0x07, 0x07 },
  1425. { "WR_DFTHRSH_25", 0x10, 0x10 },
  1426. { "WR_DFTHRSH_50", 0x20, 0x20 },
  1427. { "WR_DFTHRSH_63", 0x30, 0x30 },
  1428. { "WR_DFTHRSH_75", 0x40, 0x40 },
  1429. { "WR_DFTHRSH_85", 0x50, 0x50 },
  1430. { "WR_DFTHRSH_90", 0x60, 0x60 },
  1431. { "WR_DFTHRSH", 0x70, 0x70 },
  1432. { "WR_DFTHRSH_MAX", 0x70, 0x70 }
  1433. };
  1434. int
  1435. ahc_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1436. {
  1437. return (ahc_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH",
  1438. 0xfb, regvalue, cur_col, wrap));
  1439. }
  1440. static ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
  1441. { "LAST_SEG_DONE", 0x01, 0x01 },
  1442. { "LAST_SEG", 0x02, 0x02 },
  1443. { "SG_ADDR_MASK", 0xf8, 0xf8 }
  1444. };
  1445. int
  1446. ahc_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1447. {
  1448. return (ahc_print_register(SG_CACHE_SHADOW_parse_table, 3, "SG_CACHE_SHADOW",
  1449. 0xfc, regvalue, cur_col, wrap));
  1450. }
  1451. static ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
  1452. { "LAST_SEG_DONE", 0x01, 0x01 },
  1453. { "LAST_SEG", 0x02, 0x02 },
  1454. { "SG_ADDR_MASK", 0xf8, 0xf8 }
  1455. };
  1456. int
  1457. ahc_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1458. {
  1459. return (ahc_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE",
  1460. 0xfc, regvalue, cur_col, wrap));
  1461. }