probe.c 26 KB

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  1. /*
  2. * probe.c - PCI detection and setup code
  3. */
  4. #include <linux/kernel.h>
  5. #include <linux/delay.h>
  6. #include <linux/init.h>
  7. #include <linux/pci.h>
  8. #include <linux/slab.h>
  9. #include <linux/module.h>
  10. #include <linux/cpumask.h>
  11. #include "pci.h"
  12. #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
  13. #define CARDBUS_RESERVE_BUSNR 3
  14. #define PCI_CFG_SPACE_SIZE 256
  15. #define PCI_CFG_SPACE_EXP_SIZE 4096
  16. /* Ugh. Need to stop exporting this to modules. */
  17. LIST_HEAD(pci_root_buses);
  18. EXPORT_SYMBOL(pci_root_buses);
  19. LIST_HEAD(pci_devices);
  20. #ifdef HAVE_PCI_LEGACY
  21. /**
  22. * pci_create_legacy_files - create legacy I/O port and memory files
  23. * @b: bus to create files under
  24. *
  25. * Some platforms allow access to legacy I/O port and ISA memory space on
  26. * a per-bus basis. This routine creates the files and ties them into
  27. * their associated read, write and mmap files from pci-sysfs.c
  28. */
  29. static void pci_create_legacy_files(struct pci_bus *b)
  30. {
  31. b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
  32. GFP_ATOMIC);
  33. if (b->legacy_io) {
  34. memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
  35. b->legacy_io->attr.name = "legacy_io";
  36. b->legacy_io->size = 0xffff;
  37. b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
  38. b->legacy_io->attr.owner = THIS_MODULE;
  39. b->legacy_io->read = pci_read_legacy_io;
  40. b->legacy_io->write = pci_write_legacy_io;
  41. class_device_create_bin_file(&b->class_dev, b->legacy_io);
  42. /* Allocated above after the legacy_io struct */
  43. b->legacy_mem = b->legacy_io + 1;
  44. b->legacy_mem->attr.name = "legacy_mem";
  45. b->legacy_mem->size = 1024*1024;
  46. b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
  47. b->legacy_mem->attr.owner = THIS_MODULE;
  48. b->legacy_mem->mmap = pci_mmap_legacy_mem;
  49. class_device_create_bin_file(&b->class_dev, b->legacy_mem);
  50. }
  51. }
  52. void pci_remove_legacy_files(struct pci_bus *b)
  53. {
  54. if (b->legacy_io) {
  55. class_device_remove_bin_file(&b->class_dev, b->legacy_io);
  56. class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
  57. kfree(b->legacy_io); /* both are allocated here */
  58. }
  59. }
  60. #else /* !HAVE_PCI_LEGACY */
  61. static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
  62. void pci_remove_legacy_files(struct pci_bus *bus) { return; }
  63. #endif /* HAVE_PCI_LEGACY */
  64. /*
  65. * PCI Bus Class Devices
  66. */
  67. static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
  68. char *buf)
  69. {
  70. int ret;
  71. cpumask_t cpumask;
  72. cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
  73. ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
  74. if (ret < PAGE_SIZE)
  75. buf[ret++] = '\n';
  76. return ret;
  77. }
  78. CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
  79. /*
  80. * PCI Bus Class
  81. */
  82. static void release_pcibus_dev(struct class_device *class_dev)
  83. {
  84. struct pci_bus *pci_bus = to_pci_bus(class_dev);
  85. if (pci_bus->bridge)
  86. put_device(pci_bus->bridge);
  87. kfree(pci_bus);
  88. }
  89. static struct class pcibus_class = {
  90. .name = "pci_bus",
  91. .release = &release_pcibus_dev,
  92. };
  93. static int __init pcibus_class_init(void)
  94. {
  95. return class_register(&pcibus_class);
  96. }
  97. postcore_initcall(pcibus_class_init);
  98. /*
  99. * Translate the low bits of the PCI base
  100. * to the resource type
  101. */
  102. static inline unsigned int pci_calc_resource_flags(unsigned int flags)
  103. {
  104. if (flags & PCI_BASE_ADDRESS_SPACE_IO)
  105. return IORESOURCE_IO;
  106. if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
  107. return IORESOURCE_MEM | IORESOURCE_PREFETCH;
  108. return IORESOURCE_MEM;
  109. }
  110. /*
  111. * Find the extent of a PCI decode..
  112. */
  113. static u32 pci_size(u32 base, u32 maxbase, u32 mask)
  114. {
  115. u32 size = mask & maxbase; /* Find the significant bits */
  116. if (!size)
  117. return 0;
  118. /* Get the lowest of them to find the decode size, and
  119. from that the extent. */
  120. size = (size & ~(size-1)) - 1;
  121. /* base == maxbase can be valid only if the BAR has
  122. already been programmed with all 1s. */
  123. if (base == maxbase && ((base | size) & mask) != mask)
  124. return 0;
  125. return size;
  126. }
  127. static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
  128. {
  129. unsigned int pos, reg, next;
  130. u32 l, sz;
  131. struct resource *res;
  132. for(pos=0; pos<howmany; pos = next) {
  133. next = pos+1;
  134. res = &dev->resource[pos];
  135. res->name = pci_name(dev);
  136. reg = PCI_BASE_ADDRESS_0 + (pos << 2);
  137. pci_read_config_dword(dev, reg, &l);
  138. pci_write_config_dword(dev, reg, ~0);
  139. pci_read_config_dword(dev, reg, &sz);
  140. pci_write_config_dword(dev, reg, l);
  141. if (!sz || sz == 0xffffffff)
  142. continue;
  143. if (l == 0xffffffff)
  144. l = 0;
  145. if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
  146. sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
  147. if (!sz)
  148. continue;
  149. res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
  150. res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
  151. } else {
  152. sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
  153. if (!sz)
  154. continue;
  155. res->start = l & PCI_BASE_ADDRESS_IO_MASK;
  156. res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
  157. }
  158. res->end = res->start + (unsigned long) sz;
  159. res->flags |= pci_calc_resource_flags(l);
  160. if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
  161. == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
  162. pci_read_config_dword(dev, reg+4, &l);
  163. next++;
  164. #if BITS_PER_LONG == 64
  165. res->start |= ((unsigned long) l) << 32;
  166. res->end = res->start + sz;
  167. pci_write_config_dword(dev, reg+4, ~0);
  168. pci_read_config_dword(dev, reg+4, &sz);
  169. pci_write_config_dword(dev, reg+4, l);
  170. sz = pci_size(l, sz, 0xffffffff);
  171. if (sz) {
  172. /* This BAR needs > 4GB? Wow. */
  173. res->end |= (unsigned long)sz<<32;
  174. }
  175. #else
  176. if (l) {
  177. printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
  178. res->start = 0;
  179. res->flags = 0;
  180. continue;
  181. }
  182. #endif
  183. }
  184. }
  185. if (rom) {
  186. dev->rom_base_reg = rom;
  187. res = &dev->resource[PCI_ROM_RESOURCE];
  188. res->name = pci_name(dev);
  189. pci_read_config_dword(dev, rom, &l);
  190. pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
  191. pci_read_config_dword(dev, rom, &sz);
  192. pci_write_config_dword(dev, rom, l);
  193. if (l == 0xffffffff)
  194. l = 0;
  195. if (sz && sz != 0xffffffff) {
  196. sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
  197. if (sz) {
  198. res->flags = (l & IORESOURCE_ROM_ENABLE) |
  199. IORESOURCE_MEM | IORESOURCE_PREFETCH |
  200. IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
  201. res->start = l & PCI_ROM_ADDRESS_MASK;
  202. res->end = res->start + (unsigned long) sz;
  203. }
  204. }
  205. }
  206. }
  207. void __devinit pci_read_bridge_bases(struct pci_bus *child)
  208. {
  209. struct pci_dev *dev = child->self;
  210. u8 io_base_lo, io_limit_lo;
  211. u16 mem_base_lo, mem_limit_lo;
  212. unsigned long base, limit;
  213. struct resource *res;
  214. int i;
  215. if (!dev) /* It's a host bus, nothing to read */
  216. return;
  217. if (dev->transparent) {
  218. printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
  219. for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
  220. child->resource[i] = child->parent->resource[i - 3];
  221. }
  222. for(i=0; i<3; i++)
  223. child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
  224. res = child->resource[0];
  225. pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
  226. pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
  227. base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
  228. limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
  229. if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
  230. u16 io_base_hi, io_limit_hi;
  231. pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
  232. pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
  233. base |= (io_base_hi << 16);
  234. limit |= (io_limit_hi << 16);
  235. }
  236. if (base <= limit) {
  237. res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
  238. res->start = base;
  239. res->end = limit + 0xfff;
  240. }
  241. res = child->resource[1];
  242. pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
  243. pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
  244. base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
  245. limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
  246. if (base <= limit) {
  247. res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
  248. res->start = base;
  249. res->end = limit + 0xfffff;
  250. }
  251. res = child->resource[2];
  252. pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
  253. pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
  254. base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
  255. limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
  256. if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
  257. u32 mem_base_hi, mem_limit_hi;
  258. pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
  259. pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
  260. /*
  261. * Some bridges set the base > limit by default, and some
  262. * (broken) BIOSes do not initialize them. If we find
  263. * this, just assume they are not being used.
  264. */
  265. if (mem_base_hi <= mem_limit_hi) {
  266. #if BITS_PER_LONG == 64
  267. base |= ((long) mem_base_hi) << 32;
  268. limit |= ((long) mem_limit_hi) << 32;
  269. #else
  270. if (mem_base_hi || mem_limit_hi) {
  271. printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
  272. return;
  273. }
  274. #endif
  275. }
  276. }
  277. if (base <= limit) {
  278. res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
  279. res->start = base;
  280. res->end = limit + 0xfffff;
  281. }
  282. }
  283. static struct pci_bus * __devinit pci_alloc_bus(void)
  284. {
  285. struct pci_bus *b;
  286. b = kmalloc(sizeof(*b), GFP_KERNEL);
  287. if (b) {
  288. memset(b, 0, sizeof(*b));
  289. INIT_LIST_HEAD(&b->node);
  290. INIT_LIST_HEAD(&b->children);
  291. INIT_LIST_HEAD(&b->devices);
  292. }
  293. return b;
  294. }
  295. static struct pci_bus * __devinit
  296. pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
  297. {
  298. struct pci_bus *child;
  299. int i;
  300. /*
  301. * Allocate a new bus, and inherit stuff from the parent..
  302. */
  303. child = pci_alloc_bus();
  304. if (!child)
  305. return NULL;
  306. child->self = bridge;
  307. child->parent = parent;
  308. child->ops = parent->ops;
  309. child->sysdata = parent->sysdata;
  310. child->bridge = get_device(&bridge->dev);
  311. child->class_dev.class = &pcibus_class;
  312. sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
  313. class_device_register(&child->class_dev);
  314. class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
  315. /*
  316. * Set up the primary, secondary and subordinate
  317. * bus numbers.
  318. */
  319. child->number = child->secondary = busnr;
  320. child->primary = parent->secondary;
  321. child->subordinate = 0xff;
  322. /* Set up default resource pointers and names.. */
  323. for (i = 0; i < 4; i++) {
  324. child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
  325. child->resource[i]->name = child->name;
  326. }
  327. bridge->subordinate = child;
  328. return child;
  329. }
  330. struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
  331. {
  332. struct pci_bus *child;
  333. child = pci_alloc_child_bus(parent, dev, busnr);
  334. if (child) {
  335. spin_lock(&pci_bus_lock);
  336. list_add_tail(&child->node, &parent->children);
  337. spin_unlock(&pci_bus_lock);
  338. }
  339. return child;
  340. }
  341. static void pci_enable_crs(struct pci_dev *dev)
  342. {
  343. u16 cap, rpctl;
  344. int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
  345. if (!rpcap)
  346. return;
  347. pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
  348. if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
  349. return;
  350. pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
  351. rpctl |= PCI_EXP_RTCTL_CRSSVE;
  352. pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
  353. }
  354. static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
  355. {
  356. struct pci_bus *parent = child->parent;
  357. while (parent->parent && parent->subordinate < max) {
  358. parent->subordinate = max;
  359. pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
  360. parent = parent->parent;
  361. }
  362. }
  363. unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
  364. /*
  365. * If it's a bridge, configure it and scan the bus behind it.
  366. * For CardBus bridges, we don't scan behind as the devices will
  367. * be handled by the bridge driver itself.
  368. *
  369. * We need to process bridges in two passes -- first we scan those
  370. * already configured by the BIOS and after we are done with all of
  371. * them, we proceed to assigning numbers to the remaining buses in
  372. * order to avoid overlaps between old and new bus numbers.
  373. */
  374. int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
  375. {
  376. struct pci_bus *child;
  377. int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
  378. u32 buses, i;
  379. u16 bctl;
  380. pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
  381. pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
  382. pci_name(dev), buses & 0xffffff, pass);
  383. /* Disable MasterAbortMode during probing to avoid reporting
  384. of bus errors (in some architectures) */
  385. pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
  386. pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
  387. bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
  388. pci_enable_crs(dev);
  389. if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
  390. unsigned int cmax, busnr;
  391. /*
  392. * Bus already configured by firmware, process it in the first
  393. * pass and just note the configuration.
  394. */
  395. if (pass)
  396. return max;
  397. busnr = (buses >> 8) & 0xFF;
  398. /*
  399. * If we already got to this bus through a different bridge,
  400. * ignore it. This can happen with the i450NX chipset.
  401. */
  402. if (pci_find_bus(pci_domain_nr(bus), busnr)) {
  403. printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
  404. pci_domain_nr(bus), busnr);
  405. return max;
  406. }
  407. child = pci_add_new_bus(bus, dev, busnr);
  408. if (!child)
  409. return max;
  410. child->primary = buses & 0xFF;
  411. child->subordinate = (buses >> 16) & 0xFF;
  412. child->bridge_ctl = bctl;
  413. cmax = pci_scan_child_bus(child);
  414. if (cmax > max)
  415. max = cmax;
  416. if (child->subordinate > max)
  417. max = child->subordinate;
  418. } else {
  419. /*
  420. * We need to assign a number to this bus which we always
  421. * do in the second pass.
  422. */
  423. if (!pass)
  424. return max;
  425. /* Clear errors */
  426. pci_write_config_word(dev, PCI_STATUS, 0xffff);
  427. /* Prevent assigning a bus number that already exists.
  428. * This can happen when a bridge is hot-plugged */
  429. if (pci_find_bus(pci_domain_nr(bus), max+1))
  430. return max;
  431. child = pci_add_new_bus(bus, dev, ++max);
  432. buses = (buses & 0xff000000)
  433. | ((unsigned int)(child->primary) << 0)
  434. | ((unsigned int)(child->secondary) << 8)
  435. | ((unsigned int)(child->subordinate) << 16);
  436. /*
  437. * yenta.c forces a secondary latency timer of 176.
  438. * Copy that behaviour here.
  439. */
  440. if (is_cardbus) {
  441. buses &= ~0xff000000;
  442. buses |= CARDBUS_LATENCY_TIMER << 24;
  443. }
  444. /*
  445. * We need to blast all three values with a single write.
  446. */
  447. pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
  448. if (!is_cardbus) {
  449. child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
  450. /*
  451. * Adjust subordinate busnr in parent buses.
  452. * We do this before scanning for children because
  453. * some devices may not be detected if the bios
  454. * was lazy.
  455. */
  456. pci_fixup_parent_subordinate_busnr(child, max);
  457. /* Now we can scan all subordinate buses... */
  458. max = pci_scan_child_bus(child);
  459. } else {
  460. /*
  461. * For CardBus bridges, we leave 4 bus numbers
  462. * as cards with a PCI-to-PCI bridge can be
  463. * inserted later.
  464. */
  465. for (i=0; i<CARDBUS_RESERVE_BUSNR; i++)
  466. if (pci_find_bus(pci_domain_nr(bus),
  467. max+i+1))
  468. break;
  469. max += i;
  470. pci_fixup_parent_subordinate_busnr(child, max);
  471. }
  472. /*
  473. * Set the subordinate bus number to its real value.
  474. */
  475. child->subordinate = max;
  476. pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
  477. }
  478. pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
  479. sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
  480. return max;
  481. }
  482. /*
  483. * Read interrupt line and base address registers.
  484. * The architecture-dependent code can tweak these, of course.
  485. */
  486. static void pci_read_irq(struct pci_dev *dev)
  487. {
  488. unsigned char irq;
  489. pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
  490. if (irq)
  491. pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
  492. dev->irq = irq;
  493. }
  494. /**
  495. * pci_setup_device - fill in class and map information of a device
  496. * @dev: the device structure to fill
  497. *
  498. * Initialize the device structure with information about the device's
  499. * vendor,class,memory and IO-space addresses,IRQ lines etc.
  500. * Called at initialisation of the PCI subsystem and by CardBus services.
  501. * Returns 0 on success and -1 if unknown type of device (not normal, bridge
  502. * or CardBus).
  503. */
  504. static int pci_setup_device(struct pci_dev * dev)
  505. {
  506. u32 class;
  507. sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
  508. dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
  509. pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
  510. class >>= 8; /* upper 3 bytes */
  511. dev->class = class;
  512. class >>= 8;
  513. pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
  514. dev->vendor, dev->device, class, dev->hdr_type);
  515. /* "Unknown power state" */
  516. dev->current_state = PCI_UNKNOWN;
  517. /* Early fixups, before probing the BARs */
  518. pci_fixup_device(pci_fixup_early, dev);
  519. class = dev->class >> 8;
  520. switch (dev->hdr_type) { /* header type */
  521. case PCI_HEADER_TYPE_NORMAL: /* standard header */
  522. if (class == PCI_CLASS_BRIDGE_PCI)
  523. goto bad;
  524. pci_read_irq(dev);
  525. pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
  526. pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
  527. pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
  528. break;
  529. case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
  530. if (class != PCI_CLASS_BRIDGE_PCI)
  531. goto bad;
  532. /* The PCI-to-PCI bridge spec requires that subtractive
  533. decoding (i.e. transparent) bridge must have programming
  534. interface code of 0x01. */
  535. dev->transparent = ((dev->class & 0xff) == 1);
  536. pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
  537. break;
  538. case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
  539. if (class != PCI_CLASS_BRIDGE_CARDBUS)
  540. goto bad;
  541. pci_read_irq(dev);
  542. pci_read_bases(dev, 1, 0);
  543. pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
  544. pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
  545. break;
  546. default: /* unknown header */
  547. printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
  548. pci_name(dev), dev->hdr_type);
  549. return -1;
  550. bad:
  551. printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
  552. pci_name(dev), class, dev->hdr_type);
  553. dev->class = PCI_CLASS_NOT_DEFINED;
  554. }
  555. /* We found a fine healthy device, go go go... */
  556. return 0;
  557. }
  558. /**
  559. * pci_release_dev - free a pci device structure when all users of it are finished.
  560. * @dev: device that's been disconnected
  561. *
  562. * Will be called only by the device core when all users of this pci device are
  563. * done.
  564. */
  565. static void pci_release_dev(struct device *dev)
  566. {
  567. struct pci_dev *pci_dev;
  568. pci_dev = to_pci_dev(dev);
  569. kfree(pci_dev);
  570. }
  571. /**
  572. * pci_cfg_space_size - get the configuration space size of the PCI device.
  573. *
  574. * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
  575. * have 4096 bytes. Even if the device is capable, that doesn't mean we can
  576. * access it. Maybe we don't have a way to generate extended config space
  577. * accesses, or the device is behind a reverse Express bridge. So we try
  578. * reading the dword at 0x100 which must either be 0 or a valid extended
  579. * capability header.
  580. */
  581. static int pci_cfg_space_size(struct pci_dev *dev)
  582. {
  583. int pos;
  584. u32 status;
  585. pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
  586. if (!pos) {
  587. pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  588. if (!pos)
  589. goto fail;
  590. pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
  591. if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
  592. goto fail;
  593. }
  594. if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
  595. goto fail;
  596. if (status == 0xffffffff)
  597. goto fail;
  598. return PCI_CFG_SPACE_EXP_SIZE;
  599. fail:
  600. return PCI_CFG_SPACE_SIZE;
  601. }
  602. static void pci_release_bus_bridge_dev(struct device *dev)
  603. {
  604. kfree(dev);
  605. }
  606. /*
  607. * Read the config data for a PCI device, sanity-check it
  608. * and fill in the dev structure...
  609. */
  610. static struct pci_dev * __devinit
  611. pci_scan_device(struct pci_bus *bus, int devfn)
  612. {
  613. struct pci_dev *dev;
  614. u32 l;
  615. u8 hdr_type;
  616. int delay = 1;
  617. if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
  618. return NULL;
  619. /* some broken boards return 0 or ~0 if a slot is empty: */
  620. if (l == 0xffffffff || l == 0x00000000 ||
  621. l == 0x0000ffff || l == 0xffff0000)
  622. return NULL;
  623. /* Configuration request Retry Status */
  624. while (l == 0xffff0001) {
  625. msleep(delay);
  626. delay *= 2;
  627. if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
  628. return NULL;
  629. /* Card hasn't responded in 60 seconds? Must be stuck. */
  630. if (delay > 60 * 1000) {
  631. printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
  632. "responding\n", pci_domain_nr(bus),
  633. bus->number, PCI_SLOT(devfn),
  634. PCI_FUNC(devfn));
  635. return NULL;
  636. }
  637. }
  638. if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
  639. return NULL;
  640. dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
  641. if (!dev)
  642. return NULL;
  643. memset(dev, 0, sizeof(struct pci_dev));
  644. dev->bus = bus;
  645. dev->sysdata = bus->sysdata;
  646. dev->dev.parent = bus->bridge;
  647. dev->dev.bus = &pci_bus_type;
  648. dev->devfn = devfn;
  649. dev->hdr_type = hdr_type & 0x7f;
  650. dev->multifunction = !!(hdr_type & 0x80);
  651. dev->vendor = l & 0xffff;
  652. dev->device = (l >> 16) & 0xffff;
  653. dev->cfg_size = pci_cfg_space_size(dev);
  654. /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
  655. set this higher, assuming the system even supports it. */
  656. dev->dma_mask = 0xffffffff;
  657. if (pci_setup_device(dev) < 0) {
  658. kfree(dev);
  659. return NULL;
  660. }
  661. return dev;
  662. }
  663. void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
  664. {
  665. device_initialize(&dev->dev);
  666. dev->dev.release = pci_release_dev;
  667. pci_dev_get(dev);
  668. dev->dev.dma_mask = &dev->dma_mask;
  669. dev->dev.coherent_dma_mask = 0xffffffffull;
  670. /* Fix up broken headers */
  671. pci_fixup_device(pci_fixup_header, dev);
  672. /*
  673. * Add the device to our list of discovered devices
  674. * and the bus list for fixup functions, etc.
  675. */
  676. INIT_LIST_HEAD(&dev->global_list);
  677. spin_lock(&pci_bus_lock);
  678. list_add_tail(&dev->bus_list, &bus->devices);
  679. spin_unlock(&pci_bus_lock);
  680. }
  681. struct pci_dev * __devinit
  682. pci_scan_single_device(struct pci_bus *bus, int devfn)
  683. {
  684. struct pci_dev *dev;
  685. dev = pci_scan_device(bus, devfn);
  686. if (!dev)
  687. return NULL;
  688. pci_device_add(dev, bus);
  689. pci_scan_msi_device(dev);
  690. return dev;
  691. }
  692. /**
  693. * pci_scan_slot - scan a PCI slot on a bus for devices.
  694. * @bus: PCI bus to scan
  695. * @devfn: slot number to scan (must have zero function.)
  696. *
  697. * Scan a PCI slot on the specified PCI bus for devices, adding
  698. * discovered devices to the @bus->devices list. New devices
  699. * will have an empty dev->global_list head.
  700. */
  701. int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
  702. {
  703. int func, nr = 0;
  704. int scan_all_fns;
  705. scan_all_fns = pcibios_scan_all_fns(bus, devfn);
  706. for (func = 0; func < 8; func++, devfn++) {
  707. struct pci_dev *dev;
  708. dev = pci_scan_single_device(bus, devfn);
  709. if (dev) {
  710. nr++;
  711. /*
  712. * If this is a single function device,
  713. * don't scan past the first function.
  714. */
  715. if (!dev->multifunction) {
  716. if (func > 0) {
  717. dev->multifunction = 1;
  718. } else {
  719. break;
  720. }
  721. }
  722. } else {
  723. if (func == 0 && !scan_all_fns)
  724. break;
  725. }
  726. }
  727. return nr;
  728. }
  729. unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
  730. {
  731. unsigned int devfn, pass, max = bus->secondary;
  732. struct pci_dev *dev;
  733. pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
  734. /* Go find them, Rover! */
  735. for (devfn = 0; devfn < 0x100; devfn += 8)
  736. pci_scan_slot(bus, devfn);
  737. /*
  738. * After performing arch-dependent fixup of the bus, look behind
  739. * all PCI-to-PCI bridges on this bus.
  740. */
  741. pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
  742. pcibios_fixup_bus(bus);
  743. for (pass=0; pass < 2; pass++)
  744. list_for_each_entry(dev, &bus->devices, bus_list) {
  745. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
  746. dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
  747. max = pci_scan_bridge(bus, dev, max, pass);
  748. }
  749. /*
  750. * We've scanned the bus and so we know all about what's on
  751. * the other side of any bridges that may be on this bus plus
  752. * any devices.
  753. *
  754. * Return how far we've got finding sub-buses.
  755. */
  756. pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
  757. pci_domain_nr(bus), bus->number, max);
  758. return max;
  759. }
  760. unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
  761. {
  762. unsigned int max;
  763. max = pci_scan_child_bus(bus);
  764. /*
  765. * Make the discovered devices available.
  766. */
  767. pci_bus_add_devices(bus);
  768. return max;
  769. }
  770. struct pci_bus * __devinit pci_create_bus(struct device *parent,
  771. int bus, struct pci_ops *ops, void *sysdata)
  772. {
  773. int error;
  774. struct pci_bus *b;
  775. struct device *dev;
  776. b = pci_alloc_bus();
  777. if (!b)
  778. return NULL;
  779. dev = kmalloc(sizeof(*dev), GFP_KERNEL);
  780. if (!dev){
  781. kfree(b);
  782. return NULL;
  783. }
  784. b->sysdata = sysdata;
  785. b->ops = ops;
  786. if (pci_find_bus(pci_domain_nr(b), bus)) {
  787. /* If we already got to this bus through a different bridge, ignore it */
  788. pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
  789. goto err_out;
  790. }
  791. spin_lock(&pci_bus_lock);
  792. list_add_tail(&b->node, &pci_root_buses);
  793. spin_unlock(&pci_bus_lock);
  794. memset(dev, 0, sizeof(*dev));
  795. dev->parent = parent;
  796. dev->release = pci_release_bus_bridge_dev;
  797. sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
  798. error = device_register(dev);
  799. if (error)
  800. goto dev_reg_err;
  801. b->bridge = get_device(dev);
  802. b->class_dev.class = &pcibus_class;
  803. sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
  804. error = class_device_register(&b->class_dev);
  805. if (error)
  806. goto class_dev_reg_err;
  807. error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
  808. if (error)
  809. goto class_dev_create_file_err;
  810. /* Create legacy_io and legacy_mem files for this bus */
  811. pci_create_legacy_files(b);
  812. error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
  813. if (error)
  814. goto sys_create_link_err;
  815. b->number = b->secondary = bus;
  816. b->resource[0] = &ioport_resource;
  817. b->resource[1] = &iomem_resource;
  818. return b;
  819. sys_create_link_err:
  820. class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
  821. class_dev_create_file_err:
  822. class_device_unregister(&b->class_dev);
  823. class_dev_reg_err:
  824. device_unregister(dev);
  825. dev_reg_err:
  826. spin_lock(&pci_bus_lock);
  827. list_del(&b->node);
  828. spin_unlock(&pci_bus_lock);
  829. err_out:
  830. kfree(dev);
  831. kfree(b);
  832. return NULL;
  833. }
  834. EXPORT_SYMBOL_GPL(pci_create_bus);
  835. struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
  836. int bus, struct pci_ops *ops, void *sysdata)
  837. {
  838. struct pci_bus *b;
  839. b = pci_create_bus(parent, bus, ops, sysdata);
  840. if (b)
  841. b->subordinate = pci_scan_child_bus(b);
  842. return b;
  843. }
  844. EXPORT_SYMBOL(pci_scan_bus_parented);
  845. #ifdef CONFIG_HOTPLUG
  846. EXPORT_SYMBOL(pci_add_new_bus);
  847. EXPORT_SYMBOL(pci_do_scan_bus);
  848. EXPORT_SYMBOL(pci_scan_slot);
  849. EXPORT_SYMBOL(pci_scan_bridge);
  850. EXPORT_SYMBOL(pci_scan_single_device);
  851. EXPORT_SYMBOL_GPL(pci_scan_child_bus);
  852. #endif