shpchp_pci.c 22 KB

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  1. /*
  2. * Standard Hot Plug Controller Driver
  3. *
  4. * Copyright (C) 1995,2001 Compaq Computer Corporation
  5. * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
  6. * Copyright (C) 2001 IBM Corp.
  7. * Copyright (C) 2003-2004 Intel Corporation
  8. *
  9. * All rights reserved.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or (at
  14. * your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19. * NON INFRINGEMENT. See the GNU General Public License for more
  20. * details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25. *
  26. * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  27. *
  28. */
  29. #include <linux/config.h>
  30. #include <linux/module.h>
  31. #include <linux/kernel.h>
  32. #include <linux/types.h>
  33. #include <linux/slab.h>
  34. #include <linux/workqueue.h>
  35. #include <linux/proc_fs.h>
  36. #include <linux/pci.h>
  37. #include "../pci.h"
  38. #include "shpchp.h"
  39. #ifndef CONFIG_IA64
  40. #include "../../../arch/i386/pci/pci.h" /* horrible hack showing how processor dependant we are... */
  41. #endif
  42. int shpchp_configure_device (struct controller* ctrl, struct pci_func* func)
  43. {
  44. unsigned char bus;
  45. struct pci_bus *child;
  46. int num;
  47. if (func->pci_dev == NULL)
  48. func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
  49. /* Still NULL ? Well then scan for it ! */
  50. if (func->pci_dev == NULL) {
  51. num = pci_scan_slot(ctrl->pci_dev->subordinate, PCI_DEVFN(func->device, func->function));
  52. if (num) {
  53. dbg("%s: subordiante %p number %x\n", __FUNCTION__, ctrl->pci_dev->subordinate,
  54. ctrl->pci_dev->subordinate->number);
  55. pci_bus_add_devices(ctrl->pci_dev->subordinate);
  56. }
  57. func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
  58. if (func->pci_dev == NULL) {
  59. dbg("ERROR: pci_dev still null\n");
  60. return 0;
  61. }
  62. }
  63. if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  64. pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus);
  65. child = pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus);
  66. pci_do_scan_bus(child);
  67. }
  68. return 0;
  69. }
  70. int shpchp_unconfigure_device(struct pci_func* func)
  71. {
  72. int rc = 0;
  73. int j;
  74. dbg("%s: bus/dev/func = %x/%x/%x\n", __FUNCTION__, func->bus,
  75. func->device, func->function);
  76. for (j=0; j<8 ; j++) {
  77. struct pci_dev* temp = pci_find_slot(func->bus,
  78. (func->device << 3) | j);
  79. if (temp) {
  80. pci_remove_bus_device(temp);
  81. }
  82. }
  83. return rc;
  84. }
  85. /*
  86. * shpchp_set_irq
  87. *
  88. * @bus_num: bus number of PCI device
  89. * @dev_num: device number of PCI device
  90. * @slot: pointer to u8 where slot number will be returned
  91. */
  92. int shpchp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
  93. {
  94. #if defined(CONFIG_X86) && !defined(CONFIG_X86_IO_APIC) && !defined(CONFIG_X86_64)
  95. int rc;
  96. u16 temp_word;
  97. struct pci_dev fakedev;
  98. struct pci_bus fakebus;
  99. fakedev.devfn = dev_num << 3;
  100. fakedev.bus = &fakebus;
  101. fakebus.number = bus_num;
  102. dbg("%s: dev %d, bus %d, pin %d, num %d\n",
  103. __FUNCTION__, dev_num, bus_num, int_pin, irq_num);
  104. rc = pcibios_set_irq_routing(&fakedev, int_pin - 0x0a, irq_num);
  105. dbg("%s: rc %d\n", __FUNCTION__, rc);
  106. if (!rc)
  107. return !rc;
  108. /* set the Edge Level Control Register (ELCR) */
  109. temp_word = inb(0x4d0);
  110. temp_word |= inb(0x4d1) << 8;
  111. temp_word |= 0x01 << irq_num;
  112. /* This should only be for x86 as it sets the Edge Level Control Register */
  113. outb((u8) (temp_word & 0xFF), 0x4d0);
  114. outb((u8) ((temp_word & 0xFF00) >> 8), 0x4d1);
  115. #endif
  116. return 0;
  117. }
  118. /* More PCI configuration routines; this time centered around hotplug controller */
  119. /*
  120. * shpchp_save_config
  121. *
  122. * Reads configuration for all slots in a PCI bus and saves info.
  123. *
  124. * Note: For non-hot plug busses, the slot # saved is the device #
  125. *
  126. * returns 0 if success
  127. */
  128. int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num)
  129. {
  130. int rc;
  131. u8 class_code;
  132. u8 header_type;
  133. u32 ID;
  134. u8 secondary_bus;
  135. struct pci_func *new_slot;
  136. int sub_bus;
  137. int FirstSupported;
  138. int LastSupported;
  139. int max_functions;
  140. int function;
  141. u8 DevError;
  142. int device = 0;
  143. int cloop = 0;
  144. int stop_it;
  145. int index;
  146. int is_hot_plug = num_ctlr_slots || first_device_num;
  147. struct pci_bus lpci_bus, *pci_bus;
  148. dbg("%s: num_ctlr_slots = %d, first_device_num = %d\n", __FUNCTION__,
  149. num_ctlr_slots, first_device_num);
  150. memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
  151. pci_bus = &lpci_bus;
  152. dbg("%s: num_ctlr_slots = %d, first_device_num = %d\n", __FUNCTION__,
  153. num_ctlr_slots, first_device_num);
  154. /* Decide which slots are supported */
  155. if (is_hot_plug) {
  156. /*********************************
  157. * is_hot_plug is the slot mask
  158. *********************************/
  159. FirstSupported = first_device_num;
  160. LastSupported = FirstSupported + num_ctlr_slots - 1;
  161. } else {
  162. FirstSupported = 0;
  163. LastSupported = 0x1F;
  164. }
  165. dbg("FirstSupported = %d, LastSupported = %d\n", FirstSupported,
  166. LastSupported);
  167. /* Save PCI configuration space for all devices in supported slots */
  168. pci_bus->number = busnumber;
  169. for (device = FirstSupported; device <= LastSupported; device++) {
  170. ID = 0xFFFFFFFF;
  171. rc = pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, 0),
  172. PCI_VENDOR_ID, &ID);
  173. if (ID != 0xFFFFFFFF) { /* device in slot */
  174. rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0),
  175. 0x0B, &class_code);
  176. if (rc)
  177. return rc;
  178. rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0),
  179. PCI_HEADER_TYPE, &header_type);
  180. if (rc)
  181. return rc;
  182. dbg("class_code = %x, header_type = %x\n", class_code, header_type);
  183. /* If multi-function device, set max_functions to 8 */
  184. if (header_type & 0x80)
  185. max_functions = 8;
  186. else
  187. max_functions = 1;
  188. function = 0;
  189. do {
  190. DevError = 0;
  191. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* P-P Bridge */
  192. /* Recurse the subordinate bus
  193. * get the subordinate bus number
  194. */
  195. rc = pci_bus_read_config_byte(pci_bus,
  196. PCI_DEVFN(device, function),
  197. PCI_SECONDARY_BUS, &secondary_bus);
  198. if (rc) {
  199. return rc;
  200. } else {
  201. sub_bus = (int) secondary_bus;
  202. /* Save secondary bus cfg spc with this recursive call. */
  203. rc = shpchp_save_config(ctrl, sub_bus, 0, 0);
  204. if (rc)
  205. return rc;
  206. }
  207. }
  208. index = 0;
  209. new_slot = shpchp_slot_find(busnumber, device, index++);
  210. dbg("new_slot = %p\n", new_slot);
  211. while (new_slot && (new_slot->function != (u8) function)) {
  212. new_slot = shpchp_slot_find(busnumber, device, index++);
  213. dbg("new_slot = %p\n", new_slot);
  214. }
  215. if (!new_slot) {
  216. /* Setup slot structure. */
  217. new_slot = shpchp_slot_create(busnumber);
  218. dbg("new_slot = %p\n", new_slot);
  219. if (new_slot == NULL)
  220. return(1);
  221. }
  222. new_slot->bus = (u8) busnumber;
  223. new_slot->device = (u8) device;
  224. new_slot->function = (u8) function;
  225. new_slot->is_a_board = 1;
  226. new_slot->switch_save = 0x10;
  227. new_slot->pwr_save = 1;
  228. /* In case of unsupported board */
  229. new_slot->status = DevError;
  230. new_slot->pci_dev = pci_find_slot(new_slot->bus,
  231. (new_slot->device << 3) | new_slot->function);
  232. dbg("new_slot->pci_dev = %p\n", new_slot->pci_dev);
  233. for (cloop = 0; cloop < 0x20; cloop++) {
  234. rc = pci_bus_read_config_dword(pci_bus,
  235. PCI_DEVFN(device, function),
  236. cloop << 2,
  237. (u32 *) &(new_slot->config_space [cloop]));
  238. /* dbg("new_slot->config_space[%x] = %x\n",
  239. cloop, new_slot->config_space[cloop]); */
  240. if (rc)
  241. return rc;
  242. }
  243. function++;
  244. stop_it = 0;
  245. /* this loop skips to the next present function
  246. * reading in Class Code and Header type.
  247. */
  248. while ((function < max_functions)&&(!stop_it)) {
  249. rc = pci_bus_read_config_dword(pci_bus,
  250. PCI_DEVFN(device, function),
  251. PCI_VENDOR_ID, &ID);
  252. if (ID == 0xFFFFFFFF) { /* nothing there. */
  253. function++;
  254. dbg("Nothing there\n");
  255. } else { /* Something there */
  256. rc = pci_bus_read_config_byte(pci_bus,
  257. PCI_DEVFN(device, function),
  258. 0x0B, &class_code);
  259. if (rc)
  260. return rc;
  261. rc = pci_bus_read_config_byte(pci_bus,
  262. PCI_DEVFN(device, function),
  263. PCI_HEADER_TYPE, &header_type);
  264. if (rc)
  265. return rc;
  266. dbg("class_code = %x, header_type = %x\n",
  267. class_code, header_type);
  268. stop_it++;
  269. }
  270. }
  271. } while (function < max_functions);
  272. /* End of IF (device in slot?) */
  273. } else if (is_hot_plug) {
  274. /* Setup slot structure with entry for empty slot */
  275. new_slot = shpchp_slot_create(busnumber);
  276. if (new_slot == NULL) {
  277. return(1);
  278. }
  279. dbg("new_slot = %p\n", new_slot);
  280. new_slot->bus = (u8) busnumber;
  281. new_slot->device = (u8) device;
  282. new_slot->function = 0;
  283. new_slot->is_a_board = 0;
  284. new_slot->presence_save = 0;
  285. new_slot->switch_save = 0;
  286. }
  287. } /* End of FOR loop */
  288. return(0);
  289. }
  290. /*
  291. * shpchp_save_slot_config
  292. *
  293. * Saves configuration info for all PCI devices in a given slot
  294. * including subordinate busses.
  295. *
  296. * returns 0 if success
  297. */
  298. int shpchp_save_slot_config(struct controller *ctrl, struct pci_func * new_slot)
  299. {
  300. int rc;
  301. u8 class_code;
  302. u8 header_type;
  303. u32 ID;
  304. u8 secondary_bus;
  305. int sub_bus;
  306. int max_functions;
  307. int function;
  308. int cloop = 0;
  309. int stop_it;
  310. struct pci_bus lpci_bus, *pci_bus;
  311. memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
  312. pci_bus = &lpci_bus;
  313. pci_bus->number = new_slot->bus;
  314. ID = 0xFFFFFFFF;
  315. pci_bus_read_config_dword(pci_bus, PCI_DEVFN(new_slot->device, 0),
  316. PCI_VENDOR_ID, &ID);
  317. if (ID != 0xFFFFFFFF) { /* device in slot */
  318. pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0),
  319. 0x0B, &class_code);
  320. pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0),
  321. PCI_HEADER_TYPE, &header_type);
  322. if (header_type & 0x80) /* Multi-function device */
  323. max_functions = 8;
  324. else
  325. max_functions = 1;
  326. function = 0;
  327. do {
  328. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
  329. /* Recurse the subordinate bus */
  330. pci_bus_read_config_byte(pci_bus,
  331. PCI_DEVFN(new_slot->device, function),
  332. PCI_SECONDARY_BUS, &secondary_bus);
  333. sub_bus = (int) secondary_bus;
  334. /* Save the config headers for the secondary bus. */
  335. rc = shpchp_save_config(ctrl, sub_bus, 0, 0);
  336. if (rc)
  337. return rc;
  338. } /* End of IF */
  339. new_slot->status = 0;
  340. for (cloop = 0; cloop < 0x20; cloop++) {
  341. pci_bus_read_config_dword(pci_bus,
  342. PCI_DEVFN(new_slot->device, function),
  343. cloop << 2,
  344. (u32 *) &(new_slot->config_space [cloop]));
  345. }
  346. function++;
  347. stop_it = 0;
  348. /* this loop skips to the next present function
  349. * reading in the Class Code and the Header type.
  350. */
  351. while ((function < max_functions) && (!stop_it)) {
  352. pci_bus_read_config_dword(pci_bus,
  353. PCI_DEVFN(new_slot->device, function),
  354. PCI_VENDOR_ID, &ID);
  355. if (ID == 0xFFFFFFFF) { /* nothing there. */
  356. function++;
  357. } else { /* Something there */
  358. pci_bus_read_config_byte(pci_bus,
  359. PCI_DEVFN(new_slot->device, function),
  360. 0x0B, &class_code);
  361. pci_bus_read_config_byte(pci_bus,
  362. PCI_DEVFN(new_slot->device, function),
  363. PCI_HEADER_TYPE, &header_type);
  364. stop_it++;
  365. }
  366. }
  367. } while (function < max_functions);
  368. } /* End of IF (device in slot?) */
  369. else {
  370. return 2;
  371. }
  372. return 0;
  373. }
  374. /*
  375. * shpchp_save_used_resources
  376. *
  377. * Stores used resource information for existing boards. this is
  378. * for boards that were in the system when this driver was loaded.
  379. * this function is for hot plug ADD
  380. *
  381. * returns 0 if success
  382. * if disable == 1(DISABLE_CARD),
  383. * it loops for all functions of the slot and disables them.
  384. * else, it just get resources of the function and return.
  385. */
  386. int shpchp_save_used_resources(struct controller *ctrl, struct pci_func *func, int disable)
  387. {
  388. u8 cloop;
  389. u8 header_type;
  390. u8 secondary_bus;
  391. u8 temp_byte;
  392. u16 command;
  393. u16 save_command;
  394. u16 w_base, w_length;
  395. u32 temp_register;
  396. u32 save_base;
  397. u32 base, length;
  398. u64 base64 = 0;
  399. int index = 0;
  400. unsigned int devfn;
  401. struct pci_resource *mem_node = NULL;
  402. struct pci_resource *p_mem_node = NULL;
  403. struct pci_resource *t_mem_node;
  404. struct pci_resource *io_node;
  405. struct pci_resource *bus_node;
  406. struct pci_bus lpci_bus, *pci_bus;
  407. memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
  408. pci_bus = &lpci_bus;
  409. if (disable)
  410. func = shpchp_slot_find(func->bus, func->device, index++);
  411. while ((func != NULL) && func->is_a_board) {
  412. pci_bus->number = func->bus;
  413. devfn = PCI_DEVFN(func->device, func->function);
  414. /* Save the command register */
  415. pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
  416. if (disable) {
  417. /* disable card */
  418. command = 0x00;
  419. pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
  420. }
  421. /* Check for Bridge */
  422. pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
  423. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
  424. dbg("Save_used_res of PCI bridge b:d=0x%x:%x, sc=0x%x\n",
  425. func->bus, func->device, save_command);
  426. if (disable) {
  427. /* Clear Bridge Control Register */
  428. command = 0x00;
  429. pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
  430. }
  431. pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
  432. pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
  433. bus_node = kmalloc(sizeof(struct pci_resource),
  434. GFP_KERNEL);
  435. if (!bus_node)
  436. return -ENOMEM;
  437. bus_node->base = (ulong)secondary_bus;
  438. bus_node->length = (ulong)(temp_byte - secondary_bus + 1);
  439. bus_node->next = func->bus_head;
  440. func->bus_head = bus_node;
  441. /* Save IO base and Limit registers */
  442. pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &temp_byte);
  443. base = temp_byte;
  444. pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &temp_byte);
  445. length = temp_byte;
  446. if ((base <= length) && (!disable || (save_command & PCI_COMMAND_IO))) {
  447. io_node = kmalloc(sizeof(struct pci_resource),
  448. GFP_KERNEL);
  449. if (!io_node)
  450. return -ENOMEM;
  451. io_node->base = (ulong)(base & PCI_IO_RANGE_MASK) << 8;
  452. io_node->length = (ulong)(length - base + 0x10) << 8;
  453. io_node->next = func->io_head;
  454. func->io_head = io_node;
  455. }
  456. /* Save memory base and Limit registers */
  457. pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
  458. pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
  459. if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
  460. mem_node = kmalloc(sizeof(struct pci_resource),
  461. GFP_KERNEL);
  462. if (!mem_node)
  463. return -ENOMEM;
  464. mem_node->base = (ulong)w_base << 16;
  465. mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
  466. mem_node->next = func->mem_head;
  467. func->mem_head = mem_node;
  468. }
  469. /* Save prefetchable memory base and Limit registers */
  470. pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
  471. pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
  472. if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
  473. p_mem_node = kmalloc(sizeof(struct pci_resource),
  474. GFP_KERNEL);
  475. if (!p_mem_node)
  476. return -ENOMEM;
  477. p_mem_node->base = (ulong)w_base << 16;
  478. p_mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
  479. p_mem_node->next = func->p_mem_head;
  480. func->p_mem_head = p_mem_node;
  481. }
  482. } else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
  483. dbg("Save_used_res of PCI adapter b:d=0x%x:%x, sc=0x%x\n",
  484. func->bus, func->device, save_command);
  485. /* Figure out IO and memory base lengths */
  486. for (cloop = PCI_BASE_ADDRESS_0; cloop <= PCI_BASE_ADDRESS_5; cloop += 4) {
  487. pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
  488. temp_register = 0xFFFFFFFF;
  489. pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
  490. pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp_register);
  491. if (!disable)
  492. pci_bus_write_config_dword(pci_bus, devfn, cloop, save_base);
  493. if (!temp_register)
  494. continue;
  495. base = temp_register;
  496. if ((base & PCI_BASE_ADDRESS_SPACE_IO) &&
  497. (!disable || (save_command & PCI_COMMAND_IO))) {
  498. /* IO base */
  499. /* set temp_register = amount of IO space requested */
  500. base = base & 0xFFFFFFFCL;
  501. base = (~base) + 1;
  502. io_node = kmalloc(sizeof (struct pci_resource),
  503. GFP_KERNEL);
  504. if (!io_node)
  505. return -ENOMEM;
  506. io_node->base = (ulong)save_base & PCI_BASE_ADDRESS_IO_MASK;
  507. io_node->length = (ulong)base;
  508. dbg("sur adapter: IO bar=0x%x(length=0x%x)\n",
  509. io_node->base, io_node->length);
  510. io_node->next = func->io_head;
  511. func->io_head = io_node;
  512. } else { /* map Memory */
  513. int prefetchable = 1;
  514. /* struct pci_resources **res_node; */
  515. char *res_type_str = "PMEM";
  516. u32 temp_register2;
  517. t_mem_node = kmalloc(sizeof (struct pci_resource),
  518. GFP_KERNEL);
  519. if (!t_mem_node)
  520. return -ENOMEM;
  521. if (!(base & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
  522. (!disable || (save_command & PCI_COMMAND_MEMORY))) {
  523. prefetchable = 0;
  524. mem_node = t_mem_node;
  525. res_type_str++;
  526. } else
  527. p_mem_node = t_mem_node;
  528. base = base & 0xFFFFFFF0L;
  529. base = (~base) + 1;
  530. switch (temp_register & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
  531. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  532. if (prefetchable) {
  533. p_mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
  534. p_mem_node->length = (ulong)base;
  535. dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n",
  536. res_type_str,
  537. p_mem_node->base,
  538. p_mem_node->length);
  539. p_mem_node->next = func->p_mem_head;
  540. func->p_mem_head = p_mem_node;
  541. } else {
  542. mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
  543. mem_node->length = (ulong)base;
  544. dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n",
  545. res_type_str,
  546. mem_node->base,
  547. mem_node->length);
  548. mem_node->next = func->mem_head;
  549. func->mem_head = mem_node;
  550. }
  551. break;
  552. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  553. pci_bus_read_config_dword(pci_bus, devfn, cloop+4, &temp_register2);
  554. base64 = temp_register2;
  555. base64 = (base64 << 32) | save_base;
  556. if (temp_register2) {
  557. dbg("sur adapter: 64 %s high dword of base64(0x%x:%x) masked to 0\n",
  558. res_type_str, temp_register2, (u32)base64);
  559. base64 &= 0x00000000FFFFFFFFL;
  560. }
  561. if (prefetchable) {
  562. p_mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
  563. p_mem_node->length = base;
  564. dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n",
  565. res_type_str,
  566. p_mem_node->base,
  567. p_mem_node->length);
  568. p_mem_node->next = func->p_mem_head;
  569. func->p_mem_head = p_mem_node;
  570. } else {
  571. mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
  572. mem_node->length = base;
  573. dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n",
  574. res_type_str,
  575. mem_node->base,
  576. mem_node->length);
  577. mem_node->next = func->mem_head;
  578. func->mem_head = mem_node;
  579. }
  580. cloop += 4;
  581. break;
  582. default:
  583. dbg("asur: reserved BAR type=0x%x\n",
  584. temp_register);
  585. break;
  586. }
  587. }
  588. } /* End of base register loop */
  589. } else { /* Some other unknown header type */
  590. dbg("Save_used_res of PCI unknown type b:d=0x%x:%x. skip.\n",
  591. func->bus, func->device);
  592. }
  593. /* find the next device in this slot */
  594. if (!disable)
  595. break;
  596. func = shpchp_slot_find(func->bus, func->device, index++);
  597. }
  598. return 0;
  599. }
  600. /**
  601. * kfree_resource_list: release memory of all list members
  602. * @res: resource list to free
  603. */
  604. static inline void
  605. return_resource_list(struct pci_resource **func, struct pci_resource **res)
  606. {
  607. struct pci_resource *node;
  608. struct pci_resource *t_node;
  609. node = *func;
  610. *func = NULL;
  611. while (node) {
  612. t_node = node->next;
  613. return_resource(res, node);
  614. node = t_node;
  615. }
  616. }
  617. /*
  618. * shpchp_return_board_resources
  619. *
  620. * this routine returns all resources allocated to a board to
  621. * the available pool.
  622. *
  623. * returns 0 if success
  624. */
  625. int shpchp_return_board_resources(struct pci_func * func,
  626. struct resource_lists * resources)
  627. {
  628. int rc;
  629. dbg("%s\n", __FUNCTION__);
  630. if (!func)
  631. return 1;
  632. return_resource_list(&(func->io_head),&(resources->io_head));
  633. return_resource_list(&(func->mem_head),&(resources->mem_head));
  634. return_resource_list(&(func->p_mem_head),&(resources->p_mem_head));
  635. return_resource_list(&(func->bus_head),&(resources->bus_head));
  636. rc = shpchp_resource_sort_and_combine(&(resources->mem_head));
  637. rc |= shpchp_resource_sort_and_combine(&(resources->p_mem_head));
  638. rc |= shpchp_resource_sort_and_combine(&(resources->io_head));
  639. rc |= shpchp_resource_sort_and_combine(&(resources->bus_head));
  640. return rc;
  641. }
  642. /**
  643. * kfree_resource_list: release memory of all list members
  644. * @res: resource list to free
  645. */
  646. static inline void
  647. kfree_resource_list(struct pci_resource **r)
  648. {
  649. struct pci_resource *res, *tres;
  650. res = *r;
  651. *r = NULL;
  652. while (res) {
  653. tres = res;
  654. res = res->next;
  655. kfree(tres);
  656. }
  657. }
  658. /**
  659. * shpchp_destroy_resource_list: put node back in the resource list
  660. * @resources: list to put nodes back
  661. */
  662. void shpchp_destroy_resource_list(struct resource_lists *resources)
  663. {
  664. kfree_resource_list(&(resources->io_head));
  665. kfree_resource_list(&(resources->mem_head));
  666. kfree_resource_list(&(resources->p_mem_head));
  667. kfree_resource_list(&(resources->bus_head));
  668. }
  669. /**
  670. * shpchp_destroy_board_resources: put node back in the resource list
  671. * @resources: list to put nodes back
  672. */
  673. void shpchp_destroy_board_resources(struct pci_func * func)
  674. {
  675. kfree_resource_list(&(func->io_head));
  676. kfree_resource_list(&(func->mem_head));
  677. kfree_resource_list(&(func->p_mem_head));
  678. kfree_resource_list(&(func->bus_head));
  679. }