cpqphp_core.c 38 KB

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  1. /*
  2. * Compaq Hot Plug Controller Driver
  3. *
  4. * Copyright (C) 1995,2001 Compaq Computer Corporation
  5. * Copyright (C) 2001 Greg Kroah-Hartman <greg@kroah.com>
  6. * Copyright (C) 2001 IBM Corp.
  7. *
  8. * All rights reserved.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or (at
  13. * your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  18. * NON INFRINGEMENT. See the GNU General Public License for more
  19. * details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. * Send feedback to <greg@kroah.com>
  26. *
  27. * Jan 12, 2003 - Added 66/100/133MHz PCI-X support,
  28. * Torben Mathiasen <torben.mathiasen@hp.com>
  29. *
  30. */
  31. #include <linux/config.h>
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/kernel.h>
  35. #include <linux/types.h>
  36. #include <linux/proc_fs.h>
  37. #include <linux/slab.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/pci.h>
  40. #include <linux/init.h>
  41. #include <linux/interrupt.h>
  42. #include <asm/uaccess.h>
  43. #include "cpqphp.h"
  44. #include "cpqphp_nvram.h"
  45. #include "../../../arch/i386/pci/pci.h" /* horrible hack showing how processor dependent we are... */
  46. /* Global variables */
  47. int cpqhp_debug;
  48. int cpqhp_legacy_mode;
  49. struct controller *cpqhp_ctrl_list; /* = NULL */
  50. struct pci_func *cpqhp_slot_list[256];
  51. /* local variables */
  52. static void __iomem *smbios_table;
  53. static void __iomem *smbios_start;
  54. static void __iomem *cpqhp_rom_start;
  55. static int power_mode;
  56. static int debug;
  57. static int initialized;
  58. #define DRIVER_VERSION "0.9.8"
  59. #define DRIVER_AUTHOR "Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>"
  60. #define DRIVER_DESC "Compaq Hot Plug PCI Controller Driver"
  61. MODULE_AUTHOR(DRIVER_AUTHOR);
  62. MODULE_DESCRIPTION(DRIVER_DESC);
  63. MODULE_LICENSE("GPL");
  64. module_param(power_mode, bool, 0644);
  65. MODULE_PARM_DESC(power_mode, "Power mode enabled or not");
  66. module_param(debug, bool, 0644);
  67. MODULE_PARM_DESC(debug, "Debugging mode enabled or not");
  68. #define CPQHPC_MODULE_MINOR 208
  69. static int one_time_init (void);
  70. static int set_attention_status (struct hotplug_slot *slot, u8 value);
  71. static int process_SI (struct hotplug_slot *slot);
  72. static int process_SS (struct hotplug_slot *slot);
  73. static int hardware_test (struct hotplug_slot *slot, u32 value);
  74. static int get_power_status (struct hotplug_slot *slot, u8 *value);
  75. static int get_attention_status (struct hotplug_slot *slot, u8 *value);
  76. static int get_latch_status (struct hotplug_slot *slot, u8 *value);
  77. static int get_adapter_status (struct hotplug_slot *slot, u8 *value);
  78. static int get_max_bus_speed (struct hotplug_slot *slot, enum pci_bus_speed *value);
  79. static int get_cur_bus_speed (struct hotplug_slot *slot, enum pci_bus_speed *value);
  80. static struct hotplug_slot_ops cpqphp_hotplug_slot_ops = {
  81. .owner = THIS_MODULE,
  82. .set_attention_status = set_attention_status,
  83. .enable_slot = process_SI,
  84. .disable_slot = process_SS,
  85. .hardware_test = hardware_test,
  86. .get_power_status = get_power_status,
  87. .get_attention_status = get_attention_status,
  88. .get_latch_status = get_latch_status,
  89. .get_adapter_status = get_adapter_status,
  90. .get_max_bus_speed = get_max_bus_speed,
  91. .get_cur_bus_speed = get_cur_bus_speed,
  92. };
  93. static inline int is_slot64bit(struct slot *slot)
  94. {
  95. return (readb(slot->p_sm_slot + SMBIOS_SLOT_WIDTH) == 0x06) ? 1 : 0;
  96. }
  97. static inline int is_slot66mhz(struct slot *slot)
  98. {
  99. return (readb(slot->p_sm_slot + SMBIOS_SLOT_TYPE) == 0x0E) ? 1 : 0;
  100. }
  101. /**
  102. * detect_SMBIOS_pointer - find the System Management BIOS Table in mem region.
  103. *
  104. * @begin: begin pointer for region to be scanned.
  105. * @end: end pointer for region to be scanned.
  106. *
  107. * Returns pointer to the head of the SMBIOS tables (or NULL)
  108. *
  109. */
  110. static void __iomem * detect_SMBIOS_pointer(void __iomem *begin, void __iomem *end)
  111. {
  112. void __iomem *fp;
  113. void __iomem *endp;
  114. u8 temp1, temp2, temp3, temp4;
  115. int status = 0;
  116. endp = (end - sizeof(u32) + 1);
  117. for (fp = begin; fp <= endp; fp += 16) {
  118. temp1 = readb(fp);
  119. temp2 = readb(fp+1);
  120. temp3 = readb(fp+2);
  121. temp4 = readb(fp+3);
  122. if (temp1 == '_' &&
  123. temp2 == 'S' &&
  124. temp3 == 'M' &&
  125. temp4 == '_') {
  126. status = 1;
  127. break;
  128. }
  129. }
  130. if (!status)
  131. fp = NULL;
  132. dbg("Discovered SMBIOS Entry point at %p\n", fp);
  133. return fp;
  134. }
  135. /**
  136. * init_SERR - Initializes the per slot SERR generation.
  137. *
  138. * For unexpected switch opens
  139. *
  140. */
  141. static int init_SERR(struct controller * ctrl)
  142. {
  143. u32 tempdword;
  144. u32 number_of_slots;
  145. u8 physical_slot;
  146. if (!ctrl)
  147. return 1;
  148. tempdword = ctrl->first_slot;
  149. number_of_slots = readb(ctrl->hpc_reg + SLOT_MASK) & 0x0F;
  150. // Loop through slots
  151. while (number_of_slots) {
  152. physical_slot = tempdword;
  153. writeb(0, ctrl->hpc_reg + SLOT_SERR);
  154. tempdword++;
  155. number_of_slots--;
  156. }
  157. return 0;
  158. }
  159. /* nice debugging output */
  160. static int pci_print_IRQ_route (void)
  161. {
  162. struct irq_routing_table *routing_table;
  163. int len;
  164. int loop;
  165. u8 tbus, tdevice, tslot;
  166. routing_table = pcibios_get_irq_routing_table();
  167. if (routing_table == NULL) {
  168. err("No BIOS Routing Table??? Not good\n");
  169. return -ENOMEM;
  170. }
  171. len = (routing_table->size - sizeof(struct irq_routing_table)) /
  172. sizeof(struct irq_info);
  173. // Make sure I got at least one entry
  174. if (len == 0) {
  175. kfree(routing_table);
  176. return -1;
  177. }
  178. dbg("bus dev func slot\n");
  179. for (loop = 0; loop < len; ++loop) {
  180. tbus = routing_table->slots[loop].bus;
  181. tdevice = routing_table->slots[loop].devfn;
  182. tslot = routing_table->slots[loop].slot;
  183. dbg("%d %d %d %d\n", tbus, tdevice >> 3, tdevice & 0x7, tslot);
  184. }
  185. kfree(routing_table);
  186. return 0;
  187. }
  188. /**
  189. * get_subsequent_smbios_entry: get the next entry from bios table.
  190. *
  191. * Gets the first entry if previous == NULL
  192. * Otherwise, returns the next entry
  193. * Uses global SMBIOS Table pointer
  194. *
  195. * @curr: %NULL or pointer to previously returned structure
  196. *
  197. * returns a pointer to an SMBIOS structure or NULL if none found
  198. */
  199. static void __iomem *get_subsequent_smbios_entry(void __iomem *smbios_start,
  200. void __iomem *smbios_table,
  201. void __iomem *curr)
  202. {
  203. u8 bail = 0;
  204. u8 previous_byte = 1;
  205. void __iomem *p_temp;
  206. void __iomem *p_max;
  207. if (!smbios_table || !curr)
  208. return(NULL);
  209. // set p_max to the end of the table
  210. p_max = smbios_start + readw(smbios_table + ST_LENGTH);
  211. p_temp = curr;
  212. p_temp += readb(curr + SMBIOS_GENERIC_LENGTH);
  213. while ((p_temp < p_max) && !bail) {
  214. /* Look for the double NULL terminator
  215. * The first condition is the previous byte
  216. * and the second is the curr */
  217. if (!previous_byte && !(readb(p_temp))) {
  218. bail = 1;
  219. }
  220. previous_byte = readb(p_temp);
  221. p_temp++;
  222. }
  223. if (p_temp < p_max) {
  224. return p_temp;
  225. } else {
  226. return NULL;
  227. }
  228. }
  229. /**
  230. * get_SMBIOS_entry
  231. *
  232. * @type:SMBIOS structure type to be returned
  233. * @previous: %NULL or pointer to previously returned structure
  234. *
  235. * Gets the first entry of the specified type if previous == NULL
  236. * Otherwise, returns the next entry of the given type.
  237. * Uses global SMBIOS Table pointer
  238. * Uses get_subsequent_smbios_entry
  239. *
  240. * returns a pointer to an SMBIOS structure or %NULL if none found
  241. */
  242. static void __iomem *get_SMBIOS_entry(void __iomem *smbios_start,
  243. void __iomem *smbios_table,
  244. u8 type,
  245. void __iomem *previous)
  246. {
  247. if (!smbios_table)
  248. return NULL;
  249. if (!previous) {
  250. previous = smbios_start;
  251. } else {
  252. previous = get_subsequent_smbios_entry(smbios_start,
  253. smbios_table, previous);
  254. }
  255. while (previous) {
  256. if (readb(previous + SMBIOS_GENERIC_TYPE) != type) {
  257. previous = get_subsequent_smbios_entry(smbios_start,
  258. smbios_table, previous);
  259. } else {
  260. break;
  261. }
  262. }
  263. return previous;
  264. }
  265. static void release_slot(struct hotplug_slot *hotplug_slot)
  266. {
  267. struct slot *slot = hotplug_slot->private;
  268. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  269. kfree(slot->hotplug_slot->info);
  270. kfree(slot->hotplug_slot->name);
  271. kfree(slot->hotplug_slot);
  272. kfree(slot);
  273. }
  274. static int ctrl_slot_setup(struct controller *ctrl,
  275. void __iomem *smbios_start,
  276. void __iomem *smbios_table)
  277. {
  278. struct slot *new_slot;
  279. u8 number_of_slots;
  280. u8 slot_device;
  281. u8 slot_number;
  282. u8 ctrl_slot;
  283. u32 tempdword;
  284. void __iomem *slot_entry= NULL;
  285. int result = -ENOMEM;
  286. dbg("%s\n", __FUNCTION__);
  287. tempdword = readl(ctrl->hpc_reg + INT_INPUT_CLEAR);
  288. number_of_slots = readb(ctrl->hpc_reg + SLOT_MASK) & 0x0F;
  289. slot_device = readb(ctrl->hpc_reg + SLOT_MASK) >> 4;
  290. slot_number = ctrl->first_slot;
  291. while (number_of_slots) {
  292. new_slot = kmalloc(sizeof(*new_slot), GFP_KERNEL);
  293. if (!new_slot)
  294. goto error;
  295. memset(new_slot, 0, sizeof(struct slot));
  296. new_slot->hotplug_slot = kmalloc(sizeof(*(new_slot->hotplug_slot)),
  297. GFP_KERNEL);
  298. if (!new_slot->hotplug_slot)
  299. goto error_slot;
  300. memset(new_slot->hotplug_slot, 0, sizeof(struct hotplug_slot));
  301. new_slot->hotplug_slot->info =
  302. kmalloc(sizeof(*(new_slot->hotplug_slot->info)),
  303. GFP_KERNEL);
  304. if (!new_slot->hotplug_slot->info)
  305. goto error_hpslot;
  306. memset(new_slot->hotplug_slot->info, 0,
  307. sizeof(struct hotplug_slot_info));
  308. new_slot->hotplug_slot->name = kmalloc(SLOT_NAME_SIZE, GFP_KERNEL);
  309. if (!new_slot->hotplug_slot->name)
  310. goto error_info;
  311. new_slot->ctrl = ctrl;
  312. new_slot->bus = ctrl->bus;
  313. new_slot->device = slot_device;
  314. new_slot->number = slot_number;
  315. dbg("slot->number = %d\n",new_slot->number);
  316. slot_entry = get_SMBIOS_entry(smbios_start, smbios_table, 9,
  317. slot_entry);
  318. while (slot_entry && (readw(slot_entry + SMBIOS_SLOT_NUMBER) != new_slot->number)) {
  319. slot_entry = get_SMBIOS_entry(smbios_start,
  320. smbios_table, 9, slot_entry);
  321. }
  322. new_slot->p_sm_slot = slot_entry;
  323. init_timer(&new_slot->task_event);
  324. new_slot->task_event.expires = jiffies + 5 * HZ;
  325. new_slot->task_event.function = cpqhp_pushbutton_thread;
  326. //FIXME: these capabilities aren't used but if they are
  327. // they need to be correctly implemented
  328. new_slot->capabilities |= PCISLOT_REPLACE_SUPPORTED;
  329. new_slot->capabilities |= PCISLOT_INTERLOCK_SUPPORTED;
  330. if (is_slot64bit(new_slot))
  331. new_slot->capabilities |= PCISLOT_64_BIT_SUPPORTED;
  332. if (is_slot66mhz(new_slot))
  333. new_slot->capabilities |= PCISLOT_66_MHZ_SUPPORTED;
  334. if (ctrl->speed == PCI_SPEED_66MHz)
  335. new_slot->capabilities |= PCISLOT_66_MHZ_OPERATION;
  336. ctrl_slot = slot_device - (readb(ctrl->hpc_reg + SLOT_MASK) >> 4);
  337. // Check presence
  338. new_slot->capabilities |= ((((~tempdword) >> 23) | ((~tempdword) >> 15)) >> ctrl_slot) & 0x02;
  339. // Check the switch state
  340. new_slot->capabilities |= ((~tempdword & 0xFF) >> ctrl_slot) & 0x01;
  341. // Check the slot enable
  342. new_slot->capabilities |= ((read_slot_enable(ctrl) << 2) >> ctrl_slot) & 0x04;
  343. /* register this slot with the hotplug pci core */
  344. new_slot->hotplug_slot->release = &release_slot;
  345. new_slot->hotplug_slot->private = new_slot;
  346. make_slot_name(new_slot->hotplug_slot->name, SLOT_NAME_SIZE, new_slot);
  347. new_slot->hotplug_slot->ops = &cpqphp_hotplug_slot_ops;
  348. new_slot->hotplug_slot->info->power_status = get_slot_enabled(ctrl, new_slot);
  349. new_slot->hotplug_slot->info->attention_status = cpq_get_attention_status(ctrl, new_slot);
  350. new_slot->hotplug_slot->info->latch_status = cpq_get_latch_status(ctrl, new_slot);
  351. new_slot->hotplug_slot->info->adapter_status = get_presence_status(ctrl, new_slot);
  352. dbg ("registering bus %d, dev %d, number %d, "
  353. "ctrl->slot_device_offset %d, slot %d\n",
  354. new_slot->bus, new_slot->device,
  355. new_slot->number, ctrl->slot_device_offset,
  356. slot_number);
  357. result = pci_hp_register (new_slot->hotplug_slot);
  358. if (result) {
  359. err ("pci_hp_register failed with error %d\n", result);
  360. goto error_name;
  361. }
  362. new_slot->next = ctrl->slot;
  363. ctrl->slot = new_slot;
  364. number_of_slots--;
  365. slot_device++;
  366. slot_number++;
  367. }
  368. return 0;
  369. error_name:
  370. kfree(new_slot->hotplug_slot->name);
  371. error_info:
  372. kfree(new_slot->hotplug_slot->info);
  373. error_hpslot:
  374. kfree(new_slot->hotplug_slot);
  375. error_slot:
  376. kfree(new_slot);
  377. error:
  378. return result;
  379. }
  380. static int ctrl_slot_cleanup (struct controller * ctrl)
  381. {
  382. struct slot *old_slot, *next_slot;
  383. old_slot = ctrl->slot;
  384. ctrl->slot = NULL;
  385. while (old_slot) {
  386. /* memory will be freed by the release_slot callback */
  387. next_slot = old_slot->next;
  388. pci_hp_deregister (old_slot->hotplug_slot);
  389. old_slot = next_slot;
  390. }
  391. //Free IRQ associated with hot plug device
  392. free_irq(ctrl->interrupt, ctrl);
  393. //Unmap the memory
  394. iounmap(ctrl->hpc_reg);
  395. //Finally reclaim PCI mem
  396. release_mem_region(pci_resource_start(ctrl->pci_dev, 0),
  397. pci_resource_len(ctrl->pci_dev, 0));
  398. return(0);
  399. }
  400. //============================================================================
  401. // function: get_slot_mapping
  402. //
  403. // Description: Attempts to determine a logical slot mapping for a PCI
  404. // device. Won't work for more than one PCI-PCI bridge
  405. // in a slot.
  406. //
  407. // Input: u8 bus_num - bus number of PCI device
  408. // u8 dev_num - device number of PCI device
  409. // u8 *slot - Pointer to u8 where slot number will
  410. // be returned
  411. //
  412. // Output: SUCCESS or FAILURE
  413. //=============================================================================
  414. static int
  415. get_slot_mapping(struct pci_bus *bus, u8 bus_num, u8 dev_num, u8 *slot)
  416. {
  417. struct irq_routing_table *PCIIRQRoutingInfoLength;
  418. u32 work;
  419. long len;
  420. long loop;
  421. u8 tbus, tdevice, tslot, bridgeSlot;
  422. dbg("%s: %p, %d, %d, %p\n", __FUNCTION__, bus, bus_num, dev_num, slot);
  423. bridgeSlot = 0xFF;
  424. PCIIRQRoutingInfoLength = pcibios_get_irq_routing_table();
  425. if (!PCIIRQRoutingInfoLength)
  426. return -1;
  427. len = (PCIIRQRoutingInfoLength->size -
  428. sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
  429. // Make sure I got at least one entry
  430. if (len == 0) {
  431. kfree(PCIIRQRoutingInfoLength);
  432. return -1;
  433. }
  434. for (loop = 0; loop < len; ++loop) {
  435. tbus = PCIIRQRoutingInfoLength->slots[loop].bus;
  436. tdevice = PCIIRQRoutingInfoLength->slots[loop].devfn >> 3;
  437. tslot = PCIIRQRoutingInfoLength->slots[loop].slot;
  438. if ((tbus == bus_num) && (tdevice == dev_num)) {
  439. *slot = tslot;
  440. kfree(PCIIRQRoutingInfoLength);
  441. return 0;
  442. } else {
  443. /* Did not get a match on the target PCI device. Check
  444. * if the current IRQ table entry is a PCI-to-PCI bridge
  445. * device. If so, and it's secondary bus matches the
  446. * bus number for the target device, I need to save the
  447. * bridge's slot number. If I can not find an entry for
  448. * the target device, I will have to assume it's on the
  449. * other side of the bridge, and assign it the bridge's
  450. * slot. */
  451. bus->number = tbus;
  452. pci_bus_read_config_dword(bus, PCI_DEVFN(tdevice, 0),
  453. PCI_REVISION_ID, &work);
  454. if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
  455. pci_bus_read_config_dword(bus,
  456. PCI_DEVFN(tdevice, 0),
  457. PCI_PRIMARY_BUS, &work);
  458. // See if bridge's secondary bus matches target bus.
  459. if (((work >> 8) & 0x000000FF) == (long) bus_num) {
  460. bridgeSlot = tslot;
  461. }
  462. }
  463. }
  464. }
  465. // If we got here, we didn't find an entry in the IRQ mapping table
  466. // for the target PCI device. If we did determine that the target
  467. // device is on the other side of a PCI-to-PCI bridge, return the
  468. // slot number for the bridge.
  469. if (bridgeSlot != 0xFF) {
  470. *slot = bridgeSlot;
  471. kfree(PCIIRQRoutingInfoLength);
  472. return 0;
  473. }
  474. kfree(PCIIRQRoutingInfoLength);
  475. // Couldn't find an entry in the routing table for this PCI device
  476. return -1;
  477. }
  478. /**
  479. * cpqhp_set_attention_status - Turns the Amber LED for a slot on or off
  480. *
  481. */
  482. static int
  483. cpqhp_set_attention_status(struct controller *ctrl, struct pci_func *func,
  484. u32 status)
  485. {
  486. u8 hp_slot;
  487. if (func == NULL)
  488. return(1);
  489. hp_slot = func->device - ctrl->slot_device_offset;
  490. // Wait for exclusive access to hardware
  491. down(&ctrl->crit_sect);
  492. if (status == 1) {
  493. amber_LED_on (ctrl, hp_slot);
  494. } else if (status == 0) {
  495. amber_LED_off (ctrl, hp_slot);
  496. } else {
  497. // Done with exclusive hardware access
  498. up(&ctrl->crit_sect);
  499. return(1);
  500. }
  501. set_SOGO(ctrl);
  502. // Wait for SOBS to be unset
  503. wait_for_ctrl_irq (ctrl);
  504. // Done with exclusive hardware access
  505. up(&ctrl->crit_sect);
  506. return(0);
  507. }
  508. /**
  509. * set_attention_status - Turns the Amber LED for a slot on or off
  510. *
  511. */
  512. static int set_attention_status (struct hotplug_slot *hotplug_slot, u8 status)
  513. {
  514. struct pci_func *slot_func;
  515. struct slot *slot = hotplug_slot->private;
  516. struct controller *ctrl = slot->ctrl;
  517. u8 bus;
  518. u8 devfn;
  519. u8 device;
  520. u8 function;
  521. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  522. if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1)
  523. return -ENODEV;
  524. device = devfn >> 3;
  525. function = devfn & 0x7;
  526. dbg("bus, dev, fn = %d, %d, %d\n", bus, device, function);
  527. slot_func = cpqhp_slot_find(bus, device, function);
  528. if (!slot_func)
  529. return -ENODEV;
  530. return cpqhp_set_attention_status(ctrl, slot_func, status);
  531. }
  532. static int process_SI(struct hotplug_slot *hotplug_slot)
  533. {
  534. struct pci_func *slot_func;
  535. struct slot *slot = hotplug_slot->private;
  536. struct controller *ctrl = slot->ctrl;
  537. u8 bus;
  538. u8 devfn;
  539. u8 device;
  540. u8 function;
  541. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  542. if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1)
  543. return -ENODEV;
  544. device = devfn >> 3;
  545. function = devfn & 0x7;
  546. dbg("bus, dev, fn = %d, %d, %d\n", bus, device, function);
  547. slot_func = cpqhp_slot_find(bus, device, function);
  548. if (!slot_func)
  549. return -ENODEV;
  550. slot_func->bus = bus;
  551. slot_func->device = device;
  552. slot_func->function = function;
  553. slot_func->configured = 0;
  554. dbg("board_added(%p, %p)\n", slot_func, ctrl);
  555. return cpqhp_process_SI(ctrl, slot_func);
  556. }
  557. static int process_SS(struct hotplug_slot *hotplug_slot)
  558. {
  559. struct pci_func *slot_func;
  560. struct slot *slot = hotplug_slot->private;
  561. struct controller *ctrl = slot->ctrl;
  562. u8 bus;
  563. u8 devfn;
  564. u8 device;
  565. u8 function;
  566. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  567. if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1)
  568. return -ENODEV;
  569. device = devfn >> 3;
  570. function = devfn & 0x7;
  571. dbg("bus, dev, fn = %d, %d, %d\n", bus, device, function);
  572. slot_func = cpqhp_slot_find(bus, device, function);
  573. if (!slot_func)
  574. return -ENODEV;
  575. dbg("In %s, slot_func = %p, ctrl = %p\n", __FUNCTION__, slot_func, ctrl);
  576. return cpqhp_process_SS(ctrl, slot_func);
  577. }
  578. static int hardware_test(struct hotplug_slot *hotplug_slot, u32 value)
  579. {
  580. struct slot *slot = hotplug_slot->private;
  581. struct controller *ctrl = slot->ctrl;
  582. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  583. return cpqhp_hardware_test(ctrl, value);
  584. }
  585. static int get_power_status(struct hotplug_slot *hotplug_slot, u8 *value)
  586. {
  587. struct slot *slot = hotplug_slot->private;
  588. struct controller *ctrl = slot->ctrl;
  589. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  590. *value = get_slot_enabled(ctrl, slot);
  591. return 0;
  592. }
  593. static int get_attention_status(struct hotplug_slot *hotplug_slot, u8 *value)
  594. {
  595. struct slot *slot = hotplug_slot->private;
  596. struct controller *ctrl = slot->ctrl;
  597. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  598. *value = cpq_get_attention_status(ctrl, slot);
  599. return 0;
  600. }
  601. static int get_latch_status(struct hotplug_slot *hotplug_slot, u8 *value)
  602. {
  603. struct slot *slot = hotplug_slot->private;
  604. struct controller *ctrl = slot->ctrl;
  605. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  606. *value = cpq_get_latch_status(ctrl, slot);
  607. return 0;
  608. }
  609. static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 *value)
  610. {
  611. struct slot *slot = hotplug_slot->private;
  612. struct controller *ctrl = slot->ctrl;
  613. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  614. *value = get_presence_status(ctrl, slot);
  615. return 0;
  616. }
  617. static int get_max_bus_speed (struct hotplug_slot *hotplug_slot, enum pci_bus_speed *value)
  618. {
  619. struct slot *slot = hotplug_slot->private;
  620. struct controller *ctrl = slot->ctrl;
  621. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  622. *value = ctrl->speed_capability;
  623. return 0;
  624. }
  625. static int get_cur_bus_speed (struct hotplug_slot *hotplug_slot, enum pci_bus_speed *value)
  626. {
  627. struct slot *slot = hotplug_slot->private;
  628. struct controller *ctrl = slot->ctrl;
  629. dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
  630. *value = ctrl->speed;
  631. return 0;
  632. }
  633. static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  634. {
  635. u8 num_of_slots = 0;
  636. u8 hp_slot = 0;
  637. u8 device;
  638. u8 rev;
  639. u8 bus_cap;
  640. u16 temp_word;
  641. u16 vendor_id;
  642. u16 subsystem_vid;
  643. u16 subsystem_deviceid;
  644. u32 rc;
  645. struct controller *ctrl;
  646. struct pci_func *func;
  647. // Need to read VID early b/c it's used to differentiate CPQ and INTC discovery
  648. rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id);
  649. if (rc || ((vendor_id != PCI_VENDOR_ID_COMPAQ) && (vendor_id != PCI_VENDOR_ID_INTEL))) {
  650. err(msg_HPC_non_compaq_or_intel);
  651. return -ENODEV;
  652. }
  653. dbg("Vendor ID: %x\n", vendor_id);
  654. rc = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  655. dbg("revision: %d\n", rev);
  656. if (rc || ((vendor_id == PCI_VENDOR_ID_COMPAQ) && (!rev))) {
  657. err(msg_HPC_rev_error);
  658. return -ENODEV;
  659. }
  660. /* Check for the proper subsytem ID's
  661. * Intel uses a different SSID programming model than Compaq.
  662. * For Intel, each SSID bit identifies a PHP capability.
  663. * Also Intel HPC's may have RID=0.
  664. */
  665. if ((rev > 2) || (vendor_id == PCI_VENDOR_ID_INTEL)) {
  666. // TODO: This code can be made to support non-Compaq or Intel subsystem IDs
  667. rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vid);
  668. if (rc) {
  669. err("%s : pci_read_config_word failed\n", __FUNCTION__);
  670. return rc;
  671. }
  672. dbg("Subsystem Vendor ID: %x\n", subsystem_vid);
  673. if ((subsystem_vid != PCI_VENDOR_ID_COMPAQ) && (subsystem_vid != PCI_VENDOR_ID_INTEL)) {
  674. err(msg_HPC_non_compaq_or_intel);
  675. return -ENODEV;
  676. }
  677. ctrl = (struct controller *) kmalloc(sizeof(struct controller), GFP_KERNEL);
  678. if (!ctrl) {
  679. err("%s : out of memory\n", __FUNCTION__);
  680. return -ENOMEM;
  681. }
  682. memset(ctrl, 0, sizeof(struct controller));
  683. rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsystem_deviceid);
  684. if (rc) {
  685. err("%s : pci_read_config_word failed\n", __FUNCTION__);
  686. goto err_free_ctrl;
  687. }
  688. info("Hot Plug Subsystem Device ID: %x\n", subsystem_deviceid);
  689. /* Set Vendor ID, so it can be accessed later from other functions */
  690. ctrl->vendor_id = vendor_id;
  691. switch (subsystem_vid) {
  692. case PCI_VENDOR_ID_COMPAQ:
  693. if (rev >= 0x13) { /* CIOBX */
  694. ctrl->push_flag = 1;
  695. ctrl->slot_switch_type = 1;
  696. ctrl->push_button = 1;
  697. ctrl->pci_config_space = 1;
  698. ctrl->defeature_PHP = 1;
  699. ctrl->pcix_support = 1;
  700. ctrl->pcix_speed_capability = 1;
  701. pci_read_config_byte(pdev, 0x41, &bus_cap);
  702. if (bus_cap & 0x80) {
  703. dbg("bus max supports 133MHz PCI-X\n");
  704. ctrl->speed_capability = PCI_SPEED_133MHz_PCIX;
  705. break;
  706. }
  707. if (bus_cap & 0x40) {
  708. dbg("bus max supports 100MHz PCI-X\n");
  709. ctrl->speed_capability = PCI_SPEED_100MHz_PCIX;
  710. break;
  711. }
  712. if (bus_cap & 20) {
  713. dbg("bus max supports 66MHz PCI-X\n");
  714. ctrl->speed_capability = PCI_SPEED_66MHz_PCIX;
  715. break;
  716. }
  717. if (bus_cap & 10) {
  718. dbg("bus max supports 66MHz PCI\n");
  719. ctrl->speed_capability = PCI_SPEED_66MHz;
  720. break;
  721. }
  722. break;
  723. }
  724. switch (subsystem_deviceid) {
  725. case PCI_SUB_HPC_ID:
  726. /* Original 6500/7000 implementation */
  727. ctrl->slot_switch_type = 1;
  728. ctrl->speed_capability = PCI_SPEED_33MHz;
  729. ctrl->push_button = 0;
  730. ctrl->pci_config_space = 1;
  731. ctrl->defeature_PHP = 1;
  732. ctrl->pcix_support = 0;
  733. ctrl->pcix_speed_capability = 0;
  734. break;
  735. case PCI_SUB_HPC_ID2:
  736. /* First Pushbutton implementation */
  737. ctrl->push_flag = 1;
  738. ctrl->slot_switch_type = 1;
  739. ctrl->speed_capability = PCI_SPEED_33MHz;
  740. ctrl->push_button = 1;
  741. ctrl->pci_config_space = 1;
  742. ctrl->defeature_PHP = 1;
  743. ctrl->pcix_support = 0;
  744. ctrl->pcix_speed_capability = 0;
  745. break;
  746. case PCI_SUB_HPC_ID_INTC:
  747. /* Third party (6500/7000) */
  748. ctrl->slot_switch_type = 1;
  749. ctrl->speed_capability = PCI_SPEED_33MHz;
  750. ctrl->push_button = 0;
  751. ctrl->pci_config_space = 1;
  752. ctrl->defeature_PHP = 1;
  753. ctrl->pcix_support = 0;
  754. ctrl->pcix_speed_capability = 0;
  755. break;
  756. case PCI_SUB_HPC_ID3:
  757. /* First 66 Mhz implementation */
  758. ctrl->push_flag = 1;
  759. ctrl->slot_switch_type = 1;
  760. ctrl->speed_capability = PCI_SPEED_66MHz;
  761. ctrl->push_button = 1;
  762. ctrl->pci_config_space = 1;
  763. ctrl->defeature_PHP = 1;
  764. ctrl->pcix_support = 0;
  765. ctrl->pcix_speed_capability = 0;
  766. break;
  767. case PCI_SUB_HPC_ID4:
  768. /* First PCI-X implementation, 100MHz */
  769. ctrl->push_flag = 1;
  770. ctrl->slot_switch_type = 1;
  771. ctrl->speed_capability = PCI_SPEED_100MHz_PCIX;
  772. ctrl->push_button = 1;
  773. ctrl->pci_config_space = 1;
  774. ctrl->defeature_PHP = 1;
  775. ctrl->pcix_support = 1;
  776. ctrl->pcix_speed_capability = 0;
  777. break;
  778. default:
  779. err(msg_HPC_not_supported);
  780. rc = -ENODEV;
  781. goto err_free_ctrl;
  782. }
  783. break;
  784. case PCI_VENDOR_ID_INTEL:
  785. /* Check for speed capability (0=33, 1=66) */
  786. if (subsystem_deviceid & 0x0001) {
  787. ctrl->speed_capability = PCI_SPEED_66MHz;
  788. } else {
  789. ctrl->speed_capability = PCI_SPEED_33MHz;
  790. }
  791. /* Check for push button */
  792. if (subsystem_deviceid & 0x0002) {
  793. /* no push button */
  794. ctrl->push_button = 0;
  795. } else {
  796. /* push button supported */
  797. ctrl->push_button = 1;
  798. }
  799. /* Check for slot switch type (0=mechanical, 1=not mechanical) */
  800. if (subsystem_deviceid & 0x0004) {
  801. /* no switch */
  802. ctrl->slot_switch_type = 0;
  803. } else {
  804. /* switch */
  805. ctrl->slot_switch_type = 1;
  806. }
  807. /* PHP Status (0=De-feature PHP, 1=Normal operation) */
  808. if (subsystem_deviceid & 0x0008) {
  809. ctrl->defeature_PHP = 1; // PHP supported
  810. } else {
  811. ctrl->defeature_PHP = 0; // PHP not supported
  812. }
  813. /* Alternate Base Address Register Interface (0=not supported, 1=supported) */
  814. if (subsystem_deviceid & 0x0010) {
  815. ctrl->alternate_base_address = 1; // supported
  816. } else {
  817. ctrl->alternate_base_address = 0; // not supported
  818. }
  819. /* PCI Config Space Index (0=not supported, 1=supported) */
  820. if (subsystem_deviceid & 0x0020) {
  821. ctrl->pci_config_space = 1; // supported
  822. } else {
  823. ctrl->pci_config_space = 0; // not supported
  824. }
  825. /* PCI-X support */
  826. if (subsystem_deviceid & 0x0080) {
  827. /* PCI-X capable */
  828. ctrl->pcix_support = 1;
  829. /* Frequency of operation in PCI-X mode */
  830. if (subsystem_deviceid & 0x0040) {
  831. /* 133MHz PCI-X if bit 7 is 1 */
  832. ctrl->pcix_speed_capability = 1;
  833. } else {
  834. /* 100MHz PCI-X if bit 7 is 1 and bit 0 is 0, */
  835. /* 66MHz PCI-X if bit 7 is 1 and bit 0 is 1 */
  836. ctrl->pcix_speed_capability = 0;
  837. }
  838. } else {
  839. /* Conventional PCI */
  840. ctrl->pcix_support = 0;
  841. ctrl->pcix_speed_capability = 0;
  842. }
  843. break;
  844. default:
  845. err(msg_HPC_not_supported);
  846. rc = -ENODEV;
  847. goto err_free_ctrl;
  848. }
  849. } else {
  850. err(msg_HPC_not_supported);
  851. return -ENODEV;
  852. }
  853. // Tell the user that we found one.
  854. info("Initializing the PCI hot plug controller residing on PCI bus %d\n",
  855. pdev->bus->number);
  856. dbg("Hotplug controller capabilities:\n");
  857. dbg(" speed_capability %d\n", ctrl->speed_capability);
  858. dbg(" slot_switch_type %s\n", ctrl->slot_switch_type ?
  859. "switch present" : "no switch");
  860. dbg(" defeature_PHP %s\n", ctrl->defeature_PHP ?
  861. "PHP supported" : "PHP not supported");
  862. dbg(" alternate_base_address %s\n", ctrl->alternate_base_address ?
  863. "supported" : "not supported");
  864. dbg(" pci_config_space %s\n", ctrl->pci_config_space ?
  865. "supported" : "not supported");
  866. dbg(" pcix_speed_capability %s\n", ctrl->pcix_speed_capability ?
  867. "supported" : "not supported");
  868. dbg(" pcix_support %s\n", ctrl->pcix_support ?
  869. "supported" : "not supported");
  870. ctrl->pci_dev = pdev;
  871. pci_set_drvdata(pdev, ctrl);
  872. /* make our own copy of the pci bus structure,
  873. * as we like tweaking it a lot */
  874. ctrl->pci_bus = kmalloc(sizeof(*ctrl->pci_bus), GFP_KERNEL);
  875. if (!ctrl->pci_bus) {
  876. err("out of memory\n");
  877. rc = -ENOMEM;
  878. goto err_free_ctrl;
  879. }
  880. memcpy(ctrl->pci_bus, pdev->bus, sizeof(*ctrl->pci_bus));
  881. ctrl->bus = pdev->bus->number;
  882. ctrl->rev = rev;
  883. dbg("bus device function rev: %d %d %d %d\n", ctrl->bus,
  884. PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), ctrl->rev);
  885. init_MUTEX(&ctrl->crit_sect);
  886. init_waitqueue_head(&ctrl->queue);
  887. /* initialize our threads if they haven't already been started up */
  888. rc = one_time_init();
  889. if (rc) {
  890. goto err_free_bus;
  891. }
  892. dbg("pdev = %p\n", pdev);
  893. dbg("pci resource start %lx\n", pci_resource_start(pdev, 0));
  894. dbg("pci resource len %lx\n", pci_resource_len(pdev, 0));
  895. if (!request_mem_region(pci_resource_start(pdev, 0),
  896. pci_resource_len(pdev, 0), MY_NAME)) {
  897. err("cannot reserve MMIO region\n");
  898. rc = -ENOMEM;
  899. goto err_free_bus;
  900. }
  901. ctrl->hpc_reg = ioremap(pci_resource_start(pdev, 0),
  902. pci_resource_len(pdev, 0));
  903. if (!ctrl->hpc_reg) {
  904. err("cannot remap MMIO region %lx @ %lx\n",
  905. pci_resource_len(pdev, 0),
  906. pci_resource_start(pdev, 0));
  907. rc = -ENODEV;
  908. goto err_free_mem_region;
  909. }
  910. // Check for 66Mhz operation
  911. ctrl->speed = get_controller_speed(ctrl);
  912. /********************************************************
  913. *
  914. * Save configuration headers for this and
  915. * subordinate PCI buses
  916. *
  917. ********************************************************/
  918. // find the physical slot number of the first hot plug slot
  919. /* Get slot won't work for devices behind bridges, but
  920. * in this case it will always be called for the "base"
  921. * bus/dev/func of a slot.
  922. * CS: this is leveraging the PCIIRQ routing code from the kernel
  923. * (pci-pc.c: get_irq_routing_table) */
  924. rc = get_slot_mapping(ctrl->pci_bus, pdev->bus->number,
  925. (readb(ctrl->hpc_reg + SLOT_MASK) >> 4),
  926. &(ctrl->first_slot));
  927. dbg("get_slot_mapping: first_slot = %d, returned = %d\n",
  928. ctrl->first_slot, rc);
  929. if (rc) {
  930. err(msg_initialization_err, rc);
  931. goto err_iounmap;
  932. }
  933. // Store PCI Config Space for all devices on this bus
  934. rc = cpqhp_save_config(ctrl, ctrl->bus, readb(ctrl->hpc_reg + SLOT_MASK));
  935. if (rc) {
  936. err("%s: unable to save PCI configuration data, error %d\n",
  937. __FUNCTION__, rc);
  938. goto err_iounmap;
  939. }
  940. /*
  941. * Get IO, memory, and IRQ resources for new devices
  942. */
  943. // The next line is required for cpqhp_find_available_resources
  944. ctrl->interrupt = pdev->irq;
  945. if (ctrl->interrupt < 0x10) {
  946. cpqhp_legacy_mode = 1;
  947. dbg("System seems to be configured for Full Table Mapped MPS mode\n");
  948. }
  949. ctrl->cfgspc_irq = 0;
  950. pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &ctrl->cfgspc_irq);
  951. rc = cpqhp_find_available_resources(ctrl, cpqhp_rom_start);
  952. ctrl->add_support = !rc;
  953. if (rc) {
  954. dbg("cpqhp_find_available_resources = 0x%x\n", rc);
  955. err("unable to locate PCI configuration resources for hot plug add.\n");
  956. goto err_iounmap;
  957. }
  958. /*
  959. * Finish setting up the hot plug ctrl device
  960. */
  961. ctrl->slot_device_offset = readb(ctrl->hpc_reg + SLOT_MASK) >> 4;
  962. dbg("NumSlots %d \n", ctrl->slot_device_offset);
  963. ctrl->next_event = 0;
  964. /* Setup the slot information structures */
  965. rc = ctrl_slot_setup(ctrl, smbios_start, smbios_table);
  966. if (rc) {
  967. err(msg_initialization_err, 6);
  968. err("%s: unable to save PCI configuration data, error %d\n",
  969. __FUNCTION__, rc);
  970. goto err_iounmap;
  971. }
  972. /* Mask all general input interrupts */
  973. writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_MASK);
  974. /* set up the interrupt */
  975. dbg("HPC interrupt = %d \n", ctrl->interrupt);
  976. if (request_irq(ctrl->interrupt, cpqhp_ctrl_intr,
  977. SA_SHIRQ, MY_NAME, ctrl)) {
  978. err("Can't get irq %d for the hotplug pci controller\n",
  979. ctrl->interrupt);
  980. rc = -ENODEV;
  981. goto err_iounmap;
  982. }
  983. /* Enable Shift Out interrupt and clear it, also enable SERR on power fault */
  984. temp_word = readw(ctrl->hpc_reg + MISC);
  985. temp_word |= 0x4006;
  986. writew(temp_word, ctrl->hpc_reg + MISC);
  987. // Changed 05/05/97 to clear all interrupts at start
  988. writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_INPUT_CLEAR);
  989. ctrl->ctrl_int_comp = readl(ctrl->hpc_reg + INT_INPUT_CLEAR);
  990. writel(0x0L, ctrl->hpc_reg + INT_MASK);
  991. if (!cpqhp_ctrl_list) {
  992. cpqhp_ctrl_list = ctrl;
  993. ctrl->next = NULL;
  994. } else {
  995. ctrl->next = cpqhp_ctrl_list;
  996. cpqhp_ctrl_list = ctrl;
  997. }
  998. // turn off empty slots here unless command line option "ON" set
  999. // Wait for exclusive access to hardware
  1000. down(&ctrl->crit_sect);
  1001. num_of_slots = readb(ctrl->hpc_reg + SLOT_MASK) & 0x0F;
  1002. // find first device number for the ctrl
  1003. device = readb(ctrl->hpc_reg + SLOT_MASK) >> 4;
  1004. while (num_of_slots) {
  1005. dbg("num_of_slots: %d\n", num_of_slots);
  1006. func = cpqhp_slot_find(ctrl->bus, device, 0);
  1007. if (!func)
  1008. break;
  1009. hp_slot = func->device - ctrl->slot_device_offset;
  1010. dbg("hp_slot: %d\n", hp_slot);
  1011. // We have to save the presence info for these slots
  1012. temp_word = ctrl->ctrl_int_comp >> 16;
  1013. func->presence_save = (temp_word >> hp_slot) & 0x01;
  1014. func->presence_save |= (temp_word >> (hp_slot + 7)) & 0x02;
  1015. if (ctrl->ctrl_int_comp & (0x1L << hp_slot)) {
  1016. func->switch_save = 0;
  1017. } else {
  1018. func->switch_save = 0x10;
  1019. }
  1020. if (!power_mode) {
  1021. if (!func->is_a_board) {
  1022. green_LED_off(ctrl, hp_slot);
  1023. slot_disable(ctrl, hp_slot);
  1024. }
  1025. }
  1026. device++;
  1027. num_of_slots--;
  1028. }
  1029. if (!power_mode) {
  1030. set_SOGO(ctrl);
  1031. // Wait for SOBS to be unset
  1032. wait_for_ctrl_irq(ctrl);
  1033. }
  1034. rc = init_SERR(ctrl);
  1035. if (rc) {
  1036. err("init_SERR failed\n");
  1037. up(&ctrl->crit_sect);
  1038. goto err_free_irq;
  1039. }
  1040. // Done with exclusive hardware access
  1041. up(&ctrl->crit_sect);
  1042. cpqhp_create_ctrl_files(ctrl);
  1043. return 0;
  1044. err_free_irq:
  1045. free_irq(ctrl->interrupt, ctrl);
  1046. err_iounmap:
  1047. iounmap(ctrl->hpc_reg);
  1048. err_free_mem_region:
  1049. release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  1050. err_free_bus:
  1051. kfree(ctrl->pci_bus);
  1052. err_free_ctrl:
  1053. kfree(ctrl);
  1054. return rc;
  1055. }
  1056. static int one_time_init(void)
  1057. {
  1058. int loop;
  1059. int retval = 0;
  1060. if (initialized)
  1061. return 0;
  1062. power_mode = 0;
  1063. retval = pci_print_IRQ_route();
  1064. if (retval)
  1065. goto error;
  1066. dbg("Initialize + Start the notification mechanism \n");
  1067. retval = cpqhp_event_start_thread();
  1068. if (retval)
  1069. goto error;
  1070. dbg("Initialize slot lists\n");
  1071. for (loop = 0; loop < 256; loop++) {
  1072. cpqhp_slot_list[loop] = NULL;
  1073. }
  1074. // FIXME: We also need to hook the NMI handler eventually.
  1075. // this also needs to be worked with Christoph
  1076. // register_NMI_handler();
  1077. // Map rom address
  1078. cpqhp_rom_start = ioremap(ROM_PHY_ADDR, ROM_PHY_LEN);
  1079. if (!cpqhp_rom_start) {
  1080. err ("Could not ioremap memory region for ROM\n");
  1081. retval = -EIO;
  1082. goto error;
  1083. }
  1084. /* Now, map the int15 entry point if we are on compaq specific hardware */
  1085. compaq_nvram_init(cpqhp_rom_start);
  1086. /* Map smbios table entry point structure */
  1087. smbios_table = detect_SMBIOS_pointer(cpqhp_rom_start,
  1088. cpqhp_rom_start + ROM_PHY_LEN);
  1089. if (!smbios_table) {
  1090. err ("Could not find the SMBIOS pointer in memory\n");
  1091. retval = -EIO;
  1092. goto error_rom_start;
  1093. }
  1094. smbios_start = ioremap(readl(smbios_table + ST_ADDRESS),
  1095. readw(smbios_table + ST_LENGTH));
  1096. if (!smbios_start) {
  1097. err ("Could not ioremap memory region taken from SMBIOS values\n");
  1098. retval = -EIO;
  1099. goto error_smbios_start;
  1100. }
  1101. initialized = 1;
  1102. return retval;
  1103. error_smbios_start:
  1104. iounmap(smbios_start);
  1105. error_rom_start:
  1106. iounmap(cpqhp_rom_start);
  1107. error:
  1108. return retval;
  1109. }
  1110. static void __exit unload_cpqphpd(void)
  1111. {
  1112. struct pci_func *next;
  1113. struct pci_func *TempSlot;
  1114. int loop;
  1115. u32 rc;
  1116. struct controller *ctrl;
  1117. struct controller *tctrl;
  1118. struct pci_resource *res;
  1119. struct pci_resource *tres;
  1120. rc = compaq_nvram_store(cpqhp_rom_start);
  1121. ctrl = cpqhp_ctrl_list;
  1122. while (ctrl) {
  1123. if (ctrl->hpc_reg) {
  1124. u16 misc;
  1125. rc = read_slot_enable (ctrl);
  1126. writeb(0, ctrl->hpc_reg + SLOT_SERR);
  1127. writel(0xFFFFFFC0L | ~rc, ctrl->hpc_reg + INT_MASK);
  1128. misc = readw(ctrl->hpc_reg + MISC);
  1129. misc &= 0xFFFD;
  1130. writew(misc, ctrl->hpc_reg + MISC);
  1131. }
  1132. ctrl_slot_cleanup(ctrl);
  1133. res = ctrl->io_head;
  1134. while (res) {
  1135. tres = res;
  1136. res = res->next;
  1137. kfree(tres);
  1138. }
  1139. res = ctrl->mem_head;
  1140. while (res) {
  1141. tres = res;
  1142. res = res->next;
  1143. kfree(tres);
  1144. }
  1145. res = ctrl->p_mem_head;
  1146. while (res) {
  1147. tres = res;
  1148. res = res->next;
  1149. kfree(tres);
  1150. }
  1151. res = ctrl->bus_head;
  1152. while (res) {
  1153. tres = res;
  1154. res = res->next;
  1155. kfree(tres);
  1156. }
  1157. kfree (ctrl->pci_bus);
  1158. tctrl = ctrl;
  1159. ctrl = ctrl->next;
  1160. kfree(tctrl);
  1161. }
  1162. for (loop = 0; loop < 256; loop++) {
  1163. next = cpqhp_slot_list[loop];
  1164. while (next != NULL) {
  1165. res = next->io_head;
  1166. while (res) {
  1167. tres = res;
  1168. res = res->next;
  1169. kfree(tres);
  1170. }
  1171. res = next->mem_head;
  1172. while (res) {
  1173. tres = res;
  1174. res = res->next;
  1175. kfree(tres);
  1176. }
  1177. res = next->p_mem_head;
  1178. while (res) {
  1179. tres = res;
  1180. res = res->next;
  1181. kfree(tres);
  1182. }
  1183. res = next->bus_head;
  1184. while (res) {
  1185. tres = res;
  1186. res = res->next;
  1187. kfree(tres);
  1188. }
  1189. TempSlot = next;
  1190. next = next->next;
  1191. kfree(TempSlot);
  1192. }
  1193. }
  1194. // Stop the notification mechanism
  1195. if (initialized)
  1196. cpqhp_event_stop_thread();
  1197. //unmap the rom address
  1198. if (cpqhp_rom_start)
  1199. iounmap(cpqhp_rom_start);
  1200. if (smbios_start)
  1201. iounmap(smbios_start);
  1202. }
  1203. static struct pci_device_id hpcd_pci_tbl[] = {
  1204. {
  1205. /* handle any PCI Hotplug controller */
  1206. .class = ((PCI_CLASS_SYSTEM_PCI_HOTPLUG << 8) | 0x00),
  1207. .class_mask = ~0,
  1208. /* no matter who makes it */
  1209. .vendor = PCI_ANY_ID,
  1210. .device = PCI_ANY_ID,
  1211. .subvendor = PCI_ANY_ID,
  1212. .subdevice = PCI_ANY_ID,
  1213. }, { /* end: all zeroes */ }
  1214. };
  1215. MODULE_DEVICE_TABLE(pci, hpcd_pci_tbl);
  1216. static struct pci_driver cpqhpc_driver = {
  1217. .name = "compaq_pci_hotplug",
  1218. .id_table = hpcd_pci_tbl,
  1219. .probe = cpqhpc_probe,
  1220. /* remove: cpqhpc_remove_one, */
  1221. };
  1222. static int __init cpqhpc_init(void)
  1223. {
  1224. int result;
  1225. cpqhp_debug = debug;
  1226. info (DRIVER_DESC " version: " DRIVER_VERSION "\n");
  1227. result = pci_register_driver(&cpqhpc_driver);
  1228. dbg("pci_register_driver = %d\n", result);
  1229. return result;
  1230. }
  1231. static void __exit cpqhpc_cleanup(void)
  1232. {
  1233. dbg("unload_cpqphpd()\n");
  1234. unload_cpqphpd();
  1235. dbg("pci_unregister_driver\n");
  1236. pci_unregister_driver(&cpqhpc_driver);
  1237. }
  1238. module_init(cpqhpc_init);
  1239. module_exit(cpqhpc_cleanup);