islpci_dev.c 26 KB

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  1. /*
  2. *
  3. * Copyright (C) 2002 Intersil Americas Inc.
  4. * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
  5. * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <linux/version.h>
  22. #include <linux/module.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/pci.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/if_arp.h>
  28. #include <asm/io.h>
  29. #include "prismcompat.h"
  30. #include "isl_38xx.h"
  31. #include "isl_ioctl.h"
  32. #include "islpci_dev.h"
  33. #include "islpci_mgt.h"
  34. #include "islpci_eth.h"
  35. #include "oid_mgt.h"
  36. #define ISL3877_IMAGE_FILE "isl3877"
  37. #define ISL3886_IMAGE_FILE "isl3886"
  38. #define ISL3890_IMAGE_FILE "isl3890"
  39. static int prism54_bring_down(islpci_private *);
  40. static int islpci_alloc_memory(islpci_private *);
  41. static struct net_device_stats *islpci_statistics(struct net_device *);
  42. /* Temporary dummy MAC address to use until firmware is loaded.
  43. * The idea there is that some tools (such as nameif) may query
  44. * the MAC address before the netdev is 'open'. By using a valid
  45. * OUI prefix, they can process the netdev properly.
  46. * Of course, this is not the final/real MAC address. It doesn't
  47. * matter, as you are suppose to be able to change it anytime via
  48. * ndev->set_mac_address. Jean II */
  49. static const unsigned char dummy_mac[6] = { 0x00, 0x30, 0xB4, 0x00, 0x00, 0x00 };
  50. static int
  51. isl_upload_firmware(islpci_private *priv)
  52. {
  53. u32 reg, rc;
  54. void __iomem *device_base = priv->device_base;
  55. /* clear the RAMBoot and the Reset bit */
  56. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  57. reg &= ~ISL38XX_CTRL_STAT_RESET;
  58. reg &= ~ISL38XX_CTRL_STAT_RAMBOOT;
  59. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  60. wmb();
  61. udelay(ISL38XX_WRITEIO_DELAY);
  62. /* set the Reset bit without reading the register ! */
  63. reg |= ISL38XX_CTRL_STAT_RESET;
  64. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  65. wmb();
  66. udelay(ISL38XX_WRITEIO_DELAY);
  67. /* clear the Reset bit */
  68. reg &= ~ISL38XX_CTRL_STAT_RESET;
  69. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  70. wmb();
  71. /* wait a while for the device to reboot */
  72. mdelay(50);
  73. {
  74. const struct firmware *fw_entry = NULL;
  75. long fw_len;
  76. const u32 *fw_ptr;
  77. rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV);
  78. if (rc) {
  79. printk(KERN_ERR
  80. "%s: request_firmware() failed for '%s'\n",
  81. "prism54", priv->firmware);
  82. return rc;
  83. }
  84. /* prepare the Direct Memory Base register */
  85. reg = ISL38XX_DEV_FIRMWARE_ADDRES;
  86. fw_ptr = (u32 *) fw_entry->data;
  87. fw_len = fw_entry->size;
  88. if (fw_len % 4) {
  89. printk(KERN_ERR
  90. "%s: firmware '%s' size is not multiple of 32bit, aborting!\n",
  91. "prism54", priv->firmware);
  92. release_firmware(fw_entry);
  93. return -EILSEQ; /* Illegal byte sequence */;
  94. }
  95. while (fw_len > 0) {
  96. long _fw_len =
  97. (fw_len >
  98. ISL38XX_MEMORY_WINDOW_SIZE) ?
  99. ISL38XX_MEMORY_WINDOW_SIZE : fw_len;
  100. u32 __iomem *dev_fw_ptr = device_base + ISL38XX_DIRECT_MEM_WIN;
  101. /* set the cards base address for writting the data */
  102. isl38xx_w32_flush(device_base, reg,
  103. ISL38XX_DIR_MEM_BASE_REG);
  104. wmb(); /* be paranoid */
  105. /* increment the write address for next iteration */
  106. reg += _fw_len;
  107. fw_len -= _fw_len;
  108. /* write the data to the Direct Memory Window 32bit-wise */
  109. /* memcpy_toio() doesn't guarantee 32bit writes :-| */
  110. while (_fw_len > 0) {
  111. /* use non-swapping writel() */
  112. __raw_writel(*fw_ptr, dev_fw_ptr);
  113. fw_ptr++, dev_fw_ptr++;
  114. _fw_len -= 4;
  115. }
  116. /* flush PCI posting */
  117. (void) readl(device_base + ISL38XX_PCI_POSTING_FLUSH);
  118. wmb(); /* be paranoid again */
  119. BUG_ON(_fw_len != 0);
  120. }
  121. BUG_ON(fw_len != 0);
  122. /* Firmware version is at offset 40 (also for "newmac") */
  123. printk(KERN_DEBUG "%s: firmware version: %.8s\n",
  124. priv->ndev->name, fw_entry->data + 40);
  125. release_firmware(fw_entry);
  126. }
  127. /* now reset the device
  128. * clear the Reset & ClkRun bit, set the RAMBoot bit */
  129. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  130. reg &= ~ISL38XX_CTRL_STAT_CLKRUN;
  131. reg &= ~ISL38XX_CTRL_STAT_RESET;
  132. reg |= ISL38XX_CTRL_STAT_RAMBOOT;
  133. isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG);
  134. wmb();
  135. udelay(ISL38XX_WRITEIO_DELAY);
  136. /* set the reset bit latches the host override and RAMBoot bits
  137. * into the device for operation when the reset bit is reset */
  138. reg |= ISL38XX_CTRL_STAT_RESET;
  139. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  140. /* don't do flush PCI posting here! */
  141. wmb();
  142. udelay(ISL38XX_WRITEIO_DELAY);
  143. /* clear the reset bit should start the whole circus */
  144. reg &= ~ISL38XX_CTRL_STAT_RESET;
  145. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  146. /* don't do flush PCI posting here! */
  147. wmb();
  148. udelay(ISL38XX_WRITEIO_DELAY);
  149. return 0;
  150. }
  151. /******************************************************************************
  152. Device Interrupt Handler
  153. ******************************************************************************/
  154. irqreturn_t
  155. islpci_interrupt(int irq, void *config, struct pt_regs *regs)
  156. {
  157. u32 reg;
  158. islpci_private *priv = config;
  159. struct net_device *ndev = priv->ndev;
  160. void __iomem *device = priv->device_base;
  161. int powerstate = ISL38XX_PSM_POWERSAVE_STATE;
  162. /* lock the interrupt handler */
  163. spin_lock(&priv->slock);
  164. /* received an interrupt request on a shared IRQ line
  165. * first check whether the device is in sleep mode */
  166. reg = readl(device + ISL38XX_CTRL_STAT_REG);
  167. if (reg & ISL38XX_CTRL_STAT_SLEEPMODE)
  168. /* device is in sleep mode, IRQ was generated by someone else */
  169. {
  170. #if VERBOSE > SHOW_ERROR_MESSAGES
  171. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  172. #endif
  173. spin_unlock(&priv->slock);
  174. return IRQ_NONE;
  175. }
  176. /* check whether there is any source of interrupt on the device */
  177. reg = readl(device + ISL38XX_INT_IDENT_REG);
  178. /* also check the contents of the Interrupt Enable Register, because this
  179. * will filter out interrupt sources from other devices on the same irq ! */
  180. reg &= readl(device + ISL38XX_INT_EN_REG);
  181. reg &= ISL38XX_INT_SOURCES;
  182. if (reg != 0) {
  183. if (islpci_get_state(priv) != PRV_STATE_SLEEP)
  184. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  185. /* reset the request bits in the Identification register */
  186. isl38xx_w32_flush(device, reg, ISL38XX_INT_ACK_REG);
  187. #if VERBOSE > SHOW_ERROR_MESSAGES
  188. DEBUG(SHOW_FUNCTION_CALLS,
  189. "IRQ: Identification register 0x%p 0x%x \n", device, reg);
  190. #endif
  191. /* check for each bit in the register separately */
  192. if (reg & ISL38XX_INT_IDENT_UPDATE) {
  193. #if VERBOSE > SHOW_ERROR_MESSAGES
  194. /* Queue has been updated */
  195. DEBUG(SHOW_TRACING, "IRQ: Update flag \n");
  196. DEBUG(SHOW_QUEUE_INDEXES,
  197. "CB drv Qs: [%i][%i][%i][%i][%i][%i]\n",
  198. le32_to_cpu(priv->control_block->
  199. driver_curr_frag[0]),
  200. le32_to_cpu(priv->control_block->
  201. driver_curr_frag[1]),
  202. le32_to_cpu(priv->control_block->
  203. driver_curr_frag[2]),
  204. le32_to_cpu(priv->control_block->
  205. driver_curr_frag[3]),
  206. le32_to_cpu(priv->control_block->
  207. driver_curr_frag[4]),
  208. le32_to_cpu(priv->control_block->
  209. driver_curr_frag[5])
  210. );
  211. DEBUG(SHOW_QUEUE_INDEXES,
  212. "CB dev Qs: [%i][%i][%i][%i][%i][%i]\n",
  213. le32_to_cpu(priv->control_block->
  214. device_curr_frag[0]),
  215. le32_to_cpu(priv->control_block->
  216. device_curr_frag[1]),
  217. le32_to_cpu(priv->control_block->
  218. device_curr_frag[2]),
  219. le32_to_cpu(priv->control_block->
  220. device_curr_frag[3]),
  221. le32_to_cpu(priv->control_block->
  222. device_curr_frag[4]),
  223. le32_to_cpu(priv->control_block->
  224. device_curr_frag[5])
  225. );
  226. #endif
  227. /* cleanup the data low transmit queue */
  228. islpci_eth_cleanup_transmit(priv, priv->control_block);
  229. /* device is in active state, update the
  230. * powerstate flag if necessary */
  231. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  232. /* check all three queues in priority order
  233. * call the PIMFOR receive function until the
  234. * queue is empty */
  235. if (isl38xx_in_queue(priv->control_block,
  236. ISL38XX_CB_RX_MGMTQ) != 0) {
  237. #if VERBOSE > SHOW_ERROR_MESSAGES
  238. DEBUG(SHOW_TRACING,
  239. "Received frame in Management Queue\n");
  240. #endif
  241. islpci_mgt_receive(ndev);
  242. islpci_mgt_cleanup_transmit(ndev);
  243. /* Refill slots in receive queue */
  244. islpci_mgmt_rx_fill(ndev);
  245. /* no need to trigger the device, next
  246. islpci_mgt_transaction does it */
  247. }
  248. while (isl38xx_in_queue(priv->control_block,
  249. ISL38XX_CB_RX_DATA_LQ) != 0) {
  250. #if VERBOSE > SHOW_ERROR_MESSAGES
  251. DEBUG(SHOW_TRACING,
  252. "Received frame in Data Low Queue \n");
  253. #endif
  254. islpci_eth_receive(priv);
  255. }
  256. /* check whether the data transmit queues were full */
  257. if (priv->data_low_tx_full) {
  258. /* check whether the transmit is not full anymore */
  259. if (ISL38XX_CB_TX_QSIZE -
  260. isl38xx_in_queue(priv->control_block,
  261. ISL38XX_CB_TX_DATA_LQ) >=
  262. ISL38XX_MIN_QTHRESHOLD) {
  263. /* nope, the driver is ready for more network frames */
  264. netif_wake_queue(priv->ndev);
  265. /* reset the full flag */
  266. priv->data_low_tx_full = 0;
  267. }
  268. }
  269. }
  270. if (reg & ISL38XX_INT_IDENT_INIT) {
  271. /* Device has been initialized */
  272. #if VERBOSE > SHOW_ERROR_MESSAGES
  273. DEBUG(SHOW_TRACING,
  274. "IRQ: Init flag, device initialized \n");
  275. #endif
  276. wake_up(&priv->reset_done);
  277. }
  278. if (reg & ISL38XX_INT_IDENT_SLEEP) {
  279. /* Device intends to move to powersave state */
  280. #if VERBOSE > SHOW_ERROR_MESSAGES
  281. DEBUG(SHOW_TRACING, "IRQ: Sleep flag \n");
  282. #endif
  283. isl38xx_handle_sleep_request(priv->control_block,
  284. &powerstate,
  285. priv->device_base);
  286. }
  287. if (reg & ISL38XX_INT_IDENT_WAKEUP) {
  288. /* Device has been woken up to active state */
  289. #if VERBOSE > SHOW_ERROR_MESSAGES
  290. DEBUG(SHOW_TRACING, "IRQ: Wakeup flag \n");
  291. #endif
  292. isl38xx_handle_wakeup(priv->control_block,
  293. &powerstate, priv->device_base);
  294. }
  295. } else {
  296. #if VERBOSE > SHOW_ERROR_MESSAGES
  297. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  298. #endif
  299. spin_unlock(&priv->slock);
  300. return IRQ_NONE;
  301. }
  302. /* sleep -> ready */
  303. if (islpci_get_state(priv) == PRV_STATE_SLEEP
  304. && powerstate == ISL38XX_PSM_ACTIVE_STATE)
  305. islpci_set_state(priv, PRV_STATE_READY);
  306. /* !sleep -> sleep */
  307. if (islpci_get_state(priv) != PRV_STATE_SLEEP
  308. && powerstate == ISL38XX_PSM_POWERSAVE_STATE)
  309. islpci_set_state(priv, PRV_STATE_SLEEP);
  310. /* unlock the interrupt handler */
  311. spin_unlock(&priv->slock);
  312. return IRQ_HANDLED;
  313. }
  314. /******************************************************************************
  315. Network Interface Control & Statistical functions
  316. ******************************************************************************/
  317. static int
  318. islpci_open(struct net_device *ndev)
  319. {
  320. u32 rc;
  321. islpci_private *priv = netdev_priv(ndev);
  322. /* reset data structures, upload firmware and reset device */
  323. rc = islpci_reset(priv,1);
  324. if (rc) {
  325. prism54_bring_down(priv);
  326. return rc; /* Returns informative message */
  327. }
  328. netif_start_queue(ndev);
  329. /* netif_mark_up( ndev ); */
  330. return 0;
  331. }
  332. static int
  333. islpci_close(struct net_device *ndev)
  334. {
  335. islpci_private *priv = netdev_priv(ndev);
  336. printk(KERN_DEBUG "%s: islpci_close ()\n", ndev->name);
  337. netif_stop_queue(ndev);
  338. return prism54_bring_down(priv);
  339. }
  340. static int
  341. prism54_bring_down(islpci_private *priv)
  342. {
  343. void __iomem *device_base = priv->device_base;
  344. u32 reg;
  345. /* we are going to shutdown the device */
  346. islpci_set_state(priv, PRV_STATE_PREBOOT);
  347. /* disable all device interrupts in case they weren't */
  348. isl38xx_disable_interrupts(priv->device_base);
  349. /* For safety reasons, we may want to ensure that no DMA transfer is
  350. * currently in progress by emptying the TX and RX queues. */
  351. /* wait until interrupts have finished executing on other CPUs */
  352. synchronize_irq(priv->pdev->irq);
  353. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  354. reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT);
  355. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  356. wmb();
  357. udelay(ISL38XX_WRITEIO_DELAY);
  358. reg |= ISL38XX_CTRL_STAT_RESET;
  359. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  360. wmb();
  361. udelay(ISL38XX_WRITEIO_DELAY);
  362. /* clear the Reset bit */
  363. reg &= ~ISL38XX_CTRL_STAT_RESET;
  364. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  365. wmb();
  366. /* wait a while for the device to reset */
  367. set_current_state(TASK_UNINTERRUPTIBLE);
  368. schedule_timeout(50*HZ/1000);
  369. return 0;
  370. }
  371. static int
  372. islpci_upload_fw(islpci_private *priv)
  373. {
  374. islpci_state_t old_state;
  375. u32 rc;
  376. old_state = islpci_set_state(priv, PRV_STATE_BOOT);
  377. printk(KERN_DEBUG "%s: uploading firmware...\n", priv->ndev->name);
  378. rc = isl_upload_firmware(priv);
  379. if (rc) {
  380. /* error uploading the firmware */
  381. printk(KERN_ERR "%s: could not upload firmware ('%s')\n",
  382. priv->ndev->name, priv->firmware);
  383. islpci_set_state(priv, old_state);
  384. return rc;
  385. }
  386. printk(KERN_DEBUG "%s: firmware upload complete\n",
  387. priv->ndev->name);
  388. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  389. return 0;
  390. }
  391. static int
  392. islpci_reset_if(islpci_private *priv)
  393. {
  394. long remaining;
  395. int result = -ETIME;
  396. int count;
  397. DEFINE_WAIT(wait);
  398. prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE);
  399. /* now the last step is to reset the interface */
  400. isl38xx_interface_reset(priv->device_base, priv->device_host_address);
  401. islpci_set_state(priv, PRV_STATE_PREINIT);
  402. for(count = 0; count < 2 && result; count++) {
  403. /* The software reset acknowledge needs about 220 msec here.
  404. * Be conservative and wait for up to one second. */
  405. set_current_state(TASK_UNINTERRUPTIBLE);
  406. remaining = schedule_timeout(HZ);
  407. if(remaining > 0) {
  408. result = 0;
  409. break;
  410. }
  411. /* If we're here it's because our IRQ hasn't yet gone through.
  412. * Retry a bit more...
  413. */
  414. printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n",
  415. priv->ndev->name);
  416. }
  417. finish_wait(&priv->reset_done, &wait);
  418. if (result) {
  419. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  420. return result;
  421. }
  422. islpci_set_state(priv, PRV_STATE_INIT);
  423. /* Now that the device is 100% up, let's allow
  424. * for the other interrupts --
  425. * NOTE: this is not *yet* true since we've only allowed the
  426. * INIT interrupt on the IRQ line. We can perhaps poll
  427. * the IRQ line until we know for sure the reset went through */
  428. isl38xx_enable_common_interrupts(priv->device_base);
  429. down_write(&priv->mib_sem);
  430. result = mgt_commit(priv);
  431. if (result) {
  432. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  433. up_write(&priv->mib_sem);
  434. return result;
  435. }
  436. up_write(&priv->mib_sem);
  437. islpci_set_state(priv, PRV_STATE_READY);
  438. printk(KERN_DEBUG "%s: interface reset complete\n", priv->ndev->name);
  439. return 0;
  440. }
  441. int
  442. islpci_reset(islpci_private *priv, int reload_firmware)
  443. {
  444. isl38xx_control_block *cb = /* volatile not needed */
  445. (isl38xx_control_block *) priv->control_block;
  446. unsigned counter;
  447. int rc;
  448. if (reload_firmware)
  449. islpci_set_state(priv, PRV_STATE_PREBOOT);
  450. else
  451. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  452. printk(KERN_DEBUG "%s: resetting device...\n", priv->ndev->name);
  453. /* disable all device interrupts in case they weren't */
  454. isl38xx_disable_interrupts(priv->device_base);
  455. /* flush all management queues */
  456. priv->index_mgmt_tx = 0;
  457. priv->index_mgmt_rx = 0;
  458. /* clear the indexes in the frame pointer */
  459. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  460. cb->driver_curr_frag[counter] = cpu_to_le32(0);
  461. cb->device_curr_frag[counter] = cpu_to_le32(0);
  462. }
  463. /* reset the mgmt receive queue */
  464. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  465. isl38xx_fragment *frag = &cb->rx_data_mgmt[counter];
  466. frag->size = cpu_to_le16(MGMT_FRAME_SIZE);
  467. frag->flags = 0;
  468. frag->address = cpu_to_le32(priv->mgmt_rx[counter].pci_addr);
  469. }
  470. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  471. cb->rx_data_low[counter].address =
  472. cpu_to_le32((u32) priv->pci_map_rx_address[counter]);
  473. }
  474. /* since the receive queues are filled with empty fragments, now we can
  475. * set the corresponding indexes in the Control Block */
  476. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_DATA_LQ] =
  477. cpu_to_le32(ISL38XX_CB_RX_QSIZE);
  478. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_MGMTQ] =
  479. cpu_to_le32(ISL38XX_CB_MGMT_QSIZE);
  480. /* reset the remaining real index registers and full flags */
  481. priv->free_data_rx = 0;
  482. priv->free_data_tx = 0;
  483. priv->data_low_tx_full = 0;
  484. if (reload_firmware) { /* Should we load the firmware ? */
  485. /* now that the data structures are cleaned up, upload
  486. * firmware and reset interface */
  487. rc = islpci_upload_fw(priv);
  488. if (rc) {
  489. printk(KERN_ERR "%s: islpci_reset: failure\n",
  490. priv->ndev->name);
  491. return rc;
  492. }
  493. }
  494. /* finally reset interface */
  495. rc = islpci_reset_if(priv);
  496. if (rc)
  497. printk(KERN_ERR "prism54: Your card/socket may be faulty, or IRQ line too busy :(\n");
  498. return rc;
  499. }
  500. static struct net_device_stats *
  501. islpci_statistics(struct net_device *ndev)
  502. {
  503. islpci_private *priv = netdev_priv(ndev);
  504. #if VERBOSE > SHOW_ERROR_MESSAGES
  505. DEBUG(SHOW_FUNCTION_CALLS, "islpci_statistics\n");
  506. #endif
  507. return &priv->statistics;
  508. }
  509. /******************************************************************************
  510. Network device configuration functions
  511. ******************************************************************************/
  512. static int
  513. islpci_alloc_memory(islpci_private *priv)
  514. {
  515. int counter;
  516. #if VERBOSE > SHOW_ERROR_MESSAGES
  517. printk(KERN_DEBUG "islpci_alloc_memory\n");
  518. #endif
  519. /* remap the PCI device base address to accessable */
  520. if (!(priv->device_base =
  521. ioremap(pci_resource_start(priv->pdev, 0),
  522. ISL38XX_PCI_MEM_SIZE))) {
  523. /* error in remapping the PCI device memory address range */
  524. printk(KERN_ERR "PCI memory remapping failed \n");
  525. return -1;
  526. }
  527. /* memory layout for consistent DMA region:
  528. *
  529. * Area 1: Control Block for the device interface
  530. * Area 2: Power Save Mode Buffer for temporary frame storage. Be aware that
  531. * the number of supported stations in the AP determines the minimal
  532. * size of the buffer !
  533. */
  534. /* perform the allocation */
  535. priv->driver_mem_address = pci_alloc_consistent(priv->pdev,
  536. HOST_MEM_BLOCK,
  537. &priv->
  538. device_host_address);
  539. if (!priv->driver_mem_address) {
  540. /* error allocating the block of PCI memory */
  541. printk(KERN_ERR "%s: could not allocate DMA memory, aborting!",
  542. "prism54");
  543. return -1;
  544. }
  545. /* assign the Control Block to the first address of the allocated area */
  546. priv->control_block =
  547. (isl38xx_control_block *) priv->driver_mem_address;
  548. /* set the Power Save Buffer pointer directly behind the CB */
  549. priv->device_psm_buffer =
  550. priv->device_host_address + CONTROL_BLOCK_SIZE;
  551. /* make sure all buffer pointers are initialized */
  552. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  553. priv->control_block->driver_curr_frag[counter] = cpu_to_le32(0);
  554. priv->control_block->device_curr_frag[counter] = cpu_to_le32(0);
  555. }
  556. priv->index_mgmt_rx = 0;
  557. memset(priv->mgmt_rx, 0, sizeof(priv->mgmt_rx));
  558. memset(priv->mgmt_tx, 0, sizeof(priv->mgmt_tx));
  559. /* allocate rx queue for management frames */
  560. if (islpci_mgmt_rx_fill(priv->ndev) < 0)
  561. goto out_free;
  562. /* now get the data rx skb's */
  563. memset(priv->data_low_rx, 0, sizeof (priv->data_low_rx));
  564. memset(priv->pci_map_rx_address, 0, sizeof (priv->pci_map_rx_address));
  565. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  566. struct sk_buff *skb;
  567. /* allocate an sk_buff for received data frames storage
  568. * each frame on receive size consists of 1 fragment
  569. * include any required allignment operations */
  570. if (!(skb = dev_alloc_skb(MAX_FRAGMENT_SIZE_RX + 2))) {
  571. /* error allocating an sk_buff structure elements */
  572. printk(KERN_ERR "Error allocating skb.\n");
  573. skb = NULL;
  574. goto out_free;
  575. }
  576. skb_reserve(skb, (4 - (long) skb->data) & 0x03);
  577. /* add the new allocated sk_buff to the buffer array */
  578. priv->data_low_rx[counter] = skb;
  579. /* map the allocated skb data area to pci */
  580. priv->pci_map_rx_address[counter] =
  581. pci_map_single(priv->pdev, (void *) skb->data,
  582. MAX_FRAGMENT_SIZE_RX + 2,
  583. PCI_DMA_FROMDEVICE);
  584. if (!priv->pci_map_rx_address[counter]) {
  585. /* error mapping the buffer to device
  586. accessable memory address */
  587. printk(KERN_ERR "failed to map skb DMA'able\n");
  588. goto out_free;
  589. }
  590. }
  591. prism54_acl_init(&priv->acl);
  592. prism54_wpa_ie_init(priv);
  593. if (mgt_init(priv))
  594. goto out_free;
  595. return 0;
  596. out_free:
  597. islpci_free_memory(priv);
  598. return -1;
  599. }
  600. int
  601. islpci_free_memory(islpci_private *priv)
  602. {
  603. int counter;
  604. if (priv->device_base)
  605. iounmap(priv->device_base);
  606. priv->device_base = NULL;
  607. /* free consistent DMA area... */
  608. if (priv->driver_mem_address)
  609. pci_free_consistent(priv->pdev, HOST_MEM_BLOCK,
  610. priv->driver_mem_address,
  611. priv->device_host_address);
  612. /* clear some dangling pointers */
  613. priv->driver_mem_address = NULL;
  614. priv->device_host_address = 0;
  615. priv->device_psm_buffer = 0;
  616. priv->control_block = NULL;
  617. /* clean up mgmt rx buffers */
  618. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  619. struct islpci_membuf *buf = &priv->mgmt_rx[counter];
  620. if (buf->pci_addr)
  621. pci_unmap_single(priv->pdev, buf->pci_addr,
  622. buf->size, PCI_DMA_FROMDEVICE);
  623. buf->pci_addr = 0;
  624. if (buf->mem)
  625. kfree(buf->mem);
  626. buf->size = 0;
  627. buf->mem = NULL;
  628. }
  629. /* clean up data rx buffers */
  630. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  631. if (priv->pci_map_rx_address[counter])
  632. pci_unmap_single(priv->pdev,
  633. priv->pci_map_rx_address[counter],
  634. MAX_FRAGMENT_SIZE_RX + 2,
  635. PCI_DMA_FROMDEVICE);
  636. priv->pci_map_rx_address[counter] = 0;
  637. if (priv->data_low_rx[counter])
  638. dev_kfree_skb(priv->data_low_rx[counter]);
  639. priv->data_low_rx[counter] = NULL;
  640. }
  641. /* Free the acces control list and the WPA list */
  642. prism54_acl_clean(&priv->acl);
  643. prism54_wpa_ie_clean(priv);
  644. mgt_clean(priv);
  645. return 0;
  646. }
  647. #if 0
  648. static void
  649. islpci_set_multicast_list(struct net_device *dev)
  650. {
  651. /* put device into promisc mode and let network layer handle it */
  652. }
  653. #endif
  654. struct net_device *
  655. islpci_setup(struct pci_dev *pdev)
  656. {
  657. islpci_private *priv;
  658. struct net_device *ndev = alloc_etherdev(sizeof (islpci_private));
  659. if (!ndev)
  660. return ndev;
  661. SET_MODULE_OWNER(ndev);
  662. pci_set_drvdata(pdev, ndev);
  663. #if defined(SET_NETDEV_DEV)
  664. SET_NETDEV_DEV(ndev, &pdev->dev);
  665. #endif
  666. /* setup the structure members */
  667. ndev->base_addr = pci_resource_start(pdev, 0);
  668. ndev->irq = pdev->irq;
  669. /* initialize the function pointers */
  670. ndev->open = &islpci_open;
  671. ndev->stop = &islpci_close;
  672. ndev->get_stats = &islpci_statistics;
  673. ndev->do_ioctl = &prism54_ioctl;
  674. ndev->wireless_handlers =
  675. (struct iw_handler_def *) &prism54_handler_def;
  676. ndev->hard_start_xmit = &islpci_eth_transmit;
  677. /* ndev->set_multicast_list = &islpci_set_multicast_list; */
  678. ndev->addr_len = ETH_ALEN;
  679. ndev->set_mac_address = &prism54_set_mac_address;
  680. /* Get a non-zero dummy MAC address for nameif. Jean II */
  681. memcpy(ndev->dev_addr, dummy_mac, 6);
  682. #ifdef HAVE_TX_TIMEOUT
  683. ndev->watchdog_timeo = ISLPCI_TX_TIMEOUT;
  684. ndev->tx_timeout = &islpci_eth_tx_timeout;
  685. #endif
  686. /* allocate a private device structure to the network device */
  687. priv = netdev_priv(ndev);
  688. priv->ndev = ndev;
  689. priv->pdev = pdev;
  690. priv->monitor_type = ARPHRD_IEEE80211;
  691. priv->ndev->type = (priv->iw_mode == IW_MODE_MONITOR) ?
  692. priv->monitor_type : ARPHRD_ETHER;
  693. #if WIRELESS_EXT > 16
  694. /* Add pointers to enable iwspy support. */
  695. priv->wireless_data.spy_data = &priv->spy_data;
  696. ndev->wireless_data = &priv->wireless_data;
  697. #else /* WIRELESS_EXT > 16 */
  698. ndev->get_wireless_stats = &prism54_get_wireless_stats;
  699. #endif /* WIRELESS_EXT > 16 */
  700. /* save the start and end address of the PCI memory area */
  701. ndev->mem_start = (unsigned long) priv->device_base;
  702. ndev->mem_end = ndev->mem_start + ISL38XX_PCI_MEM_SIZE;
  703. #if VERBOSE > SHOW_ERROR_MESSAGES
  704. DEBUG(SHOW_TRACING, "PCI Memory remapped to 0x%p\n", priv->device_base);
  705. #endif
  706. init_waitqueue_head(&priv->reset_done);
  707. /* init the queue read locks, process wait counter */
  708. sema_init(&priv->mgmt_sem, 1);
  709. priv->mgmt_received = NULL;
  710. init_waitqueue_head(&priv->mgmt_wqueue);
  711. sema_init(&priv->stats_sem, 1);
  712. spin_lock_init(&priv->slock);
  713. /* init state machine with off#1 state */
  714. priv->state = PRV_STATE_OFF;
  715. priv->state_off = 1;
  716. /* initialize workqueue's */
  717. INIT_WORK(&priv->stats_work,
  718. (void (*)(void *)) prism54_update_stats, priv);
  719. priv->stats_timestamp = 0;
  720. INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake, priv);
  721. priv->reset_task_pending = 0;
  722. /* allocate various memory areas */
  723. if (islpci_alloc_memory(priv))
  724. goto do_free_netdev;
  725. /* select the firmware file depending on the device id */
  726. switch (pdev->device) {
  727. case 0x3877:
  728. strcpy(priv->firmware, ISL3877_IMAGE_FILE);
  729. break;
  730. case 0x3886:
  731. strcpy(priv->firmware, ISL3886_IMAGE_FILE);
  732. break;
  733. default:
  734. strcpy(priv->firmware, ISL3890_IMAGE_FILE);
  735. break;
  736. }
  737. if (register_netdev(ndev)) {
  738. DEBUG(SHOW_ERROR_MESSAGES,
  739. "ERROR: register_netdev() failed \n");
  740. goto do_islpci_free_memory;
  741. }
  742. return ndev;
  743. do_islpci_free_memory:
  744. islpci_free_memory(priv);
  745. do_free_netdev:
  746. pci_set_drvdata(pdev, NULL);
  747. free_netdev(ndev);
  748. priv = NULL;
  749. return NULL;
  750. }
  751. islpci_state_t
  752. islpci_set_state(islpci_private *priv, islpci_state_t new_state)
  753. {
  754. islpci_state_t old_state;
  755. /* lock */
  756. old_state = priv->state;
  757. /* this means either a race condition or some serious error in
  758. * the driver code */
  759. switch (new_state) {
  760. case PRV_STATE_OFF:
  761. priv->state_off++;
  762. default:
  763. priv->state = new_state;
  764. break;
  765. case PRV_STATE_PREBOOT:
  766. /* there are actually many off-states, enumerated by
  767. * state_off */
  768. if (old_state == PRV_STATE_OFF)
  769. priv->state_off--;
  770. /* only if hw_unavailable is zero now it means we either
  771. * were in off#1 state, or came here from
  772. * somewhere else */
  773. if (!priv->state_off)
  774. priv->state = new_state;
  775. break;
  776. };
  777. #if 0
  778. printk(KERN_DEBUG "%s: state transition %d -> %d (off#%d)\n",
  779. priv->ndev->name, old_state, new_state, priv->state_off);
  780. #endif
  781. /* invariants */
  782. BUG_ON(priv->state_off < 0);
  783. BUG_ON(priv->state_off && (priv->state != PRV_STATE_OFF));
  784. BUG_ON(!priv->state_off && (priv->state == PRV_STATE_OFF));
  785. /* unlock */
  786. return old_state;
  787. }