orinoco_plx.c 13 KB

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  1. /* orinoco_plx.c
  2. *
  3. * Driver for Prism II devices which would usually be driven by orinoco_cs,
  4. * but are connected to the PCI bus by a PLX9052.
  5. *
  6. * Current maintainers (as of 29 September 2003) are:
  7. * Pavel Roskin <proski AT gnu.org>
  8. * and David Gibson <hermes AT gibson.dropbear.id.au>
  9. *
  10. * (C) Copyright David Gibson, IBM Corp. 2001-2003.
  11. * Copyright (C) 2001 Daniel Barlow
  12. *
  13. * The contents of this file are subject to the Mozilla Public License
  14. * Version 1.1 (the "License"); you may not use this file except in
  15. * compliance with the License. You may obtain a copy of the License
  16. * at http://www.mozilla.org/MPL/
  17. *
  18. * Software distributed under the License is distributed on an "AS IS"
  19. * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  20. * the License for the specific language governing rights and
  21. * limitations under the License.
  22. *
  23. * Alternatively, the contents of this file may be used under the
  24. * terms of the GNU General Public License version 2 (the "GPL"), in
  25. * which case the provisions of the GPL are applicable instead of the
  26. * above. If you wish to allow the use of your version of this file
  27. * only under the terms of the GPL and not to allow others to use your
  28. * version of this file under the MPL, indicate your decision by
  29. * deleting the provisions above and replace them with the notice and
  30. * other provisions required by the GPL. If you do not delete the
  31. * provisions above, a recipient may use your version of this file
  32. * under either the MPL or the GPL.
  33. * Caution: this is experimental and probably buggy. For success and
  34. * failure reports for different cards and adaptors, see
  35. * orinoco_plx_pci_id_table near the end of the file. If you have a
  36. * card we don't have the PCI id for, and looks like it should work,
  37. * drop me mail with the id and "it works"/"it doesn't work".
  38. *
  39. * Note: if everything gets detected fine but it doesn't actually send
  40. * or receive packets, your first port of call should probably be to
  41. * try newer firmware in the card. Especially if you're doing Ad-Hoc
  42. * modes.
  43. *
  44. * The actual driving is done by orinoco.c, this is just resource
  45. * allocation stuff. The explanation below is courtesy of Ryan Niemi
  46. * on the linux-wlan-ng list at
  47. * http://archives.neohapsis.com/archives/dev/linux-wlan/2001-q1/0026.html
  48. *
  49. * The PLX9052-based cards (WL11000 and several others) are a
  50. * different beast than the usual PCMCIA-based PRISM2 configuration
  51. * expected by wlan-ng. Here's the general details on how the WL11000
  52. * PCI adapter works:
  53. *
  54. * - Two PCI I/O address spaces, one 0x80 long which contains the
  55. * PLX9052 registers, and one that's 0x40 long mapped to the PCMCIA
  56. * slot I/O address space.
  57. *
  58. * - One PCI memory address space, mapped to the PCMCIA memory space
  59. * (containing the CIS).
  60. *
  61. * After identifying the I/O and memory space, you can read through
  62. * the memory space to confirm the CIS's device ID or manufacturer ID
  63. * to make sure it's the expected card. qKeep in mind that the PCMCIA
  64. * spec specifies the CIS as the lower 8 bits of each word read from
  65. * the CIS, so to read the bytes of the CIS, read every other byte
  66. * (0,2,4,...). Passing that test, you need to enable the I/O address
  67. * space on the PCMCIA card via the PCMCIA COR register. This is the
  68. * first byte following the CIS. In my case (which may not have any
  69. * relation to what's on the PRISM2 cards), COR was at offset 0x800
  70. * within the PCI memory space. Write 0x41 to the COR register to
  71. * enable I/O mode and to select level triggered interrupts. To
  72. * confirm you actually succeeded, read the COR register back and make
  73. * sure it actually got set to 0x41, incase you have an unexpected
  74. * card inserted.
  75. *
  76. * Following that, you can treat the second PCI I/O address space (the
  77. * one that's not 0x80 in length) as the PCMCIA I/O space.
  78. *
  79. * Note that in the Eumitcom's source for their drivers, they register
  80. * the interrupt as edge triggered when registering it with the
  81. * Windows kernel. I don't recall how to register edge triggered on
  82. * Linux (if it can be done at all). But in some experimentation, I
  83. * don't see much operational difference between using either
  84. * interrupt mode. Don't mess with the interrupt mode in the COR
  85. * register though, as the PLX9052 wants level triggers with the way
  86. * the serial EEPROM configures it on the WL11000.
  87. *
  88. * There's some other little quirks related to timing that I bumped
  89. * into, but I don't recall right now. Also, there's two variants of
  90. * the WL11000 I've seen, revision A1 and T2. These seem to differ
  91. * slightly in the timings configured in the wait-state generator in
  92. * the PLX9052. There have also been some comments from Eumitcom that
  93. * cards shouldn't be hot swapped, apparently due to risk of cooking
  94. * the PLX9052. I'm unsure why they believe this, as I can't see
  95. * anything in the design that would really cause a problem, except
  96. * for crashing drivers not written to expect it. And having developed
  97. * drivers for the WL11000, I'd say it's quite tricky to write code
  98. * that will successfully deal with a hot unplug. Very odd things
  99. * happen on the I/O side of things. But anyway, be warned. Despite
  100. * that, I've hot-swapped a number of times during debugging and
  101. * driver development for various reasons (stuck WAIT# line after the
  102. * radio card's firmware locks up).
  103. *
  104. * Hope this is enough info for someone to add PLX9052 support to the
  105. * wlan-ng card. In the case of the WL11000, the PCI ID's are
  106. * 0x1639/0x0200, with matching subsystem ID's. Other PLX9052-based
  107. * manufacturers other than Eumitcom (or on cards other than the
  108. * WL11000) may have different PCI ID's.
  109. *
  110. * If anyone needs any more specific info, let me know. I haven't had
  111. * time to implement support myself yet, and with the way things are
  112. * going, might not have time for a while..
  113. */
  114. #define DRIVER_NAME "orinoco_plx"
  115. #define PFX DRIVER_NAME ": "
  116. #include <linux/config.h>
  117. #include <linux/module.h>
  118. #include <linux/kernel.h>
  119. #include <linux/init.h>
  120. #include <linux/sched.h>
  121. #include <linux/ptrace.h>
  122. #include <linux/slab.h>
  123. #include <linux/string.h>
  124. #include <linux/timer.h>
  125. #include <linux/ioport.h>
  126. #include <asm/uaccess.h>
  127. #include <asm/io.h>
  128. #include <asm/system.h>
  129. #include <linux/netdevice.h>
  130. #include <linux/if_arp.h>
  131. #include <linux/etherdevice.h>
  132. #include <linux/list.h>
  133. #include <linux/pci.h>
  134. #include <linux/fcntl.h>
  135. #include <pcmcia/cisreg.h>
  136. #include "hermes.h"
  137. #include "orinoco.h"
  138. #define COR_OFFSET (0x3e0) /* COR attribute offset of Prism2 PC card */
  139. #define COR_VALUE (COR_LEVEL_REQ | COR_FUNC_ENA) /* Enable PC card with interrupt in level trigger */
  140. #define COR_RESET (0x80) /* reset bit in the COR register */
  141. #define PLX_RESET_TIME (500) /* milliseconds */
  142. #define PLX_INTCSR 0x4c /* Interrupt Control & Status Register */
  143. #define PLX_INTCSR_INTEN (1<<6) /* Interrupt Enable bit */
  144. static const u8 cis_magic[] = {
  145. 0x01, 0x03, 0x00, 0x00, 0xff, 0x17, 0x04, 0x67
  146. };
  147. /* Orinoco PLX specific data */
  148. struct orinoco_plx_card {
  149. void __iomem *attr_mem;
  150. };
  151. /*
  152. * Do a soft reset of the card using the Configuration Option Register
  153. */
  154. static int orinoco_plx_cor_reset(struct orinoco_private *priv)
  155. {
  156. hermes_t *hw = &priv->hw;
  157. struct orinoco_plx_card *card = priv->card;
  158. u8 __iomem *attr_mem = card->attr_mem;
  159. unsigned long timeout;
  160. u16 reg;
  161. writeb(COR_VALUE | COR_RESET, attr_mem + COR_OFFSET);
  162. mdelay(1);
  163. writeb(COR_VALUE, attr_mem + COR_OFFSET);
  164. mdelay(1);
  165. /* Just in case, wait more until the card is no longer busy */
  166. timeout = jiffies + (PLX_RESET_TIME * HZ / 1000);
  167. reg = hermes_read_regn(hw, CMD);
  168. while (time_before(jiffies, timeout) && (reg & HERMES_CMD_BUSY)) {
  169. mdelay(1);
  170. reg = hermes_read_regn(hw, CMD);
  171. }
  172. /* Did we timeout ? */
  173. if (reg & HERMES_CMD_BUSY) {
  174. printk(KERN_ERR PFX "Busy timeout\n");
  175. return -ETIMEDOUT;
  176. }
  177. return 0;
  178. }
  179. static int orinoco_plx_init_one(struct pci_dev *pdev,
  180. const struct pci_device_id *ent)
  181. {
  182. int err = 0;
  183. u8 __iomem *attr_mem = NULL;
  184. u32 csr_reg, plx_addr;
  185. struct orinoco_private *priv = NULL;
  186. struct orinoco_plx_card *card;
  187. unsigned long pccard_ioaddr = 0;
  188. unsigned long pccard_iolen = 0;
  189. struct net_device *dev = NULL;
  190. void __iomem *mem;
  191. int i;
  192. err = pci_enable_device(pdev);
  193. if (err) {
  194. printk(KERN_ERR PFX "Cannot enable PCI device\n");
  195. return err;
  196. }
  197. err = pci_request_regions(pdev, DRIVER_NAME);
  198. if (err != 0) {
  199. printk(KERN_ERR PFX "Cannot obtain PCI resources\n");
  200. goto fail_resources;
  201. }
  202. /* Resource 1 is mapped to PLX-specific registers */
  203. plx_addr = pci_resource_start(pdev, 1);
  204. /* Resource 2 is mapped to the PCMCIA attribute memory */
  205. attr_mem = ioremap(pci_resource_start(pdev, 2),
  206. pci_resource_len(pdev, 2));
  207. if (!attr_mem) {
  208. printk(KERN_ERR PFX "Cannot remap PCMCIA space\n");
  209. goto fail_map_attr;
  210. }
  211. /* Resource 3 is mapped to the PCMCIA I/O address space */
  212. pccard_ioaddr = pci_resource_start(pdev, 3);
  213. pccard_iolen = pci_resource_len(pdev, 3);
  214. mem = pci_iomap(pdev, 3, 0);
  215. if (!mem) {
  216. err = -ENOMEM;
  217. goto fail_map_io;
  218. }
  219. /* Allocate network device */
  220. dev = alloc_orinocodev(sizeof(*card), orinoco_plx_cor_reset);
  221. if (!dev) {
  222. printk(KERN_ERR PFX "Cannot allocate network device\n");
  223. err = -ENOMEM;
  224. goto fail_alloc;
  225. }
  226. priv = netdev_priv(dev);
  227. card = priv->card;
  228. card->attr_mem = attr_mem;
  229. dev->base_addr = pccard_ioaddr;
  230. SET_MODULE_OWNER(dev);
  231. SET_NETDEV_DEV(dev, &pdev->dev);
  232. hermes_struct_init(&priv->hw, mem, HERMES_16BIT_REGSPACING);
  233. printk(KERN_DEBUG PFX "Detected Orinoco/Prism2 PLX device "
  234. "at %s irq:%d, io addr:0x%lx\n", pci_name(pdev), pdev->irq,
  235. pccard_ioaddr);
  236. err = request_irq(pdev->irq, orinoco_interrupt, SA_SHIRQ,
  237. dev->name, dev);
  238. if (err) {
  239. printk(KERN_ERR PFX "Cannot allocate IRQ %d\n", pdev->irq);
  240. err = -EBUSY;
  241. goto fail_irq;
  242. }
  243. dev->irq = pdev->irq;
  244. /* bjoern: We need to tell the card to enable interrupts, in
  245. case the serial eprom didn't do this already. See the
  246. PLX9052 data book, p8-1 and 8-24 for reference. */
  247. csr_reg = inl(plx_addr + PLX_INTCSR);
  248. if (!(csr_reg & PLX_INTCSR_INTEN)) {
  249. csr_reg |= PLX_INTCSR_INTEN;
  250. outl(csr_reg, plx_addr + PLX_INTCSR);
  251. csr_reg = inl(plx_addr + PLX_INTCSR);
  252. if (!(csr_reg & PLX_INTCSR_INTEN)) {
  253. printk(KERN_ERR PFX "Cannot enable interrupts\n");
  254. goto fail;
  255. }
  256. }
  257. err = orinoco_plx_cor_reset(priv);
  258. if (err) {
  259. printk(KERN_ERR PFX "Initial reset failed\n");
  260. goto fail;
  261. }
  262. printk(KERN_DEBUG PFX "CIS: ");
  263. for (i = 0; i < 16; i++) {
  264. printk("%02X:", readb(attr_mem + 2*i));
  265. }
  266. printk("\n");
  267. /* Verify whether a supported PC card is present */
  268. /* FIXME: we probably need to be smarted about this */
  269. for (i = 0; i < sizeof(cis_magic); i++) {
  270. if (cis_magic[i] != readb(attr_mem +2*i)) {
  271. printk(KERN_ERR PFX "The CIS value of Prism2 PC "
  272. "card is unexpected\n");
  273. err = -EIO;
  274. goto fail;
  275. }
  276. }
  277. err = register_netdev(dev);
  278. if (err) {
  279. printk(KERN_ERR PFX "Cannot register network device\n");
  280. goto fail;
  281. }
  282. pci_set_drvdata(pdev, dev);
  283. return 0;
  284. fail:
  285. free_irq(pdev->irq, dev);
  286. fail_irq:
  287. pci_set_drvdata(pdev, NULL);
  288. free_orinocodev(dev);
  289. fail_alloc:
  290. pci_iounmap(pdev, mem);
  291. fail_map_io:
  292. iounmap(attr_mem);
  293. fail_map_attr:
  294. pci_release_regions(pdev);
  295. fail_resources:
  296. pci_disable_device(pdev);
  297. return err;
  298. }
  299. static void __devexit orinoco_plx_remove_one(struct pci_dev *pdev)
  300. {
  301. struct net_device *dev = pci_get_drvdata(pdev);
  302. struct orinoco_private *priv = netdev_priv(dev);
  303. struct orinoco_plx_card *card = priv->card;
  304. u8 __iomem *attr_mem = card->attr_mem;
  305. BUG_ON(! dev);
  306. unregister_netdev(dev);
  307. free_irq(dev->irq, dev);
  308. pci_set_drvdata(pdev, NULL);
  309. free_orinocodev(dev);
  310. pci_iounmap(pdev, priv->hw.iobase);
  311. iounmap(attr_mem);
  312. pci_release_regions(pdev);
  313. pci_disable_device(pdev);
  314. }
  315. static struct pci_device_id orinoco_plx_pci_id_table[] = {
  316. {0x111a, 0x1023, PCI_ANY_ID, PCI_ANY_ID,}, /* Siemens SpeedStream SS1023 */
  317. {0x1385, 0x4100, PCI_ANY_ID, PCI_ANY_ID,}, /* Netgear MA301 */
  318. {0x15e8, 0x0130, PCI_ANY_ID, PCI_ANY_ID,}, /* Correga - does this work? */
  319. {0x1638, 0x1100, PCI_ANY_ID, PCI_ANY_ID,}, /* SMC EZConnect SMC2602W,
  320. Eumitcom PCI WL11000,
  321. Addtron AWA-100 */
  322. {0x16ab, 0x1100, PCI_ANY_ID, PCI_ANY_ID,}, /* Global Sun Tech GL24110P */
  323. {0x16ab, 0x1101, PCI_ANY_ID, PCI_ANY_ID,}, /* Reported working, but unknown */
  324. {0x16ab, 0x1102, PCI_ANY_ID, PCI_ANY_ID,}, /* Linksys WDT11 */
  325. {0x16ec, 0x3685, PCI_ANY_ID, PCI_ANY_ID,}, /* USR 2415 */
  326. {0xec80, 0xec00, PCI_ANY_ID, PCI_ANY_ID,}, /* Belkin F5D6000 tested by
  327. Brendan W. McAdams <rit AT jacked-in.org> */
  328. {0x10b7, 0x7770, PCI_ANY_ID, PCI_ANY_ID,}, /* 3Com AirConnect PCI tested by
  329. Damien Persohn <damien AT persohn.net> */
  330. {0,},
  331. };
  332. MODULE_DEVICE_TABLE(pci, orinoco_plx_pci_id_table);
  333. static struct pci_driver orinoco_plx_driver = {
  334. .name = DRIVER_NAME,
  335. .id_table = orinoco_plx_pci_id_table,
  336. .probe = orinoco_plx_init_one,
  337. .remove = __devexit_p(orinoco_plx_remove_one),
  338. };
  339. static char version[] __initdata = DRIVER_NAME " " DRIVER_VERSION
  340. " (Pavel Roskin <proski@gnu.org>,"
  341. " David Gibson <hermes@gibson.dropbear.id.au>,"
  342. " Daniel Barlow <dan@telent.net>)";
  343. MODULE_AUTHOR("Daniel Barlow <dan@telent.net>");
  344. MODULE_DESCRIPTION("Driver for wireless LAN cards using the PLX9052 PCI bridge");
  345. MODULE_LICENSE("Dual MPL/GPL");
  346. static int __init orinoco_plx_init(void)
  347. {
  348. printk(KERN_DEBUG "%s\n", version);
  349. return pci_module_init(&orinoco_plx_driver);
  350. }
  351. static void __exit orinoco_plx_exit(void)
  352. {
  353. pci_unregister_driver(&orinoco_plx_driver);
  354. ssleep(1);
  355. }
  356. module_init(orinoco_plx_init);
  357. module_exit(orinoco_plx_exit);
  358. /*
  359. * Local variables:
  360. * c-indent-level: 8
  361. * c-basic-offset: 8
  362. * tab-width: 8
  363. * End:
  364. */