3c359.c 59 KB

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  1. /*
  2. * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
  3. *
  4. * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
  5. *
  6. * Base Driver Olympic:
  7. * Written 1999 Peter De Schrijver & Mike Phillips
  8. *
  9. * This software may be used and distributed according to the terms
  10. * of the GNU General Public License, incorporated herein by reference.
  11. *
  12. * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
  13. *
  14. * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
  15. * 3/05/01 - Last clean up stuff before submission.
  16. * 2/15/01 - Finally, update to new pci api.
  17. *
  18. * To Do:
  19. */
  20. /*
  21. * Technical Card Details
  22. *
  23. * All access to data is done with 16/8 bit transfers. The transfer
  24. * method really sucks. You can only read or write one location at a time.
  25. *
  26. * Also, the microcode for the card must be uploaded if the card does not have
  27. * the flashrom on board. This is a 28K bloat in the driver when compiled
  28. * as a module.
  29. *
  30. * Rx is very simple, status into a ring of descriptors, dma data transfer,
  31. * interrupts to tell us when a packet is received.
  32. *
  33. * Tx is a little more interesting. Similar scenario, descriptor and dma data
  34. * transfers, but we don't have to interrupt the card to tell it another packet
  35. * is ready for transmission, we are just doing simple memory writes, not io or mmio
  36. * writes. The card can be set up to simply poll on the next
  37. * descriptor pointer and when this value is non-zero will automatically download
  38. * the next packet. The card then interrupts us when the packet is done.
  39. *
  40. */
  41. #define XL_DEBUG 0
  42. #include <linux/config.h>
  43. #include <linux/module.h>
  44. #include <linux/kernel.h>
  45. #include <linux/errno.h>
  46. #include <linux/timer.h>
  47. #include <linux/in.h>
  48. #include <linux/ioport.h>
  49. #include <linux/string.h>
  50. #include <linux/proc_fs.h>
  51. #include <linux/ptrace.h>
  52. #include <linux/skbuff.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/delay.h>
  55. #include <linux/netdevice.h>
  56. #include <linux/trdevice.h>
  57. #include <linux/stddef.h>
  58. #include <linux/init.h>
  59. #include <linux/pci.h>
  60. #include <linux/spinlock.h>
  61. #include <linux/bitops.h>
  62. #include <net/checksum.h>
  63. #include <asm/io.h>
  64. #include <asm/system.h>
  65. #include "3c359.h"
  66. static char version[] __devinitdata =
  67. "3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
  68. MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
  69. MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ;
  70. /* Module paramters */
  71. /* Ring Speed 0,4,16
  72. * 0 = Autosense
  73. * 4,16 = Selected speed only, no autosense
  74. * This allows the card to be the first on the ring
  75. * and become the active monitor.
  76. *
  77. * WARNING: Some hubs will allow you to insert
  78. * at the wrong speed.
  79. *
  80. * The adapter will _not_ fail to open if there are no
  81. * active monitors on the ring, it will simply open up in
  82. * its last known ringspeed if no ringspeed is specified.
  83. */
  84. static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
  85. module_param_array(ringspeed, int, NULL, 0);
  86. MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
  87. /* Packet buffer size */
  88. static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
  89. module_param_array(pkt_buf_sz, int, NULL, 0) ;
  90. MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
  91. /* Message Level */
  92. static int message_level[XL_MAX_ADAPTERS] = {0,} ;
  93. module_param_array(message_level, int, NULL, 0) ;
  94. MODULE_PARM_DESC(message_level, "3c359: Level of reported messages \n") ;
  95. /*
  96. * This is a real nasty way of doing this, but otherwise you
  97. * will be stuck with 1555 lines of hex #'s in the code.
  98. */
  99. #include "3c359_microcode.h"
  100. static struct pci_device_id xl_pci_tbl[] =
  101. {
  102. {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
  103. { } /* terminate list */
  104. };
  105. MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
  106. static int xl_init(struct net_device *dev);
  107. static int xl_open(struct net_device *dev);
  108. static int xl_open_hw(struct net_device *dev) ;
  109. static int xl_hw_reset(struct net_device *dev);
  110. static int xl_xmit(struct sk_buff *skb, struct net_device *dev);
  111. static void xl_dn_comp(struct net_device *dev);
  112. static int xl_close(struct net_device *dev);
  113. static void xl_set_rx_mode(struct net_device *dev);
  114. static irqreturn_t xl_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  115. static struct net_device_stats * xl_get_stats(struct net_device *dev);
  116. static int xl_set_mac_address(struct net_device *dev, void *addr) ;
  117. static void xl_arb_cmd(struct net_device *dev);
  118. static void xl_asb_cmd(struct net_device *dev) ;
  119. static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
  120. static void xl_wait_misr_flags(struct net_device *dev) ;
  121. static int xl_change_mtu(struct net_device *dev, int mtu);
  122. static void xl_srb_bh(struct net_device *dev) ;
  123. static void xl_asb_bh(struct net_device *dev) ;
  124. static void xl_reset(struct net_device *dev) ;
  125. static void xl_freemem(struct net_device *dev) ;
  126. /* EEProm Access Functions */
  127. static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
  128. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
  129. /* Debugging functions */
  130. #if XL_DEBUG
  131. static void print_tx_state(struct net_device *dev) ;
  132. static void print_rx_state(struct net_device *dev) ;
  133. static void print_tx_state(struct net_device *dev)
  134. {
  135. struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
  136. struct xl_tx_desc *txd ;
  137. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  138. int i ;
  139. printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head,
  140. xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
  141. printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n");
  142. for (i = 0; i < 16; i++) {
  143. txd = &(xl_priv->xl_tx_ring[i]) ;
  144. printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd),
  145. txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
  146. }
  147. printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) );
  148. printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
  149. printk("Queue status = %0x \n",netif_running(dev) ) ;
  150. }
  151. static void print_rx_state(struct net_device *dev)
  152. {
  153. struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
  154. struct xl_rx_desc *rxd ;
  155. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  156. int i ;
  157. printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ;
  158. printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n");
  159. for (i = 0; i < 16; i++) {
  160. /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
  161. rxd = &(xl_priv->xl_rx_ring[i]) ;
  162. printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd),
  163. rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
  164. }
  165. printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) );
  166. printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
  167. printk("Queue status = %0x \n",netif_running(dev) ) ;
  168. }
  169. #endif
  170. /*
  171. * Read values from the on-board EEProm. This looks very strange
  172. * but you have to wait for the EEProm to get/set the value before
  173. * passing/getting the next value from the nic. As with all requests
  174. * on this nic it has to be done in two stages, a) tell the nic which
  175. * memory address you want to access and b) pass/get the value from the nic.
  176. * With the EEProm, you have to wait before and inbetween access a) and b).
  177. * As this is only read at initialization time and the wait period is very
  178. * small we shouldn't have to worry about scheduling issues.
  179. */
  180. static u16 xl_ee_read(struct net_device *dev, int ee_addr)
  181. {
  182. struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
  183. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  184. /* Wait for EEProm to not be busy */
  185. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  186. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  187. /* Tell EEProm what we want to do and where */
  188. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  189. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  190. /* Wait for EEProm to not be busy */
  191. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  192. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  193. /* Tell EEProm what we want to do and where */
  194. writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  195. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  196. /* Finally read the value from the EEProm */
  197. writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  198. return readw(xl_mmio + MMIO_MACDATA) ;
  199. }
  200. /*
  201. * Write values to the onboard eeprom. As with eeprom read you need to
  202. * set which location to write, wait, value to write, wait, with the
  203. * added twist of having to enable eeprom writes as well.
  204. */
  205. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
  206. {
  207. struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
  208. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  209. /* Wait for EEProm to not be busy */
  210. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  211. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  212. /* Enable write/erase */
  213. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  214. writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
  215. /* Wait for EEProm to not be busy */
  216. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  217. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  218. /* Put the value we want to write into EEDATA */
  219. writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  220. writew(ee_value, xl_mmio + MMIO_MACDATA) ;
  221. /* Tell EEProm to write eevalue into ee_addr */
  222. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  223. writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
  224. /* Wait for EEProm to not be busy, to ensure write gets done */
  225. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  226. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  227. return ;
  228. }
  229. static int __devinit xl_probe(struct pci_dev *pdev,
  230. const struct pci_device_id *ent)
  231. {
  232. struct net_device *dev ;
  233. struct xl_private *xl_priv ;
  234. static int card_no = -1 ;
  235. int i ;
  236. card_no++ ;
  237. if (pci_enable_device(pdev)) {
  238. return -ENODEV ;
  239. }
  240. pci_set_master(pdev);
  241. if ((i = pci_request_regions(pdev,"3c359"))) {
  242. return i ;
  243. } ;
  244. /*
  245. * Allowing init_trdev to allocate the dev->priv structure will align xl_private
  246. * on a 32 bytes boundary which we need for the rx/tx descriptors
  247. */
  248. dev = alloc_trdev(sizeof(struct xl_private)) ;
  249. if (!dev) {
  250. pci_release_regions(pdev) ;
  251. return -ENOMEM ;
  252. }
  253. xl_priv = dev->priv ;
  254. #if XL_DEBUG
  255. printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
  256. pdev, dev, dev->priv, (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start) ;
  257. #endif
  258. dev->irq=pdev->irq;
  259. dev->base_addr=pci_resource_start(pdev,0) ;
  260. xl_priv->xl_card_name = pci_name(pdev);
  261. xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
  262. xl_priv->pdev = pdev ;
  263. if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
  264. xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
  265. else
  266. xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
  267. dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
  268. xl_priv->xl_ring_speed = ringspeed[card_no] ;
  269. xl_priv->xl_message_level = message_level[card_no] ;
  270. xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
  271. xl_priv->xl_copy_all_options = 0 ;
  272. if((i = xl_init(dev))) {
  273. iounmap(xl_priv->xl_mmio) ;
  274. free_netdev(dev) ;
  275. pci_release_regions(pdev) ;
  276. return i ;
  277. }
  278. dev->open=&xl_open;
  279. dev->hard_start_xmit=&xl_xmit;
  280. dev->change_mtu=&xl_change_mtu;
  281. dev->stop=&xl_close;
  282. dev->do_ioctl=NULL;
  283. dev->set_multicast_list=&xl_set_rx_mode;
  284. dev->get_stats=&xl_get_stats ;
  285. dev->set_mac_address=&xl_set_mac_address ;
  286. SET_MODULE_OWNER(dev);
  287. SET_NETDEV_DEV(dev, &pdev->dev);
  288. pci_set_drvdata(pdev,dev) ;
  289. if ((i = register_netdev(dev))) {
  290. printk(KERN_ERR "3C359, register netdev failed\n") ;
  291. pci_set_drvdata(pdev,NULL) ;
  292. iounmap(xl_priv->xl_mmio) ;
  293. free_netdev(dev) ;
  294. pci_release_regions(pdev) ;
  295. return i ;
  296. }
  297. printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
  298. return 0;
  299. }
  300. static int __init xl_init(struct net_device *dev)
  301. {
  302. struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
  303. printk(KERN_INFO "%s \n", version);
  304. printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
  305. xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
  306. spin_lock_init(&xl_priv->xl_lock) ;
  307. return xl_hw_reset(dev) ;
  308. }
  309. /*
  310. * Hardware reset. This needs to be a separate entity as we need to reset the card
  311. * when we change the EEProm settings.
  312. */
  313. static int xl_hw_reset(struct net_device *dev)
  314. {
  315. struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
  316. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  317. unsigned long t ;
  318. u16 i ;
  319. u16 result_16 ;
  320. u8 result_8 ;
  321. u16 start ;
  322. int j ;
  323. /*
  324. * Reset the card. If the card has got the microcode on board, we have
  325. * missed the initialization interrupt, so we must always do this.
  326. */
  327. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  328. /*
  329. * Must wait for cmdInProgress bit (12) to clear before continuing with
  330. * card configuration.
  331. */
  332. t=jiffies;
  333. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  334. schedule();
  335. if(jiffies-t > 40*HZ) {
  336. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
  337. return -ENODEV;
  338. }
  339. }
  340. /*
  341. * Enable pmbar by setting bit in CPAttention
  342. */
  343. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  344. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  345. result_8 = result_8 | CPA_PMBARVIS ;
  346. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  347. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  348. /*
  349. * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
  350. * If not, we need to upload the microcode to the card
  351. */
  352. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  353. #if XL_DEBUG
  354. printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ;
  355. #endif
  356. if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
  357. /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
  358. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  359. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  360. result_16 = result_16 & ~((0x7F) << 2) ;
  361. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  362. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  363. /* Set CPAttention, memWrEn bit */
  364. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  365. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  366. result_8 = result_8 | CPA_MEMWREN ;
  367. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  368. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  369. /*
  370. * Now to write the microcode into the shared ram
  371. * The microcode must finish at position 0xFFFF, so we must subtract
  372. * to get the start position for the code
  373. */
  374. start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */
  375. printk(KERN_INFO "3C359: Uploading Microcode: ");
  376. for (i = start, j = 0; j < mc_size; i++, j++) {
  377. writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  378. writeb(microcode[j],xl_mmio + MMIO_MACDATA) ;
  379. if (j % 1024 == 0)
  380. printk(".");
  381. }
  382. printk("\n") ;
  383. for (i=0;i < 16; i++) {
  384. writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  385. writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ;
  386. }
  387. /*
  388. * Have to write the start address of the upload to FFF4, but
  389. * the address must be >> 4. You do not want to know how long
  390. * it took me to discover this.
  391. */
  392. writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  393. writew(start >> 4, xl_mmio + MMIO_MACDATA);
  394. /* Clear the CPAttention, memWrEn Bit */
  395. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  396. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  397. result_8 = result_8 & ~CPA_MEMWREN ;
  398. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  399. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  400. /* Clear the cpHold bit in pmbar */
  401. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  402. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  403. result_16 = result_16 & ~PMB_CPHOLD ;
  404. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  405. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  406. } /* If microcode upload required */
  407. /*
  408. * The card should now go though a self test procedure and get itself ready
  409. * to be opened, we must wait for an srb response with the initialization
  410. * information.
  411. */
  412. #if XL_DEBUG
  413. printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
  414. #endif
  415. writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
  416. t=jiffies;
  417. while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
  418. schedule();
  419. if(jiffies-t > 15*HZ) {
  420. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  421. return -ENODEV;
  422. }
  423. }
  424. /*
  425. * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
  426. * DnPriReqThresh, read the tech docs if you want to know what
  427. * values they need to be.
  428. */
  429. writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  430. writew(0xD000, xl_mmio + MMIO_MACDATA) ;
  431. writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  432. writew(0X0020, xl_mmio + MMIO_MACDATA) ;
  433. writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
  434. writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
  435. writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
  436. /*
  437. * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
  438. * Tech docs have this wrong !!!!
  439. */
  440. writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  441. xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  442. writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  443. xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
  444. #if XL_DEBUG
  445. writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  446. if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
  447. printk(KERN_INFO "Default ring speed 4 mbps \n") ;
  448. } else {
  449. printk(KERN_INFO "Default ring speed 16 mbps \n") ;
  450. }
  451. printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
  452. #endif
  453. return 0;
  454. }
  455. static int xl_open(struct net_device *dev)
  456. {
  457. struct xl_private *xl_priv=(struct xl_private *)dev->priv;
  458. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  459. u8 i ;
  460. u16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
  461. int open_err ;
  462. u16 switchsettings, switchsettings_eeprom ;
  463. if(request_irq(dev->irq, &xl_interrupt, SA_SHIRQ , "3c359", dev)) {
  464. return -EAGAIN;
  465. }
  466. /*
  467. * Read the information from the EEPROM that we need. I know we
  468. * should use ntohs, but the word gets stored reversed in the 16
  469. * bit field anyway and it all works its self out when we memcpy
  470. * it into dev->dev_addr.
  471. */
  472. hwaddr[0] = xl_ee_read(dev,0x10) ;
  473. hwaddr[1] = xl_ee_read(dev,0x11) ;
  474. hwaddr[2] = xl_ee_read(dev,0x12) ;
  475. /* Ring speed */
  476. switchsettings_eeprom = xl_ee_read(dev,0x08) ;
  477. switchsettings = switchsettings_eeprom ;
  478. if (xl_priv->xl_ring_speed != 0) {
  479. if (xl_priv->xl_ring_speed == 4)
  480. switchsettings = switchsettings | 0x02 ;
  481. else
  482. switchsettings = switchsettings & ~0x02 ;
  483. }
  484. /* Only write EEProm if there has been a change */
  485. if (switchsettings != switchsettings_eeprom) {
  486. xl_ee_write(dev,0x08,switchsettings) ;
  487. /* Hardware reset after changing EEProm */
  488. xl_hw_reset(dev) ;
  489. }
  490. memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
  491. open_err = xl_open_hw(dev) ;
  492. /*
  493. * This really needs to be cleaned up with better error reporting.
  494. */
  495. if (open_err != 0) { /* Something went wrong with the open command */
  496. if (open_err & 0x07) { /* Wrong speed, retry at different speed */
  497. printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ;
  498. switchsettings = switchsettings ^ 2 ;
  499. xl_ee_write(dev,0x08,switchsettings) ;
  500. xl_hw_reset(dev) ;
  501. open_err = xl_open_hw(dev) ;
  502. if (open_err != 0) {
  503. printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
  504. free_irq(dev->irq,dev) ;
  505. return -ENODEV ;
  506. }
  507. } else {
  508. printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
  509. free_irq(dev->irq,dev) ;
  510. return -ENODEV ;
  511. }
  512. }
  513. /*
  514. * Now to set up the Rx and Tx buffer structures
  515. */
  516. /* These MUST be on 8 byte boundaries */
  517. xl_priv->xl_tx_ring = kmalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL) ;
  518. if (xl_priv->xl_tx_ring == NULL) {
  519. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
  520. dev->name);
  521. free_irq(dev->irq,dev);
  522. return -ENOMEM;
  523. }
  524. xl_priv->xl_rx_ring = kmalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL) ;
  525. if (xl_priv->xl_tx_ring == NULL) {
  526. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
  527. dev->name);
  528. free_irq(dev->irq,dev);
  529. kfree(xl_priv->xl_tx_ring);
  530. return -ENOMEM;
  531. }
  532. memset(xl_priv->xl_tx_ring,0,sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) ;
  533. memset(xl_priv->xl_rx_ring,0,sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) ;
  534. /* Setup Rx Ring */
  535. for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
  536. struct sk_buff *skb ;
  537. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  538. if (skb==NULL)
  539. break ;
  540. skb->dev = dev ;
  541. xl_priv->xl_rx_ring[i].upfragaddr = pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
  542. xl_priv->xl_rx_ring[i].upfraglen = xl_priv->pkt_buf_sz | RXUPLASTFRAG;
  543. xl_priv->rx_ring_skb[i] = skb ;
  544. }
  545. if (i==0) {
  546. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ;
  547. free_irq(dev->irq,dev) ;
  548. return -EIO ;
  549. }
  550. xl_priv->rx_ring_no = i ;
  551. xl_priv->rx_ring_tail = 0 ;
  552. xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
  553. for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
  554. xl_priv->xl_rx_ring[i].upnextptr = xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)) ;
  555. }
  556. xl_priv->xl_rx_ring[i].upnextptr = 0 ;
  557. writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
  558. /* Setup Tx Ring */
  559. xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
  560. xl_priv->tx_ring_head = 1 ;
  561. xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
  562. xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
  563. /*
  564. * Setup the first dummy DPD entry for polling to start working.
  565. */
  566. xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY ;
  567. xl_priv->xl_tx_ring[0].buffer = 0 ;
  568. xl_priv->xl_tx_ring[0].buffer_length = 0 ;
  569. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  570. writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
  571. writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
  572. writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
  573. writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
  574. writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
  575. /*
  576. * Enable interrupts on the card
  577. */
  578. writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  579. writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  580. netif_start_queue(dev) ;
  581. return 0;
  582. }
  583. static int xl_open_hw(struct net_device *dev)
  584. {
  585. struct xl_private *xl_priv=(struct xl_private *)dev->priv;
  586. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  587. u16 vsoff ;
  588. char ver_str[33];
  589. int open_err ;
  590. int i ;
  591. unsigned long t ;
  592. /*
  593. * Okay, let's build up the Open.NIC srb command
  594. *
  595. */
  596. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  597. writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
  598. /*
  599. * Use this as a test byte, if it comes back with the same value, the command didn't work
  600. */
  601. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  602. writeb(0xff,xl_mmio + MMIO_MACDATA) ;
  603. /* Open options */
  604. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  605. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  606. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  607. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  608. /*
  609. * Node address, be careful here, the docs say you can just put zeros here and it will use
  610. * the hardware address, it doesn't, you must include the node address in the open command.
  611. */
  612. if (xl_priv->xl_laa[0]) { /* If using a LAA address */
  613. for (i=10;i<16;i++) {
  614. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  615. writeb(xl_priv->xl_laa[i],xl_mmio + MMIO_MACDATA) ;
  616. }
  617. memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
  618. } else { /* Regular hardware address */
  619. for (i=10;i<16;i++) {
  620. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  621. writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
  622. }
  623. }
  624. /* Default everything else to 0 */
  625. for (i = 16; i < 34; i++) {
  626. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  627. writeb(0x00,xl_mmio + MMIO_MACDATA) ;
  628. }
  629. /*
  630. * Set the csrb bit in the MISR register
  631. */
  632. xl_wait_misr_flags(dev) ;
  633. writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  634. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  635. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  636. writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
  637. /*
  638. * Now wait for the command to run
  639. */
  640. t=jiffies;
  641. while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  642. schedule();
  643. if(jiffies-t > 40*HZ) {
  644. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  645. break ;
  646. }
  647. }
  648. /*
  649. * Let's interpret the open response
  650. */
  651. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  652. if (readb(xl_mmio + MMIO_MACDATA)!=0) {
  653. open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  654. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  655. open_err |= readb(xl_mmio + MMIO_MACDATA) ;
  656. return open_err ;
  657. } else {
  658. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  659. xl_priv->asb = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
  660. printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
  661. printk("ASB: %04x",xl_priv->asb ) ;
  662. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  663. printk(", SRB: %04x",ntohs(readw(xl_mmio + MMIO_MACDATA)) ) ;
  664. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  665. xl_priv->arb = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
  666. printk(", ARB: %04x \n",xl_priv->arb ) ;
  667. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  668. vsoff = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
  669. /*
  670. * Interesting, sending the individual characters directly to printk was causing klogd to use
  671. * use 100% of processor time, so we build up the string and print that instead.
  672. */
  673. for (i=0;i<0x20;i++) {
  674. writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  675. ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
  676. }
  677. ver_str[i] = '\0' ;
  678. printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str);
  679. }
  680. /*
  681. * Issue the AckInterrupt
  682. */
  683. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  684. return 0 ;
  685. }
  686. /*
  687. * There are two ways of implementing rx on the 359 NIC, either
  688. * interrupt driven or polling. We are going to uses interrupts,
  689. * it is the easier way of doing things.
  690. *
  691. * The Rx works with a ring of Rx descriptors. At initialise time the ring
  692. * entries point to the next entry except for the last entry in the ring
  693. * which points to 0. The card is programmed with the location of the first
  694. * available descriptor and keeps reading the next_ptr until next_ptr is set
  695. * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
  696. * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
  697. * and then point the end of the ring to our current position and point our current
  698. * position to 0, therefore making the current position the last position on the ring.
  699. * The last position on the ring therefore loops continually loops around the rx ring.
  700. *
  701. * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
  702. * expands as the card adds new packets and we go around eating the tail processing the
  703. * packets.)
  704. *
  705. * Undoubtably it could be streamlined and improved upon, but at the moment it works
  706. * and the fast path through the routine is fine.
  707. *
  708. * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
  709. * in xl_rx so would increase the size of the function significantly.
  710. */
  711. static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
  712. {
  713. struct xl_private *xl_priv=(struct xl_private *)dev->priv;
  714. int prev_ring_loc ;
  715. prev_ring_loc = (xl_priv->rx_ring_tail + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
  716. xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * xl_priv->rx_ring_tail) ;
  717. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus = 0 ;
  718. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upnextptr = 0 ;
  719. xl_priv->rx_ring_tail++ ;
  720. xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1) ;
  721. return ;
  722. }
  723. static void xl_rx(struct net_device *dev)
  724. {
  725. struct xl_private *xl_priv=(struct xl_private *)dev->priv;
  726. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  727. struct sk_buff *skb, *skb2 ;
  728. int frame_length = 0, copy_len = 0 ;
  729. int temp_ring_loc ;
  730. /*
  731. * Receive the next frame, loop around the ring until all frames
  732. * have been received.
  733. */
  734. while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
  735. if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
  736. /*
  737. * This is a pain, you need to go through all the descriptors until the last one
  738. * for this frame to find the framelength
  739. */
  740. temp_ring_loc = xl_priv->rx_ring_tail ;
  741. while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
  742. temp_ring_loc++ ;
  743. temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
  744. }
  745. frame_length = xl_priv->xl_rx_ring[temp_ring_loc].framestatus & 0x7FFF ;
  746. skb = dev_alloc_skb(frame_length) ;
  747. if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
  748. printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
  749. while (xl_priv->rx_ring_tail != temp_ring_loc)
  750. adv_rx_ring(dev) ;
  751. adv_rx_ring(dev) ; /* One more time just for luck :) */
  752. xl_priv->xl_stats.rx_dropped++ ;
  753. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  754. return ;
  755. }
  756. skb->dev = dev ;
  757. while (xl_priv->rx_ring_tail != temp_ring_loc) {
  758. copy_len = xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen & 0x7FFF ;
  759. frame_length -= copy_len ;
  760. pci_dma_sync_single_for_cpu(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  761. memcpy(skb_put(skb,copy_len), xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]->data, copy_len) ;
  762. pci_dma_sync_single_for_device(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  763. adv_rx_ring(dev) ;
  764. }
  765. /* Now we have found the last fragment */
  766. pci_dma_sync_single_for_cpu(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  767. memcpy(skb_put(skb,copy_len), xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]->data, frame_length) ;
  768. /* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
  769. pci_dma_sync_single_for_device(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  770. adv_rx_ring(dev) ;
  771. skb->protocol = tr_type_trans(skb,dev) ;
  772. netif_rx(skb) ;
  773. } else { /* Single Descriptor Used, simply swap buffers over, fast path */
  774. frame_length = xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & 0x7FFF ;
  775. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  776. if (skb==NULL) { /* Still need to fix the rx ring */
  777. printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
  778. adv_rx_ring(dev) ;
  779. xl_priv->xl_stats.rx_dropped++ ;
  780. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  781. return ;
  782. }
  783. skb->dev = dev ;
  784. skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
  785. pci_unmap_single(xl_priv->pdev, xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr, xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  786. skb_put(skb2, frame_length) ;
  787. skb2->protocol = tr_type_trans(skb2,dev) ;
  788. xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
  789. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
  790. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = xl_priv->pkt_buf_sz | RXUPLASTFRAG ;
  791. adv_rx_ring(dev) ;
  792. xl_priv->xl_stats.rx_packets++ ;
  793. xl_priv->xl_stats.rx_bytes += frame_length ;
  794. netif_rx(skb2) ;
  795. } /* if multiple buffers */
  796. dev->last_rx = jiffies ;
  797. } /* while packet to do */
  798. /* Clear the updComplete interrupt */
  799. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  800. return ;
  801. }
  802. /*
  803. * This is ruthless, it doesn't care what state the card is in it will
  804. * completely reset the adapter.
  805. */
  806. static void xl_reset(struct net_device *dev)
  807. {
  808. struct xl_private *xl_priv=(struct xl_private *)dev->priv;
  809. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  810. unsigned long t;
  811. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  812. /*
  813. * Must wait for cmdInProgress bit (12) to clear before continuing with
  814. * card configuration.
  815. */
  816. t=jiffies;
  817. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  818. if(jiffies-t > 40*HZ) {
  819. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  820. break ;
  821. }
  822. }
  823. }
  824. static void xl_freemem(struct net_device *dev)
  825. {
  826. struct xl_private *xl_priv=(struct xl_private *)dev->priv ;
  827. int i ;
  828. for (i=0;i<XL_RX_RING_SIZE;i++) {
  829. dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
  830. pci_unmap_single(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
  831. xl_priv->rx_ring_tail++ ;
  832. xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
  833. }
  834. /* unmap ring */
  835. pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
  836. pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
  837. kfree(xl_priv->xl_rx_ring) ;
  838. kfree(xl_priv->xl_tx_ring) ;
  839. return ;
  840. }
  841. static irqreturn_t xl_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  842. {
  843. struct net_device *dev = (struct net_device *)dev_id;
  844. struct xl_private *xl_priv =(struct xl_private *)dev->priv;
  845. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  846. u16 intstatus, macstatus ;
  847. if (!dev) {
  848. printk(KERN_WARNING "Device structure dead, aaahhhh !\n") ;
  849. return IRQ_NONE;
  850. }
  851. intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
  852. if (!(intstatus & 1)) /* We didn't generate the interrupt */
  853. return IRQ_NONE;
  854. spin_lock(&xl_priv->xl_lock) ;
  855. /*
  856. * Process the interrupt
  857. */
  858. /*
  859. * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
  860. */
  861. if (intstatus == 0x0001) {
  862. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  863. printk(KERN_INFO "%s: 00001 int received \n",dev->name) ;
  864. } else {
  865. if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
  866. /*
  867. * Host Error.
  868. * It may be possible to recover from this, but usually it means something
  869. * is seriously fubar, so we just close the adapter.
  870. */
  871. if (intstatus & HOSTERRINT) {
  872. printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ;
  873. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  874. printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
  875. netif_stop_queue(dev) ;
  876. xl_freemem(dev) ;
  877. free_irq(dev->irq,dev);
  878. xl_reset(dev) ;
  879. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  880. spin_unlock(&xl_priv->xl_lock) ;
  881. return IRQ_HANDLED;
  882. } /* Host Error */
  883. if (intstatus & SRBRINT ) { /* Srbc interrupt */
  884. writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  885. if (xl_priv->srb_queued)
  886. xl_srb_bh(dev) ;
  887. } /* SRBR Interrupt */
  888. if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
  889. writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  890. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
  891. /* !!! FIX-ME !!!!
  892. Must put a timeout check here ! */
  893. /* Empty Loop */
  894. }
  895. printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ;
  896. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  897. } /* TxUnderRun */
  898. if (intstatus & ARBCINT ) { /* Arbc interrupt */
  899. xl_arb_cmd(dev) ;
  900. } /* Arbc */
  901. if (intstatus & ASBFINT) {
  902. if (xl_priv->asb_queued == 1) {
  903. xl_asb_cmd(dev) ;
  904. } else if (xl_priv->asb_queued == 2) {
  905. xl_asb_bh(dev) ;
  906. } else {
  907. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  908. }
  909. } /* Asbf */
  910. if (intstatus & UPCOMPINT ) /* UpComplete */
  911. xl_rx(dev) ;
  912. if (intstatus & DNCOMPINT ) /* DnComplete */
  913. xl_dn_comp(dev) ;
  914. if (intstatus & HARDERRINT ) { /* Hardware error */
  915. writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  916. macstatus = readw(xl_mmio + MMIO_MACDATA) ;
  917. printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
  918. if (macstatus & (1<<14))
  919. printk(KERN_WARNING "tchk error: Unrecoverable error \n") ;
  920. if (macstatus & (1<<3))
  921. printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ;
  922. if (macstatus & (1<<2))
  923. printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ;
  924. printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
  925. printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
  926. netif_stop_queue(dev) ;
  927. xl_freemem(dev) ;
  928. free_irq(dev->irq,dev);
  929. unregister_netdev(dev) ;
  930. free_netdev(dev) ;
  931. xl_reset(dev) ;
  932. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  933. spin_unlock(&xl_priv->xl_lock) ;
  934. return IRQ_HANDLED;
  935. }
  936. } else {
  937. printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ;
  938. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  939. }
  940. }
  941. /* Turn interrupts back on */
  942. writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  943. writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  944. spin_unlock(&xl_priv->xl_lock) ;
  945. return IRQ_HANDLED;
  946. }
  947. /*
  948. * Tx - Polling configuration
  949. */
  950. static int xl_xmit(struct sk_buff *skb, struct net_device *dev)
  951. {
  952. struct xl_private *xl_priv=(struct xl_private *)dev->priv;
  953. struct xl_tx_desc *txd ;
  954. int tx_head, tx_tail, tx_prev ;
  955. unsigned long flags ;
  956. spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
  957. netif_stop_queue(dev) ;
  958. if (xl_priv->free_ring_entries > 1 ) {
  959. /*
  960. * Set up the descriptor for the packet
  961. */
  962. tx_head = xl_priv->tx_ring_head ;
  963. tx_tail = xl_priv->tx_ring_tail ;
  964. txd = &(xl_priv->xl_tx_ring[tx_head]) ;
  965. txd->dnnextptr = 0 ;
  966. txd->framestartheader = skb->len | TXDNINDICATE ;
  967. txd->buffer = pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE) ;
  968. txd->buffer_length = skb->len | TXDNFRAGLAST ;
  969. xl_priv->tx_ring_skb[tx_head] = skb ;
  970. xl_priv->xl_stats.tx_packets++ ;
  971. xl_priv->xl_stats.tx_bytes += skb->len ;
  972. /*
  973. * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
  974. * to ensure no negative numbers in unsigned locations.
  975. */
  976. tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
  977. xl_priv->tx_ring_head++ ;
  978. xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
  979. xl_priv->free_ring_entries-- ;
  980. xl_priv->xl_tx_ring[tx_prev].dnnextptr = xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head) ;
  981. /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
  982. /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
  983. netif_wake_queue(dev) ;
  984. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  985. return 0;
  986. } else {
  987. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  988. return 1;
  989. }
  990. }
  991. /*
  992. * The NIC has told us that a packet has been downloaded onto the card, we must
  993. * find out which packet it has done, clear the skb and information for the packet
  994. * then advance around the ring for all tranmitted packets
  995. */
  996. static void xl_dn_comp(struct net_device *dev)
  997. {
  998. struct xl_private *xl_priv=(struct xl_private *)dev->priv;
  999. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1000. struct xl_tx_desc *txd ;
  1001. if (xl_priv->tx_ring_tail == 255) {/* First time */
  1002. xl_priv->xl_tx_ring[0].framestartheader = 0 ;
  1003. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  1004. xl_priv->tx_ring_tail = 1 ;
  1005. }
  1006. while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
  1007. txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
  1008. pci_unmap_single(xl_priv->pdev,txd->buffer, xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE) ;
  1009. txd->framestartheader = 0 ;
  1010. txd->buffer = 0xdeadbeef ;
  1011. txd->buffer_length = 0 ;
  1012. dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
  1013. xl_priv->tx_ring_tail++ ;
  1014. xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
  1015. xl_priv->free_ring_entries++ ;
  1016. }
  1017. netif_wake_queue(dev) ;
  1018. writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1019. }
  1020. /*
  1021. * Close the adapter properly.
  1022. * This srb reply cannot be handled from interrupt context as we have
  1023. * to free the interrupt from the driver.
  1024. */
  1025. static int xl_close(struct net_device *dev)
  1026. {
  1027. struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
  1028. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1029. unsigned long t ;
  1030. netif_stop_queue(dev) ;
  1031. /*
  1032. * Close the adapter, need to stall the rx and tx queues.
  1033. */
  1034. writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
  1035. t=jiffies;
  1036. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1037. schedule();
  1038. if(jiffies-t > 10*HZ) {
  1039. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
  1040. break ;
  1041. }
  1042. }
  1043. writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
  1044. t=jiffies;
  1045. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1046. schedule();
  1047. if(jiffies-t > 10*HZ) {
  1048. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
  1049. break ;
  1050. }
  1051. }
  1052. writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
  1053. t=jiffies;
  1054. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1055. schedule();
  1056. if(jiffies-t > 10*HZ) {
  1057. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
  1058. break ;
  1059. }
  1060. }
  1061. /* Turn off interrupts, we will still get the indication though
  1062. * so we can trap it
  1063. */
  1064. writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
  1065. xl_srb_cmd(dev,CLOSE_NIC) ;
  1066. t=jiffies;
  1067. while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  1068. schedule();
  1069. if(jiffies-t > 10*HZ) {
  1070. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
  1071. break ;
  1072. }
  1073. }
  1074. /* Read the srb response from the adapter */
  1075. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1076. if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
  1077. printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ;
  1078. } else {
  1079. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1080. if (readb(xl_mmio + MMIO_MACDATA)==0) {
  1081. printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ;
  1082. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1083. xl_freemem(dev) ;
  1084. free_irq(dev->irq,dev) ;
  1085. } else {
  1086. printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
  1087. }
  1088. }
  1089. /* Reset the upload and download logic */
  1090. writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
  1091. t=jiffies;
  1092. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1093. schedule();
  1094. if(jiffies-t > 10*HZ) {
  1095. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
  1096. break ;
  1097. }
  1098. }
  1099. writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
  1100. t=jiffies;
  1101. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1102. schedule();
  1103. if(jiffies-t > 10*HZ) {
  1104. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
  1105. break ;
  1106. }
  1107. }
  1108. xl_hw_reset(dev) ;
  1109. return 0 ;
  1110. }
  1111. static void xl_set_rx_mode(struct net_device *dev)
  1112. {
  1113. struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
  1114. struct dev_mc_list *dmi ;
  1115. unsigned char dev_mc_address[4] ;
  1116. u16 options ;
  1117. int i ;
  1118. if (dev->flags & IFF_PROMISC)
  1119. options = 0x0004 ;
  1120. else
  1121. options = 0x0000 ;
  1122. if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
  1123. xl_priv->xl_copy_all_options = options ;
  1124. xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
  1125. return ;
  1126. }
  1127. dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
  1128. for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) {
  1129. dev_mc_address[0] |= dmi->dmi_addr[2] ;
  1130. dev_mc_address[1] |= dmi->dmi_addr[3] ;
  1131. dev_mc_address[2] |= dmi->dmi_addr[4] ;
  1132. dev_mc_address[3] |= dmi->dmi_addr[5] ;
  1133. }
  1134. if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
  1135. memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
  1136. xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
  1137. }
  1138. return ;
  1139. }
  1140. /*
  1141. * We issued an srb command and now we must read
  1142. * the response from the completed command.
  1143. */
  1144. static void xl_srb_bh(struct net_device *dev)
  1145. {
  1146. struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
  1147. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1148. u8 srb_cmd, ret_code ;
  1149. int i ;
  1150. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1151. srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1152. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1153. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1154. /* Ret_code is standard across all commands */
  1155. switch (ret_code) {
  1156. case 1:
  1157. printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
  1158. break ;
  1159. case 4:
  1160. printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ;
  1161. break ;
  1162. case 6:
  1163. printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ;
  1164. break ;
  1165. case 0: /* Successful command execution */
  1166. switch (srb_cmd) {
  1167. case READ_LOG: /* Returns 14 bytes of data from the NIC */
  1168. if(xl_priv->xl_message_level)
  1169. printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
  1170. /*
  1171. * We still have to read the log even if message_level = 0 and we don't want
  1172. * to see it
  1173. */
  1174. for (i=0;i<14;i++) {
  1175. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1176. if(xl_priv->xl_message_level)
  1177. printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
  1178. }
  1179. printk("\n") ;
  1180. break ;
  1181. case SET_FUNC_ADDRESS:
  1182. if(xl_priv->xl_message_level)
  1183. printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ;
  1184. break ;
  1185. case CLOSE_NIC:
  1186. if(xl_priv->xl_message_level)
  1187. printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ;
  1188. break ;
  1189. case SET_MULTICAST_MODE:
  1190. if(xl_priv->xl_message_level)
  1191. printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
  1192. break ;
  1193. case SET_RECEIVE_MODE:
  1194. if(xl_priv->xl_message_level) {
  1195. if (xl_priv->xl_copy_all_options == 0x0004)
  1196. printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ;
  1197. else
  1198. printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ;
  1199. }
  1200. break ;
  1201. } /* switch */
  1202. break ;
  1203. } /* switch */
  1204. return ;
  1205. }
  1206. static struct net_device_stats * xl_get_stats(struct net_device *dev)
  1207. {
  1208. struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
  1209. return (struct net_device_stats *) &xl_priv->xl_stats;
  1210. }
  1211. static int xl_set_mac_address (struct net_device *dev, void *addr)
  1212. {
  1213. struct sockaddr *saddr = addr ;
  1214. struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
  1215. if (netif_running(dev)) {
  1216. printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
  1217. return -EIO ;
  1218. }
  1219. memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
  1220. if (xl_priv->xl_message_level) {
  1221. printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
  1222. xl_priv->xl_laa[1], xl_priv->xl_laa[2],
  1223. xl_priv->xl_laa[3], xl_priv->xl_laa[4],
  1224. xl_priv->xl_laa[5]);
  1225. }
  1226. return 0 ;
  1227. }
  1228. static void xl_arb_cmd(struct net_device *dev)
  1229. {
  1230. struct xl_private *xl_priv = (struct xl_private *) dev->priv;
  1231. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1232. u8 arb_cmd ;
  1233. u16 lan_status, lan_status_diff ;
  1234. writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1235. arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1236. if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
  1237. writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1238. printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, ntohs(readw(xl_mmio + MMIO_MACDATA) )) ;
  1239. lan_status = ntohs(readw(xl_mmio + MMIO_MACDATA));
  1240. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1241. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1242. lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
  1243. if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
  1244. if (lan_status_diff & LSC_LWF)
  1245. printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
  1246. if (lan_status_diff & LSC_ARW)
  1247. printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
  1248. if (lan_status_diff & LSC_FPE)
  1249. printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
  1250. if (lan_status_diff & LSC_RR)
  1251. printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
  1252. /* Adapter has been closed by the hardware */
  1253. netif_stop_queue(dev);
  1254. xl_freemem(dev) ;
  1255. free_irq(dev->irq,dev);
  1256. printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
  1257. } /* If serious error */
  1258. if (xl_priv->xl_message_level) {
  1259. if (lan_status_diff & LSC_SIG_LOSS)
  1260. printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
  1261. if (lan_status_diff & LSC_HARD_ERR)
  1262. printk(KERN_INFO "%s: Beaconing \n",dev->name);
  1263. if (lan_status_diff & LSC_SOFT_ERR)
  1264. printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
  1265. if (lan_status_diff & LSC_TRAN_BCN)
  1266. printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
  1267. if (lan_status_diff & LSC_SS)
  1268. printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
  1269. if (lan_status_diff & LSC_RING_REC)
  1270. printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
  1271. if (lan_status_diff & LSC_FDX_MODE)
  1272. printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
  1273. }
  1274. if (lan_status_diff & LSC_CO) {
  1275. if (xl_priv->xl_message_level)
  1276. printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
  1277. /* Issue READ.LOG command */
  1278. xl_srb_cmd(dev, READ_LOG) ;
  1279. }
  1280. /* There is no command in the tech docs to issue the read_sr_counters */
  1281. if (lan_status_diff & LSC_SR_CO) {
  1282. if (xl_priv->xl_message_level)
  1283. printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
  1284. }
  1285. xl_priv->xl_lan_status = lan_status ;
  1286. } /* Lan.change.status */
  1287. else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
  1288. #if XL_DEBUG
  1289. printk(KERN_INFO "Received.Data \n") ;
  1290. #endif
  1291. writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1292. xl_priv->mac_buffer = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
  1293. /* Now we are going to be really basic here and not do anything
  1294. * with the data at all. The tech docs do not give me enough
  1295. * information to calculate the buffers properly so we're
  1296. * just going to tell the nic that we've dealt with the frame
  1297. * anyway.
  1298. */
  1299. dev->last_rx = jiffies ;
  1300. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1301. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1302. /* Is the ASB free ? */
  1303. xl_priv->asb_queued = 0 ;
  1304. writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1305. if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
  1306. xl_priv->asb_queued = 1 ;
  1307. xl_wait_misr_flags(dev) ;
  1308. writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1309. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1310. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1311. writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
  1312. return ;
  1313. /* Drop out and wait for the bottom half to be run */
  1314. }
  1315. xl_asb_cmd(dev) ;
  1316. } else {
  1317. printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ;
  1318. }
  1319. /* Acknowledge the arb interrupt */
  1320. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1321. return ;
  1322. }
  1323. /*
  1324. * There is only one asb command, but we can get called from different
  1325. * places.
  1326. */
  1327. static void xl_asb_cmd(struct net_device *dev)
  1328. {
  1329. struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
  1330. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1331. if (xl_priv->asb_queued == 1)
  1332. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1333. writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1334. writeb(0x81, xl_mmio + MMIO_MACDATA) ;
  1335. writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1336. writew(ntohs(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
  1337. xl_wait_misr_flags(dev) ;
  1338. writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1339. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1340. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1341. writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
  1342. xl_priv->asb_queued = 2 ;
  1343. return ;
  1344. }
  1345. /*
  1346. * This will only get called if there was an error
  1347. * from the asb cmd.
  1348. */
  1349. static void xl_asb_bh(struct net_device *dev)
  1350. {
  1351. struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
  1352. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1353. u8 ret_code ;
  1354. writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1355. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1356. switch (ret_code) {
  1357. case 0x01:
  1358. printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ;
  1359. break ;
  1360. case 0x26:
  1361. printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ;
  1362. break ;
  1363. case 0x40:
  1364. printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ;
  1365. break ;
  1366. }
  1367. xl_priv->asb_queued = 0 ;
  1368. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1369. return ;
  1370. }
  1371. /*
  1372. * Issue srb commands to the nic
  1373. */
  1374. static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
  1375. {
  1376. struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
  1377. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1378. switch (srb_cmd) {
  1379. case READ_LOG:
  1380. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1381. writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
  1382. break;
  1383. case CLOSE_NIC:
  1384. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1385. writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
  1386. break ;
  1387. case SET_RECEIVE_MODE:
  1388. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1389. writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
  1390. writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1391. writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
  1392. break ;
  1393. case SET_FUNC_ADDRESS:
  1394. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1395. writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
  1396. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1397. writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
  1398. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1399. writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
  1400. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1401. writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
  1402. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1403. writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
  1404. break ;
  1405. } /* switch */
  1406. xl_wait_misr_flags(dev) ;
  1407. /* Write 0xff to the CSRB flag */
  1408. writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1409. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  1410. /* Set csrb bit in MISR register to process command */
  1411. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1412. writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
  1413. xl_priv->srb_queued = 1 ;
  1414. return ;
  1415. }
  1416. /*
  1417. * This is nasty, to use the MISR command you have to wait for 6 memory locations
  1418. * to be zero. This is the way the driver does on other OS'es so we should be ok with
  1419. * the empty loop.
  1420. */
  1421. static void xl_wait_misr_flags(struct net_device *dev)
  1422. {
  1423. struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
  1424. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1425. int i ;
  1426. writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1427. if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
  1428. for (i=0; i<6; i++) {
  1429. writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1430. while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
  1431. }
  1432. }
  1433. writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1434. writeb(0x80, xl_mmio + MMIO_MACDATA) ;
  1435. return ;
  1436. }
  1437. /*
  1438. * Change mtu size, this should work the same as olympic
  1439. */
  1440. static int xl_change_mtu(struct net_device *dev, int mtu)
  1441. {
  1442. struct xl_private *xl_priv = (struct xl_private *) dev->priv;
  1443. u16 max_mtu ;
  1444. if (xl_priv->xl_ring_speed == 4)
  1445. max_mtu = 4500 ;
  1446. else
  1447. max_mtu = 18000 ;
  1448. if (mtu > max_mtu)
  1449. return -EINVAL ;
  1450. if (mtu < 100)
  1451. return -EINVAL ;
  1452. dev->mtu = mtu ;
  1453. xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
  1454. return 0 ;
  1455. }
  1456. static void __devexit xl_remove_one (struct pci_dev *pdev)
  1457. {
  1458. struct net_device *dev = pci_get_drvdata(pdev);
  1459. struct xl_private *xl_priv=(struct xl_private *)dev->priv;
  1460. unregister_netdev(dev);
  1461. iounmap(xl_priv->xl_mmio) ;
  1462. pci_release_regions(pdev) ;
  1463. pci_set_drvdata(pdev,NULL) ;
  1464. free_netdev(dev);
  1465. return ;
  1466. }
  1467. static struct pci_driver xl_3c359_driver = {
  1468. .name = "3c359",
  1469. .id_table = xl_pci_tbl,
  1470. .probe = xl_probe,
  1471. .remove = __devexit_p(xl_remove_one),
  1472. };
  1473. static int __init xl_pci_init (void)
  1474. {
  1475. return pci_module_init (&xl_3c359_driver);
  1476. }
  1477. static void __exit xl_pci_cleanup (void)
  1478. {
  1479. pci_unregister_driver (&xl_3c359_driver);
  1480. }
  1481. module_init(xl_pci_init);
  1482. module_exit(xl_pci_cleanup);
  1483. MODULE_LICENSE("GPL") ;