via-ircc.c 42 KB

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  1. /********************************************************************
  2. Filename: via-ircc.c
  3. Version: 1.0
  4. Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
  5. Author: VIA Technologies,inc
  6. Date : 08/06/2003
  7. Copyright (c) 1998-2003 VIA Technologies, Inc.
  8. This program is free software; you can redistribute it and/or modify it under
  9. the terms of the GNU General Public License as published by the Free Software
  10. Foundation; either version 2, or (at your option) any later version.
  11. This program is distributed in the hope that it will be useful, but WITHOUT
  12. ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14. See the GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License along with
  16. this program; if not, write to the Free Software Foundation, Inc.,
  17. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. F01 Oct/02/02: Modify code for V0.11(move out back to back transfer)
  19. F02 Oct/28/02: Add SB device ID for 3147 and 3177.
  20. Comment :
  21. jul/09/2002 : only implement two kind of dongle currently.
  22. Oct/02/2002 : work on VT8231 and VT8233 .
  23. Aug/06/2003 : change driver format to pci driver .
  24. 2004-02-16: <sda@bdit.de>
  25. - Removed unneeded 'legacy' pci stuff.
  26. - Make sure SIR mode is set (hw_init()) before calling mode-dependant stuff.
  27. - On speed change from core, don't send SIR frame with new speed.
  28. Use current speed and change speeds later.
  29. - Make module-param dongle_id actually work.
  30. - New dongle_id 17 (0x11): TDFS4500. Single-ended SIR only.
  31. Tested with home-grown PCB on EPIA boards.
  32. - Code cleanup.
  33. ********************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/kernel.h>
  36. #include <linux/types.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/ioport.h>
  40. #include <linux/delay.h>
  41. #include <linux/slab.h>
  42. #include <linux/init.h>
  43. #include <linux/rtnetlink.h>
  44. #include <linux/pci.h>
  45. #include <linux/dma-mapping.h>
  46. #include <asm/io.h>
  47. #include <asm/dma.h>
  48. #include <asm/byteorder.h>
  49. #include <linux/pm.h>
  50. #include <net/irda/wrapper.h>
  51. #include <net/irda/irda.h>
  52. #include <net/irda/irda_device.h>
  53. #include "via-ircc.h"
  54. #define VIA_MODULE_NAME "via-ircc"
  55. #define CHIP_IO_EXTENT 0x40
  56. static char *driver_name = VIA_MODULE_NAME;
  57. /* Module parameters */
  58. static int qos_mtt_bits = 0x07; /* 1 ms or more */
  59. static int dongle_id = 0; /* default: probe */
  60. /* We can't guess the type of connected dongle, user *must* supply it. */
  61. module_param(dongle_id, int, 0);
  62. /* FIXME : we should not need this, because instances should be automatically
  63. * managed by the PCI layer. Especially that we seem to only be using the
  64. * first entry. Jean II */
  65. /* Max 4 instances for now */
  66. static struct via_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  67. /* Some prototypes */
  68. static int via_ircc_open(int i, chipio_t * info, unsigned int id);
  69. static int via_ircc_close(struct via_ircc_cb *self);
  70. static int via_ircc_dma_receive(struct via_ircc_cb *self);
  71. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  72. int iobase);
  73. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  74. struct net_device *dev);
  75. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  76. struct net_device *dev);
  77. static void via_hw_init(struct via_ircc_cb *self);
  78. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 baud);
  79. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id,
  80. struct pt_regs *regs);
  81. static int via_ircc_is_receiving(struct via_ircc_cb *self);
  82. static int via_ircc_read_dongle_id(int iobase);
  83. static int via_ircc_net_open(struct net_device *dev);
  84. static int via_ircc_net_close(struct net_device *dev);
  85. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  86. int cmd);
  87. static struct net_device_stats *via_ircc_net_get_stats(struct net_device
  88. *dev);
  89. static void via_ircc_change_dongle_speed(int iobase, int speed,
  90. int dongle_id);
  91. static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
  92. static void hwreset(struct via_ircc_cb *self);
  93. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
  94. static int upload_rxdata(struct via_ircc_cb *self, int iobase);
  95. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id);
  96. static void __devexit via_remove_one (struct pci_dev *pdev);
  97. /* FIXME : Should use udelay() instead, even if we are x86 only - Jean II */
  98. static void iodelay(int udelay)
  99. {
  100. u8 data;
  101. int i;
  102. for (i = 0; i < udelay; i++) {
  103. data = inb(0x80);
  104. }
  105. }
  106. static struct pci_device_id via_pci_tbl[] = {
  107. { PCI_VENDOR_ID_VIA, 0x8231, PCI_ANY_ID, PCI_ANY_ID,0,0,0 },
  108. { PCI_VENDOR_ID_VIA, 0x3109, PCI_ANY_ID, PCI_ANY_ID,0,0,1 },
  109. { PCI_VENDOR_ID_VIA, 0x3074, PCI_ANY_ID, PCI_ANY_ID,0,0,2 },
  110. { PCI_VENDOR_ID_VIA, 0x3147, PCI_ANY_ID, PCI_ANY_ID,0,0,3 },
  111. { PCI_VENDOR_ID_VIA, 0x3177, PCI_ANY_ID, PCI_ANY_ID,0,0,4 },
  112. { 0, }
  113. };
  114. MODULE_DEVICE_TABLE(pci,via_pci_tbl);
  115. static struct pci_driver via_driver = {
  116. .name = VIA_MODULE_NAME,
  117. .id_table = via_pci_tbl,
  118. .probe = via_init_one,
  119. .remove = __devexit_p(via_remove_one),
  120. };
  121. /*
  122. * Function via_ircc_init ()
  123. *
  124. * Initialize chip. Just find out chip type and resource.
  125. */
  126. static int __init via_ircc_init(void)
  127. {
  128. int rc;
  129. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  130. rc = pci_register_driver(&via_driver);
  131. if (rc < 0) {
  132. IRDA_DEBUG(0, "%s(): error rc = %d, returning -ENODEV...\n",
  133. __FUNCTION__, rc);
  134. return -ENODEV;
  135. }
  136. return 0;
  137. }
  138. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id)
  139. {
  140. int rc;
  141. u8 temp,oldPCI_40,oldPCI_44,bTmp,bTmp1;
  142. u16 Chipset,FirDRQ1,FirDRQ0,FirIRQ,FirIOBase;
  143. chipio_t info;
  144. IRDA_DEBUG(2, "%s(): Device ID=(0X%X)\n", __FUNCTION__, id->device);
  145. rc = pci_enable_device (pcidev);
  146. if (rc) {
  147. IRDA_DEBUG(0, "%s(): error rc = %d\n", __FUNCTION__, rc);
  148. return -ENODEV;
  149. }
  150. // South Bridge exist
  151. if ( ReadLPCReg(0x20) != 0x3C )
  152. Chipset=0x3096;
  153. else
  154. Chipset=0x3076;
  155. if (Chipset==0x3076) {
  156. IRDA_DEBUG(2, "%s(): Chipset = 3076\n", __FUNCTION__);
  157. WriteLPCReg(7,0x0c );
  158. temp=ReadLPCReg(0x30);//check if BIOS Enable Fir
  159. if((temp&0x01)==1) { // BIOS close or no FIR
  160. WriteLPCReg(0x1d, 0x82 );
  161. WriteLPCReg(0x23,0x18);
  162. temp=ReadLPCReg(0xF0);
  163. if((temp&0x01)==0) {
  164. temp=(ReadLPCReg(0x74)&0x03); //DMA
  165. FirDRQ0=temp + 4;
  166. temp=(ReadLPCReg(0x74)&0x0C) >> 2;
  167. FirDRQ1=temp + 4;
  168. } else {
  169. temp=(ReadLPCReg(0x74)&0x0C) >> 2; //DMA
  170. FirDRQ0=temp + 4;
  171. FirDRQ1=FirDRQ0;
  172. }
  173. FirIRQ=(ReadLPCReg(0x70)&0x0f); //IRQ
  174. FirIOBase=ReadLPCReg(0x60 ) << 8; //IO Space :high byte
  175. FirIOBase=FirIOBase| ReadLPCReg(0x61) ; //low byte
  176. FirIOBase=FirIOBase ;
  177. info.fir_base=FirIOBase;
  178. info.irq=FirIRQ;
  179. info.dma=FirDRQ1;
  180. info.dma2=FirDRQ0;
  181. pci_read_config_byte(pcidev,0x40,&bTmp);
  182. pci_write_config_byte(pcidev,0x40,((bTmp | 0x08) & 0xfe));
  183. pci_read_config_byte(pcidev,0x42,&bTmp);
  184. pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
  185. pci_write_config_byte(pcidev,0x5a,0xc0);
  186. WriteLPCReg(0x28, 0x70 );
  187. if (via_ircc_open(0, &info,0x3076) == 0)
  188. rc=0;
  189. } else
  190. rc = -ENODEV; //IR not turn on
  191. } else { //Not VT1211
  192. IRDA_DEBUG(2, "%s(): Chipset = 3096\n", __FUNCTION__);
  193. pci_read_config_byte(pcidev,0x67,&bTmp);//check if BIOS Enable Fir
  194. if((bTmp&0x01)==1) { // BIOS enable FIR
  195. //Enable Double DMA clock
  196. pci_read_config_byte(pcidev,0x42,&oldPCI_40);
  197. pci_write_config_byte(pcidev,0x42,oldPCI_40 | 0x80);
  198. pci_read_config_byte(pcidev,0x40,&oldPCI_40);
  199. pci_write_config_byte(pcidev,0x40,oldPCI_40 & 0xf7);
  200. pci_read_config_byte(pcidev,0x44,&oldPCI_44);
  201. pci_write_config_byte(pcidev,0x44,0x4e);
  202. //---------- read configuration from Function0 of south bridge
  203. if((bTmp&0x02)==0) {
  204. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  205. FirDRQ0 = (bTmp1 & 0x30) >> 4;
  206. pci_read_config_byte(pcidev,0x44,&bTmp1);
  207. FirDRQ1 = (bTmp1 & 0xc0) >> 6;
  208. } else {
  209. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  210. FirDRQ0 = (bTmp1 & 0x30) >> 4 ;
  211. FirDRQ1=0;
  212. }
  213. pci_read_config_byte(pcidev,0x47,&bTmp1); //IRQ
  214. FirIRQ = bTmp1 & 0x0f;
  215. pci_read_config_byte(pcidev,0x69,&bTmp);
  216. FirIOBase = bTmp << 8;//hight byte
  217. pci_read_config_byte(pcidev,0x68,&bTmp);
  218. FirIOBase = (FirIOBase | bTmp ) & 0xfff0;
  219. //-------------------------
  220. info.fir_base=FirIOBase;
  221. info.irq=FirIRQ;
  222. info.dma=FirDRQ1;
  223. info.dma2=FirDRQ0;
  224. if (via_ircc_open(0, &info,0x3096) == 0)
  225. rc=0;
  226. } else
  227. rc = -ENODEV; //IR not turn on !!!!!
  228. }//Not VT1211
  229. IRDA_DEBUG(2, "%s(): End - rc = %d\n", __FUNCTION__, rc);
  230. return rc;
  231. }
  232. /*
  233. * Function via_ircc_clean ()
  234. *
  235. * Close all configured chips
  236. *
  237. */
  238. static void via_ircc_clean(void)
  239. {
  240. int i;
  241. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  242. for (i=0; i < 4; i++) {
  243. if (dev_self[i])
  244. via_ircc_close(dev_self[i]);
  245. }
  246. }
  247. static void __devexit via_remove_one (struct pci_dev *pdev)
  248. {
  249. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  250. /* FIXME : This is ugly. We should use pci_get_drvdata(pdev);
  251. * to get our driver instance and call directly via_ircc_close().
  252. * See vlsi_ir for details...
  253. * Jean II */
  254. via_ircc_clean();
  255. /* FIXME : This should be in via_ircc_close(), because here we may
  256. * theoritically disable still configured devices :-( - Jean II */
  257. pci_disable_device(pdev);
  258. }
  259. static void __exit via_ircc_cleanup(void)
  260. {
  261. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  262. /* FIXME : This should be redundant, as pci_unregister_driver()
  263. * should call via_remove_one() on each device.
  264. * Jean II */
  265. via_ircc_clean();
  266. /* Cleanup all instances of the driver */
  267. pci_unregister_driver (&via_driver);
  268. }
  269. /*
  270. * Function via_ircc_open (iobase, irq)
  271. *
  272. * Open driver instance
  273. *
  274. */
  275. static __devinit int via_ircc_open(int i, chipio_t * info, unsigned int id)
  276. {
  277. struct net_device *dev;
  278. struct via_ircc_cb *self;
  279. int err;
  280. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  281. /* Allocate new instance of the driver */
  282. dev = alloc_irdadev(sizeof(struct via_ircc_cb));
  283. if (dev == NULL)
  284. return -ENOMEM;
  285. self = dev->priv;
  286. self->netdev = dev;
  287. spin_lock_init(&self->lock);
  288. /* FIXME : We should store our driver instance in the PCI layer,
  289. * using pci_set_drvdata(), not in this array.
  290. * See vlsi_ir for details... - Jean II */
  291. /* FIXME : 'i' is always 0 (see via_init_one()) :-( - Jean II */
  292. /* Need to store self somewhere */
  293. dev_self[i] = self;
  294. self->index = i;
  295. /* Initialize Resource */
  296. self->io.cfg_base = info->cfg_base;
  297. self->io.fir_base = info->fir_base;
  298. self->io.irq = info->irq;
  299. self->io.fir_ext = CHIP_IO_EXTENT;
  300. self->io.dma = info->dma;
  301. self->io.dma2 = info->dma2;
  302. self->io.fifo_size = 32;
  303. self->chip_id = id;
  304. self->st_fifo.len = 0;
  305. self->RxDataReady = 0;
  306. /* Reserve the ioports that we need */
  307. if (!request_region(self->io.fir_base, self->io.fir_ext, driver_name)) {
  308. IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
  309. __FUNCTION__, self->io.fir_base);
  310. err = -ENODEV;
  311. goto err_out1;
  312. }
  313. /* Initialize QoS for this device */
  314. irda_init_max_qos_capabilies(&self->qos);
  315. /* Check if user has supplied the dongle id or not */
  316. if (!dongle_id)
  317. dongle_id = via_ircc_read_dongle_id(self->io.fir_base);
  318. self->io.dongle_id = dongle_id;
  319. /* The only value we must override it the baudrate */
  320. /* Maximum speeds and capabilities are dongle-dependant. */
  321. switch( self->io.dongle_id ){
  322. case 0x0d:
  323. self->qos.baud_rate.bits =
  324. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200 |
  325. IR_576000 | IR_1152000 | (IR_4000000 << 8);
  326. break;
  327. default:
  328. self->qos.baud_rate.bits =
  329. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200;
  330. break;
  331. }
  332. /* Following was used for testing:
  333. *
  334. * self->qos.baud_rate.bits = IR_9600;
  335. *
  336. * Is is no good, as it prohibits (error-prone) speed-changes.
  337. */
  338. self->qos.min_turn_time.bits = qos_mtt_bits;
  339. irda_qos_bits_to_value(&self->qos);
  340. /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
  341. self->rx_buff.truesize = 14384 + 2048;
  342. self->tx_buff.truesize = 14384 + 2048;
  343. /* Allocate memory if needed */
  344. self->rx_buff.head =
  345. dma_alloc_coherent(NULL, self->rx_buff.truesize,
  346. &self->rx_buff_dma, GFP_KERNEL);
  347. if (self->rx_buff.head == NULL) {
  348. err = -ENOMEM;
  349. goto err_out2;
  350. }
  351. memset(self->rx_buff.head, 0, self->rx_buff.truesize);
  352. self->tx_buff.head =
  353. dma_alloc_coherent(NULL, self->tx_buff.truesize,
  354. &self->tx_buff_dma, GFP_KERNEL);
  355. if (self->tx_buff.head == NULL) {
  356. err = -ENOMEM;
  357. goto err_out3;
  358. }
  359. memset(self->tx_buff.head, 0, self->tx_buff.truesize);
  360. self->rx_buff.in_frame = FALSE;
  361. self->rx_buff.state = OUTSIDE_FRAME;
  362. self->tx_buff.data = self->tx_buff.head;
  363. self->rx_buff.data = self->rx_buff.head;
  364. /* Reset Tx queue info */
  365. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  366. self->tx_fifo.tail = self->tx_buff.head;
  367. /* Keep track of module usage */
  368. SET_MODULE_OWNER(dev);
  369. /* Override the network functions we need to use */
  370. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  371. dev->open = via_ircc_net_open;
  372. dev->stop = via_ircc_net_close;
  373. dev->do_ioctl = via_ircc_net_ioctl;
  374. dev->get_stats = via_ircc_net_get_stats;
  375. err = register_netdev(dev);
  376. if (err)
  377. goto err_out4;
  378. IRDA_MESSAGE("IrDA: Registered device %s (via-ircc)\n", dev->name);
  379. /* Initialise the hardware..
  380. */
  381. self->io.speed = 9600;
  382. via_hw_init(self);
  383. return 0;
  384. err_out4:
  385. dma_free_coherent(NULL, self->tx_buff.truesize,
  386. self->tx_buff.head, self->tx_buff_dma);
  387. err_out3:
  388. dma_free_coherent(NULL, self->rx_buff.truesize,
  389. self->rx_buff.head, self->rx_buff_dma);
  390. err_out2:
  391. release_region(self->io.fir_base, self->io.fir_ext);
  392. err_out1:
  393. free_netdev(dev);
  394. dev_self[i] = NULL;
  395. return err;
  396. }
  397. /*
  398. * Function via_ircc_close (self)
  399. *
  400. * Close driver instance
  401. *
  402. */
  403. static int via_ircc_close(struct via_ircc_cb *self)
  404. {
  405. int iobase;
  406. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  407. IRDA_ASSERT(self != NULL, return -1;);
  408. iobase = self->io.fir_base;
  409. ResetChip(iobase, 5); //hardware reset.
  410. /* Remove netdevice */
  411. unregister_netdev(self->netdev);
  412. /* Release the PORT that this driver is using */
  413. IRDA_DEBUG(2, "%s(), Releasing Region %03x\n",
  414. __FUNCTION__, self->io.fir_base);
  415. release_region(self->io.fir_base, self->io.fir_ext);
  416. if (self->tx_buff.head)
  417. dma_free_coherent(NULL, self->tx_buff.truesize,
  418. self->tx_buff.head, self->tx_buff_dma);
  419. if (self->rx_buff.head)
  420. dma_free_coherent(NULL, self->rx_buff.truesize,
  421. self->rx_buff.head, self->rx_buff_dma);
  422. dev_self[self->index] = NULL;
  423. free_netdev(self->netdev);
  424. return 0;
  425. }
  426. /*
  427. * Function via_hw_init(self)
  428. *
  429. * Returns non-negative on success.
  430. *
  431. * Formerly via_ircc_setup
  432. */
  433. static void via_hw_init(struct via_ircc_cb *self)
  434. {
  435. int iobase = self->io.fir_base;
  436. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  437. SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
  438. // FIFO Init
  439. EnRXFIFOReadyInt(iobase, OFF);
  440. EnRXFIFOHalfLevelInt(iobase, OFF);
  441. EnTXFIFOHalfLevelInt(iobase, OFF);
  442. EnTXFIFOUnderrunEOMInt(iobase, ON);
  443. EnTXFIFOReadyInt(iobase, OFF);
  444. InvertTX(iobase, OFF);
  445. InvertRX(iobase, OFF);
  446. if (ReadLPCReg(0x20) == 0x3c)
  447. WriteLPCReg(0xF0, 0); // for VT1211
  448. /* Int Init */
  449. EnRXSpecInt(iobase, ON);
  450. /* The following is basically hwreset */
  451. /* If this is the case, why not just call hwreset() ? Jean II */
  452. ResetChip(iobase, 5);
  453. EnableDMA(iobase, OFF);
  454. EnableTX(iobase, OFF);
  455. EnableRX(iobase, OFF);
  456. EnRXDMA(iobase, OFF);
  457. EnTXDMA(iobase, OFF);
  458. RXStart(iobase, OFF);
  459. TXStart(iobase, OFF);
  460. InitCard(iobase);
  461. CommonInit(iobase);
  462. SIRFilter(iobase, ON);
  463. SetSIR(iobase, ON);
  464. CRC16(iobase, ON);
  465. EnTXCRC(iobase, 0);
  466. WriteReg(iobase, I_ST_CT_0, 0x00);
  467. SetBaudRate(iobase, 9600);
  468. SetPulseWidth(iobase, 12);
  469. SetSendPreambleCount(iobase, 0);
  470. self->io.speed = 9600;
  471. self->st_fifo.len = 0;
  472. via_ircc_change_dongle_speed(iobase, self->io.speed,
  473. self->io.dongle_id);
  474. WriteReg(iobase, I_ST_CT_0, 0x80);
  475. }
  476. /*
  477. * Function via_ircc_read_dongle_id (void)
  478. *
  479. */
  480. static int via_ircc_read_dongle_id(int iobase)
  481. {
  482. int dongle_id = 9; /* Default to IBM */
  483. IRDA_ERROR("via-ircc: dongle probing not supported, please specify dongle_id module parameter.\n");
  484. return dongle_id;
  485. }
  486. /*
  487. * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
  488. * Change speed of the attach dongle
  489. * only implement two type of dongle currently.
  490. */
  491. static void via_ircc_change_dongle_speed(int iobase, int speed,
  492. int dongle_id)
  493. {
  494. u8 mode = 0;
  495. /* speed is unused, as we use IsSIROn()/IsMIROn() */
  496. speed = speed;
  497. IRDA_DEBUG(1, "%s(): change_dongle_speed to %d for 0x%x, %d\n",
  498. __FUNCTION__, speed, iobase, dongle_id);
  499. switch (dongle_id) {
  500. /* Note: The dongle_id's listed here are derived from
  501. * nsc-ircc.c */
  502. case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
  503. UseOneRX(iobase, ON); // use one RX pin RX1,RX2
  504. InvertTX(iobase, OFF);
  505. InvertRX(iobase, OFF);
  506. EnRX2(iobase, ON); //sir to rx2
  507. EnGPIOtoRX2(iobase, OFF);
  508. if (IsSIROn(iobase)) { //sir
  509. // Mode select Off
  510. SlowIRRXLowActive(iobase, ON);
  511. udelay(1000);
  512. SlowIRRXLowActive(iobase, OFF);
  513. } else {
  514. if (IsMIROn(iobase)) { //mir
  515. // Mode select On
  516. SlowIRRXLowActive(iobase, OFF);
  517. udelay(20);
  518. } else { // fir
  519. if (IsFIROn(iobase)) { //fir
  520. // Mode select On
  521. SlowIRRXLowActive(iobase, OFF);
  522. udelay(20);
  523. }
  524. }
  525. }
  526. break;
  527. case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
  528. UseOneRX(iobase, ON); //use ONE RX....RX1
  529. InvertTX(iobase, OFF);
  530. InvertRX(iobase, OFF); // invert RX pin
  531. EnRX2(iobase, ON);
  532. EnGPIOtoRX2(iobase, OFF);
  533. if (IsSIROn(iobase)) { //sir
  534. // Mode select On
  535. SlowIRRXLowActive(iobase, ON);
  536. udelay(20);
  537. // Mode select Off
  538. SlowIRRXLowActive(iobase, OFF);
  539. }
  540. if (IsMIROn(iobase)) { //mir
  541. // Mode select On
  542. SlowIRRXLowActive(iobase, OFF);
  543. udelay(20);
  544. // Mode select Off
  545. SlowIRRXLowActive(iobase, ON);
  546. } else { // fir
  547. if (IsFIROn(iobase)) { //fir
  548. // Mode select On
  549. SlowIRRXLowActive(iobase, OFF);
  550. // TX On
  551. WriteTX(iobase, ON);
  552. udelay(20);
  553. // Mode select OFF
  554. SlowIRRXLowActive(iobase, ON);
  555. udelay(20);
  556. // TX Off
  557. WriteTX(iobase, OFF);
  558. }
  559. }
  560. break;
  561. case 0x0d:
  562. UseOneRX(iobase, OFF); // use two RX pin RX1,RX2
  563. InvertTX(iobase, OFF);
  564. InvertRX(iobase, OFF);
  565. SlowIRRXLowActive(iobase, OFF);
  566. if (IsSIROn(iobase)) { //sir
  567. EnGPIOtoRX2(iobase, OFF);
  568. WriteGIO(iobase, OFF);
  569. EnRX2(iobase, OFF); //sir to rx2
  570. } else { // fir mir
  571. EnGPIOtoRX2(iobase, OFF);
  572. WriteGIO(iobase, OFF);
  573. EnRX2(iobase, OFF); //fir to rx
  574. }
  575. break;
  576. case 0x11: /* Temic TFDS4500 */
  577. IRDA_DEBUG(2, "%s: Temic TFDS4500: One RX pin, TX normal, RX inverted.\n", __FUNCTION__);
  578. UseOneRX(iobase, ON); //use ONE RX....RX1
  579. InvertTX(iobase, OFF);
  580. InvertRX(iobase, ON); // invert RX pin
  581. EnRX2(iobase, ON); //sir to rx2
  582. EnGPIOtoRX2(iobase, OFF);
  583. if( IsSIROn(iobase) ){ //sir
  584. // Mode select On
  585. SlowIRRXLowActive(iobase, ON);
  586. udelay(20);
  587. // Mode select Off
  588. SlowIRRXLowActive(iobase, OFF);
  589. } else{
  590. IRDA_DEBUG(0, "%s: Warning: TFDS4500 not running in SIR mode !\n", __FUNCTION__);
  591. }
  592. break;
  593. case 0x0ff: /* Vishay */
  594. if (IsSIROn(iobase))
  595. mode = 0;
  596. else if (IsMIROn(iobase))
  597. mode = 1;
  598. else if (IsFIROn(iobase))
  599. mode = 2;
  600. else if (IsVFIROn(iobase))
  601. mode = 5; //VFIR-16
  602. SI_SetMode(iobase, mode);
  603. break;
  604. default:
  605. IRDA_ERROR("%s: Error: dongle_id %d unsupported !\n",
  606. __FUNCTION__, dongle_id);
  607. }
  608. }
  609. /*
  610. * Function via_ircc_change_speed (self, baud)
  611. *
  612. * Change the speed of the device
  613. *
  614. */
  615. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 speed)
  616. {
  617. struct net_device *dev = self->netdev;
  618. u16 iobase;
  619. u8 value = 0, bTmp;
  620. iobase = self->io.fir_base;
  621. /* Update accounting for new speed */
  622. self->io.speed = speed;
  623. IRDA_DEBUG(1, "%s: change_speed to %d bps.\n", __FUNCTION__, speed);
  624. WriteReg(iobase, I_ST_CT_0, 0x0);
  625. /* Controller mode sellection */
  626. switch (speed) {
  627. case 2400:
  628. case 9600:
  629. case 19200:
  630. case 38400:
  631. case 57600:
  632. case 115200:
  633. value = (115200/speed)-1;
  634. SetSIR(iobase, ON);
  635. CRC16(iobase, ON);
  636. break;
  637. case 576000:
  638. /* FIXME: this can't be right, as it's the same as 115200,
  639. * and 576000 is MIR, not SIR. */
  640. value = 0;
  641. SetSIR(iobase, ON);
  642. CRC16(iobase, ON);
  643. break;
  644. case 1152000:
  645. value = 0;
  646. SetMIR(iobase, ON);
  647. /* FIXME: CRC ??? */
  648. break;
  649. case 4000000:
  650. value = 0;
  651. SetFIR(iobase, ON);
  652. SetPulseWidth(iobase, 0);
  653. SetSendPreambleCount(iobase, 14);
  654. CRC16(iobase, OFF);
  655. EnTXCRC(iobase, ON);
  656. break;
  657. case 16000000:
  658. value = 0;
  659. SetVFIR(iobase, ON);
  660. /* FIXME: CRC ??? */
  661. break;
  662. default:
  663. value = 0;
  664. break;
  665. }
  666. /* Set baudrate to 0x19[2..7] */
  667. bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
  668. bTmp |= value << 2;
  669. WriteReg(iobase, I_CF_H_1, bTmp);
  670. /* Some dongles may need to be informed about speed changes. */
  671. via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
  672. /* Set FIFO size to 64 */
  673. SetFIFO(iobase, 64);
  674. /* Enable IR */
  675. WriteReg(iobase, I_ST_CT_0, 0x80);
  676. // EnTXFIFOHalfLevelInt(iobase,ON);
  677. /* Enable some interrupts so we can receive frames */
  678. //EnAllInt(iobase,ON);
  679. if (IsSIROn(iobase)) {
  680. SIRFilter(iobase, ON);
  681. SIRRecvAny(iobase, ON);
  682. } else {
  683. SIRFilter(iobase, OFF);
  684. SIRRecvAny(iobase, OFF);
  685. }
  686. if (speed > 115200) {
  687. /* Install FIR xmit handler */
  688. dev->hard_start_xmit = via_ircc_hard_xmit_fir;
  689. via_ircc_dma_receive(self);
  690. } else {
  691. /* Install SIR xmit handler */
  692. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  693. }
  694. netif_wake_queue(dev);
  695. }
  696. /*
  697. * Function via_ircc_hard_xmit (skb, dev)
  698. *
  699. * Transmit the frame!
  700. *
  701. */
  702. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  703. struct net_device *dev)
  704. {
  705. struct via_ircc_cb *self;
  706. unsigned long flags;
  707. u16 iobase;
  708. __u32 speed;
  709. self = (struct via_ircc_cb *) dev->priv;
  710. IRDA_ASSERT(self != NULL, return 0;);
  711. iobase = self->io.fir_base;
  712. netif_stop_queue(dev);
  713. /* Check if we need to change the speed */
  714. speed = irda_get_next_speed(skb);
  715. if ((speed != self->io.speed) && (speed != -1)) {
  716. /* Check for empty frame */
  717. if (!skb->len) {
  718. via_ircc_change_speed(self, speed);
  719. dev->trans_start = jiffies;
  720. dev_kfree_skb(skb);
  721. return 0;
  722. } else
  723. self->new_speed = speed;
  724. }
  725. InitCard(iobase);
  726. CommonInit(iobase);
  727. SIRFilter(iobase, ON);
  728. SetSIR(iobase, ON);
  729. CRC16(iobase, ON);
  730. EnTXCRC(iobase, 0);
  731. WriteReg(iobase, I_ST_CT_0, 0x00);
  732. spin_lock_irqsave(&self->lock, flags);
  733. self->tx_buff.data = self->tx_buff.head;
  734. self->tx_buff.len =
  735. async_wrap_skb(skb, self->tx_buff.data,
  736. self->tx_buff.truesize);
  737. self->stats.tx_bytes += self->tx_buff.len;
  738. /* Send this frame with old speed */
  739. SetBaudRate(iobase, self->io.speed);
  740. SetPulseWidth(iobase, 12);
  741. SetSendPreambleCount(iobase, 0);
  742. WriteReg(iobase, I_ST_CT_0, 0x80);
  743. EnableTX(iobase, ON);
  744. EnableRX(iobase, OFF);
  745. ResetChip(iobase, 0);
  746. ResetChip(iobase, 1);
  747. ResetChip(iobase, 2);
  748. ResetChip(iobase, 3);
  749. ResetChip(iobase, 4);
  750. EnAllInt(iobase, ON);
  751. EnTXDMA(iobase, ON);
  752. EnRXDMA(iobase, OFF);
  753. irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
  754. DMA_TX_MODE);
  755. SetSendByte(iobase, self->tx_buff.len);
  756. RXStart(iobase, OFF);
  757. TXStart(iobase, ON);
  758. dev->trans_start = jiffies;
  759. spin_unlock_irqrestore(&self->lock, flags);
  760. dev_kfree_skb(skb);
  761. return 0;
  762. }
  763. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  764. struct net_device *dev)
  765. {
  766. struct via_ircc_cb *self;
  767. u16 iobase;
  768. __u32 speed;
  769. unsigned long flags;
  770. self = (struct via_ircc_cb *) dev->priv;
  771. iobase = self->io.fir_base;
  772. if (self->st_fifo.len)
  773. return 0;
  774. if (self->chip_id == 0x3076)
  775. iodelay(1500);
  776. else
  777. udelay(1500);
  778. netif_stop_queue(dev);
  779. speed = irda_get_next_speed(skb);
  780. if ((speed != self->io.speed) && (speed != -1)) {
  781. if (!skb->len) {
  782. via_ircc_change_speed(self, speed);
  783. dev->trans_start = jiffies;
  784. dev_kfree_skb(skb);
  785. return 0;
  786. } else
  787. self->new_speed = speed;
  788. }
  789. spin_lock_irqsave(&self->lock, flags);
  790. self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
  791. self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
  792. self->tx_fifo.tail += skb->len;
  793. self->stats.tx_bytes += skb->len;
  794. memcpy(self->tx_fifo.queue[self->tx_fifo.free].start, skb->data,
  795. skb->len);
  796. self->tx_fifo.len++;
  797. self->tx_fifo.free++;
  798. //F01 if (self->tx_fifo.len == 1) {
  799. via_ircc_dma_xmit(self, iobase);
  800. //F01 }
  801. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) netif_wake_queue(self->netdev);
  802. dev->trans_start = jiffies;
  803. dev_kfree_skb(skb);
  804. spin_unlock_irqrestore(&self->lock, flags);
  805. return 0;
  806. }
  807. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
  808. {
  809. EnTXDMA(iobase, OFF);
  810. self->io.direction = IO_XMIT;
  811. EnPhys(iobase, ON);
  812. EnableTX(iobase, ON);
  813. EnableRX(iobase, OFF);
  814. ResetChip(iobase, 0);
  815. ResetChip(iobase, 1);
  816. ResetChip(iobase, 2);
  817. ResetChip(iobase, 3);
  818. ResetChip(iobase, 4);
  819. EnAllInt(iobase, ON);
  820. EnTXDMA(iobase, ON);
  821. EnRXDMA(iobase, OFF);
  822. irda_setup_dma(self->io.dma,
  823. ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
  824. self->tx_buff.head) + self->tx_buff_dma,
  825. self->tx_fifo.queue[self->tx_fifo.ptr].len, DMA_TX_MODE);
  826. IRDA_DEBUG(1, "%s: tx_fifo.ptr=%x,len=%x,tx_fifo.len=%x..\n",
  827. __FUNCTION__, self->tx_fifo.ptr,
  828. self->tx_fifo.queue[self->tx_fifo.ptr].len,
  829. self->tx_fifo.len);
  830. SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
  831. RXStart(iobase, OFF);
  832. TXStart(iobase, ON);
  833. return 0;
  834. }
  835. /*
  836. * Function via_ircc_dma_xmit_complete (self)
  837. *
  838. * The transfer of a frame in finished. This function will only be called
  839. * by the interrupt handler
  840. *
  841. */
  842. static int via_ircc_dma_xmit_complete(struct via_ircc_cb *self)
  843. {
  844. int iobase;
  845. int ret = TRUE;
  846. u8 Tx_status;
  847. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  848. iobase = self->io.fir_base;
  849. /* Disable DMA */
  850. // DisableDmaChannel(self->io.dma);
  851. /* Check for underrrun! */
  852. /* Clear bit, by writing 1 into it */
  853. Tx_status = GetTXStatus(iobase);
  854. if (Tx_status & 0x08) {
  855. self->stats.tx_errors++;
  856. self->stats.tx_fifo_errors++;
  857. hwreset(self);
  858. // how to clear underrrun ?
  859. } else {
  860. self->stats.tx_packets++;
  861. ResetChip(iobase, 3);
  862. ResetChip(iobase, 4);
  863. }
  864. /* Check if we need to change the speed */
  865. if (self->new_speed) {
  866. via_ircc_change_speed(self, self->new_speed);
  867. self->new_speed = 0;
  868. }
  869. /* Finished with this frame, so prepare for next */
  870. if (IsFIROn(iobase)) {
  871. if (self->tx_fifo.len) {
  872. self->tx_fifo.len--;
  873. self->tx_fifo.ptr++;
  874. }
  875. }
  876. IRDA_DEBUG(1,
  877. "%s: tx_fifo.len=%x ,tx_fifo.ptr=%x,tx_fifo.free=%x...\n",
  878. __FUNCTION__,
  879. self->tx_fifo.len, self->tx_fifo.ptr, self->tx_fifo.free);
  880. /* F01_S
  881. // Any frames to be sent back-to-back?
  882. if (self->tx_fifo.len) {
  883. // Not finished yet!
  884. via_ircc_dma_xmit(self, iobase);
  885. ret = FALSE;
  886. } else {
  887. F01_E*/
  888. // Reset Tx FIFO info
  889. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  890. self->tx_fifo.tail = self->tx_buff.head;
  891. //F01 }
  892. // Make sure we have room for more frames
  893. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) {
  894. // Not busy transmitting anymore
  895. // Tell the network layer, that we can accept more frames
  896. netif_wake_queue(self->netdev);
  897. //F01 }
  898. return ret;
  899. }
  900. /*
  901. * Function via_ircc_dma_receive (self)
  902. *
  903. * Set configuration for receive a frame.
  904. *
  905. */
  906. static int via_ircc_dma_receive(struct via_ircc_cb *self)
  907. {
  908. int iobase;
  909. iobase = self->io.fir_base;
  910. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  911. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  912. self->tx_fifo.tail = self->tx_buff.head;
  913. self->RxDataReady = 0;
  914. self->io.direction = IO_RECV;
  915. self->rx_buff.data = self->rx_buff.head;
  916. self->st_fifo.len = self->st_fifo.pending_bytes = 0;
  917. self->st_fifo.tail = self->st_fifo.head = 0;
  918. EnPhys(iobase, ON);
  919. EnableTX(iobase, OFF);
  920. EnableRX(iobase, ON);
  921. ResetChip(iobase, 0);
  922. ResetChip(iobase, 1);
  923. ResetChip(iobase, 2);
  924. ResetChip(iobase, 3);
  925. ResetChip(iobase, 4);
  926. EnAllInt(iobase, ON);
  927. EnTXDMA(iobase, OFF);
  928. EnRXDMA(iobase, ON);
  929. irda_setup_dma(self->io.dma2, self->rx_buff_dma,
  930. self->rx_buff.truesize, DMA_RX_MODE);
  931. TXStart(iobase, OFF);
  932. RXStart(iobase, ON);
  933. return 0;
  934. }
  935. /*
  936. * Function via_ircc_dma_receive_complete (self)
  937. *
  938. * Controller Finished with receiving frames,
  939. * and this routine is call by ISR
  940. *
  941. */
  942. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  943. int iobase)
  944. {
  945. struct st_fifo *st_fifo;
  946. struct sk_buff *skb;
  947. int len, i;
  948. u8 status = 0;
  949. iobase = self->io.fir_base;
  950. st_fifo = &self->st_fifo;
  951. if (self->io.speed < 4000000) { //Speed below FIR
  952. len = GetRecvByte(iobase, self);
  953. skb = dev_alloc_skb(len + 1);
  954. if (skb == NULL)
  955. return FALSE;
  956. // Make sure IP header gets aligned
  957. skb_reserve(skb, 1);
  958. skb_put(skb, len - 2);
  959. if (self->chip_id == 0x3076) {
  960. for (i = 0; i < len - 2; i++)
  961. skb->data[i] = self->rx_buff.data[i * 2];
  962. } else {
  963. if (self->chip_id == 0x3096) {
  964. for (i = 0; i < len - 2; i++)
  965. skb->data[i] =
  966. self->rx_buff.data[i];
  967. }
  968. }
  969. // Move to next frame
  970. self->rx_buff.data += len;
  971. self->stats.rx_bytes += len;
  972. self->stats.rx_packets++;
  973. skb->dev = self->netdev;
  974. skb->mac.raw = skb->data;
  975. skb->protocol = htons(ETH_P_IRDA);
  976. netif_rx(skb);
  977. return TRUE;
  978. }
  979. else { //FIR mode
  980. len = GetRecvByte(iobase, self);
  981. if (len == 0)
  982. return TRUE; //interrupt only, data maybe move by RxT
  983. if (((len - 4) < 2) || ((len - 4) > 2048)) {
  984. IRDA_DEBUG(1, "%s(): Trouble:len=%x,CurCount=%x,LastCount=%x..\n",
  985. __FUNCTION__, len, RxCurCount(iobase, self),
  986. self->RxLastCount);
  987. hwreset(self);
  988. return FALSE;
  989. }
  990. IRDA_DEBUG(2, "%s(): fifo.len=%x,len=%x,CurCount=%x..\n",
  991. __FUNCTION__,
  992. st_fifo->len, len - 4, RxCurCount(iobase, self));
  993. st_fifo->entries[st_fifo->tail].status = status;
  994. st_fifo->entries[st_fifo->tail].len = len;
  995. st_fifo->pending_bytes += len;
  996. st_fifo->tail++;
  997. st_fifo->len++;
  998. if (st_fifo->tail > MAX_RX_WINDOW)
  999. st_fifo->tail = 0;
  1000. self->RxDataReady = 0;
  1001. // It maybe have MAX_RX_WINDOW package receive by
  1002. // receive_complete before Timer IRQ
  1003. /* F01_S
  1004. if (st_fifo->len < (MAX_RX_WINDOW+2 )) {
  1005. RXStart(iobase,ON);
  1006. SetTimer(iobase,4);
  1007. }
  1008. else {
  1009. F01_E */
  1010. EnableRX(iobase, OFF);
  1011. EnRXDMA(iobase, OFF);
  1012. RXStart(iobase, OFF);
  1013. //F01_S
  1014. // Put this entry back in fifo
  1015. if (st_fifo->head > MAX_RX_WINDOW)
  1016. st_fifo->head = 0;
  1017. status = st_fifo->entries[st_fifo->head].status;
  1018. len = st_fifo->entries[st_fifo->head].len;
  1019. st_fifo->head++;
  1020. st_fifo->len--;
  1021. skb = dev_alloc_skb(len + 1 - 4);
  1022. /*
  1023. * if frame size,data ptr,or skb ptr are wrong ,the get next
  1024. * entry.
  1025. */
  1026. if ((skb == NULL) || (skb->data == NULL)
  1027. || (self->rx_buff.data == NULL) || (len < 6)) {
  1028. self->stats.rx_dropped++;
  1029. return TRUE;
  1030. }
  1031. skb_reserve(skb, 1);
  1032. skb_put(skb, len - 4);
  1033. memcpy(skb->data, self->rx_buff.data, len - 4);
  1034. IRDA_DEBUG(2, "%s(): len=%x.rx_buff=%p\n", __FUNCTION__,
  1035. len - 4, self->rx_buff.data);
  1036. // Move to next frame
  1037. self->rx_buff.data += len;
  1038. self->stats.rx_bytes += len;
  1039. self->stats.rx_packets++;
  1040. skb->dev = self->netdev;
  1041. skb->mac.raw = skb->data;
  1042. skb->protocol = htons(ETH_P_IRDA);
  1043. netif_rx(skb);
  1044. //F01_E
  1045. } //FIR
  1046. return TRUE;
  1047. }
  1048. /*
  1049. * if frame is received , but no INT ,then use this routine to upload frame.
  1050. */
  1051. static int upload_rxdata(struct via_ircc_cb *self, int iobase)
  1052. {
  1053. struct sk_buff *skb;
  1054. int len;
  1055. struct st_fifo *st_fifo;
  1056. st_fifo = &self->st_fifo;
  1057. len = GetRecvByte(iobase, self);
  1058. IRDA_DEBUG(2, "%s(): len=%x\n", __FUNCTION__, len);
  1059. skb = dev_alloc_skb(len + 1);
  1060. if ((skb == NULL) || ((len - 4) < 2)) {
  1061. self->stats.rx_dropped++;
  1062. return FALSE;
  1063. }
  1064. skb_reserve(skb, 1);
  1065. skb_put(skb, len - 4 + 1);
  1066. memcpy(skb->data, self->rx_buff.data, len - 4 + 1);
  1067. st_fifo->tail++;
  1068. st_fifo->len++;
  1069. if (st_fifo->tail > MAX_RX_WINDOW)
  1070. st_fifo->tail = 0;
  1071. // Move to next frame
  1072. self->rx_buff.data += len;
  1073. self->stats.rx_bytes += len;
  1074. self->stats.rx_packets++;
  1075. skb->dev = self->netdev;
  1076. skb->mac.raw = skb->data;
  1077. skb->protocol = htons(ETH_P_IRDA);
  1078. netif_rx(skb);
  1079. if (st_fifo->len < (MAX_RX_WINDOW + 2)) {
  1080. RXStart(iobase, ON);
  1081. } else {
  1082. EnableRX(iobase, OFF);
  1083. EnRXDMA(iobase, OFF);
  1084. RXStart(iobase, OFF);
  1085. }
  1086. return TRUE;
  1087. }
  1088. /*
  1089. * Implement back to back receive , use this routine to upload data.
  1090. */
  1091. static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
  1092. {
  1093. struct st_fifo *st_fifo;
  1094. struct sk_buff *skb;
  1095. int len;
  1096. u8 status;
  1097. st_fifo = &self->st_fifo;
  1098. if (CkRxRecv(iobase, self)) {
  1099. // if still receiving ,then return ,don't upload frame
  1100. self->RetryCount = 0;
  1101. SetTimer(iobase, 20);
  1102. self->RxDataReady++;
  1103. return FALSE;
  1104. } else
  1105. self->RetryCount++;
  1106. if ((self->RetryCount >= 1) ||
  1107. ((st_fifo->pending_bytes + 2048) > self->rx_buff.truesize)
  1108. || (st_fifo->len >= (MAX_RX_WINDOW))) {
  1109. while (st_fifo->len > 0) { //upload frame
  1110. // Put this entry back in fifo
  1111. if (st_fifo->head > MAX_RX_WINDOW)
  1112. st_fifo->head = 0;
  1113. status = st_fifo->entries[st_fifo->head].status;
  1114. len = st_fifo->entries[st_fifo->head].len;
  1115. st_fifo->head++;
  1116. st_fifo->len--;
  1117. skb = dev_alloc_skb(len + 1 - 4);
  1118. /*
  1119. * if frame size, data ptr, or skb ptr are wrong,
  1120. * then get next entry.
  1121. */
  1122. if ((skb == NULL) || (skb->data == NULL)
  1123. || (self->rx_buff.data == NULL) || (len < 6)) {
  1124. self->stats.rx_dropped++;
  1125. continue;
  1126. }
  1127. skb_reserve(skb, 1);
  1128. skb_put(skb, len - 4);
  1129. memcpy(skb->data, self->rx_buff.data, len - 4);
  1130. IRDA_DEBUG(2, "%s(): len=%x.head=%x\n", __FUNCTION__,
  1131. len - 4, st_fifo->head);
  1132. // Move to next frame
  1133. self->rx_buff.data += len;
  1134. self->stats.rx_bytes += len;
  1135. self->stats.rx_packets++;
  1136. skb->dev = self->netdev;
  1137. skb->mac.raw = skb->data;
  1138. skb->protocol = htons(ETH_P_IRDA);
  1139. netif_rx(skb);
  1140. } //while
  1141. self->RetryCount = 0;
  1142. IRDA_DEBUG(2,
  1143. "%s(): End of upload HostStatus=%x,RxStatus=%x\n",
  1144. __FUNCTION__,
  1145. GetHostStatus(iobase), GetRXStatus(iobase));
  1146. /*
  1147. * if frame is receive complete at this routine ,then upload
  1148. * frame.
  1149. */
  1150. if ((GetRXStatus(iobase) & 0x10)
  1151. && (RxCurCount(iobase, self) != self->RxLastCount)) {
  1152. upload_rxdata(self, iobase);
  1153. if (irda_device_txqueue_empty(self->netdev))
  1154. via_ircc_dma_receive(self);
  1155. }
  1156. } // timer detect complete
  1157. else
  1158. SetTimer(iobase, 4);
  1159. return TRUE;
  1160. }
  1161. /*
  1162. * Function via_ircc_interrupt (irq, dev_id, regs)
  1163. *
  1164. * An interrupt from the chip has arrived. Time to do some work
  1165. *
  1166. */
  1167. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id,
  1168. struct pt_regs *regs)
  1169. {
  1170. struct net_device *dev = (struct net_device *) dev_id;
  1171. struct via_ircc_cb *self;
  1172. int iobase;
  1173. u8 iHostIntType, iRxIntType, iTxIntType;
  1174. if (!dev) {
  1175. IRDA_WARNING("%s: irq %d for unknown device.\n", driver_name,
  1176. irq);
  1177. return IRQ_NONE;
  1178. }
  1179. self = (struct via_ircc_cb *) dev->priv;
  1180. iobase = self->io.fir_base;
  1181. spin_lock(&self->lock);
  1182. iHostIntType = GetHostStatus(iobase);
  1183. IRDA_DEBUG(4, "%s(): iHostIntType %02x: %s %s %s %02x\n",
  1184. __FUNCTION__, iHostIntType,
  1185. (iHostIntType & 0x40) ? "Timer" : "",
  1186. (iHostIntType & 0x20) ? "Tx" : "",
  1187. (iHostIntType & 0x10) ? "Rx" : "",
  1188. (iHostIntType & 0x0e) >> 1);
  1189. if ((iHostIntType & 0x40) != 0) { //Timer Event
  1190. self->EventFlag.TimeOut++;
  1191. ClearTimerInt(iobase, 1);
  1192. if (self->io.direction == IO_XMIT) {
  1193. via_ircc_dma_xmit(self, iobase);
  1194. }
  1195. if (self->io.direction == IO_RECV) {
  1196. /*
  1197. * frame ready hold too long, must reset.
  1198. */
  1199. if (self->RxDataReady > 30) {
  1200. hwreset(self);
  1201. if (irda_device_txqueue_empty(self->netdev)) {
  1202. via_ircc_dma_receive(self);
  1203. }
  1204. } else { // call this to upload frame.
  1205. RxTimerHandler(self, iobase);
  1206. }
  1207. } //RECV
  1208. } //Timer Event
  1209. if ((iHostIntType & 0x20) != 0) { //Tx Event
  1210. iTxIntType = GetTXStatus(iobase);
  1211. IRDA_DEBUG(4, "%s(): iTxIntType %02x: %s %s %s %s\n",
  1212. __FUNCTION__, iTxIntType,
  1213. (iTxIntType & 0x08) ? "FIFO underr." : "",
  1214. (iTxIntType & 0x04) ? "EOM" : "",
  1215. (iTxIntType & 0x02) ? "FIFO ready" : "",
  1216. (iTxIntType & 0x01) ? "Early EOM" : "");
  1217. if (iTxIntType & 0x4) {
  1218. self->EventFlag.EOMessage++; // read and will auto clean
  1219. if (via_ircc_dma_xmit_complete(self)) {
  1220. if (irda_device_txqueue_empty
  1221. (self->netdev)) {
  1222. via_ircc_dma_receive(self);
  1223. }
  1224. } else {
  1225. self->EventFlag.Unknown++;
  1226. }
  1227. } //EOP
  1228. } //Tx Event
  1229. //----------------------------------------
  1230. if ((iHostIntType & 0x10) != 0) { //Rx Event
  1231. /* Check if DMA has finished */
  1232. iRxIntType = GetRXStatus(iobase);
  1233. IRDA_DEBUG(4, "%s(): iRxIntType %02x: %s %s %s %s %s %s %s\n",
  1234. __FUNCTION__, iRxIntType,
  1235. (iRxIntType & 0x80) ? "PHY err." : "",
  1236. (iRxIntType & 0x40) ? "CRC err" : "",
  1237. (iRxIntType & 0x20) ? "FIFO overr." : "",
  1238. (iRxIntType & 0x10) ? "EOF" : "",
  1239. (iRxIntType & 0x08) ? "RxData" : "",
  1240. (iRxIntType & 0x02) ? "RxMaxLen" : "",
  1241. (iRxIntType & 0x01) ? "SIR bad" : "");
  1242. if (!iRxIntType)
  1243. IRDA_DEBUG(3, "%s(): RxIRQ =0\n", __FUNCTION__);
  1244. if (iRxIntType & 0x10) {
  1245. if (via_ircc_dma_receive_complete(self, iobase)) {
  1246. //F01 if(!(IsFIROn(iobase))) via_ircc_dma_receive(self);
  1247. via_ircc_dma_receive(self);
  1248. }
  1249. } // No ERR
  1250. else { //ERR
  1251. IRDA_DEBUG(4, "%s(): RxIRQ ERR:iRxIntType=%x,HostIntType=%x,CurCount=%x,RxLastCount=%x_____\n",
  1252. __FUNCTION__, iRxIntType, iHostIntType,
  1253. RxCurCount(iobase, self),
  1254. self->RxLastCount);
  1255. if (iRxIntType & 0x20) { //FIFO OverRun ERR
  1256. ResetChip(iobase, 0);
  1257. ResetChip(iobase, 1);
  1258. } else { //PHY,CRC ERR
  1259. if (iRxIntType != 0x08)
  1260. hwreset(self); //F01
  1261. }
  1262. via_ircc_dma_receive(self);
  1263. } //ERR
  1264. } //Rx Event
  1265. spin_unlock(&self->lock);
  1266. return IRQ_RETVAL(iHostIntType);
  1267. }
  1268. static void hwreset(struct via_ircc_cb *self)
  1269. {
  1270. int iobase;
  1271. iobase = self->io.fir_base;
  1272. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1273. ResetChip(iobase, 5);
  1274. EnableDMA(iobase, OFF);
  1275. EnableTX(iobase, OFF);
  1276. EnableRX(iobase, OFF);
  1277. EnRXDMA(iobase, OFF);
  1278. EnTXDMA(iobase, OFF);
  1279. RXStart(iobase, OFF);
  1280. TXStart(iobase, OFF);
  1281. InitCard(iobase);
  1282. CommonInit(iobase);
  1283. SIRFilter(iobase, ON);
  1284. SetSIR(iobase, ON);
  1285. CRC16(iobase, ON);
  1286. EnTXCRC(iobase, 0);
  1287. WriteReg(iobase, I_ST_CT_0, 0x00);
  1288. SetBaudRate(iobase, 9600);
  1289. SetPulseWidth(iobase, 12);
  1290. SetSendPreambleCount(iobase, 0);
  1291. WriteReg(iobase, I_ST_CT_0, 0x80);
  1292. /* Restore speed. */
  1293. via_ircc_change_speed(self, self->io.speed);
  1294. self->st_fifo.len = 0;
  1295. }
  1296. /*
  1297. * Function via_ircc_is_receiving (self)
  1298. *
  1299. * Return TRUE is we are currently receiving a frame
  1300. *
  1301. */
  1302. static int via_ircc_is_receiving(struct via_ircc_cb *self)
  1303. {
  1304. int status = FALSE;
  1305. int iobase;
  1306. IRDA_ASSERT(self != NULL, return FALSE;);
  1307. iobase = self->io.fir_base;
  1308. if (CkRxRecv(iobase, self))
  1309. status = TRUE;
  1310. IRDA_DEBUG(2, "%s(): status=%x....\n", __FUNCTION__, status);
  1311. return status;
  1312. }
  1313. /*
  1314. * Function via_ircc_net_open (dev)
  1315. *
  1316. * Start the device
  1317. *
  1318. */
  1319. static int via_ircc_net_open(struct net_device *dev)
  1320. {
  1321. struct via_ircc_cb *self;
  1322. int iobase;
  1323. char hwname[32];
  1324. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1325. IRDA_ASSERT(dev != NULL, return -1;);
  1326. self = (struct via_ircc_cb *) dev->priv;
  1327. self->stats.rx_packets = 0;
  1328. IRDA_ASSERT(self != NULL, return 0;);
  1329. iobase = self->io.fir_base;
  1330. if (request_irq(self->io.irq, via_ircc_interrupt, 0, dev->name, dev)) {
  1331. IRDA_WARNING("%s, unable to allocate irq=%d\n", driver_name,
  1332. self->io.irq);
  1333. return -EAGAIN;
  1334. }
  1335. /*
  1336. * Always allocate the DMA channel after the IRQ, and clean up on
  1337. * failure.
  1338. */
  1339. if (request_dma(self->io.dma, dev->name)) {
  1340. IRDA_WARNING("%s, unable to allocate dma=%d\n", driver_name,
  1341. self->io.dma);
  1342. free_irq(self->io.irq, self);
  1343. return -EAGAIN;
  1344. }
  1345. if (self->io.dma2 != self->io.dma) {
  1346. if (request_dma(self->io.dma2, dev->name)) {
  1347. IRDA_WARNING("%s, unable to allocate dma2=%d\n",
  1348. driver_name, self->io.dma2);
  1349. free_irq(self->io.irq, self);
  1350. return -EAGAIN;
  1351. }
  1352. }
  1353. /* turn on interrupts */
  1354. EnAllInt(iobase, ON);
  1355. EnInternalLoop(iobase, OFF);
  1356. EnExternalLoop(iobase, OFF);
  1357. /* */
  1358. via_ircc_dma_receive(self);
  1359. /* Ready to play! */
  1360. netif_start_queue(dev);
  1361. /*
  1362. * Open new IrLAP layer instance, now that everything should be
  1363. * initialized properly
  1364. */
  1365. sprintf(hwname, "VIA @ 0x%x", iobase);
  1366. self->irlap = irlap_open(dev, &self->qos, hwname);
  1367. self->RxLastCount = 0;
  1368. return 0;
  1369. }
  1370. /*
  1371. * Function via_ircc_net_close (dev)
  1372. *
  1373. * Stop the device
  1374. *
  1375. */
  1376. static int via_ircc_net_close(struct net_device *dev)
  1377. {
  1378. struct via_ircc_cb *self;
  1379. int iobase;
  1380. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1381. IRDA_ASSERT(dev != NULL, return -1;);
  1382. self = (struct via_ircc_cb *) dev->priv;
  1383. IRDA_ASSERT(self != NULL, return 0;);
  1384. /* Stop device */
  1385. netif_stop_queue(dev);
  1386. /* Stop and remove instance of IrLAP */
  1387. if (self->irlap)
  1388. irlap_close(self->irlap);
  1389. self->irlap = NULL;
  1390. iobase = self->io.fir_base;
  1391. EnTXDMA(iobase, OFF);
  1392. EnRXDMA(iobase, OFF);
  1393. DisableDmaChannel(self->io.dma);
  1394. /* Disable interrupts */
  1395. EnAllInt(iobase, OFF);
  1396. free_irq(self->io.irq, dev);
  1397. free_dma(self->io.dma);
  1398. return 0;
  1399. }
  1400. /*
  1401. * Function via_ircc_net_ioctl (dev, rq, cmd)
  1402. *
  1403. * Process IOCTL commands for this device
  1404. *
  1405. */
  1406. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  1407. int cmd)
  1408. {
  1409. struct if_irda_req *irq = (struct if_irda_req *) rq;
  1410. struct via_ircc_cb *self;
  1411. unsigned long flags;
  1412. int ret = 0;
  1413. IRDA_ASSERT(dev != NULL, return -1;);
  1414. self = dev->priv;
  1415. IRDA_ASSERT(self != NULL, return -1;);
  1416. IRDA_DEBUG(1, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name,
  1417. cmd);
  1418. /* Disable interrupts & save flags */
  1419. spin_lock_irqsave(&self->lock, flags);
  1420. switch (cmd) {
  1421. case SIOCSBANDWIDTH: /* Set bandwidth */
  1422. if (!capable(CAP_NET_ADMIN)) {
  1423. ret = -EPERM;
  1424. goto out;
  1425. }
  1426. via_ircc_change_speed(self, irq->ifr_baudrate);
  1427. break;
  1428. case SIOCSMEDIABUSY: /* Set media busy */
  1429. if (!capable(CAP_NET_ADMIN)) {
  1430. ret = -EPERM;
  1431. goto out;
  1432. }
  1433. irda_device_set_media_busy(self->netdev, TRUE);
  1434. break;
  1435. case SIOCGRECEIVING: /* Check if we are receiving right now */
  1436. irq->ifr_receiving = via_ircc_is_receiving(self);
  1437. break;
  1438. default:
  1439. ret = -EOPNOTSUPP;
  1440. }
  1441. out:
  1442. spin_unlock_irqrestore(&self->lock, flags);
  1443. return ret;
  1444. }
  1445. static struct net_device_stats *via_ircc_net_get_stats(struct net_device
  1446. *dev)
  1447. {
  1448. struct via_ircc_cb *self = (struct via_ircc_cb *) dev->priv;
  1449. return &self->stats;
  1450. }
  1451. MODULE_AUTHOR("VIA Technologies,inc");
  1452. MODULE_DESCRIPTION("VIA IrDA Device Driver");
  1453. MODULE_LICENSE("GPL");
  1454. module_init(via_ircc_init);
  1455. module_exit(via_ircc_cleanup);