ibm_emac_phy.c 6.3 KB

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  1. /*
  2. * ibm_ocp_phy.c
  3. *
  4. * PHY drivers for the ibm ocp ethernet driver. Borrowed
  5. * from sungem_phy.c, though I only kept the generic MII
  6. * driver for now.
  7. *
  8. * This file should be shared with other drivers or eventually
  9. * merged as the "low level" part of miilib
  10. *
  11. * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
  12. *
  13. */
  14. #include <linux/config.h>
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/sched.h>
  18. #include <linux/types.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/mii.h>
  22. #include <linux/ethtool.h>
  23. #include <linux/delay.h>
  24. #include "ibm_emac_phy.h"
  25. static int reset_one_mii_phy(struct mii_phy *phy, int phy_id)
  26. {
  27. u16 val;
  28. int limit = 10000;
  29. val = __phy_read(phy, phy_id, MII_BMCR);
  30. val &= ~BMCR_ISOLATE;
  31. val |= BMCR_RESET;
  32. __phy_write(phy, phy_id, MII_BMCR, val);
  33. udelay(100);
  34. while (limit--) {
  35. val = __phy_read(phy, phy_id, MII_BMCR);
  36. if ((val & BMCR_RESET) == 0)
  37. break;
  38. udelay(10);
  39. }
  40. if ((val & BMCR_ISOLATE) && limit > 0)
  41. __phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
  42. return (limit <= 0);
  43. }
  44. static int cis8201_init(struct mii_phy *phy)
  45. {
  46. u16 epcr;
  47. epcr = phy_read(phy, MII_CIS8201_EPCR);
  48. epcr &= ~EPCR_MODE_MASK;
  49. switch (phy->mode) {
  50. case PHY_MODE_TBI:
  51. epcr |= EPCR_TBI_MODE;
  52. break;
  53. case PHY_MODE_RTBI:
  54. epcr |= EPCR_RTBI_MODE;
  55. break;
  56. case PHY_MODE_GMII:
  57. epcr |= EPCR_GMII_MODE;
  58. break;
  59. case PHY_MODE_RGMII:
  60. default:
  61. epcr |= EPCR_RGMII_MODE;
  62. }
  63. phy_write(phy, MII_CIS8201_EPCR, epcr);
  64. return 0;
  65. }
  66. static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
  67. {
  68. u16 ctl, adv;
  69. phy->autoneg = 1;
  70. phy->speed = SPEED_10;
  71. phy->duplex = DUPLEX_HALF;
  72. phy->pause = 0;
  73. phy->advertising = advertise;
  74. /* Setup standard advertise */
  75. adv = phy_read(phy, MII_ADVERTISE);
  76. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  77. if (advertise & ADVERTISED_10baseT_Half)
  78. adv |= ADVERTISE_10HALF;
  79. if (advertise & ADVERTISED_10baseT_Full)
  80. adv |= ADVERTISE_10FULL;
  81. if (advertise & ADVERTISED_100baseT_Half)
  82. adv |= ADVERTISE_100HALF;
  83. if (advertise & ADVERTISED_100baseT_Full)
  84. adv |= ADVERTISE_100FULL;
  85. phy_write(phy, MII_ADVERTISE, adv);
  86. /* Start/Restart aneg */
  87. ctl = phy_read(phy, MII_BMCR);
  88. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  89. phy_write(phy, MII_BMCR, ctl);
  90. return 0;
  91. }
  92. static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
  93. {
  94. u16 ctl;
  95. phy->autoneg = 0;
  96. phy->speed = speed;
  97. phy->duplex = fd;
  98. phy->pause = 0;
  99. ctl = phy_read(phy, MII_BMCR);
  100. ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE);
  101. /* First reset the PHY */
  102. phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
  103. /* Select speed & duplex */
  104. switch (speed) {
  105. case SPEED_10:
  106. break;
  107. case SPEED_100:
  108. ctl |= BMCR_SPEED100;
  109. break;
  110. case SPEED_1000:
  111. default:
  112. return -EINVAL;
  113. }
  114. if (fd == DUPLEX_FULL)
  115. ctl |= BMCR_FULLDPLX;
  116. phy_write(phy, MII_BMCR, ctl);
  117. return 0;
  118. }
  119. static int genmii_poll_link(struct mii_phy *phy)
  120. {
  121. u16 status;
  122. (void)phy_read(phy, MII_BMSR);
  123. status = phy_read(phy, MII_BMSR);
  124. if ((status & BMSR_LSTATUS) == 0)
  125. return 0;
  126. if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE))
  127. return 0;
  128. return 1;
  129. }
  130. #define MII_CIS8201_ACSR 0x1c
  131. #define ACSR_DUPLEX_STATUS 0x0020
  132. #define ACSR_SPEED_1000BASET 0x0010
  133. #define ACSR_SPEED_100BASET 0x0008
  134. static int cis8201_read_link(struct mii_phy *phy)
  135. {
  136. u16 acsr;
  137. if (phy->autoneg) {
  138. acsr = phy_read(phy, MII_CIS8201_ACSR);
  139. if (acsr & ACSR_DUPLEX_STATUS)
  140. phy->duplex = DUPLEX_FULL;
  141. else
  142. phy->duplex = DUPLEX_HALF;
  143. if (acsr & ACSR_SPEED_1000BASET) {
  144. phy->speed = SPEED_1000;
  145. } else if (acsr & ACSR_SPEED_100BASET)
  146. phy->speed = SPEED_100;
  147. else
  148. phy->speed = SPEED_10;
  149. phy->pause = 0;
  150. }
  151. /* On non-aneg, we assume what we put in BMCR is the speed,
  152. * though magic-aneg shouldn't prevent this case from occurring
  153. */
  154. return 0;
  155. }
  156. static int genmii_read_link(struct mii_phy *phy)
  157. {
  158. u16 lpa;
  159. if (phy->autoneg) {
  160. lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
  161. phy->speed = SPEED_10;
  162. phy->duplex = DUPLEX_HALF;
  163. phy->pause = 0;
  164. if (lpa & (LPA_100FULL | LPA_100HALF)) {
  165. phy->speed = SPEED_100;
  166. if (lpa & LPA_100FULL)
  167. phy->duplex = DUPLEX_FULL;
  168. } else if (lpa & LPA_10FULL)
  169. phy->duplex = DUPLEX_FULL;
  170. }
  171. /* On non-aneg, we assume what we put in BMCR is the speed,
  172. * though magic-aneg shouldn't prevent this case from occurring
  173. */
  174. return 0;
  175. }
  176. #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
  177. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
  178. SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII)
  179. #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
  180. SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
  181. /* CIS8201 phy ops */
  182. static struct mii_phy_ops cis8201_phy_ops = {
  183. init:cis8201_init,
  184. setup_aneg:genmii_setup_aneg,
  185. setup_forced:genmii_setup_forced,
  186. poll_link:genmii_poll_link,
  187. read_link:cis8201_read_link
  188. };
  189. /* Generic implementation for most 10/100 PHYs */
  190. static struct mii_phy_ops generic_phy_ops = {
  191. setup_aneg:genmii_setup_aneg,
  192. setup_forced:genmii_setup_forced,
  193. poll_link:genmii_poll_link,
  194. read_link:genmii_read_link
  195. };
  196. static struct mii_phy_def cis8201_phy_def = {
  197. phy_id:0x000fc410,
  198. phy_id_mask:0x000ffff0,
  199. name:"CIS8201 Gigabit Ethernet",
  200. features:MII_GBIT_FEATURES,
  201. magic_aneg:0,
  202. ops:&cis8201_phy_ops
  203. };
  204. static struct mii_phy_def genmii_phy_def = {
  205. phy_id:0x00000000,
  206. phy_id_mask:0x00000000,
  207. name:"Generic MII",
  208. features:MII_BASIC_FEATURES,
  209. magic_aneg:0,
  210. ops:&generic_phy_ops
  211. };
  212. static struct mii_phy_def *mii_phy_table[] = {
  213. &cis8201_phy_def,
  214. &genmii_phy_def,
  215. NULL
  216. };
  217. int mii_phy_probe(struct mii_phy *phy, int mii_id)
  218. {
  219. int rc;
  220. u32 id;
  221. struct mii_phy_def *def;
  222. int i;
  223. phy->autoneg = 0;
  224. phy->advertising = 0;
  225. phy->mii_id = mii_id;
  226. phy->speed = 0;
  227. phy->duplex = 0;
  228. phy->pause = 0;
  229. /* Take PHY out of isloate mode and reset it. */
  230. rc = reset_one_mii_phy(phy, mii_id);
  231. if (rc)
  232. return -ENODEV;
  233. /* Read ID and find matching entry */
  234. id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2))
  235. & 0xfffffff0;
  236. for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
  237. if ((id & def->phy_id_mask) == def->phy_id)
  238. break;
  239. /* Should never be NULL (we have a generic entry), but... */
  240. if (def == NULL)
  241. return -ENODEV;
  242. phy->def = def;
  243. /* Setup default advertising */
  244. phy->advertising = def->features;
  245. return 0;
  246. }
  247. MODULE_LICENSE("GPL");