dm9000.c 28 KB

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  1. /*
  2. * dm9000.c: Version 1.2 03/18/2003
  3. *
  4. * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
  5. * Copyright (C) 1997 Sten Wang
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version 2
  10. * of the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
  18. *
  19. * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
  20. * 06/22/2001 Support DM9801 progrmming
  21. * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
  22. * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
  23. * R17 = (R17 & 0xfff0) | NF + 3
  24. * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
  25. * R17 = (R17 & 0xfff0) | NF
  26. *
  27. * v1.00 modify by simon 2001.9.5
  28. * change for kernel 2.4.x
  29. *
  30. * v1.1 11/09/2001 fix force mode bug
  31. *
  32. * v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
  33. * Fixed phy reset.
  34. * Added tx/rx 32 bit mode.
  35. * Cleaned up for kernel merge.
  36. *
  37. * 03/03/2004 Sascha Hauer <s.hauer@pengutronix.de>
  38. * Port to 2.6 kernel
  39. *
  40. * 24-Sep-2004 Ben Dooks <ben@simtec.co.uk>
  41. * Cleanup of code to remove ifdefs
  42. * Allowed platform device data to influence access width
  43. * Reformatting areas of code
  44. *
  45. * 17-Mar-2005 Sascha Hauer <s.hauer@pengutronix.de>
  46. * * removed 2.4 style module parameters
  47. * * removed removed unused stat counter and fixed
  48. * net_device_stats
  49. * * introduced tx_timeout function
  50. * * reworked locking
  51. *
  52. * 01-Jul-2005 Ben Dooks <ben@simtec.co.uk>
  53. * * fixed spinlock call without pointer
  54. * * ensure spinlock is initialised
  55. */
  56. #include <linux/module.h>
  57. #include <linux/ioport.h>
  58. #include <linux/netdevice.h>
  59. #include <linux/etherdevice.h>
  60. #include <linux/init.h>
  61. #include <linux/skbuff.h>
  62. #include <linux/version.h>
  63. #include <linux/spinlock.h>
  64. #include <linux/crc32.h>
  65. #include <linux/mii.h>
  66. #include <linux/dm9000.h>
  67. #include <linux/delay.h>
  68. #include <asm/delay.h>
  69. #include <asm/irq.h>
  70. #include <asm/io.h>
  71. #include "dm9000.h"
  72. /* Board/System/Debug information/definition ---------------- */
  73. #define DM9000_PHY 0x40 /* PHY address 0x01 */
  74. #define TRUE 1
  75. #define FALSE 0
  76. #define CARDNAME "dm9000"
  77. #define PFX CARDNAME ": "
  78. #define DM9000_TIMER_WUT jiffies+(HZ*2) /* timer wakeup time : 2 second */
  79. #define DM9000_DEBUG 0
  80. #if DM9000_DEBUG > 2
  81. #define PRINTK3(args...) printk(CARDNAME ": " args)
  82. #else
  83. #define PRINTK3(args...) do { } while(0)
  84. #endif
  85. #if DM9000_DEBUG > 1
  86. #define PRINTK2(args...) printk(CARDNAME ": " args)
  87. #else
  88. #define PRINTK2(args...) do { } while(0)
  89. #endif
  90. #if DM9000_DEBUG > 0
  91. #define PRINTK1(args...) printk(CARDNAME ": " args)
  92. #define PRINTK(args...) printk(CARDNAME ": " args)
  93. #else
  94. #define PRINTK1(args...) do { } while(0)
  95. #define PRINTK(args...) printk(KERN_DEBUG args)
  96. #endif
  97. /*
  98. * Transmit timeout, default 5 seconds.
  99. */
  100. static int watchdog = 5000;
  101. module_param(watchdog, int, 0400);
  102. MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
  103. /* Structure/enum declaration ------------------------------- */
  104. typedef struct board_info {
  105. void __iomem *io_addr; /* Register I/O base address */
  106. void __iomem *io_data; /* Data I/O address */
  107. u16 irq; /* IRQ */
  108. u16 tx_pkt_cnt;
  109. u16 queue_pkt_len;
  110. u16 queue_start_addr;
  111. u16 dbug_cnt;
  112. u8 io_mode; /* 0:word, 2:byte */
  113. u8 phy_addr;
  114. void (*inblk)(void __iomem *port, void *data, int length);
  115. void (*outblk)(void __iomem *port, void *data, int length);
  116. void (*dumpblk)(void __iomem *port, int length);
  117. struct resource *addr_res; /* resources found */
  118. struct resource *data_res;
  119. struct resource *addr_req; /* resources requested */
  120. struct resource *data_req;
  121. struct resource *irq_res;
  122. struct timer_list timer;
  123. struct net_device_stats stats;
  124. unsigned char srom[128];
  125. spinlock_t lock;
  126. struct mii_if_info mii;
  127. u32 msg_enable;
  128. } board_info_t;
  129. /* function declaration ------------------------------------- */
  130. static int dm9000_probe(struct device *);
  131. static int dm9000_open(struct net_device *);
  132. static int dm9000_start_xmit(struct sk_buff *, struct net_device *);
  133. static int dm9000_stop(struct net_device *);
  134. static void dm9000_timer(unsigned long);
  135. static void dm9000_init_dm9000(struct net_device *);
  136. static struct net_device_stats *dm9000_get_stats(struct net_device *);
  137. static irqreturn_t dm9000_interrupt(int, void *, struct pt_regs *);
  138. static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg);
  139. static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg,
  140. int value);
  141. static u16 read_srom_word(board_info_t *, int);
  142. static void dm9000_rx(struct net_device *);
  143. static void dm9000_hash_table(struct net_device *);
  144. //#define DM9000_PROGRAM_EEPROM
  145. #ifdef DM9000_PROGRAM_EEPROM
  146. static void program_eeprom(board_info_t * db);
  147. #endif
  148. /* DM9000 network board routine ---------------------------- */
  149. static void
  150. dm9000_reset(board_info_t * db)
  151. {
  152. PRINTK1("dm9000x: resetting\n");
  153. /* RESET device */
  154. writeb(DM9000_NCR, db->io_addr);
  155. udelay(200);
  156. writeb(NCR_RST, db->io_data);
  157. udelay(200);
  158. }
  159. /*
  160. * Read a byte from I/O port
  161. */
  162. static u8
  163. ior(board_info_t * db, int reg)
  164. {
  165. writeb(reg, db->io_addr);
  166. return readb(db->io_data);
  167. }
  168. /*
  169. * Write a byte to I/O port
  170. */
  171. static void
  172. iow(board_info_t * db, int reg, int value)
  173. {
  174. writeb(reg, db->io_addr);
  175. writeb(value, db->io_data);
  176. }
  177. /* routines for sending block to chip */
  178. static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
  179. {
  180. writesb(reg, data, count);
  181. }
  182. static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
  183. {
  184. writesw(reg, data, (count+1) >> 1);
  185. }
  186. static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
  187. {
  188. writesl(reg, data, (count+3) >> 2);
  189. }
  190. /* input block from chip to memory */
  191. static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
  192. {
  193. readsb(reg, data, count);
  194. }
  195. static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
  196. {
  197. readsw(reg, data, (count+1) >> 1);
  198. }
  199. static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
  200. {
  201. readsl(reg, data, (count+3) >> 2);
  202. }
  203. /* dump block from chip to null */
  204. static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
  205. {
  206. int i;
  207. int tmp;
  208. for (i = 0; i < count; i++)
  209. tmp = readb(reg);
  210. }
  211. static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
  212. {
  213. int i;
  214. int tmp;
  215. count = (count + 1) >> 1;
  216. for (i = 0; i < count; i++)
  217. tmp = readw(reg);
  218. }
  219. static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
  220. {
  221. int i;
  222. int tmp;
  223. count = (count + 3) >> 2;
  224. for (i = 0; i < count; i++)
  225. tmp = readl(reg);
  226. }
  227. /* dm9000_set_io
  228. *
  229. * select the specified set of io routines to use with the
  230. * device
  231. */
  232. static void dm9000_set_io(struct board_info *db, int byte_width)
  233. {
  234. /* use the size of the data resource to work out what IO
  235. * routines we want to use
  236. */
  237. switch (byte_width) {
  238. case 1:
  239. db->dumpblk = dm9000_dumpblk_8bit;
  240. db->outblk = dm9000_outblk_8bit;
  241. db->inblk = dm9000_inblk_8bit;
  242. break;
  243. case 2:
  244. db->dumpblk = dm9000_dumpblk_16bit;
  245. db->outblk = dm9000_outblk_16bit;
  246. db->inblk = dm9000_inblk_16bit;
  247. break;
  248. case 3:
  249. printk(KERN_ERR PFX ": 3 byte IO, falling back to 16bit\n");
  250. db->dumpblk = dm9000_dumpblk_16bit;
  251. db->outblk = dm9000_outblk_16bit;
  252. db->inblk = dm9000_inblk_16bit;
  253. break;
  254. case 4:
  255. default:
  256. db->dumpblk = dm9000_dumpblk_32bit;
  257. db->outblk = dm9000_outblk_32bit;
  258. db->inblk = dm9000_inblk_32bit;
  259. break;
  260. }
  261. }
  262. /* Our watchdog timed out. Called by the networking layer */
  263. static void dm9000_timeout(struct net_device *dev)
  264. {
  265. board_info_t *db = (board_info_t *) dev->priv;
  266. u8 reg_save;
  267. unsigned long flags;
  268. /* Save previous register address */
  269. reg_save = readb(db->io_addr);
  270. spin_lock_irqsave(&db->lock,flags);
  271. netif_stop_queue(dev);
  272. dm9000_reset(db);
  273. dm9000_init_dm9000(dev);
  274. /* We can accept TX packets again */
  275. dev->trans_start = jiffies;
  276. netif_wake_queue(dev);
  277. /* Restore previous register address */
  278. writeb(reg_save, db->io_addr);
  279. spin_unlock_irqrestore(&db->lock,flags);
  280. }
  281. /* dm9000_release_board
  282. *
  283. * release a board, and any mapped resources
  284. */
  285. static void
  286. dm9000_release_board(struct platform_device *pdev, struct board_info *db)
  287. {
  288. if (db->data_res == NULL) {
  289. if (db->addr_res != NULL)
  290. release_mem_region((unsigned long)db->io_addr, 4);
  291. return;
  292. }
  293. /* unmap our resources */
  294. iounmap(db->io_addr);
  295. iounmap(db->io_data);
  296. /* release the resources */
  297. if (db->data_req != NULL) {
  298. release_resource(db->data_req);
  299. kfree(db->data_req);
  300. }
  301. if (db->addr_res != NULL) {
  302. release_resource(db->addr_res);
  303. kfree(db->addr_req);
  304. }
  305. }
  306. #define res_size(_r) (((_r)->end - (_r)->start) + 1)
  307. /*
  308. * Search DM9000 board, allocate space and register it
  309. */
  310. static int
  311. dm9000_probe(struct device *dev)
  312. {
  313. struct platform_device *pdev = to_platform_device(dev);
  314. struct dm9000_plat_data *pdata = pdev->dev.platform_data;
  315. struct board_info *db; /* Point a board information structure */
  316. struct net_device *ndev;
  317. unsigned long base;
  318. int ret = 0;
  319. int iosize;
  320. int i;
  321. u32 id_val;
  322. /* Init network device */
  323. ndev = alloc_etherdev(sizeof (struct board_info));
  324. if (!ndev) {
  325. printk("%s: could not allocate device.\n", CARDNAME);
  326. return -ENOMEM;
  327. }
  328. SET_MODULE_OWNER(ndev);
  329. SET_NETDEV_DEV(ndev, dev);
  330. PRINTK2("dm9000_probe()");
  331. /* setup board info structure */
  332. db = (struct board_info *) ndev->priv;
  333. memset(db, 0, sizeof (*db));
  334. spin_lock_init(&db->lock);
  335. if (pdev->num_resources < 2) {
  336. ret = -ENODEV;
  337. goto out;
  338. }
  339. switch (pdev->num_resources) {
  340. case 2:
  341. base = pdev->resource[0].start;
  342. if (!request_mem_region(base, 4, ndev->name)) {
  343. ret = -EBUSY;
  344. goto out;
  345. }
  346. ndev->base_addr = base;
  347. ndev->irq = pdev->resource[1].start;
  348. db->io_addr = (void *)base;
  349. db->io_data = (void *)(base + 4);
  350. break;
  351. case 3:
  352. db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  353. db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  354. db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  355. if (db->addr_res == NULL || db->data_res == NULL) {
  356. printk(KERN_ERR PFX "insufficient resources\n");
  357. ret = -ENOENT;
  358. goto out;
  359. }
  360. i = res_size(db->addr_res);
  361. db->addr_req = request_mem_region(db->addr_res->start, i,
  362. pdev->name);
  363. if (db->addr_req == NULL) {
  364. printk(KERN_ERR PFX "cannot claim address reg area\n");
  365. ret = -EIO;
  366. goto out;
  367. }
  368. db->io_addr = ioremap(db->addr_res->start, i);
  369. if (db->io_addr == NULL) {
  370. printk(KERN_ERR "failed to ioremap address reg\n");
  371. ret = -EINVAL;
  372. goto out;
  373. }
  374. iosize = res_size(db->data_res);
  375. db->data_req = request_mem_region(db->data_res->start, iosize,
  376. pdev->name);
  377. if (db->data_req == NULL) {
  378. printk(KERN_ERR PFX "cannot claim data reg area\n");
  379. ret = -EIO;
  380. goto out;
  381. }
  382. db->io_data = ioremap(db->data_res->start, iosize);
  383. if (db->io_data == NULL) {
  384. printk(KERN_ERR "failed to ioremap data reg\n");
  385. ret = -EINVAL;
  386. goto out;
  387. }
  388. /* fill in parameters for net-dev structure */
  389. ndev->base_addr = (unsigned long)db->io_addr;
  390. ndev->irq = db->irq_res->start;
  391. /* ensure at least we have a default set of IO routines */
  392. dm9000_set_io(db, iosize);
  393. }
  394. /* check to see if anything is being over-ridden */
  395. if (pdata != NULL) {
  396. /* check to see if the driver wants to over-ride the
  397. * default IO width */
  398. if (pdata->flags & DM9000_PLATF_8BITONLY)
  399. dm9000_set_io(db, 1);
  400. if (pdata->flags & DM9000_PLATF_16BITONLY)
  401. dm9000_set_io(db, 2);
  402. if (pdata->flags & DM9000_PLATF_32BITONLY)
  403. dm9000_set_io(db, 4);
  404. /* check to see if there are any IO routine
  405. * over-rides */
  406. if (pdata->inblk != NULL)
  407. db->inblk = pdata->inblk;
  408. if (pdata->outblk != NULL)
  409. db->outblk = pdata->outblk;
  410. if (pdata->dumpblk != NULL)
  411. db->dumpblk = pdata->dumpblk;
  412. }
  413. dm9000_reset(db);
  414. /* try two times, DM9000 sometimes gets the first read wrong */
  415. for (i = 0; i < 2; i++) {
  416. id_val = ior(db, DM9000_VIDL);
  417. id_val |= (u32)ior(db, DM9000_VIDH) << 8;
  418. id_val |= (u32)ior(db, DM9000_PIDL) << 16;
  419. id_val |= (u32)ior(db, DM9000_PIDH) << 24;
  420. if (id_val == DM9000_ID)
  421. break;
  422. printk("%s: read wrong id 0x%08x\n", CARDNAME, id_val);
  423. }
  424. if (id_val != DM9000_ID) {
  425. printk("%s: wrong id: 0x%08x\n", CARDNAME, id_val);
  426. goto release;
  427. }
  428. /* from this point we assume that we have found a DM9000 */
  429. /* driver system function */
  430. ether_setup(ndev);
  431. ndev->open = &dm9000_open;
  432. ndev->hard_start_xmit = &dm9000_start_xmit;
  433. ndev->tx_timeout = &dm9000_timeout;
  434. ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
  435. ndev->stop = &dm9000_stop;
  436. ndev->get_stats = &dm9000_get_stats;
  437. ndev->set_multicast_list = &dm9000_hash_table;
  438. #ifdef DM9000_PROGRAM_EEPROM
  439. program_eeprom(db);
  440. #endif
  441. db->msg_enable = NETIF_MSG_LINK;
  442. db->mii.phy_id_mask = 0x1f;
  443. db->mii.reg_num_mask = 0x1f;
  444. db->mii.force_media = 0;
  445. db->mii.full_duplex = 0;
  446. db->mii.dev = ndev;
  447. db->mii.mdio_read = dm9000_phy_read;
  448. db->mii.mdio_write = dm9000_phy_write;
  449. /* Read SROM content */
  450. for (i = 0; i < 64; i++)
  451. ((u16 *) db->srom)[i] = read_srom_word(db, i);
  452. /* Set Node Address */
  453. for (i = 0; i < 6; i++)
  454. ndev->dev_addr[i] = db->srom[i];
  455. if (!is_valid_ether_addr(ndev->dev_addr))
  456. printk("%s: Invalid ethernet MAC address. Please "
  457. "set using ifconfig\n", ndev->name);
  458. dev_set_drvdata(dev, ndev);
  459. ret = register_netdev(ndev);
  460. if (ret == 0) {
  461. printk("%s: dm9000 at %p,%p IRQ %d MAC: ",
  462. ndev->name, db->io_addr, db->io_data, ndev->irq);
  463. for (i = 0; i < 5; i++)
  464. printk("%02x:", ndev->dev_addr[i]);
  465. printk("%02x\n", ndev->dev_addr[5]);
  466. }
  467. return 0;
  468. release:
  469. out:
  470. printk("%s: not found (%d).\n", CARDNAME, ret);
  471. dm9000_release_board(pdev, db);
  472. kfree(ndev);
  473. return ret;
  474. }
  475. /*
  476. * Open the interface.
  477. * The interface is opened whenever "ifconfig" actives it.
  478. */
  479. static int
  480. dm9000_open(struct net_device *dev)
  481. {
  482. board_info_t *db = (board_info_t *) dev->priv;
  483. PRINTK2("entering dm9000_open\n");
  484. if (request_irq(dev->irq, &dm9000_interrupt, SA_SHIRQ, dev->name, dev))
  485. return -EAGAIN;
  486. /* Initialize DM9000 board */
  487. dm9000_reset(db);
  488. dm9000_init_dm9000(dev);
  489. /* Init driver variable */
  490. db->dbug_cnt = 0;
  491. /* set and active a timer process */
  492. init_timer(&db->timer);
  493. db->timer.expires = DM9000_TIMER_WUT;
  494. db->timer.data = (unsigned long) dev;
  495. db->timer.function = &dm9000_timer;
  496. add_timer(&db->timer);
  497. mii_check_media(&db->mii, netif_msg_link(db), 1);
  498. netif_start_queue(dev);
  499. return 0;
  500. }
  501. /*
  502. * Initilize dm9000 board
  503. */
  504. static void
  505. dm9000_init_dm9000(struct net_device *dev)
  506. {
  507. board_info_t *db = (board_info_t *) dev->priv;
  508. PRINTK1("entering %s\n",__FUNCTION__);
  509. /* I/O mode */
  510. db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
  511. /* GPIO0 on pre-activate PHY */
  512. iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
  513. iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
  514. iow(db, DM9000_GPR, 0); /* Enable PHY */
  515. /* Program operating register */
  516. iow(db, DM9000_TCR, 0); /* TX Polling clear */
  517. iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
  518. iow(db, DM9000_FCR, 0xff); /* Flow Control */
  519. iow(db, DM9000_SMCR, 0); /* Special Mode */
  520. /* clear TX status */
  521. iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
  522. iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
  523. /* Set address filter table */
  524. dm9000_hash_table(dev);
  525. /* Activate DM9000 */
  526. iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
  527. /* Enable TX/RX interrupt mask */
  528. iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
  529. /* Init Driver variable */
  530. db->tx_pkt_cnt = 0;
  531. db->queue_pkt_len = 0;
  532. dev->trans_start = 0;
  533. spin_lock_init(&db->lock);
  534. }
  535. /*
  536. * Hardware start transmission.
  537. * Send a packet to media from the upper layer.
  538. */
  539. static int
  540. dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
  541. {
  542. board_info_t *db = (board_info_t *) dev->priv;
  543. PRINTK3("dm9000_start_xmit\n");
  544. if (db->tx_pkt_cnt > 1)
  545. return 1;
  546. netif_stop_queue(dev);
  547. /* Disable all interrupts */
  548. iow(db, DM9000_IMR, IMR_PAR);
  549. /* Move data to DM9000 TX RAM */
  550. writeb(DM9000_MWCMD, db->io_addr);
  551. (db->outblk)(db->io_data, skb->data, skb->len);
  552. db->stats.tx_bytes += skb->len;
  553. /* TX control: First packet immediately send, second packet queue */
  554. if (db->tx_pkt_cnt == 0) {
  555. /* First Packet */
  556. db->tx_pkt_cnt++;
  557. /* Set TX length to DM9000 */
  558. iow(db, DM9000_TXPLL, skb->len & 0xff);
  559. iow(db, DM9000_TXPLH, (skb->len >> 8) & 0xff);
  560. /* Issue TX polling command */
  561. iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
  562. dev->trans_start = jiffies; /* save the time stamp */
  563. } else {
  564. /* Second packet */
  565. db->tx_pkt_cnt++;
  566. db->queue_pkt_len = skb->len;
  567. }
  568. /* free this SKB */
  569. dev_kfree_skb(skb);
  570. /* Re-enable resource check */
  571. if (db->tx_pkt_cnt == 1)
  572. netif_wake_queue(dev);
  573. /* Re-enable interrupt */
  574. iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
  575. return 0;
  576. }
  577. static void
  578. dm9000_shutdown(struct net_device *dev)
  579. {
  580. board_info_t *db = (board_info_t *) dev->priv;
  581. /* RESET device */
  582. dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
  583. iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
  584. iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
  585. iow(db, DM9000_RCR, 0x00); /* Disable RX */
  586. }
  587. /*
  588. * Stop the interface.
  589. * The interface is stopped when it is brought.
  590. */
  591. static int
  592. dm9000_stop(struct net_device *ndev)
  593. {
  594. board_info_t *db = (board_info_t *) ndev->priv;
  595. PRINTK1("entering %s\n",__FUNCTION__);
  596. /* deleted timer */
  597. del_timer(&db->timer);
  598. netif_stop_queue(ndev);
  599. netif_carrier_off(ndev);
  600. /* free interrupt */
  601. free_irq(ndev->irq, ndev);
  602. dm9000_shutdown(ndev);
  603. return 0;
  604. }
  605. /*
  606. * DM9000 interrupt handler
  607. * receive the packet to upper layer, free the transmitted packet
  608. */
  609. void
  610. dm9000_tx_done(struct net_device *dev, board_info_t * db)
  611. {
  612. int tx_status = ior(db, DM9000_NSR); /* Got TX status */
  613. if (tx_status & (NSR_TX2END | NSR_TX1END)) {
  614. /* One packet sent complete */
  615. db->tx_pkt_cnt--;
  616. db->stats.tx_packets++;
  617. /* Queue packet check & send */
  618. if (db->tx_pkt_cnt > 0) {
  619. iow(db, DM9000_TXPLL, db->queue_pkt_len & 0xff);
  620. iow(db, DM9000_TXPLH, (db->queue_pkt_len >> 8) & 0xff);
  621. iow(db, DM9000_TCR, TCR_TXREQ);
  622. dev->trans_start = jiffies;
  623. }
  624. netif_wake_queue(dev);
  625. }
  626. }
  627. static irqreturn_t
  628. dm9000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  629. {
  630. struct net_device *dev = dev_id;
  631. board_info_t *db;
  632. int int_status;
  633. u8 reg_save;
  634. PRINTK3("entering %s\n",__FUNCTION__);
  635. if (!dev) {
  636. PRINTK1("dm9000_interrupt() without DEVICE arg\n");
  637. return IRQ_HANDLED;
  638. }
  639. /* A real interrupt coming */
  640. db = (board_info_t *) dev->priv;
  641. spin_lock(&db->lock);
  642. /* Save previous register address */
  643. reg_save = readb(db->io_addr);
  644. /* Disable all interrupts */
  645. iow(db, DM9000_IMR, IMR_PAR);
  646. /* Got DM9000 interrupt status */
  647. int_status = ior(db, DM9000_ISR); /* Got ISR */
  648. iow(db, DM9000_ISR, int_status); /* Clear ISR status */
  649. /* Received the coming packet */
  650. if (int_status & ISR_PRS)
  651. dm9000_rx(dev);
  652. /* Trnasmit Interrupt check */
  653. if (int_status & ISR_PTS)
  654. dm9000_tx_done(dev, db);
  655. /* Re-enable interrupt mask */
  656. iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
  657. /* Restore previous register address */
  658. writeb(reg_save, db->io_addr);
  659. spin_unlock(&db->lock);
  660. return IRQ_HANDLED;
  661. }
  662. /*
  663. * Get statistics from driver.
  664. */
  665. static struct net_device_stats *
  666. dm9000_get_stats(struct net_device *dev)
  667. {
  668. board_info_t *db = (board_info_t *) dev->priv;
  669. return &db->stats;
  670. }
  671. /*
  672. * A periodic timer routine
  673. * Dynamic media sense, allocated Rx buffer...
  674. */
  675. static void
  676. dm9000_timer(unsigned long data)
  677. {
  678. struct net_device *dev = (struct net_device *) data;
  679. board_info_t *db = (board_info_t *) dev->priv;
  680. PRINTK3("dm9000_timer()\n");
  681. mii_check_media(&db->mii, netif_msg_link(db), 0);
  682. /* Set timer again */
  683. db->timer.expires = DM9000_TIMER_WUT;
  684. add_timer(&db->timer);
  685. }
  686. struct dm9000_rxhdr {
  687. u16 RxStatus;
  688. u16 RxLen;
  689. } __attribute__((__packed__));
  690. /*
  691. * Received a packet and pass to upper layer
  692. */
  693. static void
  694. dm9000_rx(struct net_device *dev)
  695. {
  696. board_info_t *db = (board_info_t *) dev->priv;
  697. struct dm9000_rxhdr rxhdr;
  698. struct sk_buff *skb;
  699. u8 rxbyte, *rdptr;
  700. int GoodPacket;
  701. int RxLen;
  702. /* Check packet ready or not */
  703. do {
  704. ior(db, DM9000_MRCMDX); /* Dummy read */
  705. /* Get most updated data */
  706. rxbyte = readb(db->io_data);
  707. /* Status check: this byte must be 0 or 1 */
  708. if (rxbyte > DM9000_PKT_RDY) {
  709. printk("status check failed: %d\n", rxbyte);
  710. iow(db, DM9000_RCR, 0x00); /* Stop Device */
  711. iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
  712. return;
  713. }
  714. if (rxbyte != DM9000_PKT_RDY)
  715. return;
  716. /* A packet ready now & Get status/length */
  717. GoodPacket = TRUE;
  718. writeb(DM9000_MRCMD, db->io_addr);
  719. (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
  720. RxLen = rxhdr.RxLen;
  721. /* Packet Status check */
  722. if (RxLen < 0x40) {
  723. GoodPacket = FALSE;
  724. PRINTK1("Bad Packet received (runt)\n");
  725. }
  726. if (RxLen > DM9000_PKT_MAX) {
  727. PRINTK1("RST: RX Len:%x\n", RxLen);
  728. }
  729. if (rxhdr.RxStatus & 0xbf00) {
  730. GoodPacket = FALSE;
  731. if (rxhdr.RxStatus & 0x100) {
  732. PRINTK1("fifo error\n");
  733. db->stats.rx_fifo_errors++;
  734. }
  735. if (rxhdr.RxStatus & 0x200) {
  736. PRINTK1("crc error\n");
  737. db->stats.rx_crc_errors++;
  738. }
  739. if (rxhdr.RxStatus & 0x8000) {
  740. PRINTK1("length error\n");
  741. db->stats.rx_length_errors++;
  742. }
  743. }
  744. /* Move data from DM9000 */
  745. if (GoodPacket
  746. && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) {
  747. skb->dev = dev;
  748. skb_reserve(skb, 2);
  749. rdptr = (u8 *) skb_put(skb, RxLen - 4);
  750. /* Read received packet from RX SRAM */
  751. (db->inblk)(db->io_data, rdptr, RxLen);
  752. db->stats.rx_bytes += RxLen;
  753. /* Pass to upper layer */
  754. skb->protocol = eth_type_trans(skb, dev);
  755. netif_rx(skb);
  756. db->stats.rx_packets++;
  757. } else {
  758. /* need to dump the packet's data */
  759. (db->dumpblk)(db->io_data, RxLen);
  760. }
  761. } while (rxbyte == DM9000_PKT_RDY);
  762. }
  763. /*
  764. * Read a word data from SROM
  765. */
  766. static u16
  767. read_srom_word(board_info_t * db, int offset)
  768. {
  769. iow(db, DM9000_EPAR, offset);
  770. iow(db, DM9000_EPCR, EPCR_ERPRR);
  771. mdelay(8); /* according to the datasheet 200us should be enough,
  772. but it doesn't work */
  773. iow(db, DM9000_EPCR, 0x0);
  774. return (ior(db, DM9000_EPDRL) + (ior(db, DM9000_EPDRH) << 8));
  775. }
  776. #ifdef DM9000_PROGRAM_EEPROM
  777. /*
  778. * Write a word data to SROM
  779. */
  780. static void
  781. write_srom_word(board_info_t * db, int offset, u16 val)
  782. {
  783. iow(db, DM9000_EPAR, offset);
  784. iow(db, DM9000_EPDRH, ((val >> 8) & 0xff));
  785. iow(db, DM9000_EPDRL, (val & 0xff));
  786. iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
  787. mdelay(8); /* same shit */
  788. iow(db, DM9000_EPCR, 0);
  789. }
  790. /*
  791. * Only for development:
  792. * Here we write static data to the eeprom in case
  793. * we don't have valid content on a new board
  794. */
  795. static void
  796. program_eeprom(board_info_t * db)
  797. {
  798. u16 eeprom[] = { 0x0c00, 0x007f, 0x1300, /* MAC Address */
  799. 0x0000, /* Autoload: accept nothing */
  800. 0x0a46, 0x9000, /* Vendor / Product ID */
  801. 0x0000, /* pin control */
  802. 0x0000,
  803. }; /* Wake-up mode control */
  804. int i;
  805. for (i = 0; i < 8; i++)
  806. write_srom_word(db, i, eeprom[i]);
  807. }
  808. #endif
  809. /*
  810. * Calculate the CRC valude of the Rx packet
  811. * flag = 1 : return the reverse CRC (for the received packet CRC)
  812. * 0 : return the normal CRC (for Hash Table index)
  813. */
  814. static unsigned long
  815. cal_CRC(unsigned char *Data, unsigned int Len, u8 flag)
  816. {
  817. u32 crc = ether_crc_le(Len, Data);
  818. if (flag)
  819. return ~crc;
  820. return crc;
  821. }
  822. /*
  823. * Set DM9000 multicast address
  824. */
  825. static void
  826. dm9000_hash_table(struct net_device *dev)
  827. {
  828. board_info_t *db = (board_info_t *) dev->priv;
  829. struct dev_mc_list *mcptr = dev->mc_list;
  830. int mc_cnt = dev->mc_count;
  831. u32 hash_val;
  832. u16 i, oft, hash_table[4];
  833. unsigned long flags;
  834. PRINTK2("dm9000_hash_table()\n");
  835. spin_lock_irqsave(&db->lock,flags);
  836. for (i = 0, oft = 0x10; i < 6; i++, oft++)
  837. iow(db, oft, dev->dev_addr[i]);
  838. /* Clear Hash Table */
  839. for (i = 0; i < 4; i++)
  840. hash_table[i] = 0x0;
  841. /* broadcast address */
  842. hash_table[3] = 0x8000;
  843. /* the multicast address in Hash Table : 64 bits */
  844. for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
  845. hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
  846. hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
  847. }
  848. /* Write the hash table to MAC MD table */
  849. for (i = 0, oft = 0x16; i < 4; i++) {
  850. iow(db, oft++, hash_table[i] & 0xff);
  851. iow(db, oft++, (hash_table[i] >> 8) & 0xff);
  852. }
  853. spin_unlock_irqrestore(&db->lock,flags);
  854. }
  855. /*
  856. * Read a word from phyxcer
  857. */
  858. static int
  859. dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
  860. {
  861. board_info_t *db = (board_info_t *) dev->priv;
  862. unsigned long flags;
  863. unsigned int reg_save;
  864. int ret;
  865. spin_lock_irqsave(&db->lock,flags);
  866. /* Save previous register address */
  867. reg_save = readb(db->io_addr);
  868. /* Fill the phyxcer register into REG_0C */
  869. iow(db, DM9000_EPAR, DM9000_PHY | reg);
  870. iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
  871. udelay(100); /* Wait read complete */
  872. iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
  873. /* The read data keeps on REG_0D & REG_0E */
  874. ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
  875. /* restore the previous address */
  876. writeb(reg_save, db->io_addr);
  877. spin_unlock_irqrestore(&db->lock,flags);
  878. return ret;
  879. }
  880. /*
  881. * Write a word to phyxcer
  882. */
  883. static void
  884. dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
  885. {
  886. board_info_t *db = (board_info_t *) dev->priv;
  887. unsigned long flags;
  888. unsigned long reg_save;
  889. spin_lock_irqsave(&db->lock,flags);
  890. /* Save previous register address */
  891. reg_save = readb(db->io_addr);
  892. /* Fill the phyxcer register into REG_0C */
  893. iow(db, DM9000_EPAR, DM9000_PHY | reg);
  894. /* Fill the written data into REG_0D & REG_0E */
  895. iow(db, DM9000_EPDRL, (value & 0xff));
  896. iow(db, DM9000_EPDRH, ((value >> 8) & 0xff));
  897. iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
  898. udelay(500); /* Wait write complete */
  899. iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
  900. /* restore the previous address */
  901. writeb(reg_save, db->io_addr);
  902. spin_unlock_irqrestore(&db->lock,flags);
  903. }
  904. static int
  905. dm9000_drv_suspend(struct device *dev, pm_message_t state, u32 level)
  906. {
  907. struct net_device *ndev = dev_get_drvdata(dev);
  908. if (ndev && level == SUSPEND_DISABLE) {
  909. if (netif_running(ndev)) {
  910. netif_device_detach(ndev);
  911. dm9000_shutdown(ndev);
  912. }
  913. }
  914. return 0;
  915. }
  916. static int
  917. dm9000_drv_resume(struct device *dev, u32 level)
  918. {
  919. struct net_device *ndev = dev_get_drvdata(dev);
  920. board_info_t *db = (board_info_t *) ndev->priv;
  921. if (ndev && level == RESUME_ENABLE) {
  922. if (netif_running(ndev)) {
  923. dm9000_reset(db);
  924. dm9000_init_dm9000(ndev);
  925. netif_device_attach(ndev);
  926. }
  927. }
  928. return 0;
  929. }
  930. static int
  931. dm9000_drv_remove(struct device *dev)
  932. {
  933. struct platform_device *pdev = to_platform_device(dev);
  934. struct net_device *ndev = dev_get_drvdata(dev);
  935. dev_set_drvdata(dev, NULL);
  936. unregister_netdev(ndev);
  937. dm9000_release_board(pdev, (board_info_t *) ndev->priv);
  938. kfree(ndev); /* free device structure */
  939. PRINTK1("clean_module() exit\n");
  940. return 0;
  941. }
  942. static struct device_driver dm9000_driver = {
  943. .name = "dm9000",
  944. .bus = &platform_bus_type,
  945. .probe = dm9000_probe,
  946. .remove = dm9000_drv_remove,
  947. .suspend = dm9000_drv_suspend,
  948. .resume = dm9000_drv_resume,
  949. };
  950. static int __init
  951. dm9000_init(void)
  952. {
  953. printk(KERN_INFO "%s Ethernet Driver\n", CARDNAME);
  954. return driver_register(&dm9000_driver); /* search board and register */
  955. }
  956. static void __exit
  957. dm9000_cleanup(void)
  958. {
  959. driver_unregister(&dm9000_driver);
  960. }
  961. module_init(dm9000_init);
  962. module_exit(dm9000_cleanup);
  963. MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
  964. MODULE_DESCRIPTION("Davicom DM9000 network driver");
  965. MODULE_LICENSE("GPL");