dl2k.c 50 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872
  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. /*
  12. Rev Date Description
  13. ==========================================================================
  14. 0.01 2001/05/03 Created DL2000-based linux driver
  15. 0.02 2001/05/21 Added VLAN and hardware checksum support.
  16. 1.00 2001/06/26 Added jumbo frame support.
  17. 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
  18. 1.02 2001/10/08 Supported fiber media.
  19. Added flow control parameters.
  20. 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
  21. the fiber devices.
  22. 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
  23. 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
  24. 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
  25. Fixed tx_full flag incorrect.
  26. Added tx_coalesce paramter.
  27. 1.07 2002/01/03 Fixed miscount of RX frame error.
  28. 1.08 2002/01/17 Fixed the multicast bug.
  29. 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
  30. Added rio_timer() to watch rx buffers.
  31. 1.10 2002/04/16 Fixed miscount of carrier error.
  32. 1.11 2002/05/23 Added ISR schedule scheme
  33. Fixed miscount of rx frame error for DGE-550SX.
  34. Fixed VLAN bug.
  35. 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
  36. 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
  37. errs) with some mainboards.
  38. 2. Use definition "DRV_NAME" "DRV_VERSION"
  39. "DRV_RELDATE" for flexibility.
  40. 1.14 2002/08/14 Support ethtool.
  41. 1.15 2002/08/27 Changed the default media to Auto-Negotiation
  42. for the fiber devices.
  43. 1.16 2002/09/04 More power down time for fiber devices auto-
  44. negotiation.
  45. Fix disconnect bug after ifup and ifdown.
  46. 1.17 2002/10/03 Fix RMON statistics overflow.
  47. Always use I/O mapping to access eeprom,
  48. avoid system freezing with some chipsets.
  49. */
  50. #define DRV_NAME "D-Link DL2000-based linux driver"
  51. #define DRV_VERSION "v1.17a"
  52. #define DRV_RELDATE "2002/10/04"
  53. #include "dl2k.h"
  54. static char version[] __devinitdata =
  55. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  56. #define MAX_UNITS 8
  57. static int mtu[MAX_UNITS];
  58. static int vlan[MAX_UNITS];
  59. static int jumbo[MAX_UNITS];
  60. static char *media[MAX_UNITS];
  61. static int tx_flow=-1;
  62. static int rx_flow=-1;
  63. static int copy_thresh;
  64. static int rx_coalesce=10; /* Rx frame count each interrupt */
  65. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  66. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  67. MODULE_AUTHOR ("Edward Peng");
  68. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  69. MODULE_LICENSE("GPL");
  70. module_param_array(mtu, int, NULL, 0);
  71. module_param_array(media, charp, NULL, 0);
  72. module_param_array(vlan, int, NULL, 0);
  73. module_param_array(jumbo, int, NULL, 0);
  74. module_param(tx_flow, int, 0);
  75. module_param(rx_flow, int, 0);
  76. module_param(copy_thresh, int, 0);
  77. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  78. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  79. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  80. /* Enable the default interrupts */
  81. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  82. UpdateStats | LinkEvent)
  83. #define EnableInt() \
  84. writew(DEFAULT_INTR, ioaddr + IntEnable)
  85. static int max_intrloop = 50;
  86. static int multicast_filter_limit = 0x40;
  87. static int rio_open (struct net_device *dev);
  88. static void rio_timer (unsigned long data);
  89. static void rio_tx_timeout (struct net_device *dev);
  90. static void alloc_list (struct net_device *dev);
  91. static int start_xmit (struct sk_buff *skb, struct net_device *dev);
  92. static irqreturn_t rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
  93. static void rio_free_tx (struct net_device *dev, int irq);
  94. static void tx_error (struct net_device *dev, int tx_status);
  95. static int receive_packet (struct net_device *dev);
  96. static void rio_error (struct net_device *dev, int int_status);
  97. static int change_mtu (struct net_device *dev, int new_mtu);
  98. static void set_multicast (struct net_device *dev);
  99. static struct net_device_stats *get_stats (struct net_device *dev);
  100. static int clear_stats (struct net_device *dev);
  101. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  102. static int rio_close (struct net_device *dev);
  103. static int find_miiphy (struct net_device *dev);
  104. static int parse_eeprom (struct net_device *dev);
  105. static int read_eeprom (long ioaddr, int eep_addr);
  106. static int mii_wait_link (struct net_device *dev, int wait);
  107. static int mii_set_media (struct net_device *dev);
  108. static int mii_get_media (struct net_device *dev);
  109. static int mii_set_media_pcs (struct net_device *dev);
  110. static int mii_get_media_pcs (struct net_device *dev);
  111. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  112. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  113. u16 data);
  114. static struct ethtool_ops ethtool_ops;
  115. static int __devinit
  116. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  117. {
  118. struct net_device *dev;
  119. struct netdev_private *np;
  120. static int card_idx;
  121. int chip_idx = ent->driver_data;
  122. int err, irq;
  123. long ioaddr;
  124. static int version_printed;
  125. void *ring_space;
  126. dma_addr_t ring_dma;
  127. if (!version_printed++)
  128. printk ("%s", version);
  129. err = pci_enable_device (pdev);
  130. if (err)
  131. return err;
  132. irq = pdev->irq;
  133. err = pci_request_regions (pdev, "dl2k");
  134. if (err)
  135. goto err_out_disable;
  136. pci_set_master (pdev);
  137. dev = alloc_etherdev (sizeof (*np));
  138. if (!dev) {
  139. err = -ENOMEM;
  140. goto err_out_res;
  141. }
  142. SET_MODULE_OWNER (dev);
  143. SET_NETDEV_DEV(dev, &pdev->dev);
  144. #ifdef MEM_MAPPING
  145. ioaddr = pci_resource_start (pdev, 1);
  146. ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
  147. if (!ioaddr) {
  148. err = -ENOMEM;
  149. goto err_out_dev;
  150. }
  151. #else
  152. ioaddr = pci_resource_start (pdev, 0);
  153. #endif
  154. dev->base_addr = ioaddr;
  155. dev->irq = irq;
  156. np = netdev_priv(dev);
  157. np->chip_id = chip_idx;
  158. np->pdev = pdev;
  159. spin_lock_init (&np->tx_lock);
  160. spin_lock_init (&np->rx_lock);
  161. /* Parse manual configuration */
  162. np->an_enable = 1;
  163. np->tx_coalesce = 1;
  164. if (card_idx < MAX_UNITS) {
  165. if (media[card_idx] != NULL) {
  166. np->an_enable = 0;
  167. if (strcmp (media[card_idx], "auto") == 0 ||
  168. strcmp (media[card_idx], "autosense") == 0 ||
  169. strcmp (media[card_idx], "0") == 0 ) {
  170. np->an_enable = 2;
  171. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  172. strcmp (media[card_idx], "4") == 0) {
  173. np->speed = 100;
  174. np->full_duplex = 1;
  175. } else if (strcmp (media[card_idx], "100mbps_hd") == 0
  176. || strcmp (media[card_idx], "3") == 0) {
  177. np->speed = 100;
  178. np->full_duplex = 0;
  179. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  180. strcmp (media[card_idx], "2") == 0) {
  181. np->speed = 10;
  182. np->full_duplex = 1;
  183. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  184. strcmp (media[card_idx], "1") == 0) {
  185. np->speed = 10;
  186. np->full_duplex = 0;
  187. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  188. strcmp (media[card_idx], "6") == 0) {
  189. np->speed=1000;
  190. np->full_duplex=1;
  191. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  192. strcmp (media[card_idx], "5") == 0) {
  193. np->speed = 1000;
  194. np->full_duplex = 0;
  195. } else {
  196. np->an_enable = 1;
  197. }
  198. }
  199. if (jumbo[card_idx] != 0) {
  200. np->jumbo = 1;
  201. dev->mtu = MAX_JUMBO;
  202. } else {
  203. np->jumbo = 0;
  204. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  205. dev->mtu = mtu[card_idx];
  206. }
  207. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  208. vlan[card_idx] : 0;
  209. if (rx_coalesce > 0 && rx_timeout > 0) {
  210. np->rx_coalesce = rx_coalesce;
  211. np->rx_timeout = rx_timeout;
  212. np->coalesce = 1;
  213. }
  214. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  215. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  216. if (tx_coalesce < 1)
  217. tx_coalesce = 1;
  218. else if (tx_coalesce > TX_RING_SIZE-1)
  219. tx_coalesce = TX_RING_SIZE - 1;
  220. }
  221. dev->open = &rio_open;
  222. dev->hard_start_xmit = &start_xmit;
  223. dev->stop = &rio_close;
  224. dev->get_stats = &get_stats;
  225. dev->set_multicast_list = &set_multicast;
  226. dev->do_ioctl = &rio_ioctl;
  227. dev->tx_timeout = &rio_tx_timeout;
  228. dev->watchdog_timeo = TX_TIMEOUT;
  229. dev->change_mtu = &change_mtu;
  230. SET_ETHTOOL_OPS(dev, &ethtool_ops);
  231. #if 0
  232. dev->features = NETIF_F_IP_CSUM;
  233. #endif
  234. pci_set_drvdata (pdev, dev);
  235. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  236. if (!ring_space)
  237. goto err_out_iounmap;
  238. np->tx_ring = (struct netdev_desc *) ring_space;
  239. np->tx_ring_dma = ring_dma;
  240. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  241. if (!ring_space)
  242. goto err_out_unmap_tx;
  243. np->rx_ring = (struct netdev_desc *) ring_space;
  244. np->rx_ring_dma = ring_dma;
  245. /* Parse eeprom data */
  246. parse_eeprom (dev);
  247. /* Find PHY address */
  248. err = find_miiphy (dev);
  249. if (err)
  250. goto err_out_unmap_rx;
  251. /* Fiber device? */
  252. np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
  253. np->link_status = 0;
  254. /* Set media and reset PHY */
  255. if (np->phy_media) {
  256. /* default Auto-Negotiation for fiber deivices */
  257. if (np->an_enable == 2) {
  258. np->an_enable = 1;
  259. }
  260. mii_set_media_pcs (dev);
  261. } else {
  262. /* Auto-Negotiation is mandatory for 1000BASE-T,
  263. IEEE 802.3ab Annex 28D page 14 */
  264. if (np->speed == 1000)
  265. np->an_enable = 1;
  266. mii_set_media (dev);
  267. }
  268. pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
  269. err = register_netdev (dev);
  270. if (err)
  271. goto err_out_unmap_rx;
  272. card_idx++;
  273. printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
  274. dev->name, np->name,
  275. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  276. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
  277. if (tx_coalesce > 1)
  278. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  279. tx_coalesce);
  280. if (np->coalesce)
  281. printk(KERN_INFO "rx_coalesce:\t%d packets\n"
  282. KERN_INFO "rx_timeout: \t%d ns\n",
  283. np->rx_coalesce, np->rx_timeout*640);
  284. if (np->vlan)
  285. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  286. return 0;
  287. err_out_unmap_rx:
  288. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  289. err_out_unmap_tx:
  290. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  291. err_out_iounmap:
  292. #ifdef MEM_MAPPING
  293. iounmap ((void *) ioaddr);
  294. err_out_dev:
  295. #endif
  296. free_netdev (dev);
  297. err_out_res:
  298. pci_release_regions (pdev);
  299. err_out_disable:
  300. pci_disable_device (pdev);
  301. return err;
  302. }
  303. int
  304. find_miiphy (struct net_device *dev)
  305. {
  306. int i, phy_found = 0;
  307. struct netdev_private *np;
  308. long ioaddr;
  309. np = netdev_priv(dev);
  310. ioaddr = dev->base_addr;
  311. np->phy_addr = 1;
  312. for (i = 31; i >= 0; i--) {
  313. int mii_status = mii_read (dev, i, 1);
  314. if (mii_status != 0xffff && mii_status != 0x0000) {
  315. np->phy_addr = i;
  316. phy_found++;
  317. }
  318. }
  319. if (!phy_found) {
  320. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  321. return -ENODEV;
  322. }
  323. return 0;
  324. }
  325. int
  326. parse_eeprom (struct net_device *dev)
  327. {
  328. int i, j;
  329. long ioaddr = dev->base_addr;
  330. u8 sromdata[256];
  331. u8 *psib;
  332. u32 crc;
  333. PSROM_t psrom = (PSROM_t) sromdata;
  334. struct netdev_private *np = netdev_priv(dev);
  335. int cid, next;
  336. #ifdef MEM_MAPPING
  337. ioaddr = pci_resource_start (np->pdev, 0);
  338. #endif
  339. /* Read eeprom */
  340. for (i = 0; i < 128; i++) {
  341. ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
  342. }
  343. #ifdef MEM_MAPPING
  344. ioaddr = dev->base_addr;
  345. #endif
  346. /* Check CRC */
  347. crc = ~ether_crc_le (256 - 4, sromdata);
  348. if (psrom->crc != crc) {
  349. printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
  350. return -1;
  351. }
  352. /* Set MAC address */
  353. for (i = 0; i < 6; i++)
  354. dev->dev_addr[i] = psrom->mac_addr[i];
  355. /* Parse Software Infomation Block */
  356. i = 0x30;
  357. psib = (u8 *) sromdata;
  358. do {
  359. cid = psib[i++];
  360. next = psib[i++];
  361. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  362. printk (KERN_ERR "Cell data error\n");
  363. return -1;
  364. }
  365. switch (cid) {
  366. case 0: /* Format version */
  367. break;
  368. case 1: /* End of cell */
  369. return 0;
  370. case 2: /* Duplex Polarity */
  371. np->duplex_polarity = psib[i];
  372. writeb (readb (ioaddr + PhyCtrl) | psib[i],
  373. ioaddr + PhyCtrl);
  374. break;
  375. case 3: /* Wake Polarity */
  376. np->wake_polarity = psib[i];
  377. break;
  378. case 9: /* Adapter description */
  379. j = (next - i > 255) ? 255 : next - i;
  380. memcpy (np->name, &(psib[i]), j);
  381. break;
  382. case 4:
  383. case 5:
  384. case 6:
  385. case 7:
  386. case 8: /* Reversed */
  387. break;
  388. default: /* Unknown cell */
  389. return -1;
  390. }
  391. i = next;
  392. } while (1);
  393. return 0;
  394. }
  395. static int
  396. rio_open (struct net_device *dev)
  397. {
  398. struct netdev_private *np = netdev_priv(dev);
  399. long ioaddr = dev->base_addr;
  400. int i;
  401. u16 macctrl;
  402. i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
  403. if (i)
  404. return i;
  405. /* Reset all logic functions */
  406. writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
  407. ioaddr + ASICCtrl + 2);
  408. mdelay(10);
  409. /* DebugCtrl bit 4, 5, 9 must set */
  410. writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
  411. /* Jumbo frame */
  412. if (np->jumbo != 0)
  413. writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
  414. alloc_list (dev);
  415. /* Get station address */
  416. for (i = 0; i < 6; i++)
  417. writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
  418. set_multicast (dev);
  419. if (np->coalesce) {
  420. writel (np->rx_coalesce | np->rx_timeout << 16,
  421. ioaddr + RxDMAIntCtrl);
  422. }
  423. /* Set RIO to poll every N*320nsec. */
  424. writeb (0x20, ioaddr + RxDMAPollPeriod);
  425. writeb (0xff, ioaddr + TxDMAPollPeriod);
  426. writeb (0x30, ioaddr + RxDMABurstThresh);
  427. writeb (0x30, ioaddr + RxDMAUrgentThresh);
  428. writel (0x0007ffff, ioaddr + RmonStatMask);
  429. /* clear statistics */
  430. clear_stats (dev);
  431. /* VLAN supported */
  432. if (np->vlan) {
  433. /* priority field in RxDMAIntCtrl */
  434. writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
  435. ioaddr + RxDMAIntCtrl);
  436. /* VLANId */
  437. writew (np->vlan, ioaddr + VLANId);
  438. /* Length/Type should be 0x8100 */
  439. writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
  440. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  441. VLAN information tagged by TFC' VID, CFI fields. */
  442. writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
  443. ioaddr + MACCtrl);
  444. }
  445. init_timer (&np->timer);
  446. np->timer.expires = jiffies + 1*HZ;
  447. np->timer.data = (unsigned long) dev;
  448. np->timer.function = &rio_timer;
  449. add_timer (&np->timer);
  450. /* Start Tx/Rx */
  451. writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
  452. ioaddr + MACCtrl);
  453. macctrl = 0;
  454. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  455. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  456. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  457. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  458. writew(macctrl, ioaddr + MACCtrl);
  459. netif_start_queue (dev);
  460. /* Enable default interrupts */
  461. EnableInt ();
  462. return 0;
  463. }
  464. static void
  465. rio_timer (unsigned long data)
  466. {
  467. struct net_device *dev = (struct net_device *)data;
  468. struct netdev_private *np = netdev_priv(dev);
  469. unsigned int entry;
  470. int next_tick = 1*HZ;
  471. unsigned long flags;
  472. spin_lock_irqsave(&np->rx_lock, flags);
  473. /* Recover rx ring exhausted error */
  474. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  475. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  476. /* Re-allocate skbuffs to fill the descriptor ring */
  477. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  478. struct sk_buff *skb;
  479. entry = np->old_rx % RX_RING_SIZE;
  480. /* Dropped packets don't need to re-allocate */
  481. if (np->rx_skbuff[entry] == NULL) {
  482. skb = dev_alloc_skb (np->rx_buf_sz);
  483. if (skb == NULL) {
  484. np->rx_ring[entry].fraginfo = 0;
  485. printk (KERN_INFO
  486. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  487. dev->name, entry);
  488. break;
  489. }
  490. np->rx_skbuff[entry] = skb;
  491. skb->dev = dev;
  492. /* 16 byte align the IP header */
  493. skb_reserve (skb, 2);
  494. np->rx_ring[entry].fraginfo =
  495. cpu_to_le64 (pci_map_single
  496. (np->pdev, skb->data, np->rx_buf_sz,
  497. PCI_DMA_FROMDEVICE));
  498. }
  499. np->rx_ring[entry].fraginfo |=
  500. cpu_to_le64 (np->rx_buf_sz) << 48;
  501. np->rx_ring[entry].status = 0;
  502. } /* end for */
  503. } /* end if */
  504. spin_unlock_irqrestore (&np->rx_lock, flags);
  505. np->timer.expires = jiffies + next_tick;
  506. add_timer(&np->timer);
  507. }
  508. static void
  509. rio_tx_timeout (struct net_device *dev)
  510. {
  511. long ioaddr = dev->base_addr;
  512. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  513. dev->name, readl (ioaddr + TxStatus));
  514. rio_free_tx(dev, 0);
  515. dev->if_port = 0;
  516. dev->trans_start = jiffies;
  517. }
  518. /* allocate and initialize Tx and Rx descriptors */
  519. static void
  520. alloc_list (struct net_device *dev)
  521. {
  522. struct netdev_private *np = netdev_priv(dev);
  523. int i;
  524. np->cur_rx = np->cur_tx = 0;
  525. np->old_rx = np->old_tx = 0;
  526. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  527. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  528. for (i = 0; i < TX_RING_SIZE; i++) {
  529. np->tx_skbuff[i] = NULL;
  530. np->tx_ring[i].status = cpu_to_le64 (TFDDone);
  531. np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
  532. ((i+1)%TX_RING_SIZE) *
  533. sizeof (struct netdev_desc));
  534. }
  535. /* Initialize Rx descriptors */
  536. for (i = 0; i < RX_RING_SIZE; i++) {
  537. np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
  538. ((i + 1) % RX_RING_SIZE) *
  539. sizeof (struct netdev_desc));
  540. np->rx_ring[i].status = 0;
  541. np->rx_ring[i].fraginfo = 0;
  542. np->rx_skbuff[i] = NULL;
  543. }
  544. /* Allocate the rx buffers */
  545. for (i = 0; i < RX_RING_SIZE; i++) {
  546. /* Allocated fixed size of skbuff */
  547. struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
  548. np->rx_skbuff[i] = skb;
  549. if (skb == NULL) {
  550. printk (KERN_ERR
  551. "%s: alloc_list: allocate Rx buffer error! ",
  552. dev->name);
  553. break;
  554. }
  555. skb->dev = dev; /* Mark as being used by this device. */
  556. skb_reserve (skb, 2); /* 16 byte align the IP header. */
  557. /* Rubicon now supports 40 bits of addressing space. */
  558. np->rx_ring[i].fraginfo =
  559. cpu_to_le64 ( pci_map_single (
  560. np->pdev, skb->data, np->rx_buf_sz,
  561. PCI_DMA_FROMDEVICE));
  562. np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
  563. }
  564. /* Set RFDListPtr */
  565. writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
  566. writel (0, dev->base_addr + RFDListPtr1);
  567. return;
  568. }
  569. static int
  570. start_xmit (struct sk_buff *skb, struct net_device *dev)
  571. {
  572. struct netdev_private *np = netdev_priv(dev);
  573. struct netdev_desc *txdesc;
  574. unsigned entry;
  575. u32 ioaddr;
  576. u64 tfc_vlan_tag = 0;
  577. if (np->link_status == 0) { /* Link Down */
  578. dev_kfree_skb(skb);
  579. return 0;
  580. }
  581. ioaddr = dev->base_addr;
  582. entry = np->cur_tx % TX_RING_SIZE;
  583. np->tx_skbuff[entry] = skb;
  584. txdesc = &np->tx_ring[entry];
  585. #if 0
  586. if (skb->ip_summed == CHECKSUM_HW) {
  587. txdesc->status |=
  588. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  589. IPChecksumEnable);
  590. }
  591. #endif
  592. if (np->vlan) {
  593. tfc_vlan_tag =
  594. cpu_to_le64 (VLANTagInsert) |
  595. (cpu_to_le64 (np->vlan) << 32) |
  596. (cpu_to_le64 (skb->priority) << 45);
  597. }
  598. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  599. skb->len,
  600. PCI_DMA_TODEVICE));
  601. txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
  602. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  603. * Work around: Always use 1 descriptor in 10Mbps mode */
  604. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  605. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  606. WordAlignDisable |
  607. TxDMAIndicate |
  608. (1 << FragCountShift));
  609. else
  610. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  611. WordAlignDisable |
  612. (1 << FragCountShift));
  613. /* TxDMAPollNow */
  614. writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
  615. /* Schedule ISR */
  616. writel(10000, ioaddr + CountDown);
  617. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  618. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  619. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  620. /* do nothing */
  621. } else if (!netif_queue_stopped(dev)) {
  622. netif_stop_queue (dev);
  623. }
  624. /* The first TFDListPtr */
  625. if (readl (dev->base_addr + TFDListPtr0) == 0) {
  626. writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
  627. dev->base_addr + TFDListPtr0);
  628. writel (0, dev->base_addr + TFDListPtr1);
  629. }
  630. /* NETDEV WATCHDOG timer */
  631. dev->trans_start = jiffies;
  632. return 0;
  633. }
  634. static irqreturn_t
  635. rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
  636. {
  637. struct net_device *dev = dev_instance;
  638. struct netdev_private *np;
  639. unsigned int_status;
  640. long ioaddr;
  641. int cnt = max_intrloop;
  642. int handled = 0;
  643. ioaddr = dev->base_addr;
  644. np = netdev_priv(dev);
  645. while (1) {
  646. int_status = readw (ioaddr + IntStatus);
  647. writew (int_status, ioaddr + IntStatus);
  648. int_status &= DEFAULT_INTR;
  649. if (int_status == 0 || --cnt < 0)
  650. break;
  651. handled = 1;
  652. /* Processing received packets */
  653. if (int_status & RxDMAComplete)
  654. receive_packet (dev);
  655. /* TxDMAComplete interrupt */
  656. if ((int_status & (TxDMAComplete|IntRequested))) {
  657. int tx_status;
  658. tx_status = readl (ioaddr + TxStatus);
  659. if (tx_status & 0x01)
  660. tx_error (dev, tx_status);
  661. /* Free used tx skbuffs */
  662. rio_free_tx (dev, 1);
  663. }
  664. /* Handle uncommon events */
  665. if (int_status &
  666. (HostError | LinkEvent | UpdateStats))
  667. rio_error (dev, int_status);
  668. }
  669. if (np->cur_tx != np->old_tx)
  670. writel (100, ioaddr + CountDown);
  671. return IRQ_RETVAL(handled);
  672. }
  673. static void
  674. rio_free_tx (struct net_device *dev, int irq)
  675. {
  676. struct netdev_private *np = netdev_priv(dev);
  677. int entry = np->old_tx % TX_RING_SIZE;
  678. int tx_use = 0;
  679. unsigned long flag = 0;
  680. if (irq)
  681. spin_lock(&np->tx_lock);
  682. else
  683. spin_lock_irqsave(&np->tx_lock, flag);
  684. /* Free used tx skbuffs */
  685. while (entry != np->cur_tx) {
  686. struct sk_buff *skb;
  687. if (!(np->tx_ring[entry].status & TFDDone))
  688. break;
  689. skb = np->tx_skbuff[entry];
  690. pci_unmap_single (np->pdev,
  691. np->tx_ring[entry].fraginfo,
  692. skb->len, PCI_DMA_TODEVICE);
  693. if (irq)
  694. dev_kfree_skb_irq (skb);
  695. else
  696. dev_kfree_skb (skb);
  697. np->tx_skbuff[entry] = NULL;
  698. entry = (entry + 1) % TX_RING_SIZE;
  699. tx_use++;
  700. }
  701. if (irq)
  702. spin_unlock(&np->tx_lock);
  703. else
  704. spin_unlock_irqrestore(&np->tx_lock, flag);
  705. np->old_tx = entry;
  706. /* If the ring is no longer full, clear tx_full and
  707. call netif_wake_queue() */
  708. if (netif_queue_stopped(dev) &&
  709. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  710. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  711. netif_wake_queue (dev);
  712. }
  713. }
  714. static void
  715. tx_error (struct net_device *dev, int tx_status)
  716. {
  717. struct netdev_private *np;
  718. long ioaddr = dev->base_addr;
  719. int frame_id;
  720. int i;
  721. np = netdev_priv(dev);
  722. frame_id = (tx_status & 0xffff0000);
  723. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  724. dev->name, tx_status, frame_id);
  725. np->stats.tx_errors++;
  726. /* Ttransmit Underrun */
  727. if (tx_status & 0x10) {
  728. np->stats.tx_fifo_errors++;
  729. writew (readw (ioaddr + TxStartThresh) + 0x10,
  730. ioaddr + TxStartThresh);
  731. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  732. writew (TxReset | DMAReset | FIFOReset | NetworkReset,
  733. ioaddr + ASICCtrl + 2);
  734. /* Wait for ResetBusy bit clear */
  735. for (i = 50; i > 0; i--) {
  736. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  737. break;
  738. mdelay (1);
  739. }
  740. rio_free_tx (dev, 1);
  741. /* Reset TFDListPtr */
  742. writel (np->tx_ring_dma +
  743. np->old_tx * sizeof (struct netdev_desc),
  744. dev->base_addr + TFDListPtr0);
  745. writel (0, dev->base_addr + TFDListPtr1);
  746. /* Let TxStartThresh stay default value */
  747. }
  748. /* Late Collision */
  749. if (tx_status & 0x04) {
  750. np->stats.tx_fifo_errors++;
  751. /* TxReset and clear FIFO */
  752. writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
  753. /* Wait reset done */
  754. for (i = 50; i > 0; i--) {
  755. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  756. break;
  757. mdelay (1);
  758. }
  759. /* Let TxStartThresh stay default value */
  760. }
  761. /* Maximum Collisions */
  762. #ifdef ETHER_STATS
  763. if (tx_status & 0x08)
  764. np->stats.collisions16++;
  765. #else
  766. if (tx_status & 0x08)
  767. np->stats.collisions++;
  768. #endif
  769. /* Restart the Tx */
  770. writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
  771. }
  772. static int
  773. receive_packet (struct net_device *dev)
  774. {
  775. struct netdev_private *np = netdev_priv(dev);
  776. int entry = np->cur_rx % RX_RING_SIZE;
  777. int cnt = 30;
  778. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  779. while (1) {
  780. struct netdev_desc *desc = &np->rx_ring[entry];
  781. int pkt_len;
  782. u64 frame_status;
  783. if (!(desc->status & RFDDone) ||
  784. !(desc->status & FrameStart) || !(desc->status & FrameEnd))
  785. break;
  786. /* Chip omits the CRC. */
  787. pkt_len = le64_to_cpu (desc->status & 0xffff);
  788. frame_status = le64_to_cpu (desc->status);
  789. if (--cnt < 0)
  790. break;
  791. /* Update rx error statistics, drop packet. */
  792. if (frame_status & RFS_Errors) {
  793. np->stats.rx_errors++;
  794. if (frame_status & (RxRuntFrame | RxLengthError))
  795. np->stats.rx_length_errors++;
  796. if (frame_status & RxFCSError)
  797. np->stats.rx_crc_errors++;
  798. if (frame_status & RxAlignmentError && np->speed != 1000)
  799. np->stats.rx_frame_errors++;
  800. if (frame_status & RxFIFOOverrun)
  801. np->stats.rx_fifo_errors++;
  802. } else {
  803. struct sk_buff *skb;
  804. /* Small skbuffs for short packets */
  805. if (pkt_len > copy_thresh) {
  806. pci_unmap_single (np->pdev, desc->fraginfo,
  807. np->rx_buf_sz,
  808. PCI_DMA_FROMDEVICE);
  809. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  810. np->rx_skbuff[entry] = NULL;
  811. } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
  812. pci_dma_sync_single_for_cpu(np->pdev,
  813. desc->fraginfo,
  814. np->rx_buf_sz,
  815. PCI_DMA_FROMDEVICE);
  816. skb->dev = dev;
  817. /* 16 byte align the IP header */
  818. skb_reserve (skb, 2);
  819. eth_copy_and_sum (skb,
  820. np->rx_skbuff[entry]->data,
  821. pkt_len, 0);
  822. skb_put (skb, pkt_len);
  823. pci_dma_sync_single_for_device(np->pdev,
  824. desc->fraginfo,
  825. np->rx_buf_sz,
  826. PCI_DMA_FROMDEVICE);
  827. }
  828. skb->protocol = eth_type_trans (skb, dev);
  829. #if 0
  830. /* Checksum done by hw, but csum value unavailable. */
  831. if (np->pci_rev_id >= 0x0c &&
  832. !(frame_status & (TCPError | UDPError | IPError))) {
  833. skb->ip_summed = CHECKSUM_UNNECESSARY;
  834. }
  835. #endif
  836. netif_rx (skb);
  837. dev->last_rx = jiffies;
  838. }
  839. entry = (entry + 1) % RX_RING_SIZE;
  840. }
  841. spin_lock(&np->rx_lock);
  842. np->cur_rx = entry;
  843. /* Re-allocate skbuffs to fill the descriptor ring */
  844. entry = np->old_rx;
  845. while (entry != np->cur_rx) {
  846. struct sk_buff *skb;
  847. /* Dropped packets don't need to re-allocate */
  848. if (np->rx_skbuff[entry] == NULL) {
  849. skb = dev_alloc_skb (np->rx_buf_sz);
  850. if (skb == NULL) {
  851. np->rx_ring[entry].fraginfo = 0;
  852. printk (KERN_INFO
  853. "%s: receive_packet: "
  854. "Unable to re-allocate Rx skbuff.#%d\n",
  855. dev->name, entry);
  856. break;
  857. }
  858. np->rx_skbuff[entry] = skb;
  859. skb->dev = dev;
  860. /* 16 byte align the IP header */
  861. skb_reserve (skb, 2);
  862. np->rx_ring[entry].fraginfo =
  863. cpu_to_le64 (pci_map_single
  864. (np->pdev, skb->data, np->rx_buf_sz,
  865. PCI_DMA_FROMDEVICE));
  866. }
  867. np->rx_ring[entry].fraginfo |=
  868. cpu_to_le64 (np->rx_buf_sz) << 48;
  869. np->rx_ring[entry].status = 0;
  870. entry = (entry + 1) % RX_RING_SIZE;
  871. }
  872. np->old_rx = entry;
  873. spin_unlock(&np->rx_lock);
  874. return 0;
  875. }
  876. static void
  877. rio_error (struct net_device *dev, int int_status)
  878. {
  879. long ioaddr = dev->base_addr;
  880. struct netdev_private *np = netdev_priv(dev);
  881. u16 macctrl;
  882. /* Link change event */
  883. if (int_status & LinkEvent) {
  884. if (mii_wait_link (dev, 10) == 0) {
  885. printk (KERN_INFO "%s: Link up\n", dev->name);
  886. if (np->phy_media)
  887. mii_get_media_pcs (dev);
  888. else
  889. mii_get_media (dev);
  890. if (np->speed == 1000)
  891. np->tx_coalesce = tx_coalesce;
  892. else
  893. np->tx_coalesce = 1;
  894. macctrl = 0;
  895. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  896. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  897. macctrl |= (np->tx_flow) ?
  898. TxFlowControlEnable : 0;
  899. macctrl |= (np->rx_flow) ?
  900. RxFlowControlEnable : 0;
  901. writew(macctrl, ioaddr + MACCtrl);
  902. np->link_status = 1;
  903. netif_carrier_on(dev);
  904. } else {
  905. printk (KERN_INFO "%s: Link off\n", dev->name);
  906. np->link_status = 0;
  907. netif_carrier_off(dev);
  908. }
  909. }
  910. /* UpdateStats statistics registers */
  911. if (int_status & UpdateStats) {
  912. get_stats (dev);
  913. }
  914. /* PCI Error, a catastronphic error related to the bus interface
  915. occurs, set GlobalReset and HostReset to reset. */
  916. if (int_status & HostError) {
  917. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  918. dev->name, int_status);
  919. writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
  920. mdelay (500);
  921. }
  922. }
  923. static struct net_device_stats *
  924. get_stats (struct net_device *dev)
  925. {
  926. long ioaddr = dev->base_addr;
  927. struct netdev_private *np = netdev_priv(dev);
  928. #ifdef MEM_MAPPING
  929. int i;
  930. #endif
  931. unsigned int stat_reg;
  932. /* All statistics registers need to be acknowledged,
  933. else statistic overflow could cause problems */
  934. np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
  935. np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
  936. np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
  937. np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
  938. np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
  939. np->stats.collisions += readl (ioaddr + SingleColFrames)
  940. + readl (ioaddr + MultiColFrames);
  941. /* detailed tx errors */
  942. stat_reg = readw (ioaddr + FramesAbortXSColls);
  943. np->stats.tx_aborted_errors += stat_reg;
  944. np->stats.tx_errors += stat_reg;
  945. stat_reg = readw (ioaddr + CarrierSenseErrors);
  946. np->stats.tx_carrier_errors += stat_reg;
  947. np->stats.tx_errors += stat_reg;
  948. /* Clear all other statistic register. */
  949. readl (ioaddr + McstOctetXmtOk);
  950. readw (ioaddr + BcstFramesXmtdOk);
  951. readl (ioaddr + McstFramesXmtdOk);
  952. readw (ioaddr + BcstFramesRcvdOk);
  953. readw (ioaddr + MacControlFramesRcvd);
  954. readw (ioaddr + FrameTooLongErrors);
  955. readw (ioaddr + InRangeLengthErrors);
  956. readw (ioaddr + FramesCheckSeqErrors);
  957. readw (ioaddr + FramesLostRxErrors);
  958. readl (ioaddr + McstOctetXmtOk);
  959. readl (ioaddr + BcstOctetXmtOk);
  960. readl (ioaddr + McstFramesXmtdOk);
  961. readl (ioaddr + FramesWDeferredXmt);
  962. readl (ioaddr + LateCollisions);
  963. readw (ioaddr + BcstFramesXmtdOk);
  964. readw (ioaddr + MacControlFramesXmtd);
  965. readw (ioaddr + FramesWEXDeferal);
  966. #ifdef MEM_MAPPING
  967. for (i = 0x100; i <= 0x150; i += 4)
  968. readl (ioaddr + i);
  969. #endif
  970. readw (ioaddr + TxJumboFrames);
  971. readw (ioaddr + RxJumboFrames);
  972. readw (ioaddr + TCPCheckSumErrors);
  973. readw (ioaddr + UDPCheckSumErrors);
  974. readw (ioaddr + IPCheckSumErrors);
  975. return &np->stats;
  976. }
  977. static int
  978. clear_stats (struct net_device *dev)
  979. {
  980. long ioaddr = dev->base_addr;
  981. #ifdef MEM_MAPPING
  982. int i;
  983. #endif
  984. /* All statistics registers need to be acknowledged,
  985. else statistic overflow could cause problems */
  986. readl (ioaddr + FramesRcvOk);
  987. readl (ioaddr + FramesXmtOk);
  988. readl (ioaddr + OctetRcvOk);
  989. readl (ioaddr + OctetXmtOk);
  990. readl (ioaddr + McstFramesRcvdOk);
  991. readl (ioaddr + SingleColFrames);
  992. readl (ioaddr + MultiColFrames);
  993. readl (ioaddr + LateCollisions);
  994. /* detailed rx errors */
  995. readw (ioaddr + FrameTooLongErrors);
  996. readw (ioaddr + InRangeLengthErrors);
  997. readw (ioaddr + FramesCheckSeqErrors);
  998. readw (ioaddr + FramesLostRxErrors);
  999. /* detailed tx errors */
  1000. readw (ioaddr + FramesAbortXSColls);
  1001. readw (ioaddr + CarrierSenseErrors);
  1002. /* Clear all other statistic register. */
  1003. readl (ioaddr + McstOctetXmtOk);
  1004. readw (ioaddr + BcstFramesXmtdOk);
  1005. readl (ioaddr + McstFramesXmtdOk);
  1006. readw (ioaddr + BcstFramesRcvdOk);
  1007. readw (ioaddr + MacControlFramesRcvd);
  1008. readl (ioaddr + McstOctetXmtOk);
  1009. readl (ioaddr + BcstOctetXmtOk);
  1010. readl (ioaddr + McstFramesXmtdOk);
  1011. readl (ioaddr + FramesWDeferredXmt);
  1012. readw (ioaddr + BcstFramesXmtdOk);
  1013. readw (ioaddr + MacControlFramesXmtd);
  1014. readw (ioaddr + FramesWEXDeferal);
  1015. #ifdef MEM_MAPPING
  1016. for (i = 0x100; i <= 0x150; i += 4)
  1017. readl (ioaddr + i);
  1018. #endif
  1019. readw (ioaddr + TxJumboFrames);
  1020. readw (ioaddr + RxJumboFrames);
  1021. readw (ioaddr + TCPCheckSumErrors);
  1022. readw (ioaddr + UDPCheckSumErrors);
  1023. readw (ioaddr + IPCheckSumErrors);
  1024. return 0;
  1025. }
  1026. int
  1027. change_mtu (struct net_device *dev, int new_mtu)
  1028. {
  1029. struct netdev_private *np = netdev_priv(dev);
  1030. int max = (np->jumbo) ? MAX_JUMBO : 1536;
  1031. if ((new_mtu < 68) || (new_mtu > max)) {
  1032. return -EINVAL;
  1033. }
  1034. dev->mtu = new_mtu;
  1035. return 0;
  1036. }
  1037. static void
  1038. set_multicast (struct net_device *dev)
  1039. {
  1040. long ioaddr = dev->base_addr;
  1041. u32 hash_table[2];
  1042. u16 rx_mode = 0;
  1043. struct netdev_private *np = netdev_priv(dev);
  1044. hash_table[0] = hash_table[1] = 0;
  1045. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1046. hash_table[1] |= cpu_to_le32(0x02000000);
  1047. if (dev->flags & IFF_PROMISC) {
  1048. /* Receive all frames promiscuously. */
  1049. rx_mode = ReceiveAllFrames;
  1050. } else if ((dev->flags & IFF_ALLMULTI) ||
  1051. (dev->mc_count > multicast_filter_limit)) {
  1052. /* Receive broadcast and multicast frames */
  1053. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1054. } else if (dev->mc_count > 0) {
  1055. int i;
  1056. struct dev_mc_list *mclist;
  1057. /* Receive broadcast frames and multicast frames filtering
  1058. by Hashtable */
  1059. rx_mode =
  1060. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1061. for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  1062. i++, mclist=mclist->next)
  1063. {
  1064. int bit, index = 0;
  1065. int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
  1066. /* The inverted high significant 6 bits of CRC are
  1067. used as an index to hashtable */
  1068. for (bit = 0; bit < 6; bit++)
  1069. if (crc & (1 << (31 - bit)))
  1070. index |= (1 << bit);
  1071. hash_table[index / 32] |= (1 << (index % 32));
  1072. }
  1073. } else {
  1074. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1075. }
  1076. if (np->vlan) {
  1077. /* ReceiveVLANMatch field in ReceiveMode */
  1078. rx_mode |= ReceiveVLANMatch;
  1079. }
  1080. writel (hash_table[0], ioaddr + HashTable0);
  1081. writel (hash_table[1], ioaddr + HashTable1);
  1082. writew (rx_mode, ioaddr + ReceiveMode);
  1083. }
  1084. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1085. {
  1086. struct netdev_private *np = netdev_priv(dev);
  1087. strcpy(info->driver, "dl2k");
  1088. strcpy(info->version, DRV_VERSION);
  1089. strcpy(info->bus_info, pci_name(np->pdev));
  1090. }
  1091. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1092. {
  1093. struct netdev_private *np = netdev_priv(dev);
  1094. if (np->phy_media) {
  1095. /* fiber device */
  1096. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1097. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1098. cmd->port = PORT_FIBRE;
  1099. cmd->transceiver = XCVR_INTERNAL;
  1100. } else {
  1101. /* copper device */
  1102. cmd->supported = SUPPORTED_10baseT_Half |
  1103. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1104. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1105. SUPPORTED_Autoneg | SUPPORTED_MII;
  1106. cmd->advertising = ADVERTISED_10baseT_Half |
  1107. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1108. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1109. ADVERTISED_Autoneg | ADVERTISED_MII;
  1110. cmd->port = PORT_MII;
  1111. cmd->transceiver = XCVR_INTERNAL;
  1112. }
  1113. if ( np->link_status ) {
  1114. cmd->speed = np->speed;
  1115. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1116. } else {
  1117. cmd->speed = -1;
  1118. cmd->duplex = -1;
  1119. }
  1120. if ( np->an_enable)
  1121. cmd->autoneg = AUTONEG_ENABLE;
  1122. else
  1123. cmd->autoneg = AUTONEG_DISABLE;
  1124. cmd->phy_address = np->phy_addr;
  1125. return 0;
  1126. }
  1127. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1128. {
  1129. struct netdev_private *np = netdev_priv(dev);
  1130. netif_carrier_off(dev);
  1131. if (cmd->autoneg == AUTONEG_ENABLE) {
  1132. if (np->an_enable)
  1133. return 0;
  1134. else {
  1135. np->an_enable = 1;
  1136. mii_set_media(dev);
  1137. return 0;
  1138. }
  1139. } else {
  1140. np->an_enable = 0;
  1141. if (np->speed == 1000) {
  1142. cmd->speed = SPEED_100;
  1143. cmd->duplex = DUPLEX_FULL;
  1144. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1145. }
  1146. switch(cmd->speed + cmd->duplex) {
  1147. case SPEED_10 + DUPLEX_HALF:
  1148. np->speed = 10;
  1149. np->full_duplex = 0;
  1150. break;
  1151. case SPEED_10 + DUPLEX_FULL:
  1152. np->speed = 10;
  1153. np->full_duplex = 1;
  1154. break;
  1155. case SPEED_100 + DUPLEX_HALF:
  1156. np->speed = 100;
  1157. np->full_duplex = 0;
  1158. break;
  1159. case SPEED_100 + DUPLEX_FULL:
  1160. np->speed = 100;
  1161. np->full_duplex = 1;
  1162. break;
  1163. case SPEED_1000 + DUPLEX_HALF:/* not supported */
  1164. case SPEED_1000 + DUPLEX_FULL:/* not supported */
  1165. default:
  1166. return -EINVAL;
  1167. }
  1168. mii_set_media(dev);
  1169. }
  1170. return 0;
  1171. }
  1172. static u32 rio_get_link(struct net_device *dev)
  1173. {
  1174. struct netdev_private *np = netdev_priv(dev);
  1175. return np->link_status;
  1176. }
  1177. static struct ethtool_ops ethtool_ops = {
  1178. .get_drvinfo = rio_get_drvinfo,
  1179. .get_settings = rio_get_settings,
  1180. .set_settings = rio_set_settings,
  1181. .get_link = rio_get_link,
  1182. };
  1183. static int
  1184. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1185. {
  1186. int phy_addr;
  1187. struct netdev_private *np = netdev_priv(dev);
  1188. struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
  1189. struct netdev_desc *desc;
  1190. int i;
  1191. phy_addr = np->phy_addr;
  1192. switch (cmd) {
  1193. case SIOCDEVPRIVATE:
  1194. break;
  1195. case SIOCDEVPRIVATE + 1:
  1196. miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
  1197. break;
  1198. case SIOCDEVPRIVATE + 2:
  1199. mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
  1200. break;
  1201. case SIOCDEVPRIVATE + 3:
  1202. break;
  1203. case SIOCDEVPRIVATE + 4:
  1204. break;
  1205. case SIOCDEVPRIVATE + 5:
  1206. netif_stop_queue (dev);
  1207. break;
  1208. case SIOCDEVPRIVATE + 6:
  1209. netif_wake_queue (dev);
  1210. break;
  1211. case SIOCDEVPRIVATE + 7:
  1212. printk
  1213. ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
  1214. netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
  1215. np->old_rx);
  1216. break;
  1217. case SIOCDEVPRIVATE + 8:
  1218. printk("TX ring:\n");
  1219. for (i = 0; i < TX_RING_SIZE; i++) {
  1220. desc = &np->tx_ring[i];
  1221. printk
  1222. ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
  1223. i,
  1224. (u32) (np->tx_ring_dma + i * sizeof (*desc)),
  1225. (u32) desc->next_desc,
  1226. (u32) desc->status, (u32) (desc->fraginfo >> 32),
  1227. (u32) desc->fraginfo);
  1228. printk ("\n");
  1229. }
  1230. printk ("\n");
  1231. break;
  1232. default:
  1233. return -EOPNOTSUPP;
  1234. }
  1235. return 0;
  1236. }
  1237. #define EEP_READ 0x0200
  1238. #define EEP_BUSY 0x8000
  1239. /* Read the EEPROM word */
  1240. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1241. int
  1242. read_eeprom (long ioaddr, int eep_addr)
  1243. {
  1244. int i = 1000;
  1245. outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
  1246. while (i-- > 0) {
  1247. if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
  1248. return inw (ioaddr + EepromData);
  1249. }
  1250. }
  1251. return 0;
  1252. }
  1253. enum phy_ctrl_bits {
  1254. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1255. MII_DUPLEX = 0x08,
  1256. };
  1257. #define mii_delay() readb(ioaddr)
  1258. static void
  1259. mii_sendbit (struct net_device *dev, u32 data)
  1260. {
  1261. long ioaddr = dev->base_addr + PhyCtrl;
  1262. data = (data) ? MII_DATA1 : 0;
  1263. data |= MII_WRITE;
  1264. data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
  1265. writeb (data, ioaddr);
  1266. mii_delay ();
  1267. writeb (data | MII_CLK, ioaddr);
  1268. mii_delay ();
  1269. }
  1270. static int
  1271. mii_getbit (struct net_device *dev)
  1272. {
  1273. long ioaddr = dev->base_addr + PhyCtrl;
  1274. u8 data;
  1275. data = (readb (ioaddr) & 0xf8) | MII_READ;
  1276. writeb (data, ioaddr);
  1277. mii_delay ();
  1278. writeb (data | MII_CLK, ioaddr);
  1279. mii_delay ();
  1280. return ((readb (ioaddr) >> 1) & 1);
  1281. }
  1282. static void
  1283. mii_send_bits (struct net_device *dev, u32 data, int len)
  1284. {
  1285. int i;
  1286. for (i = len - 1; i >= 0; i--) {
  1287. mii_sendbit (dev, data & (1 << i));
  1288. }
  1289. }
  1290. static int
  1291. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1292. {
  1293. u32 cmd;
  1294. int i;
  1295. u32 retval = 0;
  1296. /* Preamble */
  1297. mii_send_bits (dev, 0xffffffff, 32);
  1298. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1299. /* ST,OP = 0110'b for read operation */
  1300. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1301. mii_send_bits (dev, cmd, 14);
  1302. /* Turnaround */
  1303. if (mii_getbit (dev))
  1304. goto err_out;
  1305. /* Read data */
  1306. for (i = 0; i < 16; i++) {
  1307. retval |= mii_getbit (dev);
  1308. retval <<= 1;
  1309. }
  1310. /* End cycle */
  1311. mii_getbit (dev);
  1312. return (retval >> 1) & 0xffff;
  1313. err_out:
  1314. return 0;
  1315. }
  1316. static int
  1317. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1318. {
  1319. u32 cmd;
  1320. /* Preamble */
  1321. mii_send_bits (dev, 0xffffffff, 32);
  1322. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1323. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1324. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1325. mii_send_bits (dev, cmd, 32);
  1326. /* End cycle */
  1327. mii_getbit (dev);
  1328. return 0;
  1329. }
  1330. static int
  1331. mii_wait_link (struct net_device *dev, int wait)
  1332. {
  1333. BMSR_t bmsr;
  1334. int phy_addr;
  1335. struct netdev_private *np;
  1336. np = netdev_priv(dev);
  1337. phy_addr = np->phy_addr;
  1338. do {
  1339. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1340. if (bmsr.bits.link_status)
  1341. return 0;
  1342. mdelay (1);
  1343. } while (--wait > 0);
  1344. return -1;
  1345. }
  1346. static int
  1347. mii_get_media (struct net_device *dev)
  1348. {
  1349. ANAR_t negotiate;
  1350. BMSR_t bmsr;
  1351. BMCR_t bmcr;
  1352. MSCR_t mscr;
  1353. MSSR_t mssr;
  1354. int phy_addr;
  1355. struct netdev_private *np;
  1356. np = netdev_priv(dev);
  1357. phy_addr = np->phy_addr;
  1358. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1359. if (np->an_enable) {
  1360. if (!bmsr.bits.an_complete) {
  1361. /* Auto-Negotiation not completed */
  1362. return -1;
  1363. }
  1364. negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
  1365. mii_read (dev, phy_addr, MII_ANLPAR);
  1366. mscr.image = mii_read (dev, phy_addr, MII_MSCR);
  1367. mssr.image = mii_read (dev, phy_addr, MII_MSSR);
  1368. if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
  1369. np->speed = 1000;
  1370. np->full_duplex = 1;
  1371. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1372. } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
  1373. np->speed = 1000;
  1374. np->full_duplex = 0;
  1375. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1376. } else if (negotiate.bits.media_100BX_FD) {
  1377. np->speed = 100;
  1378. np->full_duplex = 1;
  1379. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1380. } else if (negotiate.bits.media_100BX_HD) {
  1381. np->speed = 100;
  1382. np->full_duplex = 0;
  1383. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1384. } else if (negotiate.bits.media_10BT_FD) {
  1385. np->speed = 10;
  1386. np->full_duplex = 1;
  1387. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1388. } else if (negotiate.bits.media_10BT_HD) {
  1389. np->speed = 10;
  1390. np->full_duplex = 0;
  1391. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1392. }
  1393. if (negotiate.bits.pause) {
  1394. np->tx_flow &= 1;
  1395. np->rx_flow &= 1;
  1396. } else if (negotiate.bits.asymmetric) {
  1397. np->tx_flow = 0;
  1398. np->rx_flow &= 1;
  1399. }
  1400. /* else tx_flow, rx_flow = user select */
  1401. } else {
  1402. bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
  1403. if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
  1404. printk (KERN_INFO "Operating at 100 Mbps, ");
  1405. } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
  1406. printk (KERN_INFO "Operating at 10 Mbps, ");
  1407. } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
  1408. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1409. }
  1410. if (bmcr.bits.duplex_mode) {
  1411. printk ("Full duplex\n");
  1412. } else {
  1413. printk ("Half duplex\n");
  1414. }
  1415. }
  1416. if (np->tx_flow)
  1417. printk(KERN_INFO "Enable Tx Flow Control\n");
  1418. else
  1419. printk(KERN_INFO "Disable Tx Flow Control\n");
  1420. if (np->rx_flow)
  1421. printk(KERN_INFO "Enable Rx Flow Control\n");
  1422. else
  1423. printk(KERN_INFO "Disable Rx Flow Control\n");
  1424. return 0;
  1425. }
  1426. static int
  1427. mii_set_media (struct net_device *dev)
  1428. {
  1429. PHY_SCR_t pscr;
  1430. BMCR_t bmcr;
  1431. BMSR_t bmsr;
  1432. ANAR_t anar;
  1433. int phy_addr;
  1434. struct netdev_private *np;
  1435. np = netdev_priv(dev);
  1436. phy_addr = np->phy_addr;
  1437. /* Does user set speed? */
  1438. if (np->an_enable) {
  1439. /* Advertise capabilities */
  1440. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1441. anar.image = mii_read (dev, phy_addr, MII_ANAR);
  1442. anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
  1443. anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
  1444. anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
  1445. anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
  1446. anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
  1447. anar.bits.pause = 1;
  1448. anar.bits.asymmetric = 1;
  1449. mii_write (dev, phy_addr, MII_ANAR, anar.image);
  1450. /* Enable Auto crossover */
  1451. pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
  1452. pscr.bits.mdi_crossover_mode = 3; /* 11'b */
  1453. mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
  1454. /* Soft reset PHY */
  1455. mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
  1456. bmcr.image = 0;
  1457. bmcr.bits.an_enable = 1;
  1458. bmcr.bits.restart_an = 1;
  1459. bmcr.bits.reset = 1;
  1460. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1461. mdelay(1);
  1462. } else {
  1463. /* Force speed setting */
  1464. /* 1) Disable Auto crossover */
  1465. pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
  1466. pscr.bits.mdi_crossover_mode = 0;
  1467. mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
  1468. /* 2) PHY Reset */
  1469. bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
  1470. bmcr.bits.reset = 1;
  1471. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1472. /* 3) Power Down */
  1473. bmcr.image = 0x1940; /* must be 0x1940 */
  1474. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1475. mdelay (100); /* wait a certain time */
  1476. /* 4) Advertise nothing */
  1477. mii_write (dev, phy_addr, MII_ANAR, 0);
  1478. /* 5) Set media and Power Up */
  1479. bmcr.image = 0;
  1480. bmcr.bits.power_down = 1;
  1481. if (np->speed == 100) {
  1482. bmcr.bits.speed100 = 1;
  1483. bmcr.bits.speed1000 = 0;
  1484. printk (KERN_INFO "Manual 100 Mbps, ");
  1485. } else if (np->speed == 10) {
  1486. bmcr.bits.speed100 = 0;
  1487. bmcr.bits.speed1000 = 0;
  1488. printk (KERN_INFO "Manual 10 Mbps, ");
  1489. }
  1490. if (np->full_duplex) {
  1491. bmcr.bits.duplex_mode = 1;
  1492. printk ("Full duplex\n");
  1493. } else {
  1494. bmcr.bits.duplex_mode = 0;
  1495. printk ("Half duplex\n");
  1496. }
  1497. #if 0
  1498. /* Set 1000BaseT Master/Slave setting */
  1499. mscr.image = mii_read (dev, phy_addr, MII_MSCR);
  1500. mscr.bits.cfg_enable = 1;
  1501. mscr.bits.cfg_value = 0;
  1502. #endif
  1503. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1504. mdelay(10);
  1505. }
  1506. return 0;
  1507. }
  1508. static int
  1509. mii_get_media_pcs (struct net_device *dev)
  1510. {
  1511. ANAR_PCS_t negotiate;
  1512. BMSR_t bmsr;
  1513. BMCR_t bmcr;
  1514. int phy_addr;
  1515. struct netdev_private *np;
  1516. np = netdev_priv(dev);
  1517. phy_addr = np->phy_addr;
  1518. bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
  1519. if (np->an_enable) {
  1520. if (!bmsr.bits.an_complete) {
  1521. /* Auto-Negotiation not completed */
  1522. return -1;
  1523. }
  1524. negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
  1525. mii_read (dev, phy_addr, PCS_ANLPAR);
  1526. np->speed = 1000;
  1527. if (negotiate.bits.full_duplex) {
  1528. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1529. np->full_duplex = 1;
  1530. } else {
  1531. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1532. np->full_duplex = 0;
  1533. }
  1534. if (negotiate.bits.pause) {
  1535. np->tx_flow &= 1;
  1536. np->rx_flow &= 1;
  1537. } else if (negotiate.bits.asymmetric) {
  1538. np->tx_flow = 0;
  1539. np->rx_flow &= 1;
  1540. }
  1541. /* else tx_flow, rx_flow = user select */
  1542. } else {
  1543. bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
  1544. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1545. if (bmcr.bits.duplex_mode) {
  1546. printk ("Full duplex\n");
  1547. } else {
  1548. printk ("Half duplex\n");
  1549. }
  1550. }
  1551. if (np->tx_flow)
  1552. printk(KERN_INFO "Enable Tx Flow Control\n");
  1553. else
  1554. printk(KERN_INFO "Disable Tx Flow Control\n");
  1555. if (np->rx_flow)
  1556. printk(KERN_INFO "Enable Rx Flow Control\n");
  1557. else
  1558. printk(KERN_INFO "Disable Rx Flow Control\n");
  1559. return 0;
  1560. }
  1561. static int
  1562. mii_set_media_pcs (struct net_device *dev)
  1563. {
  1564. BMCR_t bmcr;
  1565. ESR_t esr;
  1566. ANAR_PCS_t anar;
  1567. int phy_addr;
  1568. struct netdev_private *np;
  1569. np = netdev_priv(dev);
  1570. phy_addr = np->phy_addr;
  1571. /* Auto-Negotiation? */
  1572. if (np->an_enable) {
  1573. /* Advertise capabilities */
  1574. esr.image = mii_read (dev, phy_addr, PCS_ESR);
  1575. anar.image = mii_read (dev, phy_addr, MII_ANAR);
  1576. anar.bits.half_duplex =
  1577. esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
  1578. anar.bits.full_duplex =
  1579. esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
  1580. anar.bits.pause = 1;
  1581. anar.bits.asymmetric = 1;
  1582. mii_write (dev, phy_addr, MII_ANAR, anar.image);
  1583. /* Soft reset PHY */
  1584. mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
  1585. bmcr.image = 0;
  1586. bmcr.bits.an_enable = 1;
  1587. bmcr.bits.restart_an = 1;
  1588. bmcr.bits.reset = 1;
  1589. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1590. mdelay(1);
  1591. } else {
  1592. /* Force speed setting */
  1593. /* PHY Reset */
  1594. bmcr.image = 0;
  1595. bmcr.bits.reset = 1;
  1596. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1597. mdelay(10);
  1598. bmcr.image = 0;
  1599. bmcr.bits.an_enable = 0;
  1600. if (np->full_duplex) {
  1601. bmcr.bits.duplex_mode = 1;
  1602. printk (KERN_INFO "Manual full duplex\n");
  1603. } else {
  1604. bmcr.bits.duplex_mode = 0;
  1605. printk (KERN_INFO "Manual half duplex\n");
  1606. }
  1607. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1608. mdelay(10);
  1609. /* Advertise nothing */
  1610. mii_write (dev, phy_addr, MII_ANAR, 0);
  1611. }
  1612. return 0;
  1613. }
  1614. static int
  1615. rio_close (struct net_device *dev)
  1616. {
  1617. long ioaddr = dev->base_addr;
  1618. struct netdev_private *np = netdev_priv(dev);
  1619. struct sk_buff *skb;
  1620. int i;
  1621. netif_stop_queue (dev);
  1622. /* Disable interrupts */
  1623. writew (0, ioaddr + IntEnable);
  1624. /* Stop Tx and Rx logics */
  1625. writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
  1626. synchronize_irq (dev->irq);
  1627. free_irq (dev->irq, dev);
  1628. del_timer_sync (&np->timer);
  1629. /* Free all the skbuffs in the queue. */
  1630. for (i = 0; i < RX_RING_SIZE; i++) {
  1631. np->rx_ring[i].status = 0;
  1632. np->rx_ring[i].fraginfo = 0;
  1633. skb = np->rx_skbuff[i];
  1634. if (skb) {
  1635. pci_unmap_single (np->pdev, np->rx_ring[i].fraginfo,
  1636. skb->len, PCI_DMA_FROMDEVICE);
  1637. dev_kfree_skb (skb);
  1638. np->rx_skbuff[i] = NULL;
  1639. }
  1640. }
  1641. for (i = 0; i < TX_RING_SIZE; i++) {
  1642. skb = np->tx_skbuff[i];
  1643. if (skb) {
  1644. pci_unmap_single (np->pdev, np->tx_ring[i].fraginfo,
  1645. skb->len, PCI_DMA_TODEVICE);
  1646. dev_kfree_skb (skb);
  1647. np->tx_skbuff[i] = NULL;
  1648. }
  1649. }
  1650. return 0;
  1651. }
  1652. static void __devexit
  1653. rio_remove1 (struct pci_dev *pdev)
  1654. {
  1655. struct net_device *dev = pci_get_drvdata (pdev);
  1656. if (dev) {
  1657. struct netdev_private *np = netdev_priv(dev);
  1658. unregister_netdev (dev);
  1659. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1660. np->rx_ring_dma);
  1661. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1662. np->tx_ring_dma);
  1663. #ifdef MEM_MAPPING
  1664. iounmap ((char *) (dev->base_addr));
  1665. #endif
  1666. free_netdev (dev);
  1667. pci_release_regions (pdev);
  1668. pci_disable_device (pdev);
  1669. }
  1670. pci_set_drvdata (pdev, NULL);
  1671. }
  1672. static struct pci_driver rio_driver = {
  1673. .name = "dl2k",
  1674. .id_table = rio_pci_tbl,
  1675. .probe = rio_probe1,
  1676. .remove = __devexit_p(rio_remove1),
  1677. };
  1678. static int __init
  1679. rio_init (void)
  1680. {
  1681. return pci_module_init (&rio_driver);
  1682. }
  1683. static void __exit
  1684. rio_exit (void)
  1685. {
  1686. pci_unregister_driver (&rio_driver);
  1687. }
  1688. module_init (rio_init);
  1689. module_exit (rio_exit);
  1690. /*
  1691. Compile command:
  1692. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1693. Read Documentation/networking/dl2k.txt for details.
  1694. */