nxt2002.c 16 KB

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  1. /*
  2. Support for B2C2/BBTI Technisat Air2PC - ATSC
  3. Copyright (C) 2004 Taylor Jacob <rtjacob@earthlink.net>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. */
  16. /*
  17. * This driver needs external firmware. Please use the command
  18. * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2002" to
  19. * download/extract it, and then copy it to /usr/lib/hotplug/firmware.
  20. */
  21. #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw"
  22. #define CRC_CCIT_MASK 0x1021
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/moduleparam.h>
  26. #include <linux/device.h>
  27. #include <linux/firmware.h>
  28. #include "dvb_frontend.h"
  29. #include "nxt2002.h"
  30. struct nxt2002_state {
  31. struct i2c_adapter* i2c;
  32. struct dvb_frontend_ops ops;
  33. const struct nxt2002_config* config;
  34. struct dvb_frontend frontend;
  35. /* demodulator private data */
  36. u8 initialised:1;
  37. };
  38. static int debug;
  39. #define dprintk(args...) \
  40. do { \
  41. if (debug) printk(KERN_DEBUG "nxt2002: " args); \
  42. } while (0)
  43. static int i2c_writebytes (struct nxt2002_state* state, u8 reg, u8 *buf, u8 len)
  44. {
  45. /* probbably a much better way or doing this */
  46. u8 buf2 [256],x;
  47. int err;
  48. struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 };
  49. buf2[0] = reg;
  50. for (x = 0 ; x < len ; x++)
  51. buf2[x+1] = buf[x];
  52. if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
  53. printk ("%s: i2c write error (addr %02x, err == %i)\n",
  54. __FUNCTION__, state->config->demod_address, err);
  55. return -EREMOTEIO;
  56. }
  57. return 0;
  58. }
  59. static u8 i2c_readbytes (struct nxt2002_state* state, u8 reg, u8* buf, u8 len)
  60. {
  61. u8 reg2 [] = { reg };
  62. struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 },
  63. { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } };
  64. int err;
  65. if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
  66. printk ("%s: i2c read error (addr %02x, err == %i)\n",
  67. __FUNCTION__, state->config->demod_address, err);
  68. return -EREMOTEIO;
  69. }
  70. return 0;
  71. }
  72. static u16 nxt2002_crc(u16 crc, u8 c)
  73. {
  74. u8 i;
  75. u16 input = (u16) c & 0xFF;
  76. input<<=8;
  77. for(i=0 ;i<8 ;i++) {
  78. if((crc ^ input) & 0x8000)
  79. crc=(crc<<1)^CRC_CCIT_MASK;
  80. else
  81. crc<<=1;
  82. input<<=1;
  83. }
  84. return crc;
  85. }
  86. static int nxt2002_writereg_multibyte (struct nxt2002_state* state, u8 reg, u8* data, u8 len)
  87. {
  88. u8 buf;
  89. dprintk("%s\n", __FUNCTION__);
  90. /* set multi register length */
  91. i2c_writebytes(state,0x34,&len,1);
  92. /* set mutli register register */
  93. i2c_writebytes(state,0x35,&reg,1);
  94. /* send the actual data */
  95. i2c_writebytes(state,0x36,data,len);
  96. /* toggle the multireg write bit*/
  97. buf = 0x02;
  98. i2c_writebytes(state,0x21,&buf,1);
  99. i2c_readbytes(state,0x21,&buf,1);
  100. if ((buf & 0x02) == 0)
  101. return 0;
  102. dprintk("Error writing multireg register %02X\n",reg);
  103. return 0;
  104. }
  105. static int nxt2002_readreg_multibyte (struct nxt2002_state* state, u8 reg, u8* data, u8 len)
  106. {
  107. u8 len2;
  108. dprintk("%s\n", __FUNCTION__);
  109. /* set multi register length */
  110. len2 = len & 0x80;
  111. i2c_writebytes(state,0x34,&len2,1);
  112. /* set mutli register register */
  113. i2c_writebytes(state,0x35,&reg,1);
  114. /* send the actual data */
  115. i2c_readbytes(state,reg,data,len);
  116. return 0;
  117. }
  118. static void nxt2002_microcontroller_stop (struct nxt2002_state* state)
  119. {
  120. u8 buf[2],counter = 0;
  121. dprintk("%s\n", __FUNCTION__);
  122. buf[0] = 0x80;
  123. i2c_writebytes(state,0x22,buf,1);
  124. while (counter < 20) {
  125. i2c_readbytes(state,0x31,buf,1);
  126. if (buf[0] & 0x40)
  127. return;
  128. msleep(10);
  129. counter++;
  130. }
  131. dprintk("Timeout waiting for micro to stop.. This is ok after firmware upload\n");
  132. return;
  133. }
  134. static void nxt2002_microcontroller_start (struct nxt2002_state* state)
  135. {
  136. u8 buf;
  137. dprintk("%s\n", __FUNCTION__);
  138. buf = 0x00;
  139. i2c_writebytes(state,0x22,&buf,1);
  140. }
  141. static int nxt2002_writetuner (struct nxt2002_state* state, u8* data)
  142. {
  143. u8 buf,count = 0;
  144. dprintk("Tuner Bytes: %02X %02X %02X %02X\n",data[0],data[1],data[2],data[3]);
  145. dprintk("%s\n", __FUNCTION__);
  146. /* stop the micro first */
  147. nxt2002_microcontroller_stop(state);
  148. /* set the i2c transfer speed to the tuner */
  149. buf = 0x03;
  150. i2c_writebytes(state,0x20,&buf,1);
  151. /* setup to transfer 4 bytes via i2c */
  152. buf = 0x04;
  153. i2c_writebytes(state,0x34,&buf,1);
  154. /* write actual tuner bytes */
  155. i2c_writebytes(state,0x36,data,4);
  156. /* set tuner i2c address */
  157. buf = 0xC2;
  158. i2c_writebytes(state,0x35,&buf,1);
  159. /* write UC Opmode to begin transfer */
  160. buf = 0x80;
  161. i2c_writebytes(state,0x21,&buf,1);
  162. while (count < 20) {
  163. i2c_readbytes(state,0x21,&buf,1);
  164. if ((buf & 0x80)== 0x00)
  165. return 0;
  166. msleep(100);
  167. count++;
  168. }
  169. printk("nxt2002: timeout error writing tuner\n");
  170. return 0;
  171. }
  172. static void nxt2002_agc_reset(struct nxt2002_state* state)
  173. {
  174. u8 buf;
  175. dprintk("%s\n", __FUNCTION__);
  176. buf = 0x08;
  177. i2c_writebytes(state,0x08,&buf,1);
  178. buf = 0x00;
  179. i2c_writebytes(state,0x08,&buf,1);
  180. return;
  181. }
  182. static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
  183. {
  184. struct nxt2002_state* state = fe->demodulator_priv;
  185. u8 buf[256],written = 0,chunkpos = 0;
  186. u16 rambase,position,crc = 0;
  187. dprintk("%s\n", __FUNCTION__);
  188. dprintk("Firmware is %zu bytes\n",fw->size);
  189. /* Get the RAM base for this nxt2002 */
  190. i2c_readbytes(state,0x10,buf,1);
  191. if (buf[0] & 0x10)
  192. rambase = 0x1000;
  193. else
  194. rambase = 0x0000;
  195. dprintk("rambase on this nxt2002 is %04X\n",rambase);
  196. /* Hold the micro in reset while loading firmware */
  197. buf[0] = 0x80;
  198. i2c_writebytes(state,0x2B,buf,1);
  199. for (position = 0; position < fw->size ; position++) {
  200. if (written == 0) {
  201. crc = 0;
  202. chunkpos = 0x28;
  203. buf[0] = ((rambase + position) >> 8);
  204. buf[1] = (rambase + position) & 0xFF;
  205. buf[2] = 0x81;
  206. /* write starting address */
  207. i2c_writebytes(state,0x29,buf,3);
  208. }
  209. written++;
  210. chunkpos++;
  211. if ((written % 4) == 0)
  212. i2c_writebytes(state,chunkpos,&fw->data[position-3],4);
  213. crc = nxt2002_crc(crc,fw->data[position]);
  214. if ((written == 255) || (position+1 == fw->size)) {
  215. /* write remaining bytes of firmware */
  216. i2c_writebytes(state, chunkpos+4-(written %4),
  217. &fw->data[position-(written %4) + 1],
  218. written %4);
  219. buf[0] = crc << 8;
  220. buf[1] = crc & 0xFF;
  221. /* write crc */
  222. i2c_writebytes(state,0x2C,buf,2);
  223. /* do a read to stop things */
  224. i2c_readbytes(state,0x2A,buf,1);
  225. /* set transfer mode to complete */
  226. buf[0] = 0x80;
  227. i2c_writebytes(state,0x2B,buf,1);
  228. written = 0;
  229. }
  230. }
  231. printk ("done.\n");
  232. return 0;
  233. };
  234. static int nxt2002_setup_frontend_parameters (struct dvb_frontend* fe,
  235. struct dvb_frontend_parameters *p)
  236. {
  237. struct nxt2002_state* state = fe->demodulator_priv;
  238. u32 freq = 0;
  239. u16 tunerfreq = 0;
  240. u8 buf[4];
  241. freq = 44000 + ( p->frequency / 1000 );
  242. dprintk("freq = %d p->frequency = %d\n",freq,p->frequency);
  243. tunerfreq = freq * 24/4000;
  244. buf[0] = (tunerfreq >> 8) & 0x7F;
  245. buf[1] = (tunerfreq & 0xFF);
  246. if (p->frequency <= 214000000) {
  247. buf[2] = 0x84 + (0x06 << 3);
  248. buf[3] = (p->frequency <= 172000000) ? 0x01 : 0x02;
  249. } else if (p->frequency <= 721000000) {
  250. buf[2] = 0x84 + (0x07 << 3);
  251. buf[3] = (p->frequency <= 467000000) ? 0x02 : 0x08;
  252. } else if (p->frequency <= 841000000) {
  253. buf[2] = 0x84 + (0x0E << 3);
  254. buf[3] = 0x08;
  255. } else {
  256. buf[2] = 0x84 + (0x0F << 3);
  257. buf[3] = 0x02;
  258. }
  259. /* write frequency information */
  260. nxt2002_writetuner(state,buf);
  261. /* reset the agc now that tuning has been completed */
  262. nxt2002_agc_reset(state);
  263. /* set target power level */
  264. switch (p->u.vsb.modulation) {
  265. case QAM_64:
  266. case QAM_256:
  267. buf[0] = 0x74;
  268. break;
  269. case VSB_8:
  270. buf[0] = 0x70;
  271. break;
  272. default:
  273. return -EINVAL;
  274. break;
  275. }
  276. i2c_writebytes(state,0x42,buf,1);
  277. /* configure sdm */
  278. buf[0] = 0x87;
  279. i2c_writebytes(state,0x57,buf,1);
  280. /* write sdm1 input */
  281. buf[0] = 0x10;
  282. buf[1] = 0x00;
  283. nxt2002_writereg_multibyte(state,0x58,buf,2);
  284. /* write sdmx input */
  285. switch (p->u.vsb.modulation) {
  286. case QAM_64:
  287. buf[0] = 0x68;
  288. break;
  289. case QAM_256:
  290. buf[0] = 0x64;
  291. break;
  292. case VSB_8:
  293. buf[0] = 0x60;
  294. break;
  295. default:
  296. return -EINVAL;
  297. break;
  298. }
  299. buf[1] = 0x00;
  300. nxt2002_writereg_multibyte(state,0x5C,buf,2);
  301. /* write adc power lpf fc */
  302. buf[0] = 0x05;
  303. i2c_writebytes(state,0x43,buf,1);
  304. /* write adc power lpf fc */
  305. buf[0] = 0x05;
  306. i2c_writebytes(state,0x43,buf,1);
  307. /* write accumulator2 input */
  308. buf[0] = 0x80;
  309. buf[1] = 0x00;
  310. nxt2002_writereg_multibyte(state,0x4B,buf,2);
  311. /* write kg1 */
  312. buf[0] = 0x00;
  313. i2c_writebytes(state,0x4D,buf,1);
  314. /* write sdm12 lpf fc */
  315. buf[0] = 0x44;
  316. i2c_writebytes(state,0x55,buf,1);
  317. /* write agc control reg */
  318. buf[0] = 0x04;
  319. i2c_writebytes(state,0x41,buf,1);
  320. /* write agc ucgp0 */
  321. switch (p->u.vsb.modulation) {
  322. case QAM_64:
  323. buf[0] = 0x02;
  324. break;
  325. case QAM_256:
  326. buf[0] = 0x03;
  327. break;
  328. case VSB_8:
  329. buf[0] = 0x00;
  330. break;
  331. default:
  332. return -EINVAL;
  333. break;
  334. }
  335. i2c_writebytes(state,0x30,buf,1);
  336. /* write agc control reg */
  337. buf[0] = 0x00;
  338. i2c_writebytes(state,0x41,buf,1);
  339. /* write accumulator2 input */
  340. buf[0] = 0x80;
  341. buf[1] = 0x00;
  342. nxt2002_writereg_multibyte(state,0x49,buf,2);
  343. nxt2002_writereg_multibyte(state,0x4B,buf,2);
  344. /* write agc control reg */
  345. buf[0] = 0x04;
  346. i2c_writebytes(state,0x41,buf,1);
  347. nxt2002_microcontroller_start(state);
  348. /* adjacent channel detection should be done here, but I don't
  349. have any stations with this need so I cannot test it */
  350. return 0;
  351. }
  352. static int nxt2002_read_status(struct dvb_frontend* fe, fe_status_t* status)
  353. {
  354. struct nxt2002_state* state = fe->demodulator_priv;
  355. u8 lock;
  356. i2c_readbytes(state,0x31,&lock,1);
  357. *status = 0;
  358. if (lock & 0x20) {
  359. *status |= FE_HAS_SIGNAL;
  360. *status |= FE_HAS_CARRIER;
  361. *status |= FE_HAS_VITERBI;
  362. *status |= FE_HAS_SYNC;
  363. *status |= FE_HAS_LOCK;
  364. }
  365. return 0;
  366. }
  367. static int nxt2002_read_ber(struct dvb_frontend* fe, u32* ber)
  368. {
  369. struct nxt2002_state* state = fe->demodulator_priv;
  370. u8 b[3];
  371. nxt2002_readreg_multibyte(state,0xE6,b,3);
  372. *ber = ((b[0] << 8) + b[1]) * 8;
  373. return 0;
  374. }
  375. static int nxt2002_read_signal_strength(struct dvb_frontend* fe, u16* strength)
  376. {
  377. struct nxt2002_state* state = fe->demodulator_priv;
  378. u8 b[2];
  379. u16 temp = 0;
  380. /* setup to read cluster variance */
  381. b[0] = 0x00;
  382. i2c_writebytes(state,0xA1,b,1);
  383. /* get multreg val */
  384. nxt2002_readreg_multibyte(state,0xA6,b,2);
  385. temp = (b[0] << 8) | b[1];
  386. *strength = ((0x7FFF - temp) & 0x0FFF) * 16;
  387. return 0;
  388. }
  389. static int nxt2002_read_snr(struct dvb_frontend* fe, u16* snr)
  390. {
  391. struct nxt2002_state* state = fe->demodulator_priv;
  392. u8 b[2];
  393. u16 temp = 0, temp2;
  394. u32 snrdb = 0;
  395. /* setup to read cluster variance */
  396. b[0] = 0x00;
  397. i2c_writebytes(state,0xA1,b,1);
  398. /* get multreg val from 0xA6 */
  399. nxt2002_readreg_multibyte(state,0xA6,b,2);
  400. temp = (b[0] << 8) | b[1];
  401. temp2 = 0x7FFF - temp;
  402. /* snr will be in db */
  403. if (temp2 > 0x7F00)
  404. snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) );
  405. else if (temp2 > 0x7EC0)
  406. snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) );
  407. else if (temp2 > 0x7C00)
  408. snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) );
  409. else
  410. snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) );
  411. /* the value reported back from the frontend will be FFFF=32db 0000=0db */
  412. *snr = snrdb * (0xFFFF/32000);
  413. return 0;
  414. }
  415. static int nxt2002_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
  416. {
  417. struct nxt2002_state* state = fe->demodulator_priv;
  418. u8 b[3];
  419. nxt2002_readreg_multibyte(state,0xE6,b,3);
  420. *ucblocks = b[2];
  421. return 0;
  422. }
  423. static int nxt2002_sleep(struct dvb_frontend* fe)
  424. {
  425. return 0;
  426. }
  427. static int nxt2002_init(struct dvb_frontend* fe)
  428. {
  429. struct nxt2002_state* state = fe->demodulator_priv;
  430. const struct firmware *fw;
  431. int ret;
  432. u8 buf[2];
  433. if (!state->initialised) {
  434. /* request the firmware, this will block until someone uploads it */
  435. printk("nxt2002: Waiting for firmware upload (%s)...\n", NXT2002_DEFAULT_FIRMWARE);
  436. ret = state->config->request_firmware(fe, &fw, NXT2002_DEFAULT_FIRMWARE);
  437. printk("nxt2002: Waiting for firmware upload(2)...\n");
  438. if (ret) {
  439. printk("nxt2002: no firmware upload (timeout or file not found?)\n");
  440. return ret;
  441. }
  442. ret = nxt2002_load_firmware(fe, fw);
  443. if (ret) {
  444. printk("nxt2002: writing firmware to device failed\n");
  445. release_firmware(fw);
  446. return ret;
  447. }
  448. printk("nxt2002: firmware upload complete\n");
  449. /* Put the micro into reset */
  450. nxt2002_microcontroller_stop(state);
  451. /* ensure transfer is complete */
  452. buf[0]=0;
  453. i2c_writebytes(state,0x2B,buf,1);
  454. /* Put the micro into reset for real this time */
  455. nxt2002_microcontroller_stop(state);
  456. /* soft reset everything (agc,frontend,eq,fec)*/
  457. buf[0] = 0x0F;
  458. i2c_writebytes(state,0x08,buf,1);
  459. buf[0] = 0x00;
  460. i2c_writebytes(state,0x08,buf,1);
  461. /* write agc sdm configure */
  462. buf[0] = 0xF1;
  463. i2c_writebytes(state,0x57,buf,1);
  464. /* write mod output format */
  465. buf[0] = 0x20;
  466. i2c_writebytes(state,0x09,buf,1);
  467. /* write fec mpeg mode */
  468. buf[0] = 0x7E;
  469. buf[1] = 0x00;
  470. i2c_writebytes(state,0xE9,buf,2);
  471. /* write mux selection */
  472. buf[0] = 0x00;
  473. i2c_writebytes(state,0xCC,buf,1);
  474. state->initialised = 1;
  475. }
  476. return 0;
  477. }
  478. static int nxt2002_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
  479. {
  480. fesettings->min_delay_ms = 500;
  481. fesettings->step_size = 0;
  482. fesettings->max_drift = 0;
  483. return 0;
  484. }
  485. static void nxt2002_release(struct dvb_frontend* fe)
  486. {
  487. struct nxt2002_state* state = fe->demodulator_priv;
  488. kfree(state);
  489. }
  490. static struct dvb_frontend_ops nxt2002_ops;
  491. struct dvb_frontend* nxt2002_attach(const struct nxt2002_config* config,
  492. struct i2c_adapter* i2c)
  493. {
  494. struct nxt2002_state* state = NULL;
  495. u8 buf [] = {0,0,0,0,0};
  496. /* allocate memory for the internal state */
  497. state = kmalloc(sizeof(struct nxt2002_state), GFP_KERNEL);
  498. if (state == NULL) goto error;
  499. /* setup the state */
  500. state->config = config;
  501. state->i2c = i2c;
  502. memcpy(&state->ops, &nxt2002_ops, sizeof(struct dvb_frontend_ops));
  503. state->initialised = 0;
  504. /* Check the first 5 registers to ensure this a revision we can handle */
  505. i2c_readbytes(state, 0x00, buf, 5);
  506. if (buf[0] != 0x04) goto error; /* device id */
  507. if (buf[1] != 0x02) goto error; /* fab id */
  508. if (buf[2] != 0x11) goto error; /* month */
  509. if (buf[3] != 0x20) goto error; /* year msb */
  510. if (buf[4] != 0x00) goto error; /* year lsb */
  511. /* create dvb_frontend */
  512. state->frontend.ops = &state->ops;
  513. state->frontend.demodulator_priv = state;
  514. return &state->frontend;
  515. error:
  516. kfree(state);
  517. return NULL;
  518. }
  519. static struct dvb_frontend_ops nxt2002_ops = {
  520. .info = {
  521. .name = "Nextwave nxt2002 VSB/QAM frontend",
  522. .type = FE_ATSC,
  523. .frequency_min = 54000000,
  524. .frequency_max = 860000000,
  525. /* stepsize is just a guess */
  526. .frequency_stepsize = 166666,
  527. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  528. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  529. FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256
  530. },
  531. .release = nxt2002_release,
  532. .init = nxt2002_init,
  533. .sleep = nxt2002_sleep,
  534. .set_frontend = nxt2002_setup_frontend_parameters,
  535. .get_tune_settings = nxt2002_get_tune_settings,
  536. .read_status = nxt2002_read_status,
  537. .read_ber = nxt2002_read_ber,
  538. .read_signal_strength = nxt2002_read_signal_strength,
  539. .read_snr = nxt2002_read_snr,
  540. .read_ucblocks = nxt2002_read_ucblocks,
  541. };
  542. module_param(debug, int, 0644);
  543. MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  544. MODULE_DESCRIPTION("NXT2002 ATSC (8VSB & ITU J83 AnnexB FEC QAM64/256) demodulator driver");
  545. MODULE_AUTHOR("Taylor Jacob");
  546. MODULE_LICENSE("GPL");
  547. EXPORT_SYMBOL(nxt2002_attach);