enternow_pci.c 12 KB

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  1. /* enternow_pci.c,v 0.99 2001/10/02
  2. *
  3. * enternow_pci.c Card-specific routines for
  4. * Formula-n enter:now ISDN PCI ab
  5. * Gerdes AG Power ISDN PCI
  6. * Woerltronic SA 16 PCI
  7. * (based on HiSax driver by Karsten Keil)
  8. *
  9. * Author Christoph Ersfeld <info@formula-n.de>
  10. * Formula-n Europe AG (www.formula-n.com)
  11. * previously Gerdes AG
  12. *
  13. *
  14. * This file is (c) under GNU PUBLIC LICENSE
  15. *
  16. * Notes:
  17. * This driver interfaces to netjet.c which performs B-channel
  18. * processing.
  19. *
  20. * Version 0.99 is the first release of this driver and there are
  21. * certainly a few bugs.
  22. * It isn't testet on linux 2.4 yet, so consider this code to be
  23. * beta.
  24. *
  25. * Please don't report me any malfunction without sending
  26. * (compressed) debug-logs.
  27. * It would be nearly impossible to retrace it.
  28. *
  29. * Log D-channel-processing as follows:
  30. *
  31. * 1. Load hisax with card-specific parameters, this example ist for
  32. * Formula-n enter:now ISDN PCI and compatible
  33. * (f.e. Gerdes Power ISDN PCI)
  34. *
  35. * modprobe hisax type=41 protocol=2 id=gerdes
  36. *
  37. * if you chose an other value for id, you need to modify the
  38. * code below, too.
  39. *
  40. * 2. set debug-level
  41. *
  42. * hisaxctrl gerdes 1 0x3ff
  43. * hisaxctrl gerdes 11 0x4f
  44. * cat /dev/isdnctrl >> ~/log &
  45. *
  46. * Please take also a look into /var/log/messages if there is
  47. * anything importand concerning HISAX.
  48. *
  49. *
  50. * Credits:
  51. * Programming the driver for Formula-n enter:now ISDN PCI and
  52. * necessary the driver for the used Amd 7930 D-channel-controller
  53. * was spnsored by Formula-n Europe AG.
  54. * Thanks to Karsten Keil and Petr Novak, who gave me support in
  55. * Hisax-specific questions.
  56. * I want so say special thanks to Carl-Friedrich Braun, who had to
  57. * answer a lot of questions about generally ISDN and about handling
  58. * of the Amd-Chip.
  59. *
  60. */
  61. #include <linux/config.h>
  62. #include "hisax.h"
  63. #include "isac.h"
  64. #include "isdnl1.h"
  65. #include "amd7930_fn.h"
  66. #include <linux/interrupt.h>
  67. #include <linux/ppp_defs.h>
  68. #include <linux/pci.h>
  69. #include <linux/init.h>
  70. #include "netjet.h"
  71. static const char *enternow_pci_rev = "$Revision: 1.1.4.5 $";
  72. /* für PowerISDN PCI */
  73. #define TJ_AMD_IRQ 0x20
  74. #define TJ_LED1 0x40
  75. #define TJ_LED2 0x80
  76. /* Das Fenster zum AMD...
  77. * Ab Adresse hw.njet.base + TJ_AMD_PORT werden vom AMD jeweils 8 Bit in
  78. * den TigerJet i/o-Raum gemappt
  79. * -> 0x01 des AMD bei hw.njet.base + 0C4 */
  80. #define TJ_AMD_PORT 0xC0
  81. /* *************************** I/O-Interface functions ************************************* */
  82. /* cs->readisac, macro rByteAMD */
  83. static unsigned char
  84. ReadByteAmd7930(struct IsdnCardState *cs, unsigned char offset)
  85. {
  86. /* direktes Register */
  87. if(offset < 8)
  88. return (inb(cs->hw.njet.isac + 4*offset));
  89. /* indirektes Register */
  90. else {
  91. outb(offset, cs->hw.njet.isac + 4*AMD_CR);
  92. return(inb(cs->hw.njet.isac + 4*AMD_DR));
  93. }
  94. }
  95. /* cs->writeisac, macro wByteAMD */
  96. static void
  97. WriteByteAmd7930(struct IsdnCardState *cs, unsigned char offset, unsigned char value)
  98. {
  99. /* direktes Register */
  100. if(offset < 8)
  101. outb(value, cs->hw.njet.isac + 4*offset);
  102. /* indirektes Register */
  103. else {
  104. outb(offset, cs->hw.njet.isac + 4*AMD_CR);
  105. outb(value, cs->hw.njet.isac + 4*AMD_DR);
  106. }
  107. }
  108. static void
  109. enpci_setIrqMask(struct IsdnCardState *cs, unsigned char val) {
  110. if (!val)
  111. outb(0x00, cs->hw.njet.base+NETJET_IRQMASK1);
  112. else
  113. outb(TJ_AMD_IRQ, cs->hw.njet.base+NETJET_IRQMASK1);
  114. }
  115. static unsigned char dummyrr(struct IsdnCardState *cs, int chan, unsigned char off)
  116. {
  117. return(5);
  118. }
  119. static void dummywr(struct IsdnCardState *cs, int chan, unsigned char off, unsigned char value)
  120. {
  121. }
  122. /* ******************************************************************************** */
  123. static void
  124. reset_enpci(struct IsdnCardState *cs)
  125. {
  126. if (cs->debug & L1_DEB_ISAC)
  127. debugl1(cs, "enter:now PCI: reset");
  128. /* Reset on, (also for AMD) */
  129. cs->hw.njet.ctrl_reg = 0x07;
  130. outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
  131. mdelay(20);
  132. /* Reset off */
  133. cs->hw.njet.ctrl_reg = 0x30;
  134. outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
  135. /* 20ms delay */
  136. mdelay(20);
  137. cs->hw.njet.auxd = 0; // LED-status
  138. cs->hw.njet.dmactrl = 0;
  139. outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL);
  140. outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1);
  141. outb(cs->hw.njet.auxd, cs->hw.njet.auxa); // LED off
  142. }
  143. static int
  144. enpci_card_msg(struct IsdnCardState *cs, int mt, void *arg)
  145. {
  146. u_long flags;
  147. unsigned char *chan;
  148. if (cs->debug & L1_DEB_ISAC)
  149. debugl1(cs, "enter:now PCI: card_msg: 0x%04X", mt);
  150. switch (mt) {
  151. case CARD_RESET:
  152. spin_lock_irqsave(&cs->lock, flags);
  153. reset_enpci(cs);
  154. Amd7930_init(cs);
  155. spin_unlock_irqrestore(&cs->lock, flags);
  156. break;
  157. case CARD_RELEASE:
  158. release_io_netjet(cs);
  159. break;
  160. case CARD_INIT:
  161. reset_enpci(cs);
  162. inittiger(cs);
  163. /* irq must be on here */
  164. Amd7930_init(cs);
  165. break;
  166. case CARD_TEST:
  167. break;
  168. case MDL_ASSIGN:
  169. /* TEI assigned, LED1 on */
  170. cs->hw.njet.auxd = TJ_AMD_IRQ << 1;
  171. outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA);
  172. break;
  173. case MDL_REMOVE:
  174. /* TEI removed, LEDs off */
  175. cs->hw.njet.auxd = 0;
  176. outb(0x00, cs->hw.njet.base + NETJET_AUXDATA);
  177. break;
  178. case MDL_BC_ASSIGN:
  179. /* activate B-channel */
  180. chan = (unsigned char *)arg;
  181. if (cs->debug & L1_DEB_ISAC)
  182. debugl1(cs, "enter:now PCI: assign phys. BC %d in AMD LMR1", *chan);
  183. cs->dc.amd7930.ph_command(cs, (cs->dc.amd7930.lmr1 | (*chan + 1)), "MDL_BC_ASSIGN");
  184. /* at least one b-channel in use, LED 2 on */
  185. cs->hw.njet.auxd |= TJ_AMD_IRQ << 2;
  186. outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA);
  187. break;
  188. case MDL_BC_RELEASE:
  189. /* deactivate B-channel */
  190. chan = (unsigned char *)arg;
  191. if (cs->debug & L1_DEB_ISAC)
  192. debugl1(cs, "enter:now PCI: release phys. BC %d in Amd LMR1", *chan);
  193. cs->dc.amd7930.ph_command(cs, (cs->dc.amd7930.lmr1 & ~(*chan + 1)), "MDL_BC_RELEASE");
  194. /* no b-channel active -> LED2 off */
  195. if (!(cs->dc.amd7930.lmr1 & 3)) {
  196. cs->hw.njet.auxd &= ~(TJ_AMD_IRQ << 2);
  197. outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA);
  198. }
  199. break;
  200. default:
  201. break;
  202. }
  203. return(0);
  204. }
  205. static irqreturn_t
  206. enpci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
  207. {
  208. struct IsdnCardState *cs = dev_id;
  209. unsigned char s0val, s1val, ir;
  210. u_long flags;
  211. spin_lock_irqsave(&cs->lock, flags);
  212. s1val = inb(cs->hw.njet.base + NETJET_IRQSTAT1);
  213. /* AMD threw an interrupt */
  214. if (!(s1val & TJ_AMD_IRQ)) {
  215. /* read and clear interrupt-register */
  216. ir = ReadByteAmd7930(cs, 0x00);
  217. Amd7930_interrupt(cs, ir);
  218. s1val = 1;
  219. } else
  220. s1val = 0;
  221. s0val = inb(cs->hw.njet.base + NETJET_IRQSTAT0);
  222. if ((s0val | s1val)==0) { // shared IRQ
  223. spin_unlock_irqrestore(&cs->lock, flags);
  224. return IRQ_NONE;
  225. }
  226. if (s0val)
  227. outb(s0val, cs->hw.njet.base + NETJET_IRQSTAT0);
  228. /* DMA-Interrupt: B-channel-stuff */
  229. /* set bits in sval to indicate which page is free */
  230. if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) <
  231. inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ))
  232. /* the 2nd write page is free */
  233. s0val = 0x08;
  234. else /* the 1st write page is free */
  235. s0val = 0x04;
  236. if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) <
  237. inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ))
  238. /* the 2nd read page is free */
  239. s0val = s0val | 0x02;
  240. else /* the 1st read page is free */
  241. s0val = s0val | 0x01;
  242. if (s0val != cs->hw.njet.last_is0) /* we have a DMA interrupt */
  243. {
  244. if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  245. spin_unlock_irqrestore(&cs->lock, flags);
  246. return IRQ_HANDLED;
  247. }
  248. cs->hw.njet.irqstat0 = s0val;
  249. if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) !=
  250. (cs->hw.njet.last_is0 & NETJET_IRQM0_READ))
  251. /* we have a read dma int */
  252. read_tiger(cs);
  253. if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) !=
  254. (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE))
  255. /* we have a write dma int */
  256. write_tiger(cs);
  257. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  258. }
  259. spin_unlock_irqrestore(&cs->lock, flags);
  260. return IRQ_HANDLED;
  261. }
  262. static struct pci_dev *dev_netjet __initdata = NULL;
  263. /* called by config.c */
  264. int __init
  265. setup_enternow_pci(struct IsdnCard *card)
  266. {
  267. int bytecnt;
  268. struct IsdnCardState *cs = card->cs;
  269. char tmp[64];
  270. #ifdef CONFIG_PCI
  271. #ifdef __BIG_ENDIAN
  272. #error "not running on big endian machines now"
  273. #endif
  274. strcpy(tmp, enternow_pci_rev);
  275. printk(KERN_INFO "HiSax: Formula-n Europe AG enter:now ISDN PCI driver Rev. %s\n", HiSax_getrev(tmp));
  276. if (cs->typ != ISDN_CTYPE_ENTERNOW)
  277. return(0);
  278. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  279. for ( ;; )
  280. {
  281. if ((dev_netjet = pci_find_device(PCI_VENDOR_ID_TIGERJET,
  282. PCI_DEVICE_ID_TIGERJET_300, dev_netjet))) {
  283. if (pci_enable_device(dev_netjet))
  284. return(0);
  285. cs->irq = dev_netjet->irq;
  286. if (!cs->irq) {
  287. printk(KERN_WARNING "enter:now PCI: No IRQ for PCI card found\n");
  288. return(0);
  289. }
  290. cs->hw.njet.base = pci_resource_start(dev_netjet, 0);
  291. if (!cs->hw.njet.base) {
  292. printk(KERN_WARNING "enter:now PCI: No IO-Adr for PCI card found\n");
  293. return(0);
  294. }
  295. /* checks Sub-Vendor ID because system crashes with Traverse-Card */
  296. if ((dev_netjet->subsystem_vendor != 0x55) ||
  297. (dev_netjet->subsystem_device != 0x02)) {
  298. printk(KERN_WARNING "enter:now: You tried to load this driver with an incompatible TigerJet-card\n");
  299. printk(KERN_WARNING "Use type=20 for Traverse NetJet PCI Card.\n");
  300. return(0);
  301. }
  302. } else {
  303. printk(KERN_WARNING "enter:now PCI: No PCI card found\n");
  304. return(0);
  305. }
  306. cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA;
  307. cs->hw.njet.isac = cs->hw.njet.base + 0xC0; // Fenster zum AMD
  308. /* Reset an */
  309. cs->hw.njet.ctrl_reg = 0x07; // geändert von 0xff
  310. outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
  311. /* 20 ms Pause */
  312. mdelay(20);
  313. cs->hw.njet.ctrl_reg = 0x30; /* Reset Off and status read clear */
  314. outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
  315. mdelay(10);
  316. cs->hw.njet.auxd = 0x00; // war 0xc0
  317. cs->hw.njet.dmactrl = 0;
  318. outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL);
  319. outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1);
  320. outb(cs->hw.njet.auxd, cs->hw.njet.auxa);
  321. break;
  322. }
  323. #else
  324. printk(KERN_WARNING "enter:now PCI: NO_PCI_BIOS\n");
  325. printk(KERN_WARNING "enter:now PCI: unable to config Formula-n enter:now ISDN PCI ab\n");
  326. return (0);
  327. #endif /* CONFIG_PCI */
  328. bytecnt = 256;
  329. printk(KERN_INFO
  330. "enter:now PCI: PCI card configured at 0x%lx IRQ %d\n",
  331. cs->hw.njet.base, cs->irq);
  332. if (!request_region(cs->hw.njet.base, bytecnt, "Fn_ISDN")) {
  333. printk(KERN_WARNING
  334. "HiSax: %s config port %lx-%lx already in use\n",
  335. CardType[card->typ],
  336. cs->hw.njet.base,
  337. cs->hw.njet.base + bytecnt);
  338. return (0);
  339. }
  340. setup_Amd7930(cs);
  341. cs->hw.njet.last_is0 = 0;
  342. /* macro rByteAMD */
  343. cs->readisac = &ReadByteAmd7930;
  344. /* macro wByteAMD */
  345. cs->writeisac = &WriteByteAmd7930;
  346. cs->dc.amd7930.setIrqMask = &enpci_setIrqMask;
  347. cs->BC_Read_Reg = &dummyrr;
  348. cs->BC_Write_Reg = &dummywr;
  349. cs->BC_Send_Data = &netjet_fill_dma;
  350. cs->cardmsg = &enpci_card_msg;
  351. cs->irq_func = &enpci_interrupt;
  352. cs->irq_flags |= SA_SHIRQ;
  353. return (1);
  354. }