maceps2.c 4.9 KB

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  1. /*
  2. * SGI O2 MACE PS2 controller driver for linux
  3. *
  4. * Copyright (C) 2002 Vivien Chappelier
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/serio.h>
  13. #include <linux/errno.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/ioport.h>
  16. #include <linux/delay.h>
  17. #include <linux/device.h>
  18. #include <linux/slab.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/err.h>
  21. #include <asm/io.h>
  22. #include <asm/irq.h>
  23. #include <asm/system.h>
  24. #include <asm/ip32/mace.h>
  25. #include <asm/ip32/ip32_ints.h>
  26. MODULE_AUTHOR("Vivien Chappelier <vivien.chappelier@linux-mips.org");
  27. MODULE_DESCRIPTION("SGI O2 MACE PS2 controller driver");
  28. MODULE_LICENSE("GPL");
  29. #define MACE_PS2_TIMEOUT 10000 /* in 50us unit */
  30. #define PS2_STATUS_CLOCK_SIGNAL BIT(0) /* external clock signal */
  31. #define PS2_STATUS_CLOCK_INHIBIT BIT(1) /* clken output signal */
  32. #define PS2_STATUS_TX_INPROGRESS BIT(2) /* transmission in progress */
  33. #define PS2_STATUS_TX_EMPTY BIT(3) /* empty transmit buffer */
  34. #define PS2_STATUS_RX_FULL BIT(4) /* full receive buffer */
  35. #define PS2_STATUS_RX_INPROGRESS BIT(5) /* reception in progress */
  36. #define PS2_STATUS_ERROR_PARITY BIT(6) /* parity error */
  37. #define PS2_STATUS_ERROR_FRAMING BIT(7) /* framing error */
  38. #define PS2_CONTROL_TX_CLOCK_DISABLE BIT(0) /* inhibit clock signal after TX */
  39. #define PS2_CONTROL_TX_ENABLE BIT(1) /* transmit enable */
  40. #define PS2_CONTROL_TX_INT_ENABLE BIT(2) /* enable transmit interrupt */
  41. #define PS2_CONTROL_RX_INT_ENABLE BIT(3) /* enable receive interrupt */
  42. #define PS2_CONTROL_RX_CLOCK_ENABLE BIT(4) /* pause reception if set to 0 */
  43. #define PS2_CONTROL_RESET BIT(5) /* reset */
  44. struct maceps2_data {
  45. struct mace_ps2port *port;
  46. int irq;
  47. };
  48. static struct maceps2_data port_data[2];
  49. static struct serio *maceps2_port[2];
  50. static struct platform_device *maceps2_device;
  51. static int maceps2_write(struct serio *dev, unsigned char val)
  52. {
  53. struct mace_ps2port *port = ((struct maceps2_data *)dev->port_data)->port;
  54. unsigned int timeout = MACE_PS2_TIMEOUT;
  55. do {
  56. if (port->status & PS2_STATUS_TX_EMPTY) {
  57. port->tx = val;
  58. return 0;
  59. }
  60. udelay(50);
  61. } while (timeout--);
  62. return -1;
  63. }
  64. static irqreturn_t maceps2_interrupt(int irq, void *dev_id,
  65. struct pt_regs *regs)
  66. {
  67. struct serio *dev = dev_id;
  68. struct mace_ps2port *port = ((struct maceps2_data *)dev->port_data)->port;
  69. unsigned long byte;
  70. if (port->status & PS2_STATUS_RX_FULL) {
  71. byte = port->rx;
  72. serio_interrupt(dev, byte & 0xff, 0, regs);
  73. }
  74. return IRQ_HANDLED;
  75. }
  76. static int maceps2_open(struct serio *dev)
  77. {
  78. struct maceps2_data *data = (struct maceps2_data *)dev->port_data;
  79. if (request_irq(data->irq, maceps2_interrupt, 0, "PS2 port", dev)) {
  80. printk(KERN_ERR "Could not allocate PS/2 IRQ\n");
  81. return -EBUSY;
  82. }
  83. /* Reset port */
  84. data->port->control = PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET;
  85. udelay(100);
  86. /* Enable interrupts */
  87. data->port->control = PS2_CONTROL_RX_CLOCK_ENABLE |
  88. PS2_CONTROL_TX_ENABLE |
  89. PS2_CONTROL_RX_INT_ENABLE;
  90. return 0;
  91. }
  92. static void maceps2_close(struct serio *dev)
  93. {
  94. struct maceps2_data *data = (struct maceps2_data *)dev->port_data;
  95. data->port->control = PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET;
  96. udelay(100);
  97. free_irq(data->irq, dev);
  98. }
  99. static struct serio * __init maceps2_allocate_port(int idx)
  100. {
  101. struct serio *serio;
  102. serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
  103. if (serio) {
  104. memset(serio, 0, sizeof(struct serio));
  105. serio->id.type = SERIO_8042;
  106. serio->write = maceps2_write;
  107. serio->open = maceps2_open;
  108. serio->close = maceps2_close;
  109. snprintf(serio->name, sizeof(serio->name), "MACE PS/2 port%d", idx);
  110. snprintf(serio->phys, sizeof(serio->phys), "mace/serio%d", idx);
  111. serio->port_data = &port_data[idx];
  112. serio->dev.parent = &maceps2_device->dev;
  113. }
  114. return serio;
  115. }
  116. static int __init maceps2_init(void)
  117. {
  118. maceps2_device = platform_device_register_simple("maceps2", -1, NULL, 0);
  119. if (IS_ERR(maceps2_device))
  120. return PTR_ERR(maceps2_device);
  121. port_data[0].port = &mace->perif.ps2.keyb;
  122. port_data[0].irq = MACEISA_KEYB_IRQ;
  123. port_data[1].port = &mace->perif.ps2.mouse;
  124. port_data[1].irq = MACEISA_MOUSE_IRQ;
  125. maceps2_port[0] = maceps2_allocate_port(0);
  126. maceps2_port[1] = maceps2_allocate_port(1);
  127. if (!maceps2_port[0] || !maceps2_port[1]) {
  128. kfree(maceps2_port[0]);
  129. kfree(maceps2_port[1]);
  130. platform_device_unregister(maceps2_device);
  131. return -ENOMEM;
  132. }
  133. serio_register_port(maceps2_port[0]);
  134. serio_register_port(maceps2_port[1]);
  135. return 0;
  136. }
  137. static void __exit maceps2_exit(void)
  138. {
  139. serio_unregister_port(maceps2_port[0]);
  140. serio_unregister_port(maceps2_port[1]);
  141. platform_device_unregister(maceps2_device);
  142. }
  143. module_init(maceps2_init);
  144. module_exit(maceps2_exit);