mthca_main.c 32 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_PCI_MSI
  52. static int msi_x = 0;
  53. module_param(msi_x, int, 0444);
  54. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  55. static int msi = 0;
  56. module_param(msi, int, 0444);
  57. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #define msi (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static const char mthca_version[] __devinitdata =
  63. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  64. DRV_VERSION " (" DRV_RELDATE ")\n";
  65. static struct mthca_profile default_profile = {
  66. .num_qp = 1 << 16,
  67. .rdb_per_qp = 4,
  68. .num_cq = 1 << 16,
  69. .num_mcg = 1 << 13,
  70. .num_mpt = 1 << 17,
  71. .num_mtt = 1 << 20,
  72. .num_udav = 1 << 15, /* Tavor only */
  73. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  74. .uarc_size = 1 << 18, /* Arbel only */
  75. };
  76. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  77. {
  78. int cap;
  79. u16 val;
  80. /* First try to max out Read Byte Count */
  81. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  82. if (cap) {
  83. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  84. mthca_err(mdev, "Couldn't read PCI-X command register, "
  85. "aborting.\n");
  86. return -ENODEV;
  87. }
  88. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  89. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  90. mthca_err(mdev, "Couldn't write PCI-X command register, "
  91. "aborting.\n");
  92. return -ENODEV;
  93. }
  94. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  95. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  96. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  97. if (cap) {
  98. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  99. mthca_err(mdev, "Couldn't read PCI Express device control "
  100. "register, aborting.\n");
  101. return -ENODEV;
  102. }
  103. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  104. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  105. mthca_err(mdev, "Couldn't write PCI Express device control "
  106. "register, aborting.\n");
  107. return -ENODEV;
  108. }
  109. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  110. mthca_info(mdev, "No PCI Express capability, "
  111. "not setting Max Read Request Size.\n");
  112. return 0;
  113. }
  114. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  115. {
  116. int err;
  117. u8 status;
  118. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  119. if (err) {
  120. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  121. return err;
  122. }
  123. if (status) {
  124. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  125. "aborting.\n", status);
  126. return -EINVAL;
  127. }
  128. if (dev_lim->min_page_sz > PAGE_SIZE) {
  129. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  130. "kernel PAGE_SIZE of %ld, aborting.\n",
  131. dev_lim->min_page_sz, PAGE_SIZE);
  132. return -ENODEV;
  133. }
  134. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  135. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  136. "aborting.\n",
  137. dev_lim->num_ports, MTHCA_MAX_PORTS);
  138. return -ENODEV;
  139. }
  140. mdev->limits.num_ports = dev_lim->num_ports;
  141. mdev->limits.vl_cap = dev_lim->max_vl;
  142. mdev->limits.mtu_cap = dev_lim->max_mtu;
  143. mdev->limits.gid_table_len = dev_lim->max_gids;
  144. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  145. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  146. mdev->limits.max_sg = dev_lim->max_sg;
  147. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  148. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  149. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  150. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  151. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  152. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  153. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  154. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  155. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  156. mdev->limits.port_width_cap = dev_lim->max_port_width;
  157. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  158. May be doable since hardware supports it for SRQ.
  159. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  160. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  161. supported by driver. */
  162. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  163. IB_DEVICE_PORT_ACTIVE_EVENT |
  164. IB_DEVICE_SYS_IMAGE_GUID |
  165. IB_DEVICE_RC_RNR_NAK_GEN;
  166. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  167. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  168. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  169. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  170. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  171. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  172. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  173. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  174. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  175. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  176. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  177. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  178. return 0;
  179. }
  180. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  181. {
  182. u8 status;
  183. int err;
  184. struct mthca_dev_lim dev_lim;
  185. struct mthca_profile profile;
  186. struct mthca_init_hca_param init_hca;
  187. err = mthca_SYS_EN(mdev, &status);
  188. if (err) {
  189. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  190. return err;
  191. }
  192. if (status) {
  193. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  194. "aborting.\n", status);
  195. return -EINVAL;
  196. }
  197. err = mthca_QUERY_FW(mdev, &status);
  198. if (err) {
  199. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  200. goto err_disable;
  201. }
  202. if (status) {
  203. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  204. "aborting.\n", status);
  205. err = -EINVAL;
  206. goto err_disable;
  207. }
  208. err = mthca_QUERY_DDR(mdev, &status);
  209. if (err) {
  210. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  211. goto err_disable;
  212. }
  213. if (status) {
  214. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  215. "aborting.\n", status);
  216. err = -EINVAL;
  217. goto err_disable;
  218. }
  219. err = mthca_dev_lim(mdev, &dev_lim);
  220. profile = default_profile;
  221. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  222. profile.uarc_size = 0;
  223. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  224. profile.num_srq = dev_lim.max_srqs;
  225. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  226. if (err < 0)
  227. goto err_disable;
  228. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  229. if (err) {
  230. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  231. goto err_disable;
  232. }
  233. if (status) {
  234. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  235. "aborting.\n", status);
  236. err = -EINVAL;
  237. goto err_disable;
  238. }
  239. return 0;
  240. err_disable:
  241. mthca_SYS_DIS(mdev, &status);
  242. return err;
  243. }
  244. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  245. {
  246. u8 status;
  247. int err;
  248. /* FIXME: use HCA-attached memory for FW if present */
  249. mdev->fw.arbel.fw_icm =
  250. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  251. GFP_HIGHUSER | __GFP_NOWARN);
  252. if (!mdev->fw.arbel.fw_icm) {
  253. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  254. return -ENOMEM;
  255. }
  256. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  257. if (err) {
  258. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  259. goto err_free;
  260. }
  261. if (status) {
  262. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  263. err = -EINVAL;
  264. goto err_free;
  265. }
  266. err = mthca_RUN_FW(mdev, &status);
  267. if (err) {
  268. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  269. goto err_unmap_fa;
  270. }
  271. if (status) {
  272. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  273. err = -EINVAL;
  274. goto err_unmap_fa;
  275. }
  276. return 0;
  277. err_unmap_fa:
  278. mthca_UNMAP_FA(mdev, &status);
  279. err_free:
  280. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  281. return err;
  282. }
  283. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  284. struct mthca_dev_lim *dev_lim,
  285. struct mthca_init_hca_param *init_hca,
  286. u64 icm_size)
  287. {
  288. u64 aux_pages;
  289. u8 status;
  290. int err;
  291. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  292. if (err) {
  293. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  294. return err;
  295. }
  296. if (status) {
  297. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  298. "aborting.\n", status);
  299. return -EINVAL;
  300. }
  301. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  302. (unsigned long long) icm_size >> 10,
  303. (unsigned long long) aux_pages << 2);
  304. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  305. GFP_HIGHUSER | __GFP_NOWARN);
  306. if (!mdev->fw.arbel.aux_icm) {
  307. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  308. return -ENOMEM;
  309. }
  310. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  311. if (err) {
  312. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  313. goto err_free_aux;
  314. }
  315. if (status) {
  316. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  317. err = -EINVAL;
  318. goto err_free_aux;
  319. }
  320. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  321. if (err) {
  322. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  323. goto err_unmap_aux;
  324. }
  325. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  326. MTHCA_MTT_SEG_SIZE,
  327. mdev->limits.num_mtt_segs,
  328. mdev->limits.reserved_mtts, 1);
  329. if (!mdev->mr_table.mtt_table) {
  330. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  331. err = -ENOMEM;
  332. goto err_unmap_eq;
  333. }
  334. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  335. dev_lim->mpt_entry_sz,
  336. mdev->limits.num_mpts,
  337. mdev->limits.reserved_mrws, 1);
  338. if (!mdev->mr_table.mpt_table) {
  339. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  340. err = -ENOMEM;
  341. goto err_unmap_mtt;
  342. }
  343. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  344. dev_lim->qpc_entry_sz,
  345. mdev->limits.num_qps,
  346. mdev->limits.reserved_qps, 0);
  347. if (!mdev->qp_table.qp_table) {
  348. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  349. err = -ENOMEM;
  350. goto err_unmap_mpt;
  351. }
  352. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  353. dev_lim->eqpc_entry_sz,
  354. mdev->limits.num_qps,
  355. mdev->limits.reserved_qps, 0);
  356. if (!mdev->qp_table.eqp_table) {
  357. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  358. err = -ENOMEM;
  359. goto err_unmap_qp;
  360. }
  361. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  362. MTHCA_RDB_ENTRY_SIZE,
  363. mdev->limits.num_qps <<
  364. mdev->qp_table.rdb_shift,
  365. 0, 0);
  366. if (!mdev->qp_table.rdb_table) {
  367. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  368. err = -ENOMEM;
  369. goto err_unmap_eqp;
  370. }
  371. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  372. dev_lim->cqc_entry_sz,
  373. mdev->limits.num_cqs,
  374. mdev->limits.reserved_cqs, 0);
  375. if (!mdev->cq_table.table) {
  376. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  377. err = -ENOMEM;
  378. goto err_unmap_rdb;
  379. }
  380. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  381. mdev->srq_table.table =
  382. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  383. dev_lim->srq_entry_sz,
  384. mdev->limits.num_srqs,
  385. mdev->limits.reserved_srqs, 0);
  386. if (!mdev->srq_table.table) {
  387. mthca_err(mdev, "Failed to map SRQ context memory, "
  388. "aborting.\n");
  389. err = -ENOMEM;
  390. goto err_unmap_cq;
  391. }
  392. }
  393. /*
  394. * It's not strictly required, but for simplicity just map the
  395. * whole multicast group table now. The table isn't very big
  396. * and it's a lot easier than trying to track ref counts.
  397. */
  398. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  399. MTHCA_MGM_ENTRY_SIZE,
  400. mdev->limits.num_mgms +
  401. mdev->limits.num_amgms,
  402. mdev->limits.num_mgms +
  403. mdev->limits.num_amgms,
  404. 0);
  405. if (!mdev->mcg_table.table) {
  406. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  407. err = -ENOMEM;
  408. goto err_unmap_srq;
  409. }
  410. return 0;
  411. err_unmap_srq:
  412. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  413. mthca_free_icm_table(mdev, mdev->srq_table.table);
  414. err_unmap_cq:
  415. mthca_free_icm_table(mdev, mdev->cq_table.table);
  416. err_unmap_rdb:
  417. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  418. err_unmap_eqp:
  419. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  420. err_unmap_qp:
  421. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  422. err_unmap_mpt:
  423. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  424. err_unmap_mtt:
  425. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  426. err_unmap_eq:
  427. mthca_unmap_eq_icm(mdev);
  428. err_unmap_aux:
  429. mthca_UNMAP_ICM_AUX(mdev, &status);
  430. err_free_aux:
  431. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  432. return err;
  433. }
  434. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  435. {
  436. struct mthca_dev_lim dev_lim;
  437. struct mthca_profile profile;
  438. struct mthca_init_hca_param init_hca;
  439. u64 icm_size;
  440. u8 status;
  441. int err;
  442. err = mthca_QUERY_FW(mdev, &status);
  443. if (err) {
  444. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  445. return err;
  446. }
  447. if (status) {
  448. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  449. "aborting.\n", status);
  450. return -EINVAL;
  451. }
  452. err = mthca_ENABLE_LAM(mdev, &status);
  453. if (err) {
  454. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  455. return err;
  456. }
  457. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  458. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  459. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  460. } else if (status) {
  461. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  462. "aborting.\n", status);
  463. return -EINVAL;
  464. }
  465. err = mthca_load_fw(mdev);
  466. if (err) {
  467. mthca_err(mdev, "Failed to start FW, aborting.\n");
  468. goto err_disable;
  469. }
  470. err = mthca_dev_lim(mdev, &dev_lim);
  471. if (err) {
  472. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  473. goto err_stop_fw;
  474. }
  475. profile = default_profile;
  476. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  477. profile.num_udav = 0;
  478. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  479. profile.num_srq = dev_lim.max_srqs;
  480. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  481. if ((int) icm_size < 0) {
  482. err = icm_size;
  483. goto err_stop_fw;
  484. }
  485. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  486. if (err)
  487. goto err_stop_fw;
  488. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  489. if (err) {
  490. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  491. goto err_free_icm;
  492. }
  493. if (status) {
  494. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  495. "aborting.\n", status);
  496. err = -EINVAL;
  497. goto err_free_icm;
  498. }
  499. return 0;
  500. err_free_icm:
  501. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  502. mthca_free_icm_table(mdev, mdev->srq_table.table);
  503. mthca_free_icm_table(mdev, mdev->cq_table.table);
  504. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  505. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  506. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  507. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  508. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  509. mthca_unmap_eq_icm(mdev);
  510. mthca_UNMAP_ICM_AUX(mdev, &status);
  511. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  512. err_stop_fw:
  513. mthca_UNMAP_FA(mdev, &status);
  514. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  515. err_disable:
  516. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  517. mthca_DISABLE_LAM(mdev, &status);
  518. return err;
  519. }
  520. static void mthca_close_hca(struct mthca_dev *mdev)
  521. {
  522. u8 status;
  523. mthca_CLOSE_HCA(mdev, 0, &status);
  524. if (mthca_is_memfree(mdev)) {
  525. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  526. mthca_free_icm_table(mdev, mdev->srq_table.table);
  527. mthca_free_icm_table(mdev, mdev->cq_table.table);
  528. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  529. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  530. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  531. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  532. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  533. mthca_unmap_eq_icm(mdev);
  534. mthca_UNMAP_ICM_AUX(mdev, &status);
  535. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  536. mthca_UNMAP_FA(mdev, &status);
  537. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  538. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  539. mthca_DISABLE_LAM(mdev, &status);
  540. } else
  541. mthca_SYS_DIS(mdev, &status);
  542. }
  543. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  544. {
  545. u8 status;
  546. int err;
  547. struct mthca_adapter adapter;
  548. if (mthca_is_memfree(mdev))
  549. err = mthca_init_arbel(mdev);
  550. else
  551. err = mthca_init_tavor(mdev);
  552. if (err)
  553. return err;
  554. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  555. if (err) {
  556. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  557. goto err_close;
  558. }
  559. if (status) {
  560. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  561. "aborting.\n", status);
  562. err = -EINVAL;
  563. goto err_close;
  564. }
  565. mdev->eq_table.inta_pin = adapter.inta_pin;
  566. mdev->rev_id = adapter.revision_id;
  567. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  568. return 0;
  569. err_close:
  570. mthca_close_hca(mdev);
  571. return err;
  572. }
  573. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  574. {
  575. int err;
  576. u8 status;
  577. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  578. err = mthca_init_uar_table(dev);
  579. if (err) {
  580. mthca_err(dev, "Failed to initialize "
  581. "user access region table, aborting.\n");
  582. return err;
  583. }
  584. err = mthca_uar_alloc(dev, &dev->driver_uar);
  585. if (err) {
  586. mthca_err(dev, "Failed to allocate driver access region, "
  587. "aborting.\n");
  588. goto err_uar_table_free;
  589. }
  590. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  591. if (!dev->kar) {
  592. mthca_err(dev, "Couldn't map kernel access region, "
  593. "aborting.\n");
  594. err = -ENOMEM;
  595. goto err_uar_free;
  596. }
  597. err = mthca_init_pd_table(dev);
  598. if (err) {
  599. mthca_err(dev, "Failed to initialize "
  600. "protection domain table, aborting.\n");
  601. goto err_kar_unmap;
  602. }
  603. err = mthca_init_mr_table(dev);
  604. if (err) {
  605. mthca_err(dev, "Failed to initialize "
  606. "memory region table, aborting.\n");
  607. goto err_pd_table_free;
  608. }
  609. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  610. if (err) {
  611. mthca_err(dev, "Failed to create driver PD, "
  612. "aborting.\n");
  613. goto err_mr_table_free;
  614. }
  615. err = mthca_init_eq_table(dev);
  616. if (err) {
  617. mthca_err(dev, "Failed to initialize "
  618. "event queue table, aborting.\n");
  619. goto err_pd_free;
  620. }
  621. err = mthca_cmd_use_events(dev);
  622. if (err) {
  623. mthca_err(dev, "Failed to switch to event-driven "
  624. "firmware commands, aborting.\n");
  625. goto err_eq_table_free;
  626. }
  627. err = mthca_NOP(dev, &status);
  628. if (err || status) {
  629. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  630. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  631. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  632. dev->pdev->irq);
  633. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  634. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  635. else
  636. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  637. goto err_cmd_poll;
  638. }
  639. mthca_dbg(dev, "NOP command IRQ test passed\n");
  640. err = mthca_init_cq_table(dev);
  641. if (err) {
  642. mthca_err(dev, "Failed to initialize "
  643. "completion queue table, aborting.\n");
  644. goto err_cmd_poll;
  645. }
  646. err = mthca_init_srq_table(dev);
  647. if (err) {
  648. mthca_err(dev, "Failed to initialize "
  649. "shared receive queue table, aborting.\n");
  650. goto err_cq_table_free;
  651. }
  652. err = mthca_init_qp_table(dev);
  653. if (err) {
  654. mthca_err(dev, "Failed to initialize "
  655. "queue pair table, aborting.\n");
  656. goto err_srq_table_free;
  657. }
  658. err = mthca_init_av_table(dev);
  659. if (err) {
  660. mthca_err(dev, "Failed to initialize "
  661. "address vector table, aborting.\n");
  662. goto err_qp_table_free;
  663. }
  664. err = mthca_init_mcg_table(dev);
  665. if (err) {
  666. mthca_err(dev, "Failed to initialize "
  667. "multicast group table, aborting.\n");
  668. goto err_av_table_free;
  669. }
  670. return 0;
  671. err_av_table_free:
  672. mthca_cleanup_av_table(dev);
  673. err_qp_table_free:
  674. mthca_cleanup_qp_table(dev);
  675. err_srq_table_free:
  676. mthca_cleanup_srq_table(dev);
  677. err_cq_table_free:
  678. mthca_cleanup_cq_table(dev);
  679. err_cmd_poll:
  680. mthca_cmd_use_polling(dev);
  681. err_eq_table_free:
  682. mthca_cleanup_eq_table(dev);
  683. err_pd_free:
  684. mthca_pd_free(dev, &dev->driver_pd);
  685. err_mr_table_free:
  686. mthca_cleanup_mr_table(dev);
  687. err_pd_table_free:
  688. mthca_cleanup_pd_table(dev);
  689. err_kar_unmap:
  690. iounmap(dev->kar);
  691. err_uar_free:
  692. mthca_uar_free(dev, &dev->driver_uar);
  693. err_uar_table_free:
  694. mthca_cleanup_uar_table(dev);
  695. return err;
  696. }
  697. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  698. int ddr_hidden)
  699. {
  700. int err;
  701. /*
  702. * We can't just use pci_request_regions() because the MSI-X
  703. * table is right in the middle of the first BAR. If we did
  704. * pci_request_region and grab all of the first BAR, then
  705. * setting up MSI-X would fail, since the PCI core wants to do
  706. * request_mem_region on the MSI-X vector table.
  707. *
  708. * So just request what we need right now, and request any
  709. * other regions we need when setting up EQs.
  710. */
  711. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  712. MTHCA_HCR_SIZE, DRV_NAME))
  713. return -EBUSY;
  714. err = pci_request_region(pdev, 2, DRV_NAME);
  715. if (err)
  716. goto err_bar2_failed;
  717. if (!ddr_hidden) {
  718. err = pci_request_region(pdev, 4, DRV_NAME);
  719. if (err)
  720. goto err_bar4_failed;
  721. }
  722. return 0;
  723. err_bar4_failed:
  724. pci_release_region(pdev, 2);
  725. err_bar2_failed:
  726. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  727. MTHCA_HCR_SIZE);
  728. return err;
  729. }
  730. static void mthca_release_regions(struct pci_dev *pdev,
  731. int ddr_hidden)
  732. {
  733. if (!ddr_hidden)
  734. pci_release_region(pdev, 4);
  735. pci_release_region(pdev, 2);
  736. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  737. MTHCA_HCR_SIZE);
  738. }
  739. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  740. {
  741. struct msix_entry entries[3];
  742. int err;
  743. entries[0].entry = 0;
  744. entries[1].entry = 1;
  745. entries[2].entry = 2;
  746. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  747. if (err) {
  748. if (err > 0)
  749. mthca_info(mdev, "Only %d MSI-X vectors available, "
  750. "not using MSI-X\n", err);
  751. return err;
  752. }
  753. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  754. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  755. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  756. return 0;
  757. }
  758. /* Types of supported HCA */
  759. enum {
  760. TAVOR, /* MT23108 */
  761. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  762. ARBEL_NATIVE, /* MT25208 with extended features */
  763. SINAI /* MT25204 */
  764. };
  765. #define MTHCA_FW_VER(major, minor, subminor) \
  766. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  767. static struct {
  768. u64 latest_fw;
  769. int is_memfree;
  770. int is_pcie;
  771. } mthca_hca_table[] = {
  772. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3), .is_memfree = 0, .is_pcie = 0 },
  773. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0), .is_memfree = 0, .is_pcie = 1 },
  774. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0), .is_memfree = 1, .is_pcie = 1 },
  775. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1), .is_memfree = 1, .is_pcie = 1 }
  776. };
  777. static int __devinit mthca_init_one(struct pci_dev *pdev,
  778. const struct pci_device_id *id)
  779. {
  780. static int mthca_version_printed = 0;
  781. int ddr_hidden = 0;
  782. int err;
  783. struct mthca_dev *mdev;
  784. if (!mthca_version_printed) {
  785. printk(KERN_INFO "%s", mthca_version);
  786. ++mthca_version_printed;
  787. }
  788. printk(KERN_INFO PFX "Initializing %s\n",
  789. pci_name(pdev));
  790. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  791. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  792. pci_name(pdev), id->driver_data);
  793. return -ENODEV;
  794. }
  795. err = pci_enable_device(pdev);
  796. if (err) {
  797. dev_err(&pdev->dev, "Cannot enable PCI device, "
  798. "aborting.\n");
  799. return err;
  800. }
  801. /*
  802. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  803. * be present)
  804. */
  805. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  806. pci_resource_len(pdev, 0) != 1 << 20) {
  807. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  808. err = -ENODEV;
  809. goto err_disable_pdev;
  810. }
  811. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM) ||
  812. pci_resource_len(pdev, 2) != 1 << 23) {
  813. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  814. err = -ENODEV;
  815. goto err_disable_pdev;
  816. }
  817. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  818. ddr_hidden = 1;
  819. err = mthca_request_regions(pdev, ddr_hidden);
  820. if (err) {
  821. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  822. "aborting.\n");
  823. goto err_disable_pdev;
  824. }
  825. pci_set_master(pdev);
  826. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  827. if (err) {
  828. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  829. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  830. if (err) {
  831. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  832. goto err_free_res;
  833. }
  834. }
  835. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  836. if (err) {
  837. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  838. "consistent PCI DMA mask.\n");
  839. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  840. if (err) {
  841. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  842. "aborting.\n");
  843. goto err_free_res;
  844. }
  845. }
  846. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  847. if (!mdev) {
  848. dev_err(&pdev->dev, "Device struct alloc failed, "
  849. "aborting.\n");
  850. err = -ENOMEM;
  851. goto err_free_res;
  852. }
  853. mdev->pdev = pdev;
  854. if (ddr_hidden)
  855. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  856. if (mthca_hca_table[id->driver_data].is_memfree)
  857. mdev->mthca_flags |= MTHCA_FLAG_MEMFREE;
  858. if (mthca_hca_table[id->driver_data].is_pcie)
  859. mdev->mthca_flags |= MTHCA_FLAG_PCIE;
  860. /*
  861. * Now reset the HCA before we touch the PCI capabilities or
  862. * attempt a firmware command, since a boot ROM may have left
  863. * the HCA in an undefined state.
  864. */
  865. err = mthca_reset(mdev);
  866. if (err) {
  867. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  868. goto err_free_dev;
  869. }
  870. if (msi_x && !mthca_enable_msi_x(mdev))
  871. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  872. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  873. !pci_enable_msi(pdev))
  874. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  875. if (mthca_cmd_init(mdev)) {
  876. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  877. goto err_free_dev;
  878. }
  879. err = mthca_tune_pci(mdev);
  880. if (err)
  881. goto err_cmd;
  882. err = mthca_init_hca(mdev);
  883. if (err)
  884. goto err_cmd;
  885. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  886. mthca_warn(mdev, "HCA FW version %x.%x.%x is old (%x.%x.%x is current).\n",
  887. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  888. (int) (mdev->fw_ver & 0xffff),
  889. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  890. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  891. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  892. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  893. }
  894. err = mthca_setup_hca(mdev);
  895. if (err)
  896. goto err_close;
  897. err = mthca_register_device(mdev);
  898. if (err)
  899. goto err_cleanup;
  900. err = mthca_create_agents(mdev);
  901. if (err)
  902. goto err_unregister;
  903. pci_set_drvdata(pdev, mdev);
  904. return 0;
  905. err_unregister:
  906. mthca_unregister_device(mdev);
  907. err_cleanup:
  908. mthca_cleanup_mcg_table(mdev);
  909. mthca_cleanup_av_table(mdev);
  910. mthca_cleanup_qp_table(mdev);
  911. mthca_cleanup_srq_table(mdev);
  912. mthca_cleanup_cq_table(mdev);
  913. mthca_cmd_use_polling(mdev);
  914. mthca_cleanup_eq_table(mdev);
  915. mthca_pd_free(mdev, &mdev->driver_pd);
  916. mthca_cleanup_mr_table(mdev);
  917. mthca_cleanup_pd_table(mdev);
  918. mthca_cleanup_uar_table(mdev);
  919. err_close:
  920. mthca_close_hca(mdev);
  921. err_cmd:
  922. mthca_cmd_cleanup(mdev);
  923. err_free_dev:
  924. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  925. pci_disable_msix(pdev);
  926. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  927. pci_disable_msi(pdev);
  928. ib_dealloc_device(&mdev->ib_dev);
  929. err_free_res:
  930. mthca_release_regions(pdev, ddr_hidden);
  931. err_disable_pdev:
  932. pci_disable_device(pdev);
  933. pci_set_drvdata(pdev, NULL);
  934. return err;
  935. }
  936. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  937. {
  938. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  939. u8 status;
  940. int p;
  941. if (mdev) {
  942. mthca_free_agents(mdev);
  943. mthca_unregister_device(mdev);
  944. for (p = 1; p <= mdev->limits.num_ports; ++p)
  945. mthca_CLOSE_IB(mdev, p, &status);
  946. mthca_cleanup_mcg_table(mdev);
  947. mthca_cleanup_av_table(mdev);
  948. mthca_cleanup_qp_table(mdev);
  949. mthca_cleanup_srq_table(mdev);
  950. mthca_cleanup_cq_table(mdev);
  951. mthca_cmd_use_polling(mdev);
  952. mthca_cleanup_eq_table(mdev);
  953. mthca_pd_free(mdev, &mdev->driver_pd);
  954. mthca_cleanup_mr_table(mdev);
  955. mthca_cleanup_pd_table(mdev);
  956. iounmap(mdev->kar);
  957. mthca_uar_free(mdev, &mdev->driver_uar);
  958. mthca_cleanup_uar_table(mdev);
  959. mthca_close_hca(mdev);
  960. mthca_cmd_cleanup(mdev);
  961. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  962. pci_disable_msix(pdev);
  963. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  964. pci_disable_msi(pdev);
  965. ib_dealloc_device(&mdev->ib_dev);
  966. mthca_release_regions(pdev, mdev->mthca_flags &
  967. MTHCA_FLAG_DDR_HIDDEN);
  968. pci_disable_device(pdev);
  969. pci_set_drvdata(pdev, NULL);
  970. }
  971. }
  972. static struct pci_device_id mthca_pci_table[] = {
  973. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  974. .driver_data = TAVOR },
  975. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  976. .driver_data = TAVOR },
  977. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  978. .driver_data = ARBEL_COMPAT },
  979. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  980. .driver_data = ARBEL_COMPAT },
  981. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  982. .driver_data = ARBEL_NATIVE },
  983. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  984. .driver_data = ARBEL_NATIVE },
  985. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  986. .driver_data = SINAI },
  987. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  988. .driver_data = SINAI },
  989. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  990. .driver_data = SINAI },
  991. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  992. .driver_data = SINAI },
  993. { 0, }
  994. };
  995. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  996. static struct pci_driver mthca_driver = {
  997. .name = DRV_NAME,
  998. .id_table = mthca_pci_table,
  999. .probe = mthca_init_one,
  1000. .remove = __devexit_p(mthca_remove_one)
  1001. };
  1002. static int __init mthca_init(void)
  1003. {
  1004. int ret;
  1005. ret = pci_register_driver(&mthca_driver);
  1006. return ret < 0 ? ret : 0;
  1007. }
  1008. static void __exit mthca_cleanup(void)
  1009. {
  1010. pci_unregister_driver(&mthca_driver);
  1011. }
  1012. module_init(mthca_init);
  1013. module_exit(mthca_cleanup);