video1394.c 44 KB

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  1. /*
  2. * video1394.c - video driver for OHCI 1394 boards
  3. * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
  4. * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. * NOTES:
  21. *
  22. * jds -- add private data to file to keep track of iso contexts associated
  23. * with each open -- so release won't kill all iso transfers.
  24. *
  25. * Damien Douxchamps: Fix failure when the number of DMA pages per frame is
  26. * one.
  27. *
  28. * ioctl return codes:
  29. * EFAULT is only for invalid address for the argp
  30. * EINVAL for out of range values
  31. * EBUSY when trying to use an already used resource
  32. * ESRCH when trying to free/stop a not used resource
  33. * EAGAIN for resource allocation failure that could perhaps succeed later
  34. * ENOTTY for unsupported ioctl request
  35. *
  36. */
  37. /* Markus Tavenrath <speedygoo@speedygoo.de> :
  38. - fixed checks for valid buffer-numbers in video1394_icotl
  39. - changed the ways the dma prg's are used, now it's possible to use
  40. even a single dma buffer
  41. */
  42. #include <linux/config.h>
  43. #include <linux/kernel.h>
  44. #include <linux/list.h>
  45. #include <linux/slab.h>
  46. #include <linux/interrupt.h>
  47. #include <linux/wait.h>
  48. #include <linux/errno.h>
  49. #include <linux/module.h>
  50. #include <linux/init.h>
  51. #include <linux/pci.h>
  52. #include <linux/fs.h>
  53. #include <linux/poll.h>
  54. #include <linux/smp_lock.h>
  55. #include <linux/delay.h>
  56. #include <linux/devfs_fs_kernel.h>
  57. #include <linux/bitops.h>
  58. #include <linux/types.h>
  59. #include <linux/vmalloc.h>
  60. #include <linux/timex.h>
  61. #include <linux/mm.h>
  62. #include <linux/ioctl32.h>
  63. #include <linux/compat.h>
  64. #include <linux/cdev.h>
  65. #include "ieee1394.h"
  66. #include "ieee1394_types.h"
  67. #include "hosts.h"
  68. #include "ieee1394_core.h"
  69. #include "highlevel.h"
  70. #include "video1394.h"
  71. #include "nodemgr.h"
  72. #include "dma.h"
  73. #include "ohci1394.h"
  74. #define ISO_CHANNELS 64
  75. #ifndef virt_to_page
  76. #define virt_to_page(x) MAP_NR(x)
  77. #endif
  78. #ifndef vmalloc_32
  79. #define vmalloc_32(x) vmalloc(x)
  80. #endif
  81. struct it_dma_prg {
  82. struct dma_cmd begin;
  83. quadlet_t data[4];
  84. struct dma_cmd end;
  85. quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  86. };
  87. struct dma_iso_ctx {
  88. struct ti_ohci *ohci;
  89. int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
  90. struct ohci1394_iso_tasklet iso_tasklet;
  91. int channel;
  92. int ctx;
  93. int last_buffer;
  94. int * next_buffer; /* For ISO Transmit of video packets
  95. to write the correct SYT field
  96. into the next block */
  97. unsigned int num_desc;
  98. unsigned int buf_size;
  99. unsigned int frame_size;
  100. unsigned int packet_size;
  101. unsigned int left_size;
  102. unsigned int nb_cmd;
  103. struct dma_region dma;
  104. struct dma_prog_region *prg_reg;
  105. struct dma_cmd **ir_prg;
  106. struct it_dma_prg **it_prg;
  107. unsigned int *buffer_status;
  108. unsigned int *buffer_prg_assignment;
  109. struct timeval *buffer_time; /* time when the buffer was received */
  110. unsigned int *last_used_cmd; /* For ISO Transmit with
  111. variable sized packets only ! */
  112. int ctrlClear;
  113. int ctrlSet;
  114. int cmdPtr;
  115. int ctxMatch;
  116. wait_queue_head_t waitq;
  117. spinlock_t lock;
  118. unsigned int syt_offset;
  119. int flags;
  120. struct list_head link;
  121. };
  122. struct file_ctx {
  123. struct ti_ohci *ohci;
  124. struct list_head context_list;
  125. struct dma_iso_ctx *current_ctx;
  126. };
  127. #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  128. #define VIDEO1394_DEBUG
  129. #endif
  130. #ifdef DBGMSG
  131. #undef DBGMSG
  132. #endif
  133. #ifdef VIDEO1394_DEBUG
  134. #define DBGMSG(card, fmt, args...) \
  135. printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
  136. #else
  137. #define DBGMSG(card, fmt, args...)
  138. #endif
  139. /* print general (card independent) information */
  140. #define PRINT_G(level, fmt, args...) \
  141. printk(level "video1394: " fmt "\n" , ## args)
  142. /* print card specific information */
  143. #define PRINT(level, card, fmt, args...) \
  144. printk(level "video1394_%d: " fmt "\n" , card , ## args)
  145. static void wakeup_dma_ir_ctx(unsigned long l);
  146. static void wakeup_dma_it_ctx(unsigned long l);
  147. static struct hpsb_highlevel video1394_highlevel;
  148. static int free_dma_iso_ctx(struct dma_iso_ctx *d)
  149. {
  150. int i;
  151. DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
  152. ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
  153. if (d->iso_tasklet.link.next != NULL)
  154. ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
  155. dma_region_free(&d->dma);
  156. if (d->prg_reg) {
  157. for (i = 0; i < d->num_desc; i++)
  158. dma_prog_region_free(&d->prg_reg[i]);
  159. kfree(d->prg_reg);
  160. }
  161. kfree(d->ir_prg);
  162. kfree(d->it_prg);
  163. kfree(d->buffer_status);
  164. kfree(d->buffer_prg_assignment);
  165. kfree(d->buffer_time);
  166. kfree(d->last_used_cmd);
  167. kfree(d->next_buffer);
  168. list_del(&d->link);
  169. kfree(d);
  170. return 0;
  171. }
  172. static struct dma_iso_ctx *
  173. alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
  174. int buf_size, int channel, unsigned int packet_size)
  175. {
  176. struct dma_iso_ctx *d;
  177. int i;
  178. d = kmalloc(sizeof(struct dma_iso_ctx), GFP_KERNEL);
  179. if (d == NULL) {
  180. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
  181. return NULL;
  182. }
  183. memset(d, 0, sizeof *d);
  184. d->ohci = ohci;
  185. d->type = type;
  186. d->channel = channel;
  187. d->num_desc = num_desc;
  188. d->frame_size = buf_size;
  189. d->buf_size = PAGE_ALIGN(buf_size);
  190. d->last_buffer = -1;
  191. INIT_LIST_HEAD(&d->link);
  192. init_waitqueue_head(&d->waitq);
  193. /* Init the regions for easy cleanup */
  194. dma_region_init(&d->dma);
  195. if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev,
  196. PCI_DMA_BIDIRECTIONAL)) {
  197. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
  198. free_dma_iso_ctx(d);
  199. return NULL;
  200. }
  201. if (type == OHCI_ISO_RECEIVE)
  202. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  203. wakeup_dma_ir_ctx,
  204. (unsigned long) d);
  205. else
  206. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  207. wakeup_dma_it_ctx,
  208. (unsigned long) d);
  209. if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
  210. PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
  211. type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
  212. free_dma_iso_ctx(d);
  213. return NULL;
  214. }
  215. d->ctx = d->iso_tasklet.context;
  216. d->prg_reg = kmalloc(d->num_desc * sizeof(struct dma_prog_region),
  217. GFP_KERNEL);
  218. if (d->prg_reg == NULL) {
  219. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
  220. free_dma_iso_ctx(d);
  221. return NULL;
  222. }
  223. /* Makes for easier cleanup */
  224. for (i = 0; i < d->num_desc; i++)
  225. dma_prog_region_init(&d->prg_reg[i]);
  226. if (type == OHCI_ISO_RECEIVE) {
  227. d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
  228. d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
  229. d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
  230. d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
  231. d->ir_prg = kmalloc(d->num_desc * sizeof(struct dma_cmd *),
  232. GFP_KERNEL);
  233. if (d->ir_prg == NULL) {
  234. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  235. free_dma_iso_ctx(d);
  236. return NULL;
  237. }
  238. memset(d->ir_prg, 0, d->num_desc * sizeof(struct dma_cmd *));
  239. d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
  240. d->left_size = (d->frame_size % PAGE_SIZE) ?
  241. d->frame_size % PAGE_SIZE : PAGE_SIZE;
  242. for (i = 0;i < d->num_desc; i++) {
  243. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  244. sizeof(struct dma_cmd), ohci->dev)) {
  245. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  246. free_dma_iso_ctx(d);
  247. return NULL;
  248. }
  249. d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
  250. }
  251. } else { /* OHCI_ISO_TRANSMIT */
  252. d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
  253. d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
  254. d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
  255. d->it_prg = kmalloc(d->num_desc * sizeof(struct it_dma_prg *),
  256. GFP_KERNEL);
  257. if (d->it_prg == NULL) {
  258. PRINT(KERN_ERR, ohci->host->id,
  259. "Failed to allocate dma it prg");
  260. free_dma_iso_ctx(d);
  261. return NULL;
  262. }
  263. memset(d->it_prg, 0, d->num_desc*sizeof(struct it_dma_prg *));
  264. d->packet_size = packet_size;
  265. if (PAGE_SIZE % packet_size || packet_size>4096) {
  266. PRINT(KERN_ERR, ohci->host->id,
  267. "Packet size %d (page_size: %ld) "
  268. "not yet supported\n",
  269. packet_size, PAGE_SIZE);
  270. free_dma_iso_ctx(d);
  271. return NULL;
  272. }
  273. d->nb_cmd = d->frame_size / d->packet_size;
  274. if (d->frame_size % d->packet_size) {
  275. d->nb_cmd++;
  276. d->left_size = d->frame_size % d->packet_size;
  277. } else
  278. d->left_size = d->packet_size;
  279. for (i = 0; i < d->num_desc; i++) {
  280. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  281. sizeof(struct it_dma_prg), ohci->dev)) {
  282. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
  283. free_dma_iso_ctx(d);
  284. return NULL;
  285. }
  286. d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
  287. }
  288. }
  289. d->buffer_status = kmalloc(d->num_desc * sizeof(unsigned int),
  290. GFP_KERNEL);
  291. d->buffer_prg_assignment = kmalloc(d->num_desc * sizeof(unsigned int),
  292. GFP_KERNEL);
  293. d->buffer_time = kmalloc(d->num_desc * sizeof(struct timeval),
  294. GFP_KERNEL);
  295. d->last_used_cmd = kmalloc(d->num_desc * sizeof(unsigned int),
  296. GFP_KERNEL);
  297. d->next_buffer = kmalloc(d->num_desc * sizeof(int),
  298. GFP_KERNEL);
  299. if (d->buffer_status == NULL) {
  300. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate buffer_status");
  301. free_dma_iso_ctx(d);
  302. return NULL;
  303. }
  304. if (d->buffer_prg_assignment == NULL) {
  305. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate buffer_prg_assignment");
  306. free_dma_iso_ctx(d);
  307. return NULL;
  308. }
  309. if (d->buffer_time == NULL) {
  310. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate buffer_time");
  311. free_dma_iso_ctx(d);
  312. return NULL;
  313. }
  314. if (d->last_used_cmd == NULL) {
  315. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate last_used_cmd");
  316. free_dma_iso_ctx(d);
  317. return NULL;
  318. }
  319. if (d->next_buffer == NULL) {
  320. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate next_buffer");
  321. free_dma_iso_ctx(d);
  322. return NULL;
  323. }
  324. memset(d->buffer_status, 0, d->num_desc * sizeof(unsigned int));
  325. memset(d->buffer_prg_assignment, 0, d->num_desc * sizeof(unsigned int));
  326. memset(d->buffer_time, 0, d->num_desc * sizeof(struct timeval));
  327. memset(d->last_used_cmd, 0, d->num_desc * sizeof(unsigned int));
  328. memset(d->next_buffer, -1, d->num_desc * sizeof(int));
  329. spin_lock_init(&d->lock);
  330. PRINT(KERN_INFO, ohci->host->id, "Iso %s DMA: %d buffers "
  331. "of size %d allocated for a frame size %d, each with %d prgs",
  332. (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
  333. d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd);
  334. return d;
  335. }
  336. static void reset_ir_status(struct dma_iso_ctx *d, int n)
  337. {
  338. int i;
  339. d->ir_prg[n][0].status = cpu_to_le32(4);
  340. d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
  341. for (i = 2; i < d->nb_cmd - 1; i++)
  342. d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
  343. d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
  344. }
  345. static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags)
  346. {
  347. struct dma_cmd *ir_prg = d->ir_prg[n];
  348. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  349. int i;
  350. d->buffer_prg_assignment[n] = buffer;
  351. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  352. (unsigned long)d->dma.kvirt));
  353. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  354. (buf + 4) - (unsigned long)d->dma.kvirt));
  355. for (i=2;i<d->nb_cmd-1;i++) {
  356. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  357. (buf+(i-1)*PAGE_SIZE) -
  358. (unsigned long)d->dma.kvirt));
  359. }
  360. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  361. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  362. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  363. (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt));
  364. }
  365. static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
  366. {
  367. struct dma_cmd *ir_prg = d->ir_prg[n];
  368. struct dma_prog_region *ir_reg = &d->prg_reg[n];
  369. unsigned long buf = (unsigned long)d->dma.kvirt;
  370. int i;
  371. /* the first descriptor will read only 4 bytes */
  372. ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  373. DMA_CTL_BRANCH | 4);
  374. /* set the sync flag */
  375. if (flags & VIDEO1394_SYNC_FRAMES)
  376. ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
  377. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  378. (unsigned long)d->dma.kvirt));
  379. ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  380. 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  381. /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
  382. if (d->nb_cmd > 2) {
  383. /* The second descriptor will read PAGE_SIZE-4 bytes */
  384. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  385. DMA_CTL_BRANCH | (PAGE_SIZE-4));
  386. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
  387. (unsigned long)d->dma.kvirt));
  388. ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  389. 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  390. for (i = 2; i < d->nb_cmd - 1; i++) {
  391. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  392. DMA_CTL_BRANCH | PAGE_SIZE);
  393. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  394. (buf+(i-1)*PAGE_SIZE) -
  395. (unsigned long)d->dma.kvirt));
  396. ir_prg[i].branchAddress =
  397. cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  398. (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  399. }
  400. /* The last descriptor will generate an interrupt */
  401. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  402. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  403. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  404. (buf+(i-1)*PAGE_SIZE) -
  405. (unsigned long)d->dma.kvirt));
  406. } else {
  407. /* Only one DMA page is used. Read d->left_size immediately and */
  408. /* generate an interrupt as this is also the last page. */
  409. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  410. DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
  411. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  412. (buf + 4) - (unsigned long)d->dma.kvirt));
  413. }
  414. }
  415. static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
  416. {
  417. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  418. int i;
  419. d->flags = flags;
  420. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  421. for (i=0;i<d->num_desc;i++) {
  422. initialize_dma_ir_prg(d, i, flags);
  423. reset_ir_status(d, i);
  424. }
  425. /* reset the ctrl register */
  426. reg_write(ohci, d->ctrlClear, 0xf0000000);
  427. /* Set bufferFill */
  428. reg_write(ohci, d->ctrlSet, 0x80000000);
  429. /* Set isoch header */
  430. if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
  431. reg_write(ohci, d->ctrlSet, 0x40000000);
  432. /* Set the context match register to match on all tags,
  433. sync for sync tag, and listen to d->channel */
  434. reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
  435. /* Set up isoRecvIntMask to generate interrupts */
  436. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
  437. }
  438. /* find which context is listening to this channel */
  439. static struct dma_iso_ctx *
  440. find_ctx(struct list_head *list, int type, int channel)
  441. {
  442. struct dma_iso_ctx *ctx;
  443. list_for_each_entry(ctx, list, link) {
  444. if (ctx->type == type && ctx->channel == channel)
  445. return ctx;
  446. }
  447. return NULL;
  448. }
  449. static void wakeup_dma_ir_ctx(unsigned long l)
  450. {
  451. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  452. int i;
  453. spin_lock(&d->lock);
  454. for (i = 0; i < d->num_desc; i++) {
  455. if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
  456. reset_ir_status(d, i);
  457. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  458. do_gettimeofday(&d->buffer_time[i]);
  459. }
  460. }
  461. spin_unlock(&d->lock);
  462. if (waitqueue_active(&d->waitq))
  463. wake_up_interruptible(&d->waitq);
  464. }
  465. static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
  466. int n)
  467. {
  468. unsigned char* buf = d->dma.kvirt + n * d->buf_size;
  469. u32 cycleTimer;
  470. u32 timeStamp;
  471. if (n == -1) {
  472. return;
  473. }
  474. cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  475. timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
  476. timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
  477. + (cycleTimer & 0xf000)) & 0xffff;
  478. buf[6] = timeStamp >> 8;
  479. buf[7] = timeStamp & 0xff;
  480. /* if first packet is empty packet, then put timestamp into the next full one too */
  481. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  482. buf += d->packet_size;
  483. buf[6] = timeStamp >> 8;
  484. buf[7] = timeStamp & 0xff;
  485. }
  486. /* do the next buffer frame too in case of irq latency */
  487. n = d->next_buffer[n];
  488. if (n == -1) {
  489. return;
  490. }
  491. buf = d->dma.kvirt + n * d->buf_size;
  492. timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
  493. buf[6] = timeStamp >> 8;
  494. buf[7] = timeStamp & 0xff;
  495. /* if first packet is empty packet, then put timestamp into the next full one too */
  496. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  497. buf += d->packet_size;
  498. buf[6] = timeStamp >> 8;
  499. buf[7] = timeStamp & 0xff;
  500. }
  501. #if 0
  502. printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
  503. curr, n, cycleTimer, timeStamp);
  504. #endif
  505. }
  506. static void wakeup_dma_it_ctx(unsigned long l)
  507. {
  508. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  509. struct ti_ohci *ohci = d->ohci;
  510. int i;
  511. spin_lock(&d->lock);
  512. for (i = 0; i < d->num_desc; i++) {
  513. if (d->it_prg[i][d->last_used_cmd[i]].end.status &
  514. cpu_to_le32(0xFFFF0000)) {
  515. int next = d->next_buffer[i];
  516. put_timestamp(ohci, d, next);
  517. d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
  518. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  519. }
  520. }
  521. spin_unlock(&d->lock);
  522. if (waitqueue_active(&d->waitq))
  523. wake_up_interruptible(&d->waitq);
  524. }
  525. static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer)
  526. {
  527. struct it_dma_prg *it_prg = d->it_prg[n];
  528. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  529. int i;
  530. d->buffer_prg_assignment[n] = buffer;
  531. for (i=0;i<d->nb_cmd;i++) {
  532. it_prg[i].end.address =
  533. cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  534. (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt));
  535. }
  536. }
  537. static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
  538. {
  539. struct it_dma_prg *it_prg = d->it_prg[n];
  540. struct dma_prog_region *it_reg = &d->prg_reg[n];
  541. unsigned long buf = (unsigned long)d->dma.kvirt;
  542. int i;
  543. d->last_used_cmd[n] = d->nb_cmd - 1;
  544. for (i=0;i<d->nb_cmd;i++) {
  545. it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
  546. DMA_CTL_IMMEDIATE | 8) ;
  547. it_prg[i].begin.address = 0;
  548. it_prg[i].begin.status = 0;
  549. it_prg[i].data[0] = cpu_to_le32(
  550. (IEEE1394_SPEED_100 << 16)
  551. | (/* tag */ 1 << 14)
  552. | (d->channel << 8)
  553. | (TCODE_ISO_DATA << 4));
  554. if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
  555. it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
  556. it_prg[i].data[2] = 0;
  557. it_prg[i].data[3] = 0;
  558. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
  559. DMA_CTL_BRANCH);
  560. it_prg[i].end.address =
  561. cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
  562. (unsigned long)d->dma.kvirt));
  563. if (i<d->nb_cmd-1) {
  564. it_prg[i].end.control |= cpu_to_le32(d->packet_size);
  565. it_prg[i].begin.branchAddress =
  566. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  567. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  568. it_prg[i].end.branchAddress =
  569. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  570. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  571. } else {
  572. /* the last prg generates an interrupt */
  573. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  574. DMA_CTL_IRQ | d->left_size);
  575. /* the last prg doesn't branch */
  576. it_prg[i].begin.branchAddress = 0;
  577. it_prg[i].end.branchAddress = 0;
  578. }
  579. it_prg[i].end.status = 0;
  580. }
  581. }
  582. static void initialize_dma_it_prg_var_packet_queue(
  583. struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
  584. struct ti_ohci *ohci)
  585. {
  586. struct it_dma_prg *it_prg = d->it_prg[n];
  587. struct dma_prog_region *it_reg = &d->prg_reg[n];
  588. int i;
  589. #if 0
  590. if (n != -1) {
  591. put_timestamp(ohci, d, n);
  592. }
  593. #endif
  594. d->last_used_cmd[n] = d->nb_cmd - 1;
  595. for (i = 0; i < d->nb_cmd; i++) {
  596. unsigned int size;
  597. if (packet_sizes[i] > d->packet_size) {
  598. size = d->packet_size;
  599. } else {
  600. size = packet_sizes[i];
  601. }
  602. it_prg[i].data[1] = cpu_to_le32(size << 16);
  603. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
  604. if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
  605. it_prg[i].end.control |= cpu_to_le32(size);
  606. it_prg[i].begin.branchAddress =
  607. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  608. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  609. it_prg[i].end.branchAddress =
  610. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  611. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  612. } else {
  613. /* the last prg generates an interrupt */
  614. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  615. DMA_CTL_IRQ | size);
  616. /* the last prg doesn't branch */
  617. it_prg[i].begin.branchAddress = 0;
  618. it_prg[i].end.branchAddress = 0;
  619. d->last_used_cmd[n] = i;
  620. break;
  621. }
  622. }
  623. }
  624. static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
  625. unsigned int syt_offset, int flags)
  626. {
  627. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  628. int i;
  629. d->flags = flags;
  630. d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
  631. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  632. for (i=0;i<d->num_desc;i++)
  633. initialize_dma_it_prg(d, i, sync_tag);
  634. /* Set up isoRecvIntMask to generate interrupts */
  635. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
  636. }
  637. static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
  638. unsigned int buffer)
  639. {
  640. unsigned long flags;
  641. unsigned int ret;
  642. spin_lock_irqsave(&d->lock, flags);
  643. ret = d->buffer_status[buffer];
  644. spin_unlock_irqrestore(&d->lock, flags);
  645. return ret;
  646. }
  647. static int __video1394_ioctl(struct file *file,
  648. unsigned int cmd, unsigned long arg)
  649. {
  650. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  651. struct ti_ohci *ohci = ctx->ohci;
  652. unsigned long flags;
  653. void __user *argp = (void __user *)arg;
  654. switch(cmd)
  655. {
  656. case VIDEO1394_IOC_LISTEN_CHANNEL:
  657. case VIDEO1394_IOC_TALK_CHANNEL:
  658. {
  659. struct video1394_mmap v;
  660. u64 mask;
  661. struct dma_iso_ctx *d;
  662. int i;
  663. if (copy_from_user(&v, argp, sizeof(v)))
  664. return -EFAULT;
  665. /* if channel < 0, find lowest available one */
  666. if (v.channel < 0) {
  667. mask = (u64)0x1;
  668. for (i=0; ; i++) {
  669. if (i == ISO_CHANNELS) {
  670. PRINT(KERN_ERR, ohci->host->id,
  671. "No free channel found");
  672. return EAGAIN;
  673. }
  674. if (!(ohci->ISO_channel_usage & mask)) {
  675. v.channel = i;
  676. PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
  677. break;
  678. }
  679. mask = mask << 1;
  680. }
  681. } else if (v.channel >= ISO_CHANNELS) {
  682. PRINT(KERN_ERR, ohci->host->id,
  683. "Iso channel %d out of bounds", v.channel);
  684. return -EINVAL;
  685. } else {
  686. mask = (u64)0x1<<v.channel;
  687. }
  688. PRINT(KERN_INFO, ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
  689. (u32)(mask>>32),(u32)(mask&0xffffffff),
  690. (u32)(ohci->ISO_channel_usage>>32),
  691. (u32)(ohci->ISO_channel_usage&0xffffffff));
  692. if (ohci->ISO_channel_usage & mask) {
  693. PRINT(KERN_ERR, ohci->host->id,
  694. "Channel %d is already taken", v.channel);
  695. return -EBUSY;
  696. }
  697. if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
  698. PRINT(KERN_ERR, ohci->host->id,
  699. "Invalid %d length buffer requested",v.buf_size);
  700. return -EINVAL;
  701. }
  702. if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
  703. PRINT(KERN_ERR, ohci->host->id,
  704. "Invalid %d buffers requested",v.nb_buffers);
  705. return -EINVAL;
  706. }
  707. if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
  708. PRINT(KERN_ERR, ohci->host->id,
  709. "%d buffers of size %d bytes is too big",
  710. v.nb_buffers, v.buf_size);
  711. return -EINVAL;
  712. }
  713. if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
  714. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
  715. v.nb_buffers + 1, v.buf_size,
  716. v.channel, 0);
  717. if (d == NULL) {
  718. PRINT(KERN_ERR, ohci->host->id,
  719. "Couldn't allocate ir context");
  720. return -EAGAIN;
  721. }
  722. initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
  723. ctx->current_ctx = d;
  724. v.buf_size = d->buf_size;
  725. list_add_tail(&d->link, &ctx->context_list);
  726. PRINT(KERN_INFO, ohci->host->id,
  727. "iso context %d listen on channel %d",
  728. d->ctx, v.channel);
  729. }
  730. else {
  731. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
  732. v.nb_buffers + 1, v.buf_size,
  733. v.channel, v.packet_size);
  734. if (d == NULL) {
  735. PRINT(KERN_ERR, ohci->host->id,
  736. "Couldn't allocate it context");
  737. return -EAGAIN;
  738. }
  739. initialize_dma_it_ctx(d, v.sync_tag,
  740. v.syt_offset, v.flags);
  741. ctx->current_ctx = d;
  742. v.buf_size = d->buf_size;
  743. list_add_tail(&d->link, &ctx->context_list);
  744. PRINT(KERN_INFO, ohci->host->id,
  745. "Iso context %d talk on channel %d", d->ctx,
  746. v.channel);
  747. }
  748. if (copy_to_user(argp, &v, sizeof(v))) {
  749. /* FIXME : free allocated dma resources */
  750. return -EFAULT;
  751. }
  752. ohci->ISO_channel_usage |= mask;
  753. return 0;
  754. }
  755. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  756. case VIDEO1394_IOC_UNTALK_CHANNEL:
  757. {
  758. int channel;
  759. u64 mask;
  760. struct dma_iso_ctx *d;
  761. if (copy_from_user(&channel, argp, sizeof(int)))
  762. return -EFAULT;
  763. if (channel < 0 || channel >= ISO_CHANNELS) {
  764. PRINT(KERN_ERR, ohci->host->id,
  765. "Iso channel %d out of bound", channel);
  766. return -EINVAL;
  767. }
  768. mask = (u64)0x1<<channel;
  769. if (!(ohci->ISO_channel_usage & mask)) {
  770. PRINT(KERN_ERR, ohci->host->id,
  771. "Channel %d is not being used", channel);
  772. return -ESRCH;
  773. }
  774. /* Mark this channel as unused */
  775. ohci->ISO_channel_usage &= ~mask;
  776. if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
  777. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
  778. else
  779. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
  780. if (d == NULL) return -ESRCH;
  781. PRINT(KERN_INFO, ohci->host->id, "Iso context %d "
  782. "stop talking on channel %d", d->ctx, channel);
  783. free_dma_iso_ctx(d);
  784. return 0;
  785. }
  786. case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
  787. {
  788. struct video1394_wait v;
  789. struct dma_iso_ctx *d;
  790. int next_prg;
  791. if (copy_from_user(&v, argp, sizeof(v)))
  792. return -EFAULT;
  793. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  794. if (d == NULL) return -EFAULT;
  795. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  796. PRINT(KERN_ERR, ohci->host->id,
  797. "Buffer %d out of range",v.buffer);
  798. return -EINVAL;
  799. }
  800. spin_lock_irqsave(&d->lock,flags);
  801. if (d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED) {
  802. PRINT(KERN_ERR, ohci->host->id,
  803. "Buffer %d is already used",v.buffer);
  804. spin_unlock_irqrestore(&d->lock,flags);
  805. return -EBUSY;
  806. }
  807. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  808. next_prg = (d->last_buffer + 1) % d->num_desc;
  809. if (d->last_buffer>=0)
  810. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
  811. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0)
  812. & 0xfffffff0) | 0x1);
  813. d->last_buffer = next_prg;
  814. reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags);
  815. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
  816. spin_unlock_irqrestore(&d->lock,flags);
  817. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  818. {
  819. DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
  820. /* Tell the controller where the first program is */
  821. reg_write(ohci, d->cmdPtr,
  822. dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1);
  823. /* Run IR context */
  824. reg_write(ohci, d->ctrlSet, 0x8000);
  825. }
  826. else {
  827. /* Wake up dma context if necessary */
  828. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  829. PRINT(KERN_INFO, ohci->host->id,
  830. "Waking up iso dma ctx=%d", d->ctx);
  831. reg_write(ohci, d->ctrlSet, 0x1000);
  832. }
  833. }
  834. return 0;
  835. }
  836. case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
  837. case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
  838. {
  839. struct video1394_wait v;
  840. struct dma_iso_ctx *d;
  841. int i = 0;
  842. if (copy_from_user(&v, argp, sizeof(v)))
  843. return -EFAULT;
  844. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  845. if (d == NULL) return -EFAULT;
  846. if ((v.buffer<0) || (v.buffer>d->num_desc - 1)) {
  847. PRINT(KERN_ERR, ohci->host->id,
  848. "Buffer %d out of range",v.buffer);
  849. return -EINVAL;
  850. }
  851. /*
  852. * I change the way it works so that it returns
  853. * the last received frame.
  854. */
  855. spin_lock_irqsave(&d->lock, flags);
  856. switch(d->buffer_status[v.buffer]) {
  857. case VIDEO1394_BUFFER_READY:
  858. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  859. break;
  860. case VIDEO1394_BUFFER_QUEUED:
  861. if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
  862. /* for polling, return error code EINTR */
  863. spin_unlock_irqrestore(&d->lock, flags);
  864. return -EINTR;
  865. }
  866. spin_unlock_irqrestore(&d->lock, flags);
  867. wait_event_interruptible(d->waitq,
  868. video1394_buffer_state(d, v.buffer) ==
  869. VIDEO1394_BUFFER_READY);
  870. if (signal_pending(current))
  871. return -EINTR;
  872. spin_lock_irqsave(&d->lock, flags);
  873. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  874. break;
  875. default:
  876. PRINT(KERN_ERR, ohci->host->id,
  877. "Buffer %d is not queued",v.buffer);
  878. spin_unlock_irqrestore(&d->lock, flags);
  879. return -ESRCH;
  880. }
  881. /* set time of buffer */
  882. v.filltime = d->buffer_time[v.buffer];
  883. // printk("Buffer %d time %d\n", v.buffer, (d->buffer_time[v.buffer]).tv_usec);
  884. /*
  885. * Look ahead to see how many more buffers have been received
  886. */
  887. i=0;
  888. while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]==
  889. VIDEO1394_BUFFER_READY) {
  890. v.buffer=(v.buffer+1)%(d->num_desc - 1);
  891. i++;
  892. }
  893. spin_unlock_irqrestore(&d->lock, flags);
  894. v.buffer=i;
  895. if (copy_to_user(argp, &v, sizeof(v)))
  896. return -EFAULT;
  897. return 0;
  898. }
  899. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  900. {
  901. struct video1394_wait v;
  902. unsigned int *psizes = NULL;
  903. struct dma_iso_ctx *d;
  904. int next_prg;
  905. if (copy_from_user(&v, argp, sizeof(v)))
  906. return -EFAULT;
  907. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  908. if (d == NULL) return -EFAULT;
  909. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  910. PRINT(KERN_ERR, ohci->host->id,
  911. "Buffer %d out of range",v.buffer);
  912. return -EINVAL;
  913. }
  914. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  915. int buf_size = d->nb_cmd * sizeof(unsigned int);
  916. struct video1394_queue_variable __user *p = argp;
  917. unsigned int __user *qv;
  918. if (get_user(qv, &p->packet_sizes))
  919. return -EFAULT;
  920. psizes = kmalloc(buf_size, GFP_KERNEL);
  921. if (!psizes)
  922. return -ENOMEM;
  923. if (copy_from_user(psizes, qv, buf_size)) {
  924. kfree(psizes);
  925. return -EFAULT;
  926. }
  927. }
  928. spin_lock_irqsave(&d->lock,flags);
  929. // last_buffer is last_prg
  930. next_prg = (d->last_buffer + 1) % d->num_desc;
  931. if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
  932. PRINT(KERN_ERR, ohci->host->id,
  933. "Buffer %d is already used",v.buffer);
  934. spin_unlock_irqrestore(&d->lock,flags);
  935. kfree(psizes);
  936. return -EBUSY;
  937. }
  938. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  939. initialize_dma_it_prg_var_packet_queue(
  940. d, next_prg, psizes, ohci);
  941. }
  942. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  943. if (d->last_buffer >= 0) {
  944. d->it_prg[d->last_buffer]
  945. [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
  946. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  947. 0) & 0xfffffff0) | 0x3);
  948. d->it_prg[d->last_buffer]
  949. [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
  950. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  951. 0) & 0xfffffff0) | 0x3);
  952. d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1);
  953. }
  954. d->last_buffer = next_prg;
  955. reprogram_dma_it_prg(d, d->last_buffer, v.buffer);
  956. d->next_buffer[d->last_buffer] = -1;
  957. d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
  958. spin_unlock_irqrestore(&d->lock,flags);
  959. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  960. {
  961. DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
  962. d->ctx);
  963. put_timestamp(ohci, d, d->last_buffer);
  964. /* Tell the controller where the first program is */
  965. reg_write(ohci, d->cmdPtr,
  966. dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3);
  967. /* Run IT context */
  968. reg_write(ohci, d->ctrlSet, 0x8000);
  969. }
  970. else {
  971. /* Wake up dma context if necessary */
  972. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  973. PRINT(KERN_INFO, ohci->host->id,
  974. "Waking up iso transmit dma ctx=%d",
  975. d->ctx);
  976. put_timestamp(ohci, d, d->last_buffer);
  977. reg_write(ohci, d->ctrlSet, 0x1000);
  978. }
  979. }
  980. kfree(psizes);
  981. return 0;
  982. }
  983. case VIDEO1394_IOC_TALK_WAIT_BUFFER:
  984. {
  985. struct video1394_wait v;
  986. struct dma_iso_ctx *d;
  987. if (copy_from_user(&v, argp, sizeof(v)))
  988. return -EFAULT;
  989. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  990. if (d == NULL) return -EFAULT;
  991. if ((v.buffer<0) || (v.buffer>=d->num_desc-1)) {
  992. PRINT(KERN_ERR, ohci->host->id,
  993. "Buffer %d out of range",v.buffer);
  994. return -EINVAL;
  995. }
  996. switch(d->buffer_status[v.buffer]) {
  997. case VIDEO1394_BUFFER_READY:
  998. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  999. return 0;
  1000. case VIDEO1394_BUFFER_QUEUED:
  1001. wait_event_interruptible(d->waitq,
  1002. (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
  1003. if (signal_pending(current))
  1004. return -EINTR;
  1005. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  1006. return 0;
  1007. default:
  1008. PRINT(KERN_ERR, ohci->host->id,
  1009. "Buffer %d is not queued",v.buffer);
  1010. return -ESRCH;
  1011. }
  1012. }
  1013. default:
  1014. return -ENOTTY;
  1015. }
  1016. }
  1017. static long video1394_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  1018. {
  1019. int err;
  1020. lock_kernel();
  1021. err = __video1394_ioctl(file, cmd, arg);
  1022. unlock_kernel();
  1023. return err;
  1024. }
  1025. /*
  1026. * This maps the vmalloced and reserved buffer to user space.
  1027. *
  1028. * FIXME:
  1029. * - PAGE_READONLY should suffice!?
  1030. * - remap_pfn_range is kind of inefficient for page by page remapping.
  1031. * But e.g. pte_alloc() does not work in modules ... :-(
  1032. */
  1033. static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
  1034. {
  1035. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1036. int res = -EINVAL;
  1037. lock_kernel();
  1038. if (ctx->current_ctx == NULL) {
  1039. PRINT(KERN_ERR, ctx->ohci->host->id, "Current iso context not set");
  1040. } else
  1041. res = dma_region_mmap(&ctx->current_ctx->dma, file, vma);
  1042. unlock_kernel();
  1043. return res;
  1044. }
  1045. static int video1394_open(struct inode *inode, struct file *file)
  1046. {
  1047. int i = ieee1394_file_to_instance(file);
  1048. struct ti_ohci *ohci;
  1049. struct file_ctx *ctx;
  1050. ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
  1051. if (ohci == NULL)
  1052. return -EIO;
  1053. ctx = kmalloc(sizeof(struct file_ctx), GFP_KERNEL);
  1054. if (ctx == NULL) {
  1055. PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
  1056. return -ENOMEM;
  1057. }
  1058. memset(ctx, 0, sizeof(struct file_ctx));
  1059. ctx->ohci = ohci;
  1060. INIT_LIST_HEAD(&ctx->context_list);
  1061. ctx->current_ctx = NULL;
  1062. file->private_data = ctx;
  1063. return 0;
  1064. }
  1065. static int video1394_release(struct inode *inode, struct file *file)
  1066. {
  1067. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1068. struct ti_ohci *ohci = ctx->ohci;
  1069. struct list_head *lh, *next;
  1070. u64 mask;
  1071. lock_kernel();
  1072. list_for_each_safe(lh, next, &ctx->context_list) {
  1073. struct dma_iso_ctx *d;
  1074. d = list_entry(lh, struct dma_iso_ctx, link);
  1075. mask = (u64) 1 << d->channel;
  1076. if (!(ohci->ISO_channel_usage & mask))
  1077. PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
  1078. "is not being used", d->channel);
  1079. else
  1080. ohci->ISO_channel_usage &= ~mask;
  1081. PRINT(KERN_INFO, ohci->host->id, "On release: Iso %s context "
  1082. "%d stop listening on channel %d",
  1083. d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
  1084. d->ctx, d->channel);
  1085. free_dma_iso_ctx(d);
  1086. }
  1087. kfree(ctx);
  1088. file->private_data = NULL;
  1089. unlock_kernel();
  1090. return 0;
  1091. }
  1092. #ifdef CONFIG_COMPAT
  1093. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
  1094. #endif
  1095. static struct cdev video1394_cdev;
  1096. static struct file_operations video1394_fops=
  1097. {
  1098. .owner = THIS_MODULE,
  1099. .unlocked_ioctl = video1394_ioctl,
  1100. #ifdef CONFIG_COMPAT
  1101. .compat_ioctl = video1394_compat_ioctl,
  1102. #endif
  1103. .mmap = video1394_mmap,
  1104. .open = video1394_open,
  1105. .release = video1394_release
  1106. };
  1107. /*** HOTPLUG STUFF **********************************************************/
  1108. /*
  1109. * Export information about protocols/devices supported by this driver.
  1110. */
  1111. static struct ieee1394_device_id video1394_id_table[] = {
  1112. {
  1113. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1114. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1115. .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
  1116. },
  1117. {
  1118. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1119. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1120. .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
  1121. },
  1122. {
  1123. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1124. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1125. .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
  1126. },
  1127. { }
  1128. };
  1129. MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
  1130. static struct hpsb_protocol_driver video1394_driver = {
  1131. .name = "1394 Digital Camera Driver",
  1132. .id_table = video1394_id_table,
  1133. .driver = {
  1134. .name = VIDEO1394_DRIVER_NAME,
  1135. .bus = &ieee1394_bus_type,
  1136. },
  1137. };
  1138. static void video1394_add_host (struct hpsb_host *host)
  1139. {
  1140. struct ti_ohci *ohci;
  1141. int minor;
  1142. /* We only work with the OHCI-1394 driver */
  1143. if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
  1144. return;
  1145. ohci = (struct ti_ohci *)host->hostdata;
  1146. if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
  1147. PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
  1148. return;
  1149. }
  1150. hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
  1151. hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
  1152. minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
  1153. class_device_create(hpsb_protocol_class, MKDEV(
  1154. IEEE1394_MAJOR, minor),
  1155. NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1156. devfs_mk_cdev(MKDEV(IEEE1394_MAJOR, minor),
  1157. S_IFCHR | S_IRUSR | S_IWUSR,
  1158. "%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1159. }
  1160. static void video1394_remove_host (struct hpsb_host *host)
  1161. {
  1162. struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
  1163. if (ohci) {
  1164. class_device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
  1165. IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
  1166. devfs_remove("%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1167. }
  1168. return;
  1169. }
  1170. static struct hpsb_highlevel video1394_highlevel = {
  1171. .name = VIDEO1394_DRIVER_NAME,
  1172. .add_host = video1394_add_host,
  1173. .remove_host = video1394_remove_host,
  1174. };
  1175. MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
  1176. MODULE_DESCRIPTION("driver for digital video on OHCI board");
  1177. MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
  1178. MODULE_LICENSE("GPL");
  1179. #ifdef CONFIG_COMPAT
  1180. #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
  1181. _IOW ('#', 0x12, struct video1394_wait32)
  1182. #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
  1183. _IOWR('#', 0x13, struct video1394_wait32)
  1184. #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
  1185. _IOW ('#', 0x17, struct video1394_wait32)
  1186. #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
  1187. _IOWR('#', 0x18, struct video1394_wait32)
  1188. struct video1394_wait32 {
  1189. u32 channel;
  1190. u32 buffer;
  1191. struct compat_timeval filltime;
  1192. };
  1193. static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1194. {
  1195. struct video1394_wait32 __user *argp = (void __user *)arg;
  1196. struct video1394_wait32 wait32;
  1197. struct video1394_wait wait;
  1198. mm_segment_t old_fs;
  1199. int ret;
  1200. if (copy_from_user(&wait32, argp, sizeof(wait32)))
  1201. return -EFAULT;
  1202. wait.channel = wait32.channel;
  1203. wait.buffer = wait32.buffer;
  1204. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1205. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1206. old_fs = get_fs();
  1207. set_fs(KERNEL_DS);
  1208. if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
  1209. ret = video1394_ioctl(file,
  1210. VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
  1211. (unsigned long) &wait);
  1212. else
  1213. ret = video1394_ioctl(file,
  1214. VIDEO1394_IOC_LISTEN_POLL_BUFFER,
  1215. (unsigned long) &wait);
  1216. set_fs(old_fs);
  1217. if (!ret) {
  1218. wait32.channel = wait.channel;
  1219. wait32.buffer = wait.buffer;
  1220. wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
  1221. wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
  1222. if (copy_to_user(argp, &wait32, sizeof(wait32)))
  1223. ret = -EFAULT;
  1224. }
  1225. return ret;
  1226. }
  1227. static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1228. {
  1229. struct video1394_wait32 wait32;
  1230. struct video1394_wait wait;
  1231. mm_segment_t old_fs;
  1232. int ret;
  1233. if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
  1234. return -EFAULT;
  1235. wait.channel = wait32.channel;
  1236. wait.buffer = wait32.buffer;
  1237. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1238. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1239. old_fs = get_fs();
  1240. set_fs(KERNEL_DS);
  1241. if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
  1242. ret = video1394_ioctl(file,
  1243. VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
  1244. (unsigned long) &wait);
  1245. else
  1246. ret = video1394_ioctl(file,
  1247. VIDEO1394_IOC_TALK_WAIT_BUFFER,
  1248. (unsigned long) &wait);
  1249. set_fs(old_fs);
  1250. return ret;
  1251. }
  1252. static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
  1253. {
  1254. return -EFAULT; /* ??? was there before. */
  1255. return video1394_ioctl(file,
  1256. VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
  1257. }
  1258. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
  1259. {
  1260. switch (cmd) {
  1261. case VIDEO1394_IOC_LISTEN_CHANNEL:
  1262. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  1263. case VIDEO1394_IOC_TALK_CHANNEL:
  1264. case VIDEO1394_IOC_UNTALK_CHANNEL:
  1265. return video1394_ioctl(f, cmd, arg);
  1266. case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
  1267. return video1394_w_wait32(f, cmd, arg);
  1268. case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
  1269. return video1394_wr_wait32(f, cmd, arg);
  1270. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  1271. return video1394_queue_buf32(f, cmd, arg);
  1272. case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
  1273. return video1394_w_wait32(f, cmd, arg);
  1274. case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
  1275. return video1394_wr_wait32(f, cmd, arg);
  1276. default:
  1277. return -ENOIOCTLCMD;
  1278. }
  1279. }
  1280. #endif /* CONFIG_COMPAT */
  1281. static void __exit video1394_exit_module (void)
  1282. {
  1283. hpsb_unregister_protocol(&video1394_driver);
  1284. hpsb_unregister_highlevel(&video1394_highlevel);
  1285. devfs_remove(VIDEO1394_DRIVER_NAME);
  1286. cdev_del(&video1394_cdev);
  1287. PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
  1288. }
  1289. static int __init video1394_init_module (void)
  1290. {
  1291. int ret;
  1292. cdev_init(&video1394_cdev, &video1394_fops);
  1293. video1394_cdev.owner = THIS_MODULE;
  1294. kobject_set_name(&video1394_cdev.kobj, VIDEO1394_DRIVER_NAME);
  1295. ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
  1296. if (ret) {
  1297. PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
  1298. return ret;
  1299. }
  1300. devfs_mk_dir(VIDEO1394_DRIVER_NAME);
  1301. hpsb_register_highlevel(&video1394_highlevel);
  1302. ret = hpsb_register_protocol(&video1394_driver);
  1303. if (ret) {
  1304. PRINT_G(KERN_ERR, "video1394: failed to register protocol");
  1305. hpsb_unregister_highlevel(&video1394_highlevel);
  1306. devfs_remove(VIDEO1394_DRIVER_NAME);
  1307. cdev_del(&video1394_cdev);
  1308. return ret;
  1309. }
  1310. PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
  1311. return 0;
  1312. }
  1313. module_init(video1394_init_module);
  1314. module_exit(video1394_exit_module);
  1315. MODULE_ALIAS_CHARDEV(IEEE1394_MAJOR, IEEE1394_MINOR_BLOCK_VIDEO1394 * 16);