pdc202xx_new.c 13 KB

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  1. /*
  2. * Promise TX2/TX4/TX2000/133 IDE driver
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version
  7. * 2 of the License, or (at your option) any later version.
  8. *
  9. * Split from:
  10. * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
  11. * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
  12. * Portions Copyright (C) 1999 Promise Technology, Inc.
  13. * Author: Frank Tiernan (frankt@promise.com)
  14. * Released under terms of General Public License
  15. */
  16. #include <linux/config.h>
  17. #include <linux/module.h>
  18. #include <linux/types.h>
  19. #include <linux/kernel.h>
  20. #include <linux/delay.h>
  21. #include <linux/timer.h>
  22. #include <linux/mm.h>
  23. #include <linux/ioport.h>
  24. #include <linux/blkdev.h>
  25. #include <linux/hdreg.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/pci.h>
  28. #include <linux/init.h>
  29. #include <linux/ide.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #ifdef CONFIG_PPC_PMAC
  33. #include <asm/prom.h>
  34. #include <asm/pci-bridge.h>
  35. #endif
  36. #define PDC202_DEBUG_CABLE 0
  37. const static char *pdc_quirk_drives[] = {
  38. "QUANTUM FIREBALLlct08 08",
  39. "QUANTUM FIREBALLP KA6.4",
  40. "QUANTUM FIREBALLP KA9.1",
  41. "QUANTUM FIREBALLP LM20.4",
  42. "QUANTUM FIREBALLP KX13.6",
  43. "QUANTUM FIREBALLP KX20.5",
  44. "QUANTUM FIREBALLP KX27.3",
  45. "QUANTUM FIREBALLP LM20.5",
  46. NULL
  47. };
  48. #define set_2regs(a, b) \
  49. do { \
  50. hwif->OUTB((a + adj), indexreg); \
  51. hwif->OUTB(b, datareg); \
  52. } while(0)
  53. #define set_ultra(a, b, c) \
  54. do { \
  55. set_2regs(0x10,(a)); \
  56. set_2regs(0x11,(b)); \
  57. set_2regs(0x12,(c)); \
  58. } while(0)
  59. #define set_ata2(a, b) \
  60. do { \
  61. set_2regs(0x0e,(a)); \
  62. set_2regs(0x0f,(b)); \
  63. } while(0)
  64. #define set_pio(a, b, c) \
  65. do { \
  66. set_2regs(0x0c,(a)); \
  67. set_2regs(0x0d,(b)); \
  68. set_2regs(0x13,(c)); \
  69. } while(0)
  70. static u8 pdcnew_ratemask (ide_drive_t *drive)
  71. {
  72. u8 mode;
  73. switch(HWIF(drive)->pci_dev->device) {
  74. case PCI_DEVICE_ID_PROMISE_20277:
  75. case PCI_DEVICE_ID_PROMISE_20276:
  76. case PCI_DEVICE_ID_PROMISE_20275:
  77. case PCI_DEVICE_ID_PROMISE_20271:
  78. case PCI_DEVICE_ID_PROMISE_20269:
  79. mode = 4;
  80. break;
  81. case PCI_DEVICE_ID_PROMISE_20270:
  82. case PCI_DEVICE_ID_PROMISE_20268:
  83. mode = 3;
  84. break;
  85. default:
  86. return 0;
  87. }
  88. if (!eighty_ninty_three(drive))
  89. mode = min(mode, (u8)1);
  90. return mode;
  91. }
  92. static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  93. {
  94. struct hd_driveid *id = drive->id;
  95. if (pdc_quirk_drives == list) {
  96. while (*list) {
  97. if (strstr(id->model, *list++)) {
  98. return 2;
  99. }
  100. }
  101. } else {
  102. while (*list) {
  103. if (!strcmp(*list++,id->model)) {
  104. return 1;
  105. }
  106. }
  107. }
  108. return 0;
  109. }
  110. static int pdcnew_new_tune_chipset (ide_drive_t *drive, u8 xferspeed)
  111. {
  112. ide_hwif_t *hwif = HWIF(drive);
  113. unsigned long indexreg = hwif->dma_vendor1;
  114. unsigned long datareg = hwif->dma_vendor3;
  115. u8 thold = 0x10;
  116. u8 adj = (drive->dn%2) ? 0x08 : 0x00;
  117. u8 speed = ide_rate_filter(pdcnew_ratemask(drive), xferspeed);
  118. if (speed == XFER_UDMA_2) {
  119. hwif->OUTB((thold + adj), indexreg);
  120. hwif->OUTB((hwif->INB(datareg) & 0x7f), datareg);
  121. }
  122. switch (speed) {
  123. case XFER_UDMA_7:
  124. speed = XFER_UDMA_6;
  125. case XFER_UDMA_6: set_ultra(0x1a, 0x01, 0xcb); break;
  126. case XFER_UDMA_5: set_ultra(0x1a, 0x02, 0xcb); break;
  127. case XFER_UDMA_4: set_ultra(0x1a, 0x03, 0xcd); break;
  128. case XFER_UDMA_3: set_ultra(0x1a, 0x05, 0xcd); break;
  129. case XFER_UDMA_2: set_ultra(0x2a, 0x07, 0xcd); break;
  130. case XFER_UDMA_1: set_ultra(0x3a, 0x0a, 0xd0); break;
  131. case XFER_UDMA_0: set_ultra(0x4a, 0x0f, 0xd5); break;
  132. case XFER_MW_DMA_2: set_ata2(0x69, 0x25); break;
  133. case XFER_MW_DMA_1: set_ata2(0x6b, 0x27); break;
  134. case XFER_MW_DMA_0: set_ata2(0xdf, 0x5f); break;
  135. case XFER_PIO_4: set_pio(0x23, 0x09, 0x25); break;
  136. case XFER_PIO_3: set_pio(0x27, 0x0d, 0x35); break;
  137. case XFER_PIO_2: set_pio(0x23, 0x26, 0x64); break;
  138. case XFER_PIO_1: set_pio(0x46, 0x29, 0xa4); break;
  139. case XFER_PIO_0: set_pio(0xfb, 0x2b, 0xac); break;
  140. default:
  141. ;
  142. }
  143. return (ide_config_drive_speed(drive, speed));
  144. }
  145. /* 0 1 2 3 4 5 6 7 8
  146. * 960, 480, 390, 300, 240, 180, 120, 90, 60
  147. * 180, 150, 120, 90, 60
  148. * DMA_Speed
  149. * 180, 120, 90, 90, 90, 60, 30
  150. * 11, 5, 4, 3, 2, 1, 0
  151. */
  152. static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
  153. {
  154. u8 speed;
  155. if (pio == 5) pio = 4;
  156. speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
  157. (void)pdcnew_new_tune_chipset(drive, speed);
  158. }
  159. static u8 pdcnew_new_cable_detect (ide_hwif_t *hwif)
  160. {
  161. hwif->OUTB(0x0b, hwif->dma_vendor1);
  162. return ((u8)((hwif->INB(hwif->dma_vendor3) & 0x04)));
  163. }
  164. static int config_chipset_for_dma (ide_drive_t *drive)
  165. {
  166. struct hd_driveid *id = drive->id;
  167. ide_hwif_t *hwif = HWIF(drive);
  168. u8 speed = -1;
  169. u8 cable;
  170. u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
  171. (id->dma_ultra & 0x0008)) ? 1 : 0;
  172. cable = pdcnew_new_cable_detect(hwif);
  173. if (ultra_66 && cable) {
  174. printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
  175. printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
  176. }
  177. if (drive->media != ide_disk)
  178. return 0;
  179. if (id->capability & 4) { /* IORDY_EN & PREFETCH_EN */
  180. hwif->OUTB((0x13 + ((drive->dn%2) ? 0x08 : 0x00)), hwif->dma_vendor1);
  181. hwif->OUTB((hwif->INB(hwif->dma_vendor3)|0x03), hwif->dma_vendor3);
  182. }
  183. speed = ide_dma_speed(drive, pdcnew_ratemask(drive));
  184. if (!(speed)) {
  185. hwif->tuneproc(drive, 5);
  186. return 0;
  187. }
  188. (void) hwif->speedproc(drive, speed);
  189. return ide_dma_enable(drive);
  190. }
  191. static int pdcnew_config_drive_xfer_rate (ide_drive_t *drive)
  192. {
  193. ide_hwif_t *hwif = HWIF(drive);
  194. struct hd_driveid *id = drive->id;
  195. drive->init_speed = 0;
  196. if (id && (id->capability & 1) && drive->autodma) {
  197. if (ide_use_dma(drive)) {
  198. if (config_chipset_for_dma(drive))
  199. return hwif->ide_dma_on(drive);
  200. }
  201. goto fast_ata_pio;
  202. } else if ((id->capability & 8) || (id->field_valid & 2)) {
  203. fast_ata_pio:
  204. hwif->tuneproc(drive, 5);
  205. return hwif->ide_dma_off_quietly(drive);
  206. }
  207. /* IORDY not supported */
  208. return 0;
  209. }
  210. static int pdcnew_quirkproc (ide_drive_t *drive)
  211. {
  212. return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
  213. }
  214. static int pdcnew_ide_dma_lostirq(ide_drive_t *drive)
  215. {
  216. if (HWIF(drive)->resetproc != NULL)
  217. HWIF(drive)->resetproc(drive);
  218. return __ide_dma_lostirq(drive);
  219. }
  220. static int pdcnew_ide_dma_timeout(ide_drive_t *drive)
  221. {
  222. if (HWIF(drive)->resetproc != NULL)
  223. HWIF(drive)->resetproc(drive);
  224. return __ide_dma_timeout(drive);
  225. }
  226. static void pdcnew_new_reset (ide_drive_t *drive)
  227. {
  228. /*
  229. * Deleted this because it is redundant from the caller.
  230. */
  231. printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
  232. HWIF(drive)->channel ? "Secondary" : "Primary");
  233. }
  234. #ifdef CONFIG_PPC_PMAC
  235. static void __devinit apple_kiwi_init(struct pci_dev *pdev)
  236. {
  237. struct device_node *np = pci_device_to_OF_node(pdev);
  238. unsigned int class_rev = 0;
  239. void __iomem *mmio;
  240. u8 conf;
  241. if (np == NULL || !device_is_compatible(np, "kiwi-root"))
  242. return;
  243. pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
  244. class_rev &= 0xff;
  245. if (class_rev >= 0x03) {
  246. /* Setup chip magic config stuff (from darwin) */
  247. pci_read_config_byte(pdev, 0x40, &conf);
  248. pci_write_config_byte(pdev, 0x40, conf | 0x01);
  249. }
  250. mmio = ioremap(pci_resource_start(pdev, 5),
  251. pci_resource_len(pdev, 5));
  252. /* Setup some PLL stuffs */
  253. switch (pdev->device) {
  254. case PCI_DEVICE_ID_PROMISE_20270:
  255. writew(0x0d2b, mmio + 0x1202);
  256. mdelay(30);
  257. break;
  258. case PCI_DEVICE_ID_PROMISE_20271:
  259. writew(0x0826, mmio + 0x1202);
  260. mdelay(30);
  261. break;
  262. }
  263. iounmap(mmio);
  264. }
  265. #endif /* CONFIG_PPC_PMAC */
  266. static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
  267. {
  268. if (dev->resource[PCI_ROM_RESOURCE].start) {
  269. pci_write_config_dword(dev, PCI_ROM_ADDRESS,
  270. dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
  271. printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
  272. name, dev->resource[PCI_ROM_RESOURCE].start);
  273. }
  274. #ifdef CONFIG_PPC_PMAC
  275. apple_kiwi_init(dev);
  276. #endif
  277. return dev->irq;
  278. }
  279. static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
  280. {
  281. hwif->autodma = 0;
  282. hwif->tuneproc = &pdcnew_tune_drive;
  283. hwif->quirkproc = &pdcnew_quirkproc;
  284. hwif->speedproc = &pdcnew_new_tune_chipset;
  285. hwif->resetproc = &pdcnew_new_reset;
  286. hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
  287. hwif->ultra_mask = 0x7f;
  288. hwif->mwdma_mask = 0x07;
  289. hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
  290. hwif->ide_dma_lostirq = &pdcnew_ide_dma_lostirq;
  291. hwif->ide_dma_timeout = &pdcnew_ide_dma_timeout;
  292. if (!(hwif->udma_four))
  293. hwif->udma_four = (pdcnew_new_cable_detect(hwif)) ? 0 : 1;
  294. if (!noautodma)
  295. hwif->autodma = 1;
  296. hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
  297. #if PDC202_DEBUG_CABLE
  298. printk(KERN_DEBUG "%s: %s-pin cable\n",
  299. hwif->name, hwif->udma_four ? "80" : "40");
  300. #endif /* PDC202_DEBUG_CABLE */
  301. }
  302. static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
  303. {
  304. return ide_setup_pci_device(dev, d);
  305. }
  306. static int __devinit init_setup_pdc20270(struct pci_dev *dev,
  307. ide_pci_device_t *d)
  308. {
  309. struct pci_dev *findev = NULL;
  310. if ((dev->bus->self &&
  311. dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
  312. (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
  313. if (PCI_SLOT(dev->devfn) & 2)
  314. return -ENODEV;
  315. d->extra = 0;
  316. while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
  317. if ((findev->vendor == dev->vendor) &&
  318. (findev->device == dev->device) &&
  319. (PCI_SLOT(findev->devfn) & 2)) {
  320. if (findev->irq != dev->irq) {
  321. findev->irq = dev->irq;
  322. }
  323. return ide_setup_pci_devices(dev, findev, d);
  324. }
  325. }
  326. }
  327. return ide_setup_pci_device(dev, d);
  328. }
  329. static int __devinit init_setup_pdc20276(struct pci_dev *dev,
  330. ide_pci_device_t *d)
  331. {
  332. if ((dev->bus->self) &&
  333. (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
  334. ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
  335. (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
  336. printk(KERN_INFO "ide: Skipping Promise PDC20276 "
  337. "attached to I2O RAID controller.\n");
  338. return -ENODEV;
  339. }
  340. return ide_setup_pci_device(dev, d);
  341. }
  342. static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
  343. { /* 0 */
  344. .name = "PDC20268",
  345. .init_setup = init_setup_pdcnew,
  346. .init_chipset = init_chipset_pdcnew,
  347. .init_hwif = init_hwif_pdc202new,
  348. .channels = 2,
  349. .autodma = AUTODMA,
  350. .bootable = OFF_BOARD,
  351. },{ /* 1 */
  352. .name = "PDC20269",
  353. .init_setup = init_setup_pdcnew,
  354. .init_chipset = init_chipset_pdcnew,
  355. .init_hwif = init_hwif_pdc202new,
  356. .channels = 2,
  357. .autodma = AUTODMA,
  358. .bootable = OFF_BOARD,
  359. },{ /* 2 */
  360. .name = "PDC20270",
  361. .init_setup = init_setup_pdc20270,
  362. .init_chipset = init_chipset_pdcnew,
  363. .init_hwif = init_hwif_pdc202new,
  364. .channels = 2,
  365. .autodma = AUTODMA,
  366. #ifndef CONFIG_PDC202XX_FORCE
  367. .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
  368. #endif
  369. .bootable = OFF_BOARD,
  370. },{ /* 3 */
  371. .name = "PDC20271",
  372. .init_setup = init_setup_pdcnew,
  373. .init_chipset = init_chipset_pdcnew,
  374. .init_hwif = init_hwif_pdc202new,
  375. .channels = 2,
  376. .autodma = AUTODMA,
  377. .bootable = OFF_BOARD,
  378. },{ /* 4 */
  379. .name = "PDC20275",
  380. .init_setup = init_setup_pdcnew,
  381. .init_chipset = init_chipset_pdcnew,
  382. .init_hwif = init_hwif_pdc202new,
  383. .channels = 2,
  384. .autodma = AUTODMA,
  385. .bootable = OFF_BOARD,
  386. },{ /* 5 */
  387. .name = "PDC20276",
  388. .init_setup = init_setup_pdc20276,
  389. .init_chipset = init_chipset_pdcnew,
  390. .init_hwif = init_hwif_pdc202new,
  391. .channels = 2,
  392. .autodma = AUTODMA,
  393. #ifndef CONFIG_PDC202XX_FORCE
  394. .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
  395. #endif
  396. .bootable = OFF_BOARD,
  397. },{ /* 6 */
  398. .name = "PDC20277",
  399. .init_setup = init_setup_pdcnew,
  400. .init_chipset = init_chipset_pdcnew,
  401. .init_hwif = init_hwif_pdc202new,
  402. .channels = 2,
  403. .autodma = AUTODMA,
  404. .bootable = OFF_BOARD,
  405. }
  406. };
  407. /**
  408. * pdc202new_init_one - called when a pdc202xx is found
  409. * @dev: the pdc202new device
  410. * @id: the matching pci id
  411. *
  412. * Called when the PCI registration layer (or the IDE initialization)
  413. * finds a device matching our IDE device tables.
  414. */
  415. static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  416. {
  417. ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
  418. return d->init_setup(dev, d);
  419. }
  420. static struct pci_device_id pdc202new_pci_tbl[] = {
  421. { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  422. { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
  423. { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
  424. { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
  425. { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
  426. { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
  427. { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
  428. { 0, },
  429. };
  430. MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
  431. static struct pci_driver driver = {
  432. .name = "Promise_IDE",
  433. .id_table = pdc202new_pci_tbl,
  434. .probe = pdc202new_init_one,
  435. };
  436. static int pdc202new_ide_init(void)
  437. {
  438. return ide_pci_register_driver(&driver);
  439. }
  440. module_init(pdc202new_ide_init);
  441. MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
  442. MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
  443. MODULE_LICENSE("GPL");