i810_dma.c 37 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/pagemap.h>
  39. #define I810_BUF_FREE 2
  40. #define I810_BUF_CLIENT 1
  41. #define I810_BUF_HARDWARE 0
  42. #define I810_BUF_UNMAPPED 0
  43. #define I810_BUF_MAPPED 1
  44. static drm_buf_t *i810_freelist_get(drm_device_t *dev)
  45. {
  46. drm_device_dma_t *dma = dev->dma;
  47. int i;
  48. int used;
  49. /* Linear search might not be the best solution */
  50. for (i = 0; i < dma->buf_count; i++) {
  51. drm_buf_t *buf = dma->buflist[ i ];
  52. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  53. /* In use is already a pointer */
  54. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  55. I810_BUF_CLIENT);
  56. if (used == I810_BUF_FREE) {
  57. return buf;
  58. }
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. drm_file_t *priv = filp->private_data;
  80. drm_device_t *dev;
  81. drm_i810_private_t *dev_priv;
  82. drm_buf_t *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. lock_kernel();
  85. dev = priv->head->dev;
  86. dev_priv = dev->dev_private;
  87. buf = dev_priv->mmap_buffer;
  88. buf_priv = buf->dev_private;
  89. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  90. vma->vm_file = filp;
  91. buf_priv->currently_mapped = I810_BUF_MAPPED;
  92. unlock_kernel();
  93. if (io_remap_pfn_range(vma, vma->vm_start,
  94. VM_OFFSET(vma) >> PAGE_SHIFT,
  95. vma->vm_end - vma->vm_start,
  96. vma->vm_page_prot)) return -EAGAIN;
  97. return 0;
  98. }
  99. static struct file_operations i810_buffer_fops = {
  100. .open = drm_open,
  101. .flush = drm_flush,
  102. .release = drm_release,
  103. .ioctl = drm_ioctl,
  104. .mmap = i810_mmap_buffers,
  105. .fasync = drm_fasync,
  106. };
  107. static int i810_map_buffer(drm_buf_t *buf, struct file *filp)
  108. {
  109. drm_file_t *priv = filp->private_data;
  110. drm_device_t *dev = priv->head->dev;
  111. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  112. drm_i810_private_t *dev_priv = dev->dev_private;
  113. struct file_operations *old_fops;
  114. int retcode = 0;
  115. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  116. return -EINVAL;
  117. down_write( &current->mm->mmap_sem );
  118. old_fops = filp->f_op;
  119. filp->f_op = &i810_buffer_fops;
  120. dev_priv->mmap_buffer = buf;
  121. buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total,
  122. PROT_READ|PROT_WRITE,
  123. MAP_SHARED,
  124. buf->bus_address);
  125. dev_priv->mmap_buffer = NULL;
  126. filp->f_op = old_fops;
  127. if ((unsigned long)buf_priv->virtual > -1024UL) {
  128. /* Real error */
  129. DRM_ERROR("mmap error\n");
  130. retcode = (signed int)buf_priv->virtual;
  131. buf_priv->virtual = NULL;
  132. }
  133. up_write( &current->mm->mmap_sem );
  134. return retcode;
  135. }
  136. static int i810_unmap_buffer(drm_buf_t *buf)
  137. {
  138. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  139. int retcode = 0;
  140. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  141. return -EINVAL;
  142. down_write(&current->mm->mmap_sem);
  143. retcode = do_munmap(current->mm,
  144. (unsigned long)buf_priv->virtual,
  145. (size_t) buf->total);
  146. up_write(&current->mm->mmap_sem);
  147. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  148. buf_priv->virtual = NULL;
  149. return retcode;
  150. }
  151. static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d,
  152. struct file *filp)
  153. {
  154. drm_buf_t *buf;
  155. drm_i810_buf_priv_t *buf_priv;
  156. int retcode = 0;
  157. buf = i810_freelist_get(dev);
  158. if (!buf) {
  159. retcode = -ENOMEM;
  160. DRM_DEBUG("retcode=%d\n", retcode);
  161. return retcode;
  162. }
  163. retcode = i810_map_buffer(buf, filp);
  164. if (retcode) {
  165. i810_freelist_put(dev, buf);
  166. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  167. return retcode;
  168. }
  169. buf->filp = filp;
  170. buf_priv = buf->dev_private;
  171. d->granted = 1;
  172. d->request_idx = buf->idx;
  173. d->request_size = buf->total;
  174. d->virtual = buf_priv->virtual;
  175. return retcode;
  176. }
  177. static int i810_dma_cleanup(drm_device_t *dev)
  178. {
  179. drm_device_dma_t *dma = dev->dma;
  180. /* Make sure interrupts are disabled here because the uninstall ioctl
  181. * may not have been called from userspace and after dev_private
  182. * is freed, it's too late.
  183. */
  184. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  185. drm_irq_uninstall(dev);
  186. if (dev->dev_private) {
  187. int i;
  188. drm_i810_private_t *dev_priv =
  189. (drm_i810_private_t *) dev->dev_private;
  190. if (dev_priv->ring.virtual_start) {
  191. drm_ioremapfree((void *) dev_priv->ring.virtual_start,
  192. dev_priv->ring.Size, dev);
  193. }
  194. if (dev_priv->hw_status_page) {
  195. pci_free_consistent(dev->pdev, PAGE_SIZE,
  196. dev_priv->hw_status_page,
  197. dev_priv->dma_status_page);
  198. /* Need to rewrite hardware status page */
  199. I810_WRITE(0x02080, 0x1ffff000);
  200. }
  201. drm_free(dev->dev_private, sizeof(drm_i810_private_t),
  202. DRM_MEM_DRIVER);
  203. dev->dev_private = NULL;
  204. for (i = 0; i < dma->buf_count; i++) {
  205. drm_buf_t *buf = dma->buflist[ i ];
  206. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  207. if ( buf_priv->kernel_virtual && buf->total )
  208. drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev);
  209. }
  210. }
  211. return 0;
  212. }
  213. static int i810_wait_ring(drm_device_t *dev, int n)
  214. {
  215. drm_i810_private_t *dev_priv = dev->dev_private;
  216. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  217. int iters = 0;
  218. unsigned long end;
  219. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  220. end = jiffies + (HZ*3);
  221. while (ring->space < n) {
  222. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  223. ring->space = ring->head - (ring->tail+8);
  224. if (ring->space < 0) ring->space += ring->Size;
  225. if (ring->head != last_head) {
  226. end = jiffies + (HZ*3);
  227. last_head = ring->head;
  228. }
  229. iters++;
  230. if (time_before(end, jiffies)) {
  231. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  232. DRM_ERROR("lockup\n");
  233. goto out_wait_ring;
  234. }
  235. udelay(1);
  236. }
  237. out_wait_ring:
  238. return iters;
  239. }
  240. static void i810_kernel_lost_context(drm_device_t *dev)
  241. {
  242. drm_i810_private_t *dev_priv = dev->dev_private;
  243. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  244. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  245. ring->tail = I810_READ(LP_RING + RING_TAIL);
  246. ring->space = ring->head - (ring->tail+8);
  247. if (ring->space < 0) ring->space += ring->Size;
  248. }
  249. static int i810_freelist_init(drm_device_t *dev, drm_i810_private_t *dev_priv)
  250. {
  251. drm_device_dma_t *dma = dev->dma;
  252. int my_idx = 24;
  253. u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx);
  254. int i;
  255. if (dma->buf_count > 1019) {
  256. /* Not enough space in the status page for the freelist */
  257. return -EINVAL;
  258. }
  259. for (i = 0; i < dma->buf_count; i++) {
  260. drm_buf_t *buf = dma->buflist[ i ];
  261. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  262. buf_priv->in_use = hw_status++;
  263. buf_priv->my_use_idx = my_idx;
  264. my_idx += 4;
  265. *buf_priv->in_use = I810_BUF_FREE;
  266. buf_priv->kernel_virtual = drm_ioremap(buf->bus_address,
  267. buf->total, dev);
  268. }
  269. return 0;
  270. }
  271. static int i810_dma_initialize(drm_device_t *dev,
  272. drm_i810_private_t *dev_priv,
  273. drm_i810_init_t *init)
  274. {
  275. struct list_head *list;
  276. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  277. list_for_each(list, &dev->maplist->head) {
  278. drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
  279. if (r_list->map &&
  280. r_list->map->type == _DRM_SHM &&
  281. r_list->map->flags & _DRM_CONTAINS_LOCK ) {
  282. dev_priv->sarea_map = r_list->map;
  283. break;
  284. }
  285. }
  286. if (!dev_priv->sarea_map) {
  287. dev->dev_private = (void *)dev_priv;
  288. i810_dma_cleanup(dev);
  289. DRM_ERROR("can not find sarea!\n");
  290. return -EINVAL;
  291. }
  292. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  293. if (!dev_priv->mmio_map) {
  294. dev->dev_private = (void *)dev_priv;
  295. i810_dma_cleanup(dev);
  296. DRM_ERROR("can not find mmio map!\n");
  297. return -EINVAL;
  298. }
  299. dev->agp_buffer_token = init->buffers_offset;
  300. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  301. if (!dev->agp_buffer_map) {
  302. dev->dev_private = (void *)dev_priv;
  303. i810_dma_cleanup(dev);
  304. DRM_ERROR("can not find dma buffer map!\n");
  305. return -EINVAL;
  306. }
  307. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  308. ((u8 *)dev_priv->sarea_map->handle +
  309. init->sarea_priv_offset);
  310. dev_priv->ring.Start = init->ring_start;
  311. dev_priv->ring.End = init->ring_end;
  312. dev_priv->ring.Size = init->ring_size;
  313. dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base +
  314. init->ring_start,
  315. init->ring_size, dev);
  316. if (dev_priv->ring.virtual_start == NULL) {
  317. dev->dev_private = (void *) dev_priv;
  318. i810_dma_cleanup(dev);
  319. DRM_ERROR("can not ioremap virtual address for"
  320. " ring buffer\n");
  321. return -ENOMEM;
  322. }
  323. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  324. dev_priv->w = init->w;
  325. dev_priv->h = init->h;
  326. dev_priv->pitch = init->pitch;
  327. dev_priv->back_offset = init->back_offset;
  328. dev_priv->depth_offset = init->depth_offset;
  329. dev_priv->front_offset = init->front_offset;
  330. dev_priv->overlay_offset = init->overlay_offset;
  331. dev_priv->overlay_physical = init->overlay_physical;
  332. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  333. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  334. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  335. /* Program Hardware Status Page */
  336. dev_priv->hw_status_page =
  337. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  338. &dev_priv->dma_status_page);
  339. if (!dev_priv->hw_status_page) {
  340. dev->dev_private = (void *)dev_priv;
  341. i810_dma_cleanup(dev);
  342. DRM_ERROR("Can not allocate hardware status page\n");
  343. return -ENOMEM;
  344. }
  345. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  346. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  347. I810_WRITE(0x02080, dev_priv->dma_status_page);
  348. DRM_DEBUG("Enabled hardware status page\n");
  349. /* Now we need to init our freelist */
  350. if (i810_freelist_init(dev, dev_priv) != 0) {
  351. dev->dev_private = (void *)dev_priv;
  352. i810_dma_cleanup(dev);
  353. DRM_ERROR("Not enough space in the status page for"
  354. " the freelist\n");
  355. return -ENOMEM;
  356. }
  357. dev->dev_private = (void *)dev_priv;
  358. return 0;
  359. }
  360. /* i810 DRM version 1.1 used a smaller init structure with different
  361. * ordering of values than is currently used (drm >= 1.2). There is
  362. * no defined way to detect the XFree version to correct this problem,
  363. * however by checking using this procedure we can detect the correct
  364. * thing to do.
  365. *
  366. * #1 Read the Smaller init structure from user-space
  367. * #2 Verify the overlay_physical is a valid physical address, or NULL
  368. * If it isn't then we have a v1.1 client. Fix up params.
  369. * If it is, then we have a 1.2 client... get the rest of the data.
  370. */
  371. static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg)
  372. {
  373. /* Get v1.1 init data */
  374. if (copy_from_user(init, (drm_i810_pre12_init_t __user *)arg,
  375. sizeof(drm_i810_pre12_init_t))) {
  376. return -EFAULT;
  377. }
  378. if ((!init->overlay_physical) || (init->overlay_physical > 4096)) {
  379. /* This is a v1.2 client, just get the v1.2 init data */
  380. DRM_INFO("Using POST v1.2 init.\n");
  381. if (copy_from_user(init, (drm_i810_init_t __user *)arg,
  382. sizeof(drm_i810_init_t))) {
  383. return -EFAULT;
  384. }
  385. } else {
  386. /* This is a v1.1 client, fix the params */
  387. DRM_INFO("Using PRE v1.2 init.\n");
  388. init->pitch_bits = init->h;
  389. init->pitch = init->w;
  390. init->h = init->overlay_physical;
  391. init->w = init->overlay_offset;
  392. init->overlay_physical = 0;
  393. init->overlay_offset = 0;
  394. }
  395. return 0;
  396. }
  397. static int i810_dma_init(struct inode *inode, struct file *filp,
  398. unsigned int cmd, unsigned long arg)
  399. {
  400. drm_file_t *priv = filp->private_data;
  401. drm_device_t *dev = priv->head->dev;
  402. drm_i810_private_t *dev_priv;
  403. drm_i810_init_t init;
  404. int retcode = 0;
  405. /* Get only the init func */
  406. if (copy_from_user(&init, (void __user *)arg, sizeof(drm_i810_init_func_t)))
  407. return -EFAULT;
  408. switch(init.func) {
  409. case I810_INIT_DMA:
  410. /* This case is for backward compatibility. It
  411. * handles XFree 4.1.0 and 4.2.0, and has to
  412. * do some parameter checking as described below.
  413. * It will someday go away.
  414. */
  415. retcode = i810_dma_init_compat(&init, arg);
  416. if (retcode)
  417. return retcode;
  418. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  419. DRM_MEM_DRIVER);
  420. if (dev_priv == NULL)
  421. return -ENOMEM;
  422. retcode = i810_dma_initialize(dev, dev_priv, &init);
  423. break;
  424. default:
  425. case I810_INIT_DMA_1_4:
  426. DRM_INFO("Using v1.4 init.\n");
  427. if (copy_from_user(&init, (drm_i810_init_t __user *)arg,
  428. sizeof(drm_i810_init_t))) {
  429. return -EFAULT;
  430. }
  431. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  432. DRM_MEM_DRIVER);
  433. if (dev_priv == NULL)
  434. return -ENOMEM;
  435. retcode = i810_dma_initialize(dev, dev_priv, &init);
  436. break;
  437. case I810_CLEANUP_DMA:
  438. DRM_INFO("DMA Cleanup\n");
  439. retcode = i810_dma_cleanup(dev);
  440. break;
  441. }
  442. return retcode;
  443. }
  444. /* Most efficient way to verify state for the i810 is as it is
  445. * emitted. Non-conformant state is silently dropped.
  446. *
  447. * Use 'volatile' & local var tmp to force the emitted values to be
  448. * identical to the verified ones.
  449. */
  450. static void i810EmitContextVerified( drm_device_t *dev,
  451. volatile unsigned int *code )
  452. {
  453. drm_i810_private_t *dev_priv = dev->dev_private;
  454. int i, j = 0;
  455. unsigned int tmp;
  456. RING_LOCALS;
  457. BEGIN_LP_RING( I810_CTX_SETUP_SIZE );
  458. OUT_RING( GFX_OP_COLOR_FACTOR );
  459. OUT_RING( code[I810_CTXREG_CF1] );
  460. OUT_RING( GFX_OP_STIPPLE );
  461. OUT_RING( code[I810_CTXREG_ST1] );
  462. for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) {
  463. tmp = code[i];
  464. if ((tmp & (7<<29)) == (3<<29) &&
  465. (tmp & (0x1f<<24)) < (0x1d<<24))
  466. {
  467. OUT_RING( tmp );
  468. j++;
  469. }
  470. else printk("constext state dropped!!!\n");
  471. }
  472. if (j & 1)
  473. OUT_RING( 0 );
  474. ADVANCE_LP_RING();
  475. }
  476. static void i810EmitTexVerified( drm_device_t *dev,
  477. volatile unsigned int *code )
  478. {
  479. drm_i810_private_t *dev_priv = dev->dev_private;
  480. int i, j = 0;
  481. unsigned int tmp;
  482. RING_LOCALS;
  483. BEGIN_LP_RING( I810_TEX_SETUP_SIZE );
  484. OUT_RING( GFX_OP_MAP_INFO );
  485. OUT_RING( code[I810_TEXREG_MI1] );
  486. OUT_RING( code[I810_TEXREG_MI2] );
  487. OUT_RING( code[I810_TEXREG_MI3] );
  488. for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) {
  489. tmp = code[i];
  490. if ((tmp & (7<<29)) == (3<<29) &&
  491. (tmp & (0x1f<<24)) < (0x1d<<24))
  492. {
  493. OUT_RING( tmp );
  494. j++;
  495. }
  496. else printk("texture state dropped!!!\n");
  497. }
  498. if (j & 1)
  499. OUT_RING( 0 );
  500. ADVANCE_LP_RING();
  501. }
  502. /* Need to do some additional checking when setting the dest buffer.
  503. */
  504. static void i810EmitDestVerified( drm_device_t *dev,
  505. volatile unsigned int *code )
  506. {
  507. drm_i810_private_t *dev_priv = dev->dev_private;
  508. unsigned int tmp;
  509. RING_LOCALS;
  510. BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 );
  511. tmp = code[I810_DESTREG_DI1];
  512. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  513. OUT_RING( CMD_OP_DESTBUFFER_INFO );
  514. OUT_RING( tmp );
  515. } else
  516. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  517. tmp, dev_priv->front_di1, dev_priv->back_di1);
  518. /* invarient:
  519. */
  520. OUT_RING( CMD_OP_Z_BUFFER_INFO );
  521. OUT_RING( dev_priv->zi1 );
  522. OUT_RING( GFX_OP_DESTBUFFER_VARS );
  523. OUT_RING( code[I810_DESTREG_DV1] );
  524. OUT_RING( GFX_OP_DRAWRECT_INFO );
  525. OUT_RING( code[I810_DESTREG_DR1] );
  526. OUT_RING( code[I810_DESTREG_DR2] );
  527. OUT_RING( code[I810_DESTREG_DR3] );
  528. OUT_RING( code[I810_DESTREG_DR4] );
  529. OUT_RING( 0 );
  530. ADVANCE_LP_RING();
  531. }
  532. static void i810EmitState( drm_device_t *dev )
  533. {
  534. drm_i810_private_t *dev_priv = dev->dev_private;
  535. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  536. unsigned int dirty = sarea_priv->dirty;
  537. DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
  538. if (dirty & I810_UPLOAD_BUFFERS) {
  539. i810EmitDestVerified( dev, sarea_priv->BufferState );
  540. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  541. }
  542. if (dirty & I810_UPLOAD_CTX) {
  543. i810EmitContextVerified( dev, sarea_priv->ContextState );
  544. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  545. }
  546. if (dirty & I810_UPLOAD_TEX0) {
  547. i810EmitTexVerified( dev, sarea_priv->TexState[0] );
  548. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  549. }
  550. if (dirty & I810_UPLOAD_TEX1) {
  551. i810EmitTexVerified( dev, sarea_priv->TexState[1] );
  552. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  553. }
  554. }
  555. /* need to verify
  556. */
  557. static void i810_dma_dispatch_clear( drm_device_t *dev, int flags,
  558. unsigned int clear_color,
  559. unsigned int clear_zval )
  560. {
  561. drm_i810_private_t *dev_priv = dev->dev_private;
  562. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  563. int nbox = sarea_priv->nbox;
  564. drm_clip_rect_t *pbox = sarea_priv->boxes;
  565. int pitch = dev_priv->pitch;
  566. int cpp = 2;
  567. int i;
  568. RING_LOCALS;
  569. if ( dev_priv->current_page == 1 ) {
  570. unsigned int tmp = flags;
  571. flags &= ~(I810_FRONT | I810_BACK);
  572. if (tmp & I810_FRONT) flags |= I810_BACK;
  573. if (tmp & I810_BACK) flags |= I810_FRONT;
  574. }
  575. i810_kernel_lost_context(dev);
  576. if (nbox > I810_NR_SAREA_CLIPRECTS)
  577. nbox = I810_NR_SAREA_CLIPRECTS;
  578. for (i = 0 ; i < nbox ; i++, pbox++) {
  579. unsigned int x = pbox->x1;
  580. unsigned int y = pbox->y1;
  581. unsigned int width = (pbox->x2 - x) * cpp;
  582. unsigned int height = pbox->y2 - y;
  583. unsigned int start = y * pitch + x * cpp;
  584. if (pbox->x1 > pbox->x2 ||
  585. pbox->y1 > pbox->y2 ||
  586. pbox->x2 > dev_priv->w ||
  587. pbox->y2 > dev_priv->h)
  588. continue;
  589. if ( flags & I810_FRONT ) {
  590. BEGIN_LP_RING( 6 );
  591. OUT_RING( BR00_BITBLT_CLIENT |
  592. BR00_OP_COLOR_BLT | 0x3 );
  593. OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
  594. OUT_RING( (height << 16) | width );
  595. OUT_RING( start );
  596. OUT_RING( clear_color );
  597. OUT_RING( 0 );
  598. ADVANCE_LP_RING();
  599. }
  600. if ( flags & I810_BACK ) {
  601. BEGIN_LP_RING( 6 );
  602. OUT_RING( BR00_BITBLT_CLIENT |
  603. BR00_OP_COLOR_BLT | 0x3 );
  604. OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
  605. OUT_RING( (height << 16) | width );
  606. OUT_RING( dev_priv->back_offset + start );
  607. OUT_RING( clear_color );
  608. OUT_RING( 0 );
  609. ADVANCE_LP_RING();
  610. }
  611. if ( flags & I810_DEPTH ) {
  612. BEGIN_LP_RING( 6 );
  613. OUT_RING( BR00_BITBLT_CLIENT |
  614. BR00_OP_COLOR_BLT | 0x3 );
  615. OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
  616. OUT_RING( (height << 16) | width );
  617. OUT_RING( dev_priv->depth_offset + start );
  618. OUT_RING( clear_zval );
  619. OUT_RING( 0 );
  620. ADVANCE_LP_RING();
  621. }
  622. }
  623. }
  624. static void i810_dma_dispatch_swap( drm_device_t *dev )
  625. {
  626. drm_i810_private_t *dev_priv = dev->dev_private;
  627. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  628. int nbox = sarea_priv->nbox;
  629. drm_clip_rect_t *pbox = sarea_priv->boxes;
  630. int pitch = dev_priv->pitch;
  631. int cpp = 2;
  632. int i;
  633. RING_LOCALS;
  634. DRM_DEBUG("swapbuffers\n");
  635. i810_kernel_lost_context(dev);
  636. if (nbox > I810_NR_SAREA_CLIPRECTS)
  637. nbox = I810_NR_SAREA_CLIPRECTS;
  638. for (i = 0 ; i < nbox; i++, pbox++)
  639. {
  640. unsigned int w = pbox->x2 - pbox->x1;
  641. unsigned int h = pbox->y2 - pbox->y1;
  642. unsigned int dst = pbox->x1*cpp + pbox->y1*pitch;
  643. unsigned int start = dst;
  644. if (pbox->x1 > pbox->x2 ||
  645. pbox->y1 > pbox->y2 ||
  646. pbox->x2 > dev_priv->w ||
  647. pbox->y2 > dev_priv->h)
  648. continue;
  649. BEGIN_LP_RING( 6 );
  650. OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 );
  651. OUT_RING( pitch | (0xCC << 16));
  652. OUT_RING( (h << 16) | (w * cpp));
  653. if (dev_priv->current_page == 0)
  654. OUT_RING(dev_priv->front_offset + start);
  655. else
  656. OUT_RING(dev_priv->back_offset + start);
  657. OUT_RING( pitch );
  658. if (dev_priv->current_page == 0)
  659. OUT_RING(dev_priv->back_offset + start);
  660. else
  661. OUT_RING(dev_priv->front_offset + start);
  662. ADVANCE_LP_RING();
  663. }
  664. }
  665. static void i810_dma_dispatch_vertex(drm_device_t *dev,
  666. drm_buf_t *buf,
  667. int discard,
  668. int used)
  669. {
  670. drm_i810_private_t *dev_priv = dev->dev_private;
  671. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  672. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  673. drm_clip_rect_t *box = sarea_priv->boxes;
  674. int nbox = sarea_priv->nbox;
  675. unsigned long address = (unsigned long)buf->bus_address;
  676. unsigned long start = address - dev->agp->base;
  677. int i = 0;
  678. RING_LOCALS;
  679. i810_kernel_lost_context(dev);
  680. if (nbox > I810_NR_SAREA_CLIPRECTS)
  681. nbox = I810_NR_SAREA_CLIPRECTS;
  682. if (used > 4*1024)
  683. used = 0;
  684. if (sarea_priv->dirty)
  685. i810EmitState( dev );
  686. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  687. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  688. *(u32 *)buf_priv->kernel_virtual = ((GFX_OP_PRIMITIVE | prim | ((used/4)-2)));
  689. if (used & 4) {
  690. *(u32 *)((u32)buf_priv->kernel_virtual + used) = 0;
  691. used += 4;
  692. }
  693. i810_unmap_buffer(buf);
  694. }
  695. if (used) {
  696. do {
  697. if (i < nbox) {
  698. BEGIN_LP_RING(4);
  699. OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  700. SC_ENABLE );
  701. OUT_RING( GFX_OP_SCISSOR_INFO );
  702. OUT_RING( box[i].x1 | (box[i].y1<<16) );
  703. OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) );
  704. ADVANCE_LP_RING();
  705. }
  706. BEGIN_LP_RING(4);
  707. OUT_RING( CMD_OP_BATCH_BUFFER );
  708. OUT_RING( start | BB1_PROTECTED );
  709. OUT_RING( start + used - 4 );
  710. OUT_RING( 0 );
  711. ADVANCE_LP_RING();
  712. } while (++i < nbox);
  713. }
  714. if (discard) {
  715. dev_priv->counter++;
  716. (void) cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  717. I810_BUF_HARDWARE);
  718. BEGIN_LP_RING(8);
  719. OUT_RING( CMD_STORE_DWORD_IDX );
  720. OUT_RING( 20 );
  721. OUT_RING( dev_priv->counter );
  722. OUT_RING( CMD_STORE_DWORD_IDX );
  723. OUT_RING( buf_priv->my_use_idx );
  724. OUT_RING( I810_BUF_FREE );
  725. OUT_RING( CMD_REPORT_HEAD );
  726. OUT_RING( 0 );
  727. ADVANCE_LP_RING();
  728. }
  729. }
  730. static void i810_dma_dispatch_flip( drm_device_t *dev )
  731. {
  732. drm_i810_private_t *dev_priv = dev->dev_private;
  733. int pitch = dev_priv->pitch;
  734. RING_LOCALS;
  735. DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
  736. __FUNCTION__,
  737. dev_priv->current_page,
  738. dev_priv->sarea_priv->pf_current_page);
  739. i810_kernel_lost_context(dev);
  740. BEGIN_LP_RING( 2 );
  741. OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
  742. OUT_RING( 0 );
  743. ADVANCE_LP_RING();
  744. BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 );
  745. /* On i815 at least ASYNC is buggy */
  746. /* pitch<<5 is from 11.2.8 p158,
  747. its the pitch / 8 then left shifted 8,
  748. so (pitch >> 3) << 8 */
  749. OUT_RING( CMD_OP_FRONTBUFFER_INFO | (pitch<<5) /*| ASYNC_FLIP */ );
  750. if ( dev_priv->current_page == 0 ) {
  751. OUT_RING( dev_priv->back_offset );
  752. dev_priv->current_page = 1;
  753. } else {
  754. OUT_RING( dev_priv->front_offset );
  755. dev_priv->current_page = 0;
  756. }
  757. OUT_RING(0);
  758. ADVANCE_LP_RING();
  759. BEGIN_LP_RING(2);
  760. OUT_RING( CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP );
  761. OUT_RING( 0 );
  762. ADVANCE_LP_RING();
  763. /* Increment the frame counter. The client-side 3D driver must
  764. * throttle the framerate by waiting for this value before
  765. * performing the swapbuffer ioctl.
  766. */
  767. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  768. }
  769. static void i810_dma_quiescent(drm_device_t *dev)
  770. {
  771. drm_i810_private_t *dev_priv = dev->dev_private;
  772. RING_LOCALS;
  773. /* printk("%s\n", __FUNCTION__); */
  774. i810_kernel_lost_context(dev);
  775. BEGIN_LP_RING(4);
  776. OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
  777. OUT_RING( CMD_REPORT_HEAD );
  778. OUT_RING( 0 );
  779. OUT_RING( 0 );
  780. ADVANCE_LP_RING();
  781. i810_wait_ring( dev, dev_priv->ring.Size - 8 );
  782. }
  783. static int i810_flush_queue(drm_device_t *dev)
  784. {
  785. drm_i810_private_t *dev_priv = dev->dev_private;
  786. drm_device_dma_t *dma = dev->dma;
  787. int i, ret = 0;
  788. RING_LOCALS;
  789. /* printk("%s\n", __FUNCTION__); */
  790. i810_kernel_lost_context(dev);
  791. BEGIN_LP_RING(2);
  792. OUT_RING( CMD_REPORT_HEAD );
  793. OUT_RING( 0 );
  794. ADVANCE_LP_RING();
  795. i810_wait_ring( dev, dev_priv->ring.Size - 8 );
  796. for (i = 0; i < dma->buf_count; i++) {
  797. drm_buf_t *buf = dma->buflist[ i ];
  798. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  799. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  800. I810_BUF_FREE);
  801. if (used == I810_BUF_HARDWARE)
  802. DRM_DEBUG("reclaimed from HARDWARE\n");
  803. if (used == I810_BUF_CLIENT)
  804. DRM_DEBUG("still on client\n");
  805. }
  806. return ret;
  807. }
  808. /* Must be called with the lock held */
  809. void i810_reclaim_buffers(drm_device_t *dev, struct file *filp)
  810. {
  811. drm_device_dma_t *dma = dev->dma;
  812. int i;
  813. if (!dma) return;
  814. if (!dev->dev_private) return;
  815. if (!dma->buflist) return;
  816. i810_flush_queue(dev);
  817. for (i = 0; i < dma->buf_count; i++) {
  818. drm_buf_t *buf = dma->buflist[ i ];
  819. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  820. if (buf->filp == filp && buf_priv) {
  821. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  822. I810_BUF_FREE);
  823. if (used == I810_BUF_CLIENT)
  824. DRM_DEBUG("reclaimed from client\n");
  825. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  826. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  827. }
  828. }
  829. }
  830. static int i810_flush_ioctl(struct inode *inode, struct file *filp,
  831. unsigned int cmd, unsigned long arg)
  832. {
  833. drm_file_t *priv = filp->private_data;
  834. drm_device_t *dev = priv->head->dev;
  835. LOCK_TEST_WITH_RETURN(dev, filp);
  836. i810_flush_queue(dev);
  837. return 0;
  838. }
  839. static int i810_dma_vertex(struct inode *inode, struct file *filp,
  840. unsigned int cmd, unsigned long arg)
  841. {
  842. drm_file_t *priv = filp->private_data;
  843. drm_device_t *dev = priv->head->dev;
  844. drm_device_dma_t *dma = dev->dma;
  845. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  846. u32 *hw_status = dev_priv->hw_status_page;
  847. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  848. dev_priv->sarea_priv;
  849. drm_i810_vertex_t vertex;
  850. if (copy_from_user(&vertex, (drm_i810_vertex_t __user *)arg, sizeof(vertex)))
  851. return -EFAULT;
  852. LOCK_TEST_WITH_RETURN(dev, filp);
  853. DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
  854. vertex.idx, vertex.used, vertex.discard);
  855. if (vertex.idx < 0 || vertex.idx > dma->buf_count)
  856. return -EINVAL;
  857. i810_dma_dispatch_vertex( dev,
  858. dma->buflist[ vertex.idx ],
  859. vertex.discard, vertex.used );
  860. atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
  861. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  862. sarea_priv->last_enqueue = dev_priv->counter-1;
  863. sarea_priv->last_dispatch = (int) hw_status[5];
  864. return 0;
  865. }
  866. static int i810_clear_bufs(struct inode *inode, struct file *filp,
  867. unsigned int cmd, unsigned long arg)
  868. {
  869. drm_file_t *priv = filp->private_data;
  870. drm_device_t *dev = priv->head->dev;
  871. drm_i810_clear_t clear;
  872. if (copy_from_user(&clear, (drm_i810_clear_t __user *)arg, sizeof(clear)))
  873. return -EFAULT;
  874. LOCK_TEST_WITH_RETURN(dev, filp);
  875. /* GH: Someone's doing nasty things... */
  876. if (!dev->dev_private) {
  877. return -EINVAL;
  878. }
  879. i810_dma_dispatch_clear( dev, clear.flags,
  880. clear.clear_color,
  881. clear.clear_depth );
  882. return 0;
  883. }
  884. static int i810_swap_bufs(struct inode *inode, struct file *filp,
  885. unsigned int cmd, unsigned long arg)
  886. {
  887. drm_file_t *priv = filp->private_data;
  888. drm_device_t *dev = priv->head->dev;
  889. DRM_DEBUG("i810_swap_bufs\n");
  890. LOCK_TEST_WITH_RETURN(dev, filp);
  891. i810_dma_dispatch_swap( dev );
  892. return 0;
  893. }
  894. static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
  895. unsigned long arg)
  896. {
  897. drm_file_t *priv = filp->private_data;
  898. drm_device_t *dev = priv->head->dev;
  899. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  900. u32 *hw_status = dev_priv->hw_status_page;
  901. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  902. dev_priv->sarea_priv;
  903. sarea_priv->last_dispatch = (int) hw_status[5];
  904. return 0;
  905. }
  906. static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
  907. unsigned long arg)
  908. {
  909. drm_file_t *priv = filp->private_data;
  910. drm_device_t *dev = priv->head->dev;
  911. int retcode = 0;
  912. drm_i810_dma_t d;
  913. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  914. u32 *hw_status = dev_priv->hw_status_page;
  915. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  916. dev_priv->sarea_priv;
  917. if (copy_from_user(&d, (drm_i810_dma_t __user *)arg, sizeof(d)))
  918. return -EFAULT;
  919. LOCK_TEST_WITH_RETURN(dev, filp);
  920. d.granted = 0;
  921. retcode = i810_dma_get_buffer(dev, &d, filp);
  922. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  923. current->pid, retcode, d.granted);
  924. if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d)))
  925. return -EFAULT;
  926. sarea_priv->last_dispatch = (int) hw_status[5];
  927. return retcode;
  928. }
  929. static int i810_copybuf(struct inode *inode,
  930. struct file *filp, unsigned int cmd, unsigned long arg)
  931. {
  932. /* Never copy - 2.4.x doesn't need it */
  933. return 0;
  934. }
  935. static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
  936. unsigned long arg)
  937. {
  938. /* Never copy - 2.4.x doesn't need it */
  939. return 0;
  940. }
  941. static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used,
  942. unsigned int last_render)
  943. {
  944. drm_i810_private_t *dev_priv = dev->dev_private;
  945. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  946. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  947. unsigned long address = (unsigned long)buf->bus_address;
  948. unsigned long start = address - dev->agp->base;
  949. int u;
  950. RING_LOCALS;
  951. i810_kernel_lost_context(dev);
  952. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  953. I810_BUF_HARDWARE);
  954. if (u != I810_BUF_CLIENT) {
  955. DRM_DEBUG("MC found buffer that isn't mine!\n");
  956. }
  957. if (used > 4*1024)
  958. used = 0;
  959. sarea_priv->dirty = 0x7f;
  960. DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n",
  961. address, used);
  962. dev_priv->counter++;
  963. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  964. DRM_DEBUG("i810_dma_dispatch_mc\n");
  965. DRM_DEBUG("start : %lx\n", start);
  966. DRM_DEBUG("used : %d\n", used);
  967. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  968. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  969. if (used & 4) {
  970. *(u32 *)((u32)buf_priv->virtual + used) = 0;
  971. used += 4;
  972. }
  973. i810_unmap_buffer(buf);
  974. }
  975. BEGIN_LP_RING(4);
  976. OUT_RING( CMD_OP_BATCH_BUFFER );
  977. OUT_RING( start | BB1_PROTECTED );
  978. OUT_RING( start + used - 4 );
  979. OUT_RING( 0 );
  980. ADVANCE_LP_RING();
  981. BEGIN_LP_RING(8);
  982. OUT_RING( CMD_STORE_DWORD_IDX );
  983. OUT_RING( buf_priv->my_use_idx );
  984. OUT_RING( I810_BUF_FREE );
  985. OUT_RING( 0 );
  986. OUT_RING( CMD_STORE_DWORD_IDX );
  987. OUT_RING( 16 );
  988. OUT_RING( last_render );
  989. OUT_RING( 0 );
  990. ADVANCE_LP_RING();
  991. }
  992. static int i810_dma_mc(struct inode *inode, struct file *filp,
  993. unsigned int cmd, unsigned long arg)
  994. {
  995. drm_file_t *priv = filp->private_data;
  996. drm_device_t *dev = priv->head->dev;
  997. drm_device_dma_t *dma = dev->dma;
  998. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  999. u32 *hw_status = dev_priv->hw_status_page;
  1000. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  1001. dev_priv->sarea_priv;
  1002. drm_i810_mc_t mc;
  1003. if (copy_from_user(&mc, (drm_i810_mc_t __user *)arg, sizeof(mc)))
  1004. return -EFAULT;
  1005. LOCK_TEST_WITH_RETURN(dev, filp);
  1006. if (mc.idx >= dma->buf_count || mc.idx < 0)
  1007. return -EINVAL;
  1008. i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used,
  1009. mc.last_render );
  1010. atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]);
  1011. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  1012. sarea_priv->last_enqueue = dev_priv->counter-1;
  1013. sarea_priv->last_dispatch = (int) hw_status[5];
  1014. return 0;
  1015. }
  1016. static int i810_rstatus(struct inode *inode, struct file *filp,
  1017. unsigned int cmd, unsigned long arg)
  1018. {
  1019. drm_file_t *priv = filp->private_data;
  1020. drm_device_t *dev = priv->head->dev;
  1021. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1022. return (int)(((u32 *)(dev_priv->hw_status_page))[4]);
  1023. }
  1024. static int i810_ov0_info(struct inode *inode, struct file *filp,
  1025. unsigned int cmd, unsigned long arg)
  1026. {
  1027. drm_file_t *priv = filp->private_data;
  1028. drm_device_t *dev = priv->head->dev;
  1029. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1030. drm_i810_overlay_t data;
  1031. data.offset = dev_priv->overlay_offset;
  1032. data.physical = dev_priv->overlay_physical;
  1033. if (copy_to_user((drm_i810_overlay_t __user *)arg,&data,sizeof(data)))
  1034. return -EFAULT;
  1035. return 0;
  1036. }
  1037. static int i810_fstatus(struct inode *inode, struct file *filp,
  1038. unsigned int cmd, unsigned long arg)
  1039. {
  1040. drm_file_t *priv = filp->private_data;
  1041. drm_device_t *dev = priv->head->dev;
  1042. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1043. LOCK_TEST_WITH_RETURN(dev, filp);
  1044. return I810_READ(0x30008);
  1045. }
  1046. static int i810_ov0_flip(struct inode *inode, struct file *filp,
  1047. unsigned int cmd, unsigned long arg)
  1048. {
  1049. drm_file_t *priv = filp->private_data;
  1050. drm_device_t *dev = priv->head->dev;
  1051. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1052. LOCK_TEST_WITH_RETURN(dev, filp);
  1053. //Tell the overlay to update
  1054. I810_WRITE(0x30000,dev_priv->overlay_physical | 0x80000000);
  1055. return 0;
  1056. }
  1057. /* Not sure why this isn't set all the time:
  1058. */
  1059. static void i810_do_init_pageflip( drm_device_t *dev )
  1060. {
  1061. drm_i810_private_t *dev_priv = dev->dev_private;
  1062. DRM_DEBUG("%s\n", __FUNCTION__);
  1063. dev_priv->page_flipping = 1;
  1064. dev_priv->current_page = 0;
  1065. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  1066. }
  1067. static int i810_do_cleanup_pageflip( drm_device_t *dev )
  1068. {
  1069. drm_i810_private_t *dev_priv = dev->dev_private;
  1070. DRM_DEBUG("%s\n", __FUNCTION__);
  1071. if (dev_priv->current_page != 0)
  1072. i810_dma_dispatch_flip( dev );
  1073. dev_priv->page_flipping = 0;
  1074. return 0;
  1075. }
  1076. static int i810_flip_bufs(struct inode *inode, struct file *filp,
  1077. unsigned int cmd, unsigned long arg)
  1078. {
  1079. drm_file_t *priv = filp->private_data;
  1080. drm_device_t *dev = priv->head->dev;
  1081. drm_i810_private_t *dev_priv = dev->dev_private;
  1082. DRM_DEBUG("%s\n", __FUNCTION__);
  1083. LOCK_TEST_WITH_RETURN(dev, filp);
  1084. if (!dev_priv->page_flipping)
  1085. i810_do_init_pageflip( dev );
  1086. i810_dma_dispatch_flip( dev );
  1087. return 0;
  1088. }
  1089. void i810_driver_pretakedown(drm_device_t *dev)
  1090. {
  1091. i810_dma_cleanup( dev );
  1092. }
  1093. void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp)
  1094. {
  1095. if (dev->dev_private) {
  1096. drm_i810_private_t *dev_priv = dev->dev_private;
  1097. if (dev_priv->page_flipping) {
  1098. i810_do_cleanup_pageflip(dev);
  1099. }
  1100. }
  1101. }
  1102. void i810_driver_release(drm_device_t *dev, struct file *filp)
  1103. {
  1104. i810_reclaim_buffers(dev, filp);
  1105. }
  1106. int i810_driver_dma_quiescent(drm_device_t *dev)
  1107. {
  1108. i810_dma_quiescent( dev );
  1109. return 0;
  1110. }
  1111. drm_ioctl_desc_t i810_ioctls[] = {
  1112. [DRM_IOCTL_NR(DRM_I810_INIT)] = { i810_dma_init, 1, 1 },
  1113. [DRM_IOCTL_NR(DRM_I810_VERTEX)] = { i810_dma_vertex, 1, 0 },
  1114. [DRM_IOCTL_NR(DRM_I810_CLEAR)] = { i810_clear_bufs, 1, 0 },
  1115. [DRM_IOCTL_NR(DRM_I810_FLUSH)] = { i810_flush_ioctl, 1, 0 },
  1116. [DRM_IOCTL_NR(DRM_I810_GETAGE)] = { i810_getage, 1, 0 },
  1117. [DRM_IOCTL_NR(DRM_I810_GETBUF)] = { i810_getbuf, 1, 0 },
  1118. [DRM_IOCTL_NR(DRM_I810_SWAP)] = { i810_swap_bufs, 1, 0 },
  1119. [DRM_IOCTL_NR(DRM_I810_COPY)] = { i810_copybuf, 1, 0 },
  1120. [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = { i810_docopy, 1, 0 },
  1121. [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = { i810_ov0_info, 1, 0 },
  1122. [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = { i810_fstatus, 1, 0 },
  1123. [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = { i810_ov0_flip, 1, 0 },
  1124. [DRM_IOCTL_NR(DRM_I810_MC)] = { i810_dma_mc, 1, 1 },
  1125. [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = { i810_rstatus, 1, 0 },
  1126. [DRM_IOCTL_NR(DRM_I810_FLIP)] = { i810_flip_bufs, 1, 0 }
  1127. };
  1128. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1129. /**
  1130. * Determine if the device really is AGP or not.
  1131. *
  1132. * All Intel graphics chipsets are treated as AGP, even if they are really
  1133. * PCI-e.
  1134. *
  1135. * \param dev The device to be tested.
  1136. *
  1137. * \returns
  1138. * A value of 1 is always retured to indictate every i810 is AGP.
  1139. */
  1140. int i810_driver_device_is_agp(drm_device_t * dev)
  1141. {
  1142. return 1;
  1143. }