bte.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved.
  7. */
  8. #include <linux/config.h>
  9. #include <linux/module.h>
  10. #include <asm/sn/nodepda.h>
  11. #include <asm/sn/addrs.h>
  12. #include <asm/sn/arch.h>
  13. #include <asm/sn/sn_cpuid.h>
  14. #include <asm/sn/pda.h>
  15. #include <asm/sn/shubio.h>
  16. #include <asm/nodedata.h>
  17. #include <asm/delay.h>
  18. #include <linux/bootmem.h>
  19. #include <linux/string.h>
  20. #include <linux/sched.h>
  21. #include <asm/sn/bte.h>
  22. #ifndef L1_CACHE_MASK
  23. #define L1_CACHE_MASK (L1_CACHE_BYTES - 1)
  24. #endif
  25. /* two interfaces on two btes */
  26. #define MAX_INTERFACES_TO_TRY 4
  27. #define MAX_NODES_TO_TRY 2
  28. static struct bteinfo_s *bte_if_on_node(nasid_t nasid, int interface)
  29. {
  30. nodepda_t *tmp_nodepda;
  31. if (nasid_to_cnodeid(nasid) == -1)
  32. return (struct bteinfo_s *)NULL;;
  33. tmp_nodepda = NODEPDA(nasid_to_cnodeid(nasid));
  34. return &tmp_nodepda->bte_if[interface];
  35. }
  36. static inline void bte_start_transfer(struct bteinfo_s *bte, u64 len, u64 mode)
  37. {
  38. if (is_shub2()) {
  39. BTE_CTRL_STORE(bte, (IBLS_BUSY | ((len) | (mode) << 24)));
  40. } else {
  41. BTE_LNSTAT_STORE(bte, len);
  42. BTE_CTRL_STORE(bte, mode);
  43. }
  44. }
  45. /************************************************************************
  46. * Block Transfer Engine copy related functions.
  47. *
  48. ***********************************************************************/
  49. /*
  50. * bte_copy(src, dest, len, mode, notification)
  51. *
  52. * Use the block transfer engine to move kernel memory from src to dest
  53. * using the assigned mode.
  54. *
  55. * Paramaters:
  56. * src - physical address of the transfer source.
  57. * dest - physical address of the transfer destination.
  58. * len - number of bytes to transfer from source to dest.
  59. * mode - hardware defined. See reference information
  60. * for IBCT0/1 in the SHUB Programmers Reference
  61. * notification - kernel virtual address of the notification cache
  62. * line. If NULL, the default is used and
  63. * the bte_copy is synchronous.
  64. *
  65. * NOTE: This function requires src, dest, and len to
  66. * be cacheline aligned.
  67. */
  68. bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
  69. {
  70. u64 transfer_size;
  71. u64 transfer_stat;
  72. u64 notif_phys_addr;
  73. struct bteinfo_s *bte;
  74. bte_result_t bte_status;
  75. unsigned long irq_flags;
  76. unsigned long itc_end = 0;
  77. int nasid_to_try[MAX_NODES_TO_TRY];
  78. int my_nasid = get_nasid();
  79. int bte_if_index, nasid_index;
  80. int bte_first, btes_per_node = BTES_PER_NODE;
  81. BTE_PRINTK(("bte_copy(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%p)\n",
  82. src, dest, len, mode, notification));
  83. if (len == 0) {
  84. return BTE_SUCCESS;
  85. }
  86. BUG_ON((len & L1_CACHE_MASK) ||
  87. (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK));
  88. BUG_ON(!(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT)));
  89. /*
  90. * Start with interface corresponding to cpu number
  91. */
  92. bte_first = raw_smp_processor_id() % btes_per_node;
  93. if (mode & BTE_USE_DEST) {
  94. /* try remote then local */
  95. nasid_to_try[0] = NASID_GET(dest);
  96. if (mode & BTE_USE_ANY) {
  97. nasid_to_try[1] = my_nasid;
  98. } else {
  99. nasid_to_try[1] = (int)NULL;
  100. }
  101. } else {
  102. /* try local then remote */
  103. nasid_to_try[0] = my_nasid;
  104. if (mode & BTE_USE_ANY) {
  105. nasid_to_try[1] = NASID_GET(dest);
  106. } else {
  107. nasid_to_try[1] = (int)NULL;
  108. }
  109. }
  110. retry_bteop:
  111. do {
  112. local_irq_save(irq_flags);
  113. bte_if_index = bte_first;
  114. nasid_index = 0;
  115. /* Attempt to lock one of the BTE interfaces. */
  116. while (nasid_index < MAX_NODES_TO_TRY) {
  117. bte = bte_if_on_node(nasid_to_try[nasid_index],bte_if_index);
  118. if (bte == NULL) {
  119. continue;
  120. }
  121. if (spin_trylock(&bte->spinlock)) {
  122. if (!(*bte->most_rcnt_na & BTE_WORD_AVAILABLE) ||
  123. (BTE_LNSTAT_LOAD(bte) & BTE_ACTIVE)) {
  124. /* Got the lock but BTE still busy */
  125. spin_unlock(&bte->spinlock);
  126. } else {
  127. /* we got the lock and it's not busy */
  128. break;
  129. }
  130. }
  131. bte_if_index = (bte_if_index + 1) % btes_per_node; /* Next interface */
  132. if (bte_if_index == bte_first) {
  133. /*
  134. * We've tried all interfaces on this node
  135. */
  136. nasid_index++;
  137. }
  138. bte = NULL;
  139. }
  140. if (bte != NULL) {
  141. break;
  142. }
  143. local_irq_restore(irq_flags);
  144. if (!(mode & BTE_WACQUIRE)) {
  145. return BTEFAIL_NOTAVAIL;
  146. }
  147. } while (1);
  148. if (notification == NULL) {
  149. /* User does not want to be notified. */
  150. bte->most_rcnt_na = &bte->notify;
  151. } else {
  152. bte->most_rcnt_na = notification;
  153. }
  154. /* Calculate the number of cache lines to transfer. */
  155. transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK);
  156. /* Initialize the notification to a known value. */
  157. *bte->most_rcnt_na = BTE_WORD_BUSY;
  158. notif_phys_addr = TO_PHYS(ia64_tpa((unsigned long)bte->most_rcnt_na));
  159. if (is_shub2()) {
  160. src = SH2_TIO_PHYS_TO_DMA(src);
  161. dest = SH2_TIO_PHYS_TO_DMA(dest);
  162. notif_phys_addr = SH2_TIO_PHYS_TO_DMA(notif_phys_addr);
  163. }
  164. /* Set the source and destination registers */
  165. BTE_PRINTKV(("IBSA = 0x%lx)\n", (TO_PHYS(src))));
  166. BTE_SRC_STORE(bte, TO_PHYS(src));
  167. BTE_PRINTKV(("IBDA = 0x%lx)\n", (TO_PHYS(dest))));
  168. BTE_DEST_STORE(bte, TO_PHYS(dest));
  169. /* Set the notification register */
  170. BTE_PRINTKV(("IBNA = 0x%lx)\n", notif_phys_addr));
  171. BTE_NOTIF_STORE(bte, notif_phys_addr);
  172. /* Initiate the transfer */
  173. BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode)));
  174. bte_start_transfer(bte, transfer_size, BTE_VALID_MODE(mode));
  175. itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec);
  176. spin_unlock_irqrestore(&bte->spinlock, irq_flags);
  177. if (notification != NULL) {
  178. return BTE_SUCCESS;
  179. }
  180. while ((transfer_stat = *bte->most_rcnt_na) == BTE_WORD_BUSY) {
  181. cpu_relax();
  182. if (ia64_get_itc() > itc_end) {
  183. BTE_PRINTK(("BTE timeout nasid 0x%x bte%d IBLS = 0x%lx na 0x%lx\n",
  184. NASID_GET(bte->bte_base_addr), bte->bte_num,
  185. BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na) );
  186. bte->bte_error_count++;
  187. bte->bh_error = IBLS_ERROR;
  188. bte_error_handler((unsigned long)NODEPDA(bte->bte_cnode));
  189. *bte->most_rcnt_na = BTE_WORD_AVAILABLE;
  190. goto retry_bteop;
  191. }
  192. }
  193. BTE_PRINTKV((" Delay Done. IBLS = 0x%lx, most_rcnt_na = 0x%lx\n",
  194. BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
  195. if (transfer_stat & IBLS_ERROR) {
  196. bte_status = transfer_stat & ~IBLS_ERROR;
  197. } else {
  198. bte_status = BTE_SUCCESS;
  199. }
  200. *bte->most_rcnt_na = BTE_WORD_AVAILABLE;
  201. BTE_PRINTK(("Returning status is 0x%lx and most_rcnt_na is 0x%lx\n",
  202. BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
  203. return bte_status;
  204. }
  205. EXPORT_SYMBOL(bte_copy);
  206. /*
  207. * bte_unaligned_copy(src, dest, len, mode)
  208. *
  209. * use the block transfer engine to move kernel
  210. * memory from src to dest using the assigned mode.
  211. *
  212. * Paramaters:
  213. * src - physical address of the transfer source.
  214. * dest - physical address of the transfer destination.
  215. * len - number of bytes to transfer from source to dest.
  216. * mode - hardware defined. See reference information
  217. * for IBCT0/1 in the SGI documentation.
  218. *
  219. * NOTE: If the source, dest, and len are all cache line aligned,
  220. * then it would be _FAR_ preferrable to use bte_copy instead.
  221. */
  222. bte_result_t bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode)
  223. {
  224. int destFirstCacheOffset;
  225. u64 headBteSource;
  226. u64 headBteLen;
  227. u64 headBcopySrcOffset;
  228. u64 headBcopyDest;
  229. u64 headBcopyLen;
  230. u64 footBteSource;
  231. u64 footBteLen;
  232. u64 footBcopyDest;
  233. u64 footBcopyLen;
  234. bte_result_t rv;
  235. char *bteBlock, *bteBlock_unaligned;
  236. if (len == 0) {
  237. return BTE_SUCCESS;
  238. }
  239. /* temporary buffer used during unaligned transfers */
  240. bteBlock_unaligned = kmalloc(len + 3 * L1_CACHE_BYTES,
  241. GFP_KERNEL | GFP_DMA);
  242. if (bteBlock_unaligned == NULL) {
  243. return BTEFAIL_NOTAVAIL;
  244. }
  245. bteBlock = (char *)L1_CACHE_ALIGN((u64) bteBlock_unaligned);
  246. headBcopySrcOffset = src & L1_CACHE_MASK;
  247. destFirstCacheOffset = dest & L1_CACHE_MASK;
  248. /*
  249. * At this point, the transfer is broken into
  250. * (up to) three sections. The first section is
  251. * from the start address to the first physical
  252. * cache line, the second is from the first physical
  253. * cache line to the last complete cache line,
  254. * and the third is from the last cache line to the
  255. * end of the buffer. The first and third sections
  256. * are handled by bte copying into a temporary buffer
  257. * and then bcopy'ing the necessary section into the
  258. * final location. The middle section is handled with
  259. * a standard bte copy.
  260. *
  261. * One nasty exception to the above rule is when the
  262. * source and destination are not symetrically
  263. * mis-aligned. If the source offset from the first
  264. * cache line is different from the destination offset,
  265. * we make the first section be the entire transfer
  266. * and the bcopy the entire block into place.
  267. */
  268. if (headBcopySrcOffset == destFirstCacheOffset) {
  269. /*
  270. * Both the source and destination are the same
  271. * distance from a cache line boundary so we can
  272. * use the bte to transfer the bulk of the
  273. * data.
  274. */
  275. headBteSource = src & ~L1_CACHE_MASK;
  276. headBcopyDest = dest;
  277. if (headBcopySrcOffset) {
  278. headBcopyLen =
  279. (len >
  280. (L1_CACHE_BYTES -
  281. headBcopySrcOffset) ? L1_CACHE_BYTES
  282. - headBcopySrcOffset : len);
  283. headBteLen = L1_CACHE_BYTES;
  284. } else {
  285. headBcopyLen = 0;
  286. headBteLen = 0;
  287. }
  288. if (len > headBcopyLen) {
  289. footBcopyLen = (len - headBcopyLen) & L1_CACHE_MASK;
  290. footBteLen = L1_CACHE_BYTES;
  291. footBteSource = src + len - footBcopyLen;
  292. footBcopyDest = dest + len - footBcopyLen;
  293. if (footBcopyDest == (headBcopyDest + headBcopyLen)) {
  294. /*
  295. * We have two contigous bcopy
  296. * blocks. Merge them.
  297. */
  298. headBcopyLen += footBcopyLen;
  299. headBteLen += footBteLen;
  300. } else if (footBcopyLen > 0) {
  301. rv = bte_copy(footBteSource,
  302. ia64_tpa((unsigned long)bteBlock),
  303. footBteLen, mode, NULL);
  304. if (rv != BTE_SUCCESS) {
  305. kfree(bteBlock_unaligned);
  306. return rv;
  307. }
  308. memcpy(__va(footBcopyDest),
  309. (char *)bteBlock, footBcopyLen);
  310. }
  311. } else {
  312. footBcopyLen = 0;
  313. footBteLen = 0;
  314. }
  315. if (len > (headBcopyLen + footBcopyLen)) {
  316. /* now transfer the middle. */
  317. rv = bte_copy((src + headBcopyLen),
  318. (dest +
  319. headBcopyLen),
  320. (len - headBcopyLen -
  321. footBcopyLen), mode, NULL);
  322. if (rv != BTE_SUCCESS) {
  323. kfree(bteBlock_unaligned);
  324. return rv;
  325. }
  326. }
  327. } else {
  328. /*
  329. * The transfer is not symetric, we will
  330. * allocate a buffer large enough for all the
  331. * data, bte_copy into that buffer and then
  332. * bcopy to the destination.
  333. */
  334. /* Add the leader from source */
  335. headBteLen = len + (src & L1_CACHE_MASK);
  336. /* Add the trailing bytes from footer. */
  337. headBteLen += L1_CACHE_BYTES - (headBteLen & L1_CACHE_MASK);
  338. headBteSource = src & ~L1_CACHE_MASK;
  339. headBcopySrcOffset = src & L1_CACHE_MASK;
  340. headBcopyDest = dest;
  341. headBcopyLen = len;
  342. }
  343. if (headBcopyLen > 0) {
  344. rv = bte_copy(headBteSource,
  345. ia64_tpa((unsigned long)bteBlock), headBteLen,
  346. mode, NULL);
  347. if (rv != BTE_SUCCESS) {
  348. kfree(bteBlock_unaligned);
  349. return rv;
  350. }
  351. memcpy(__va(headBcopyDest), ((char *)bteBlock +
  352. headBcopySrcOffset), headBcopyLen);
  353. }
  354. kfree(bteBlock_unaligned);
  355. return BTE_SUCCESS;
  356. }
  357. EXPORT_SYMBOL(bte_unaligned_copy);
  358. /************************************************************************
  359. * Block Transfer Engine initialization functions.
  360. *
  361. ***********************************************************************/
  362. /*
  363. * bte_init_node(nodepda, cnode)
  364. *
  365. * Initialize the nodepda structure with BTE base addresses and
  366. * spinlocks.
  367. */
  368. void bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode)
  369. {
  370. int i;
  371. /*
  372. * Indicate that all the block transfer engines on this node
  373. * are available.
  374. */
  375. /*
  376. * Allocate one bte_recover_t structure per node. It holds
  377. * the recovery lock for node. All the bte interface structures
  378. * will point at this one bte_recover structure to get the lock.
  379. */
  380. spin_lock_init(&mynodepda->bte_recovery_lock);
  381. init_timer(&mynodepda->bte_recovery_timer);
  382. mynodepda->bte_recovery_timer.function = bte_error_handler;
  383. mynodepda->bte_recovery_timer.data = (unsigned long)mynodepda;
  384. for (i = 0; i < BTES_PER_NODE; i++) {
  385. u64 *base_addr;
  386. /* Which link status register should we use? */
  387. base_addr = (u64 *)
  388. REMOTE_HUB_ADDR(cnodeid_to_nasid(cnode), BTE_BASE_ADDR(i));
  389. mynodepda->bte_if[i].bte_base_addr = base_addr;
  390. mynodepda->bte_if[i].bte_source_addr = BTE_SOURCE_ADDR(base_addr);
  391. mynodepda->bte_if[i].bte_destination_addr = BTE_DEST_ADDR(base_addr);
  392. mynodepda->bte_if[i].bte_control_addr = BTE_CTRL_ADDR(base_addr);
  393. mynodepda->bte_if[i].bte_notify_addr = BTE_NOTIF_ADDR(base_addr);
  394. /*
  395. * Initialize the notification and spinlock
  396. * so the first transfer can occur.
  397. */
  398. mynodepda->bte_if[i].most_rcnt_na =
  399. &(mynodepda->bte_if[i].notify);
  400. mynodepda->bte_if[i].notify = BTE_WORD_AVAILABLE;
  401. spin_lock_init(&mynodepda->bte_if[i].spinlock);
  402. mynodepda->bte_if[i].bte_cnode = cnode;
  403. mynodepda->bte_if[i].bte_error_count = 0;
  404. mynodepda->bte_if[i].bte_num = i;
  405. mynodepda->bte_if[i].cleanup_active = 0;
  406. mynodepda->bte_if[i].bh_error = 0;
  407. }
  408. }