tlb.c 4.6 KB

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  1. /*
  2. * TLB support routines.
  3. *
  4. * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
  5. * David Mosberger-Tang <davidm@hpl.hp.com>
  6. *
  7. * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
  8. * Modified RID allocation for SMP
  9. * Goutham Rao <goutham.rao@intel.com>
  10. * IPI based ptc implementation and A-step IPI implementation.
  11. */
  12. #include <linux/config.h>
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/kernel.h>
  16. #include <linux/sched.h>
  17. #include <linux/smp.h>
  18. #include <linux/mm.h>
  19. #include <asm/delay.h>
  20. #include <asm/mmu_context.h>
  21. #include <asm/pgalloc.h>
  22. #include <asm/pal.h>
  23. #include <asm/tlbflush.h>
  24. static struct {
  25. unsigned long mask; /* mask of supported purge page-sizes */
  26. unsigned long max_bits; /* log2() of largest supported purge page-size */
  27. } purge;
  28. struct ia64_ctx ia64_ctx = {
  29. .lock = SPIN_LOCK_UNLOCKED,
  30. .next = 1,
  31. .limit = (1 << 15) - 1, /* start out with the safe (architected) limit */
  32. .max_ctx = ~0U
  33. };
  34. DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
  35. /*
  36. * Acquire the ia64_ctx.lock before calling this function!
  37. */
  38. void
  39. wrap_mmu_context (struct mm_struct *mm)
  40. {
  41. unsigned long tsk_context, max_ctx = ia64_ctx.max_ctx;
  42. struct task_struct *tsk;
  43. int i;
  44. if (ia64_ctx.next > max_ctx)
  45. ia64_ctx.next = 300; /* skip daemons */
  46. ia64_ctx.limit = max_ctx + 1;
  47. /*
  48. * Scan all the task's mm->context and set proper safe range
  49. */
  50. read_lock(&tasklist_lock);
  51. repeat:
  52. for_each_process(tsk) {
  53. if (!tsk->mm)
  54. continue;
  55. tsk_context = tsk->mm->context;
  56. if (tsk_context == ia64_ctx.next) {
  57. if (++ia64_ctx.next >= ia64_ctx.limit) {
  58. /* empty range: reset the range limit and start over */
  59. if (ia64_ctx.next > max_ctx)
  60. ia64_ctx.next = 300;
  61. ia64_ctx.limit = max_ctx + 1;
  62. goto repeat;
  63. }
  64. }
  65. if ((tsk_context > ia64_ctx.next) && (tsk_context < ia64_ctx.limit))
  66. ia64_ctx.limit = tsk_context;
  67. }
  68. read_unlock(&tasklist_lock);
  69. /* can't call flush_tlb_all() here because of race condition with O(1) scheduler [EF] */
  70. {
  71. int cpu = get_cpu(); /* prevent preemption/migration */
  72. for (i = 0; i < NR_CPUS; ++i)
  73. if (cpu_online(i) && (i != cpu))
  74. per_cpu(ia64_need_tlb_flush, i) = 1;
  75. put_cpu();
  76. }
  77. local_flush_tlb_all();
  78. }
  79. void
  80. ia64_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
  81. {
  82. static DEFINE_SPINLOCK(ptcg_lock);
  83. /* HW requires global serialization of ptc.ga. */
  84. spin_lock(&ptcg_lock);
  85. {
  86. do {
  87. /*
  88. * Flush ALAT entries also.
  89. */
  90. ia64_ptcga(start, (nbits<<2));
  91. ia64_srlz_i();
  92. start += (1UL << nbits);
  93. } while (start < end);
  94. }
  95. spin_unlock(&ptcg_lock);
  96. }
  97. void
  98. local_flush_tlb_all (void)
  99. {
  100. unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
  101. addr = local_cpu_data->ptce_base;
  102. count0 = local_cpu_data->ptce_count[0];
  103. count1 = local_cpu_data->ptce_count[1];
  104. stride0 = local_cpu_data->ptce_stride[0];
  105. stride1 = local_cpu_data->ptce_stride[1];
  106. local_irq_save(flags);
  107. for (i = 0; i < count0; ++i) {
  108. for (j = 0; j < count1; ++j) {
  109. ia64_ptce(addr);
  110. addr += stride1;
  111. }
  112. addr += stride0;
  113. }
  114. local_irq_restore(flags);
  115. ia64_srlz_i(); /* srlz.i implies srlz.d */
  116. }
  117. void
  118. flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end)
  119. {
  120. struct mm_struct *mm = vma->vm_mm;
  121. unsigned long size = end - start;
  122. unsigned long nbits;
  123. if (mm != current->active_mm) {
  124. /* this does happen, but perhaps it's not worth optimizing for? */
  125. #ifdef CONFIG_SMP
  126. flush_tlb_all();
  127. #else
  128. mm->context = 0;
  129. #endif
  130. return;
  131. }
  132. nbits = ia64_fls(size + 0xfff);
  133. while (unlikely (((1UL << nbits) & purge.mask) == 0) && (nbits < purge.max_bits))
  134. ++nbits;
  135. if (nbits > purge.max_bits)
  136. nbits = purge.max_bits;
  137. start &= ~((1UL << nbits) - 1);
  138. # ifdef CONFIG_SMP
  139. platform_global_tlb_purge(start, end, nbits);
  140. # else
  141. do {
  142. ia64_ptcl(start, (nbits<<2));
  143. start += (1UL << nbits);
  144. } while (start < end);
  145. # endif
  146. ia64_srlz_i(); /* srlz.i implies srlz.d */
  147. }
  148. EXPORT_SYMBOL(flush_tlb_range);
  149. void __devinit
  150. ia64_tlb_init (void)
  151. {
  152. ia64_ptce_info_t ptce_info;
  153. unsigned long tr_pgbits;
  154. long status;
  155. if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
  156. printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld;"
  157. "defaulting to architected purge page-sizes.\n", status);
  158. purge.mask = 0x115557000UL;
  159. }
  160. purge.max_bits = ia64_fls(purge.mask);
  161. ia64_get_ptce(&ptce_info);
  162. local_cpu_data->ptce_base = ptce_info.base;
  163. local_cpu_data->ptce_count[0] = ptce_info.count[0];
  164. local_cpu_data->ptce_count[1] = ptce_info.count[1];
  165. local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
  166. local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
  167. local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
  168. }