ipath_intr.c 34 KB

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  1. /*
  2. * Copyright (c) 2006 QLogic, Inc. All rights reserved.
  3. * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/pci.h>
  34. #include "ipath_kernel.h"
  35. #include "ipath_verbs.h"
  36. #include "ipath_common.h"
  37. /*
  38. * clear (write) a pio buffer, to clear a parity error. This routine
  39. * should only be called when in freeze mode, and the buffer should be
  40. * canceled afterwards.
  41. */
  42. static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum)
  43. {
  44. u32 __iomem *pbuf;
  45. u32 dwcnt; /* dword count to write */
  46. if (pnum < dd->ipath_piobcnt2k) {
  47. pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum *
  48. dd->ipath_palign);
  49. dwcnt = dd->ipath_piosize2k >> 2;
  50. }
  51. else {
  52. pbuf = (u32 __iomem *) (dd->ipath_pio4kbase +
  53. (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
  54. dwcnt = dd->ipath_piosize4k >> 2;
  55. }
  56. dev_info(&dd->pcidev->dev,
  57. "Rewrite PIO buffer %u, to recover from parity error\n",
  58. pnum);
  59. *pbuf = dwcnt+1; /* no flush required, since already in freeze */
  60. while(--dwcnt)
  61. *pbuf++ = 0;
  62. }
  63. /*
  64. * Called when we might have an error that is specific to a particular
  65. * PIO buffer, and may need to cancel that buffer, so it can be re-used.
  66. * If rewrite is true, and bits are set in the sendbufferror registers,
  67. * we'll write to the buffer, for error recovery on parity errors.
  68. */
  69. void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
  70. {
  71. u32 piobcnt;
  72. unsigned long sbuf[4];
  73. /*
  74. * it's possible that sendbuffererror could have bits set; might
  75. * have already done this as a result of hardware error handling
  76. */
  77. piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
  78. /* read these before writing errorclear */
  79. sbuf[0] = ipath_read_kreg64(
  80. dd, dd->ipath_kregs->kr_sendbuffererror);
  81. sbuf[1] = ipath_read_kreg64(
  82. dd, dd->ipath_kregs->kr_sendbuffererror + 1);
  83. if (piobcnt > 128) {
  84. sbuf[2] = ipath_read_kreg64(
  85. dd, dd->ipath_kregs->kr_sendbuffererror + 2);
  86. sbuf[3] = ipath_read_kreg64(
  87. dd, dd->ipath_kregs->kr_sendbuffererror + 3);
  88. }
  89. if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
  90. int i;
  91. if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) &&
  92. dd->ipath_lastcancel > jiffies) {
  93. __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG,
  94. "SendbufErrs %lx %lx", sbuf[0],
  95. sbuf[1]);
  96. if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
  97. printk(" %lx %lx ", sbuf[2], sbuf[3]);
  98. printk("\n");
  99. }
  100. for (i = 0; i < piobcnt; i++)
  101. if (test_bit(i, sbuf)) {
  102. if (rewrite)
  103. ipath_clrpiobuf(dd, i);
  104. ipath_disarm_piobufs(dd, i, 1);
  105. }
  106. /* ignore armlaunch errs for a bit */
  107. dd->ipath_lastcancel = jiffies+3;
  108. }
  109. }
  110. /* These are all rcv-related errors which we want to count for stats */
  111. #define E_SUM_PKTERRS \
  112. (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
  113. INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
  114. INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
  115. INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  116. INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
  117. INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
  118. /* These are all send-related errors which we want to count for stats */
  119. #define E_SUM_ERRS \
  120. (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
  121. INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  122. INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
  123. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  124. INFINIPATH_E_INVALIDADDR)
  125. /*
  126. * these are errors that can occur when the link changes state while
  127. * a packet is being sent or received. This doesn't cover things
  128. * like EBP or VCRC that can be the result of a sending having the
  129. * link change state, so we receive a "known bad" packet.
  130. */
  131. #define E_SUM_LINK_PKTERRS \
  132. (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  133. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  134. INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  135. INFINIPATH_E_RUNEXPCHAR)
  136. static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
  137. {
  138. u64 ignore_this_time = 0;
  139. ipath_disarm_senderrbufs(dd, 0);
  140. if ((errs & E_SUM_LINK_PKTERRS) &&
  141. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  142. /*
  143. * This can happen when SMA is trying to bring the link
  144. * up, but the IB link changes state at the "wrong" time.
  145. * The IB logic then complains that the packet isn't
  146. * valid. We don't want to confuse people, so we just
  147. * don't print them, except at debug
  148. */
  149. ipath_dbg("Ignoring packet errors %llx, because link not "
  150. "ACTIVE\n", (unsigned long long) errs);
  151. ignore_this_time = errs & E_SUM_LINK_PKTERRS;
  152. }
  153. return ignore_this_time;
  154. }
  155. /* generic hw error messages... */
  156. #define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \
  157. { \
  158. .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \
  159. INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \
  160. .msg = "TXE " #a " Memory Parity" \
  161. }
  162. #define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \
  163. { \
  164. .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \
  165. INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \
  166. .msg = "RXE " #a " Memory Parity" \
  167. }
  168. static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = {
  169. INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"),
  170. INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"),
  171. INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF),
  172. INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC),
  173. INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO),
  174. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF),
  175. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ),
  176. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID),
  177. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID),
  178. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF),
  179. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO),
  180. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO),
  181. };
  182. /**
  183. * ipath_format_hwmsg - format a single hwerror message
  184. * @msg message buffer
  185. * @msgl length of message buffer
  186. * @hwmsg message to add to message buffer
  187. */
  188. static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg)
  189. {
  190. strlcat(msg, "[", msgl);
  191. strlcat(msg, hwmsg, msgl);
  192. strlcat(msg, "]", msgl);
  193. }
  194. /**
  195. * ipath_format_hwerrors - format hardware error messages for display
  196. * @hwerrs hardware errors bit vector
  197. * @hwerrmsgs hardware error descriptions
  198. * @nhwerrmsgs number of hwerrmsgs
  199. * @msg message buffer
  200. * @msgl message buffer length
  201. */
  202. void ipath_format_hwerrors(u64 hwerrs,
  203. const struct ipath_hwerror_msgs *hwerrmsgs,
  204. size_t nhwerrmsgs,
  205. char *msg, size_t msgl)
  206. {
  207. int i;
  208. const int glen =
  209. sizeof(ipath_generic_hwerror_msgs) /
  210. sizeof(ipath_generic_hwerror_msgs[0]);
  211. for (i=0; i<glen; i++) {
  212. if (hwerrs & ipath_generic_hwerror_msgs[i].mask) {
  213. ipath_format_hwmsg(msg, msgl,
  214. ipath_generic_hwerror_msgs[i].msg);
  215. }
  216. }
  217. for (i=0; i<nhwerrmsgs; i++) {
  218. if (hwerrs & hwerrmsgs[i].mask) {
  219. ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg);
  220. }
  221. }
  222. }
  223. /* return the strings for the most common link states */
  224. static char *ib_linkstate(u32 linkstate)
  225. {
  226. char *ret;
  227. switch (linkstate) {
  228. case IPATH_IBSTATE_INIT:
  229. ret = "Init";
  230. break;
  231. case IPATH_IBSTATE_ARM:
  232. ret = "Arm";
  233. break;
  234. case IPATH_IBSTATE_ACTIVE:
  235. ret = "Active";
  236. break;
  237. default:
  238. ret = "Down";
  239. }
  240. return ret;
  241. }
  242. static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
  243. ipath_err_t errs, int noprint)
  244. {
  245. u64 val;
  246. u32 ltstate, lstate;
  247. /*
  248. * even if diags are enabled, we want to notice LINKINIT, etc.
  249. * We just don't want to change the LED state, or
  250. * dd->ipath_kregs->kr_ibcctrl
  251. */
  252. val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
  253. lstate = val & IPATH_IBSTATE_MASK;
  254. /*
  255. * this is confusing enough when it happens that I want to always put it
  256. * on the console and in the logs. If it was a requested state change,
  257. * we'll have already cleared the flags, so we won't print this warning
  258. */
  259. if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE)
  260. && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
  261. dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n",
  262. (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE",
  263. ib_linkstate(lstate));
  264. /*
  265. * Flush all queued sends when link went to DOWN or INIT,
  266. * to be sure that they don't block SMA and other MAD packets
  267. */
  268. ipath_cancel_sends(dd);
  269. }
  270. else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM ||
  271. lstate == IPATH_IBSTATE_ACTIVE) {
  272. /*
  273. * only print at SMA if there is a change, debug if not
  274. * (sometimes we want to know that, usually not).
  275. */
  276. if (lstate == ((unsigned) dd->ipath_lastibcstat
  277. & IPATH_IBSTATE_MASK)) {
  278. ipath_dbg("Status change intr but no change (%s)\n",
  279. ib_linkstate(lstate));
  280. }
  281. else
  282. ipath_cdbg(VERBOSE, "Unit %u link state %s, last "
  283. "was %s\n", dd->ipath_unit,
  284. ib_linkstate(lstate),
  285. ib_linkstate((unsigned)
  286. dd->ipath_lastibcstat
  287. & IPATH_IBSTATE_MASK));
  288. }
  289. else {
  290. lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK;
  291. if (lstate == IPATH_IBSTATE_INIT ||
  292. lstate == IPATH_IBSTATE_ARM ||
  293. lstate == IPATH_IBSTATE_ACTIVE)
  294. ipath_cdbg(VERBOSE, "Unit %u link state down"
  295. " (state 0x%x), from %s\n",
  296. dd->ipath_unit,
  297. (u32)val & IPATH_IBSTATE_MASK,
  298. ib_linkstate(lstate));
  299. else
  300. ipath_cdbg(VERBOSE, "Unit %u link state changed "
  301. "to 0x%x from down (%x)\n",
  302. dd->ipath_unit, (u32) val, lstate);
  303. }
  304. ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
  305. INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  306. lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  307. INFINIPATH_IBCS_LINKSTATE_MASK;
  308. if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
  309. ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  310. u32 last_ltstate;
  311. /*
  312. * Ignore cycling back and forth from Polling.Active
  313. * to Polling.Quiet while waiting for the other end of
  314. * the link to come up. We will cycle back and forth
  315. * between them if no cable is plugged in,
  316. * the other device is powered off or disabled, etc.
  317. */
  318. last_ltstate = (dd->ipath_lastibcstat >>
  319. INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)
  320. & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  321. if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE
  322. || last_ltstate ==
  323. INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  324. if (dd->ipath_ibpollcnt > 40) {
  325. dd->ipath_flags |= IPATH_NOCABLE;
  326. *dd->ipath_statusp |=
  327. IPATH_STATUS_IB_NOCABLE;
  328. } else
  329. dd->ipath_ibpollcnt++;
  330. goto skip_ibchange;
  331. }
  332. }
  333. dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */
  334. ipath_stats.sps_iblink++;
  335. if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
  336. dd->ipath_flags |= IPATH_LINKDOWN;
  337. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  338. | IPATH_LINKACTIVE |
  339. IPATH_LINKARMED);
  340. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  341. dd->ipath_lli_counter = 0;
  342. if (!noprint) {
  343. if (((dd->ipath_lastibcstat >>
  344. INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  345. INFINIPATH_IBCS_LINKSTATE_MASK)
  346. == INFINIPATH_IBCS_L_STATE_ACTIVE)
  347. /* if from up to down be more vocal */
  348. ipath_cdbg(VERBOSE,
  349. "Unit %u link now down (%s)\n",
  350. dd->ipath_unit,
  351. ipath_ibcstatus_str[ltstate]);
  352. else
  353. ipath_cdbg(VERBOSE, "Unit %u link is "
  354. "down (%s)\n", dd->ipath_unit,
  355. ipath_ibcstatus_str[ltstate]);
  356. }
  357. dd->ipath_f_setextled(dd, lstate, ltstate);
  358. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) {
  359. dd->ipath_flags |= IPATH_LINKACTIVE;
  360. dd->ipath_flags &=
  361. ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN |
  362. IPATH_LINKARMED | IPATH_NOCABLE);
  363. *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
  364. *dd->ipath_statusp |=
  365. IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
  366. dd->ipath_f_setextled(dd, lstate, ltstate);
  367. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) {
  368. /*
  369. * set INIT and DOWN. Down is checked by most of the other
  370. * code, but INIT is useful to know in a few places.
  371. */
  372. dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN;
  373. dd->ipath_flags &=
  374. ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED
  375. | IPATH_NOCABLE);
  376. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  377. | IPATH_STATUS_IB_READY);
  378. dd->ipath_f_setextled(dd, lstate, ltstate);
  379. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) {
  380. dd->ipath_flags |= IPATH_LINKARMED;
  381. dd->ipath_flags &=
  382. ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT |
  383. IPATH_LINKACTIVE | IPATH_NOCABLE);
  384. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  385. | IPATH_STATUS_IB_READY);
  386. dd->ipath_f_setextled(dd, lstate, ltstate);
  387. } else {
  388. if (!noprint)
  389. ipath_dbg("IBstatuschange unit %u: %s (%x)\n",
  390. dd->ipath_unit,
  391. ipath_ibcstatus_str[ltstate], ltstate);
  392. }
  393. skip_ibchange:
  394. dd->ipath_lastibcstat = val;
  395. }
  396. static void handle_supp_msgs(struct ipath_devdata *dd,
  397. unsigned supp_msgs, char msg[512])
  398. {
  399. /*
  400. * Print the message unless it's ibc status change only, which
  401. * happens so often we never want to count it.
  402. */
  403. if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
  404. int iserr;
  405. iserr = ipath_decode_err(msg, sizeof msg,
  406. dd->ipath_lasterror &
  407. ~INFINIPATH_E_IBSTATUSCHANGED);
  408. if (dd->ipath_lasterror &
  409. ~(INFINIPATH_E_RRCVEGRFULL |
  410. INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
  411. ipath_dev_err(dd, "Suppressed %u messages for "
  412. "fast-repeating errors (%s) (%llx)\n",
  413. supp_msgs, msg,
  414. (unsigned long long)
  415. dd->ipath_lasterror);
  416. else {
  417. /*
  418. * rcvegrfull and rcvhdrqfull are "normal", for some
  419. * types of processes (mostly benchmarks) that send
  420. * huge numbers of messages, while not processing
  421. * them. So only complain about these at debug
  422. * level.
  423. */
  424. if (iserr)
  425. ipath_dbg("Suppressed %u messages for %s\n",
  426. supp_msgs, msg);
  427. else
  428. ipath_cdbg(ERRPKT,
  429. "Suppressed %u messages for %s\n",
  430. supp_msgs, msg);
  431. }
  432. }
  433. }
  434. static unsigned handle_frequent_errors(struct ipath_devdata *dd,
  435. ipath_err_t errs, char msg[512],
  436. int *noprint)
  437. {
  438. unsigned long nc;
  439. static unsigned long nextmsg_time;
  440. static unsigned nmsgs, supp_msgs;
  441. /*
  442. * Throttle back "fast" messages to no more than 10 per 5 seconds.
  443. * This isn't perfect, but it's a reasonable heuristic. If we get
  444. * more than 10, give a 6x longer delay.
  445. */
  446. nc = jiffies;
  447. if (nmsgs > 10) {
  448. if (time_before(nc, nextmsg_time)) {
  449. *noprint = 1;
  450. if (!supp_msgs++)
  451. nextmsg_time = nc + HZ * 3;
  452. }
  453. else if (supp_msgs) {
  454. handle_supp_msgs(dd, supp_msgs, msg);
  455. supp_msgs = 0;
  456. nmsgs = 0;
  457. }
  458. }
  459. else if (!nmsgs++ || time_after(nc, nextmsg_time))
  460. nextmsg_time = nc + HZ / 2;
  461. return supp_msgs;
  462. }
  463. static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
  464. {
  465. char msg[512];
  466. u64 ignore_this_time = 0;
  467. int i, iserr = 0;
  468. int chkerrpkts = 0, noprint = 0;
  469. unsigned supp_msgs;
  470. int log_idx;
  471. supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint);
  472. /*
  473. * don't report errors that are masked (includes those always
  474. * ignored)
  475. */
  476. errs &= ~dd->ipath_maskederrs;
  477. /* do these first, they are most important */
  478. if (errs & INFINIPATH_E_HARDWARE) {
  479. /* reuse same msg buf */
  480. dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
  481. } else {
  482. u64 mask;
  483. for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) {
  484. mask = dd->ipath_eep_st_masks[log_idx].errs_to_log;
  485. if (errs & mask)
  486. ipath_inc_eeprom_err(dd, log_idx, 1);
  487. }
  488. }
  489. if (!noprint && (errs & ~dd->ipath_e_bitsextant))
  490. ipath_dev_err(dd, "error interrupt with unknown errors "
  491. "%llx set\n", (unsigned long long)
  492. (errs & ~dd->ipath_e_bitsextant));
  493. if (errs & E_SUM_ERRS)
  494. ignore_this_time = handle_e_sum_errs(dd, errs);
  495. else if ((errs & E_SUM_LINK_PKTERRS) &&
  496. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  497. /*
  498. * This can happen when SMA is trying to bring the link
  499. * up, but the IB link changes state at the "wrong" time.
  500. * The IB logic then complains that the packet isn't
  501. * valid. We don't want to confuse people, so we just
  502. * don't print them, except at debug
  503. */
  504. ipath_dbg("Ignoring packet errors %llx, because link not "
  505. "ACTIVE\n", (unsigned long long) errs);
  506. ignore_this_time = errs & E_SUM_LINK_PKTERRS;
  507. }
  508. if (supp_msgs == 250000) {
  509. int s_iserr;
  510. /*
  511. * It's not entirely reasonable assuming that the errors set
  512. * in the last clear period are all responsible for the
  513. * problem, but the alternative is to assume it's the only
  514. * ones on this particular interrupt, which also isn't great
  515. */
  516. dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
  517. ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
  518. ~dd->ipath_maskederrs);
  519. s_iserr = ipath_decode_err(msg, sizeof msg,
  520. (dd->ipath_maskederrs & ~dd->
  521. ipath_ignorederrs));
  522. if ((dd->ipath_maskederrs & ~dd->ipath_ignorederrs) &
  523. ~(INFINIPATH_E_RRCVEGRFULL |
  524. INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
  525. ipath_dev_err(dd, "Temporarily disabling "
  526. "error(s) %llx reporting; too frequent (%s)\n",
  527. (unsigned long long) (dd->ipath_maskederrs &
  528. ~dd->ipath_ignorederrs), msg);
  529. else {
  530. /*
  531. * rcvegrfull and rcvhdrqfull are "normal",
  532. * for some types of processes (mostly benchmarks)
  533. * that send huge numbers of messages, while not
  534. * processing them. So only complain about
  535. * these at debug level.
  536. */
  537. if (s_iserr)
  538. ipath_dbg("Temporarily disabling reporting "
  539. "too frequent queue full errors (%s)\n",
  540. msg);
  541. else
  542. ipath_cdbg(ERRPKT,
  543. "Temporarily disabling reporting too"
  544. " frequent packet errors (%s)\n",
  545. msg);
  546. }
  547. /*
  548. * Re-enable the masked errors after around 3 minutes. in
  549. * ipath_get_faststats(). If we have a series of fast
  550. * repeating but different errors, the interval will keep
  551. * stretching out, but that's OK, as that's pretty
  552. * catastrophic.
  553. */
  554. dd->ipath_unmasktime = jiffies + HZ * 180;
  555. }
  556. ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
  557. if (ignore_this_time)
  558. errs &= ~ignore_this_time;
  559. if (errs & ~dd->ipath_lasterror) {
  560. errs &= ~dd->ipath_lasterror;
  561. /* never suppress duplicate hwerrors or ibstatuschange */
  562. dd->ipath_lasterror |= errs &
  563. ~(INFINIPATH_E_HARDWARE |
  564. INFINIPATH_E_IBSTATUSCHANGED);
  565. }
  566. /* likely due to cancel, so suppress */
  567. if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) &&
  568. dd->ipath_lastcancel > jiffies) {
  569. ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n");
  570. errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN);
  571. }
  572. if (!errs)
  573. return 0;
  574. if (!noprint)
  575. /*
  576. * the ones we mask off are handled specially below or above
  577. */
  578. ipath_decode_err(msg, sizeof msg,
  579. errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
  580. INFINIPATH_E_RRCVEGRFULL |
  581. INFINIPATH_E_RRCVHDRFULL |
  582. INFINIPATH_E_HARDWARE));
  583. else
  584. /* so we don't need if (!noprint) at strlcat's below */
  585. *msg = 0;
  586. if (errs & E_SUM_PKTERRS) {
  587. ipath_stats.sps_pkterrs++;
  588. chkerrpkts = 1;
  589. }
  590. if (errs & E_SUM_ERRS)
  591. ipath_stats.sps_errs++;
  592. if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
  593. ipath_stats.sps_crcerrs++;
  594. chkerrpkts = 1;
  595. }
  596. iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS);
  597. /*
  598. * We don't want to print these two as they happen, or we can make
  599. * the situation even worse, because it takes so long to print
  600. * messages to serial consoles. Kernel ports get printed from
  601. * fast_stats, no more than every 5 seconds, user ports get printed
  602. * on close
  603. */
  604. if (errs & INFINIPATH_E_RRCVHDRFULL) {
  605. u32 hd, tl;
  606. ipath_stats.sps_hdrqfull++;
  607. for (i = 0; i < dd->ipath_cfgports; i++) {
  608. struct ipath_portdata *pd = dd->ipath_pd[i];
  609. if (i == 0) {
  610. hd = dd->ipath_port0head;
  611. tl = (u32) le64_to_cpu(
  612. *dd->ipath_hdrqtailptr);
  613. } else if (pd && pd->port_cnt &&
  614. pd->port_rcvhdrtail_kvaddr) {
  615. /*
  616. * don't report same point multiple times,
  617. * except kernel
  618. */
  619. tl = *(u64 *) pd->port_rcvhdrtail_kvaddr;
  620. if (tl == dd->ipath_lastrcvhdrqtails[i])
  621. continue;
  622. hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
  623. i);
  624. } else
  625. continue;
  626. if (hd == (tl + 1) ||
  627. (!hd && tl == dd->ipath_hdrqlast)) {
  628. if (i == 0)
  629. chkerrpkts = 1;
  630. dd->ipath_lastrcvhdrqtails[i] = tl;
  631. pd->port_hdrqfull++;
  632. }
  633. }
  634. }
  635. if (errs & INFINIPATH_E_RRCVEGRFULL) {
  636. /*
  637. * since this is of less importance and not likely to
  638. * happen without also getting hdrfull, only count
  639. * occurrences; don't check each port (or even the kernel
  640. * vs user)
  641. */
  642. ipath_stats.sps_etidfull++;
  643. if (dd->ipath_port0head !=
  644. (u32) le64_to_cpu(*dd->ipath_hdrqtailptr))
  645. chkerrpkts = 1;
  646. }
  647. /*
  648. * do this before IBSTATUSCHANGED, in case both bits set in a single
  649. * interrupt; we want the STATUSCHANGE to "win", so we do our
  650. * internal copy of state machine correctly
  651. */
  652. if (errs & INFINIPATH_E_RIBLOSTLINK) {
  653. /*
  654. * force through block below
  655. */
  656. errs |= INFINIPATH_E_IBSTATUSCHANGED;
  657. ipath_stats.sps_iblink++;
  658. dd->ipath_flags |= IPATH_LINKDOWN;
  659. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  660. | IPATH_LINKARMED | IPATH_LINKACTIVE);
  661. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  662. if (!noprint) {
  663. u64 st = ipath_read_kreg64(
  664. dd, dd->ipath_kregs->kr_ibcstatus);
  665. ipath_dbg("Lost link, link now down (%s)\n",
  666. ipath_ibcstatus_str[st & 0xf]);
  667. }
  668. }
  669. if (errs & INFINIPATH_E_IBSTATUSCHANGED)
  670. handle_e_ibstatuschanged(dd, errs, noprint);
  671. if (errs & INFINIPATH_E_RESET) {
  672. if (!noprint)
  673. ipath_dev_err(dd, "Got reset, requires re-init "
  674. "(unload and reload driver)\n");
  675. dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
  676. /* mark as having had error */
  677. *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
  678. *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
  679. }
  680. if (!noprint && *msg) {
  681. if (iserr)
  682. ipath_dev_err(dd, "%s error\n", msg);
  683. else
  684. dev_info(&dd->pcidev->dev, "%s packet problems\n",
  685. msg);
  686. }
  687. if (dd->ipath_state_wanted & dd->ipath_flags) {
  688. ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, "
  689. "waking\n", dd->ipath_state_wanted,
  690. dd->ipath_flags);
  691. wake_up_interruptible(&ipath_state_wait);
  692. }
  693. return chkerrpkts;
  694. }
  695. /* this is separate to allow for better optimization of ipath_intr() */
  696. static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp)
  697. {
  698. /*
  699. * sometimes happen during driver init and unload, don't want
  700. * to process any interrupts at that point
  701. */
  702. /* this is just a bandaid, not a fix, if something goes badly
  703. * wrong */
  704. if (++*unexpectp > 100) {
  705. if (++*unexpectp > 105) {
  706. /*
  707. * ok, we must be taking somebody else's interrupts,
  708. * due to a messed up mptable and/or PIRQ table, so
  709. * unregister the interrupt. We've seen this during
  710. * linuxbios development work, and it may happen in
  711. * the future again.
  712. */
  713. if (dd->pcidev && dd->ipath_irq) {
  714. ipath_dev_err(dd, "Now %u unexpected "
  715. "interrupts, unregistering "
  716. "interrupt handler\n",
  717. *unexpectp);
  718. ipath_dbg("free_irq of irq %d\n",
  719. dd->ipath_irq);
  720. dd->ipath_f_free_irq(dd);
  721. }
  722. }
  723. if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) {
  724. ipath_dev_err(dd, "%u unexpected interrupts, "
  725. "disabling interrupts completely\n",
  726. *unexpectp);
  727. /*
  728. * disable all interrupts, something is very wrong
  729. */
  730. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
  731. 0ULL);
  732. }
  733. } else if (*unexpectp > 1)
  734. ipath_dbg("Interrupt when not ready, should not happen, "
  735. "ignoring\n");
  736. }
  737. static void ipath_bad_regread(struct ipath_devdata *dd)
  738. {
  739. static int allbits;
  740. /* separate routine, for better optimization of ipath_intr() */
  741. /*
  742. * We print the message and disable interrupts, in hope of
  743. * having a better chance of debugging the problem.
  744. */
  745. ipath_dev_err(dd,
  746. "Read of interrupt status failed (all bits set)\n");
  747. if (allbits++) {
  748. /* disable all interrupts, something is very wrong */
  749. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
  750. if (allbits == 2) {
  751. ipath_dev_err(dd, "Still bad interrupt status, "
  752. "unregistering interrupt\n");
  753. dd->ipath_f_free_irq(dd);
  754. } else if (allbits > 2) {
  755. if ((allbits % 10000) == 0)
  756. printk(".");
  757. } else
  758. ipath_dev_err(dd, "Disabling interrupts, "
  759. "multiple errors\n");
  760. }
  761. }
  762. static void handle_port_pioavail(struct ipath_devdata *dd)
  763. {
  764. u32 i;
  765. /*
  766. * start from port 1, since for now port 0 is never using
  767. * wait_event for PIO
  768. */
  769. for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) {
  770. struct ipath_portdata *pd = dd->ipath_pd[i];
  771. if (pd && pd->port_cnt &&
  772. dd->ipath_portpiowait & (1U << i)) {
  773. clear_bit(i, &dd->ipath_portpiowait);
  774. if (test_bit(IPATH_PORT_WAITING_PIO,
  775. &pd->port_flag)) {
  776. clear_bit(IPATH_PORT_WAITING_PIO,
  777. &pd->port_flag);
  778. wake_up_interruptible(&pd->port_wait);
  779. }
  780. }
  781. }
  782. }
  783. static void handle_layer_pioavail(struct ipath_devdata *dd)
  784. {
  785. int ret;
  786. ret = ipath_ib_piobufavail(dd->verbs_dev);
  787. if (ret > 0)
  788. goto set;
  789. return;
  790. set:
  791. set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  792. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  793. dd->ipath_sendctrl);
  794. }
  795. /*
  796. * Handle receive interrupts for user ports; this means a user
  797. * process was waiting for a packet to arrive, and didn't want
  798. * to poll
  799. */
  800. static void handle_urcv(struct ipath_devdata *dd, u32 istat)
  801. {
  802. u64 portr;
  803. int i;
  804. int rcvdint = 0;
  805. portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) &
  806. dd->ipath_i_rcvavail_mask)
  807. | ((istat >> INFINIPATH_I_RCVURG_SHIFT) &
  808. dd->ipath_i_rcvurg_mask);
  809. for (i = 1; i < dd->ipath_cfgports; i++) {
  810. struct ipath_portdata *pd = dd->ipath_pd[i];
  811. if (portr & (1 << i) && pd && pd->port_cnt &&
  812. test_bit(IPATH_PORT_WAITING_RCV, &pd->port_flag)) {
  813. clear_bit(IPATH_PORT_WAITING_RCV,
  814. &pd->port_flag);
  815. clear_bit(i + INFINIPATH_R_INTRAVAIL_SHIFT,
  816. &dd->ipath_rcvctrl);
  817. wake_up_interruptible(&pd->port_wait);
  818. rcvdint = 1;
  819. }
  820. }
  821. if (rcvdint) {
  822. /* only want to take one interrupt, so turn off the rcv
  823. * interrupt for all the ports that we did the wakeup on
  824. * (but never for kernel port)
  825. */
  826. ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
  827. dd->ipath_rcvctrl);
  828. }
  829. }
  830. irqreturn_t ipath_intr(int irq, void *data)
  831. {
  832. struct ipath_devdata *dd = data;
  833. u32 istat, chk0rcv = 0;
  834. ipath_err_t estat = 0;
  835. irqreturn_t ret;
  836. u32 oldhead, curtail;
  837. static unsigned unexpected = 0;
  838. static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) |
  839. (1U<<INFINIPATH_I_RCVURG_SHIFT);
  840. ipath_stats.sps_ints++;
  841. if (!(dd->ipath_flags & IPATH_PRESENT)) {
  842. /*
  843. * This return value is not great, but we do not want the
  844. * interrupt core code to remove our interrupt handler
  845. * because we don't appear to be handling an interrupt
  846. * during a chip reset.
  847. */
  848. return IRQ_HANDLED;
  849. }
  850. /*
  851. * this needs to be flags&initted, not statusp, so we keep
  852. * taking interrupts even after link goes down, etc.
  853. * Also, we *must* clear the interrupt at some point, or we won't
  854. * take it again, which can be real bad for errors, etc...
  855. */
  856. if (!(dd->ipath_flags & IPATH_INITTED)) {
  857. ipath_bad_intr(dd, &unexpected);
  858. ret = IRQ_NONE;
  859. goto bail;
  860. }
  861. /*
  862. * We try to avoid reading the interrupt status register, since
  863. * that's a PIO read, and stalls the processor for up to about
  864. * ~0.25 usec. The idea is that if we processed a port0 packet,
  865. * we blindly clear the port 0 receive interrupt bits, and nothing
  866. * else, then return. If other interrupts are pending, the chip
  867. * will re-interrupt us as soon as we write the intclear register.
  868. * We then won't process any more kernel packets (if not the 2nd
  869. * time, then the 3rd or 4th) and we'll then handle the other
  870. * interrupts. We clear the interrupts first so that we don't
  871. * lose intr for later packets that arrive while we are processing.
  872. */
  873. oldhead = dd->ipath_port0head;
  874. curtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
  875. if (oldhead != curtail) {
  876. if (dd->ipath_flags & IPATH_GPIO_INTR) {
  877. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  878. (u64) (1 << IPATH_GPIO_PORT0_BIT));
  879. istat = port0rbits | INFINIPATH_I_GPIO;
  880. }
  881. else
  882. istat = port0rbits;
  883. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
  884. ipath_kreceive(dd);
  885. if (oldhead != dd->ipath_port0head) {
  886. ipath_stats.sps_fastrcvint++;
  887. goto done;
  888. }
  889. }
  890. istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus);
  891. if (unlikely(!istat)) {
  892. ipath_stats.sps_nullintr++;
  893. ret = IRQ_NONE; /* not our interrupt, or already handled */
  894. goto bail;
  895. }
  896. if (unlikely(istat == -1)) {
  897. ipath_bad_regread(dd);
  898. /* don't know if it was our interrupt or not */
  899. ret = IRQ_NONE;
  900. goto bail;
  901. }
  902. if (unexpected)
  903. unexpected = 0;
  904. if (unlikely(istat & ~dd->ipath_i_bitsextant))
  905. ipath_dev_err(dd,
  906. "interrupt with unknown interrupts %x set\n",
  907. istat & (u32) ~ dd->ipath_i_bitsextant);
  908. else
  909. ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
  910. if (unlikely(istat & INFINIPATH_I_ERROR)) {
  911. ipath_stats.sps_errints++;
  912. estat = ipath_read_kreg64(dd,
  913. dd->ipath_kregs->kr_errorstatus);
  914. if (!estat)
  915. dev_info(&dd->pcidev->dev, "error interrupt (%x), "
  916. "but no error bits set!\n", istat);
  917. else if (estat == -1LL)
  918. /*
  919. * should we try clearing all, or hope next read
  920. * works?
  921. */
  922. ipath_dev_err(dd, "Read of error status failed "
  923. "(all bits set); ignoring\n");
  924. else
  925. if (handle_errors(dd, estat))
  926. /* force calling ipath_kreceive() */
  927. chk0rcv = 1;
  928. }
  929. if (istat & INFINIPATH_I_GPIO) {
  930. /*
  931. * GPIO interrupts fall in two broad classes:
  932. * GPIO_2 indicates (on some HT4xx boards) that a packet
  933. * has arrived for Port 0. Checking for this
  934. * is controlled by flag IPATH_GPIO_INTR.
  935. * GPIO_3..5 on IBA6120 Rev2 chips indicate errors
  936. * that we need to count. Checking for this
  937. * is controlled by flag IPATH_GPIO_ERRINTRS.
  938. */
  939. u32 gpiostatus;
  940. u32 to_clear = 0;
  941. gpiostatus = ipath_read_kreg32(
  942. dd, dd->ipath_kregs->kr_gpio_status);
  943. /* First the error-counter case.
  944. */
  945. if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) &&
  946. (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) {
  947. /* want to clear the bits we see asserted. */
  948. to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK);
  949. /*
  950. * Count appropriately, clear bits out of our copy,
  951. * as they have been "handled".
  952. */
  953. if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) {
  954. ipath_dbg("FlowCtl on UnsupVL\n");
  955. dd->ipath_rxfc_unsupvl_errs++;
  956. }
  957. if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) {
  958. ipath_dbg("Overrun Threshold exceeded\n");
  959. dd->ipath_overrun_thresh_errs++;
  960. }
  961. if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) {
  962. ipath_dbg("Local Link Integrity error\n");
  963. dd->ipath_lli_errs++;
  964. }
  965. gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK;
  966. }
  967. /* Now the Port0 Receive case */
  968. if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) &&
  969. (dd->ipath_flags & IPATH_GPIO_INTR)) {
  970. /*
  971. * GPIO status bit 2 is set, and we expected it.
  972. * clear it and indicate in p0bits.
  973. * This probably only happens if a Port0 pkt
  974. * arrives at _just_ the wrong time, and we
  975. * handle that by seting chk0rcv;
  976. */
  977. to_clear |= (1 << IPATH_GPIO_PORT0_BIT);
  978. gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT);
  979. chk0rcv = 1;
  980. }
  981. if (gpiostatus) {
  982. /*
  983. * Some unexpected bits remain. If they could have
  984. * caused the interrupt, complain and clear.
  985. * MEA: this is almost certainly non-ideal.
  986. * we should look into auto-disable of unexpected
  987. * GPIO interrupts, possibly on a "three strikes"
  988. * basis.
  989. */
  990. const u32 mask = (u32) dd->ipath_gpio_mask;
  991. if (mask & gpiostatus) {
  992. ipath_dbg("Unexpected GPIO IRQ bits %x\n",
  993. gpiostatus & mask);
  994. to_clear |= (gpiostatus & mask);
  995. }
  996. }
  997. if (to_clear) {
  998. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  999. (u64) to_clear);
  1000. }
  1001. }
  1002. chk0rcv |= istat & port0rbits;
  1003. /*
  1004. * Clear the interrupt bits we found set, unless they are receive
  1005. * related, in which case we already cleared them above, and don't
  1006. * want to clear them again, because we might lose an interrupt.
  1007. * Clear it early, so we "know" know the chip will have seen this by
  1008. * the time we process the queue, and will re-interrupt if necessary.
  1009. * The processor itself won't take the interrupt again until we return.
  1010. */
  1011. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
  1012. /*
  1013. * handle port0 receive before checking for pio buffers available,
  1014. * since receives can overflow; piobuf waiters can afford a few
  1015. * extra cycles, since they were waiting anyway, and user's waiting
  1016. * for receive are at the bottom.
  1017. */
  1018. if (chk0rcv) {
  1019. ipath_kreceive(dd);
  1020. istat &= ~port0rbits;
  1021. }
  1022. if (istat & ((dd->ipath_i_rcvavail_mask <<
  1023. INFINIPATH_I_RCVAVAIL_SHIFT)
  1024. | (dd->ipath_i_rcvurg_mask <<
  1025. INFINIPATH_I_RCVURG_SHIFT)))
  1026. handle_urcv(dd, istat);
  1027. if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
  1028. clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  1029. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  1030. dd->ipath_sendctrl);
  1031. if (dd->ipath_portpiowait)
  1032. handle_port_pioavail(dd);
  1033. handle_layer_pioavail(dd);
  1034. }
  1035. done:
  1036. ret = IRQ_HANDLED;
  1037. bail:
  1038. return ret;
  1039. }