cpufreq-cpu0.c 6.2 KB

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  1. /*
  2. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The OPP code in function cpu0_set_target() is reused from
  5. * drivers/cpufreq/omap-cpufreq.c
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/clk.h>
  13. #include <linux/cpu.h>
  14. #include <linux/cpufreq.h>
  15. #include <linux/err.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/pm_opp.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. static unsigned int transition_latency;
  23. static unsigned int voltage_tolerance; /* in percentage */
  24. static struct device *cpu_dev;
  25. static struct clk *cpu_clk;
  26. static struct regulator *cpu_reg;
  27. static struct cpufreq_frequency_table *freq_table;
  28. static unsigned int cpu0_get_speed(unsigned int cpu)
  29. {
  30. return clk_get_rate(cpu_clk) / 1000;
  31. }
  32. static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
  33. {
  34. struct cpufreq_freqs freqs;
  35. struct dev_pm_opp *opp;
  36. unsigned long volt = 0, volt_old = 0, tol = 0;
  37. long freq_Hz, freq_exact;
  38. int ret;
  39. freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
  40. if (freq_Hz < 0)
  41. freq_Hz = freq_table[index].frequency * 1000;
  42. freq_exact = freq_Hz;
  43. freqs.new = freq_Hz / 1000;
  44. freqs.old = clk_get_rate(cpu_clk) / 1000;
  45. cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  46. if (!IS_ERR(cpu_reg)) {
  47. rcu_read_lock();
  48. opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
  49. if (IS_ERR(opp)) {
  50. rcu_read_unlock();
  51. pr_err("failed to find OPP for %ld\n", freq_Hz);
  52. freqs.new = freqs.old;
  53. ret = PTR_ERR(opp);
  54. goto post_notify;
  55. }
  56. volt = dev_pm_opp_get_voltage(opp);
  57. rcu_read_unlock();
  58. tol = volt * voltage_tolerance / 100;
  59. volt_old = regulator_get_voltage(cpu_reg);
  60. }
  61. pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
  62. freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
  63. freqs.new / 1000, volt ? volt / 1000 : -1);
  64. /* scaling up? scale voltage before frequency */
  65. if (!IS_ERR(cpu_reg) && freqs.new > freqs.old) {
  66. ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
  67. if (ret) {
  68. pr_err("failed to scale voltage up: %d\n", ret);
  69. freqs.new = freqs.old;
  70. goto post_notify;
  71. }
  72. }
  73. ret = clk_set_rate(cpu_clk, freq_exact);
  74. if (ret) {
  75. pr_err("failed to set clock rate: %d\n", ret);
  76. if (!IS_ERR(cpu_reg))
  77. regulator_set_voltage_tol(cpu_reg, volt_old, tol);
  78. freqs.new = freqs.old;
  79. goto post_notify;
  80. }
  81. /* scaling down? scale voltage after frequency */
  82. if (!IS_ERR(cpu_reg) && freqs.new < freqs.old) {
  83. ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
  84. if (ret) {
  85. pr_err("failed to scale voltage down: %d\n", ret);
  86. clk_set_rate(cpu_clk, freqs.old * 1000);
  87. freqs.new = freqs.old;
  88. }
  89. }
  90. post_notify:
  91. cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
  92. return ret;
  93. }
  94. static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
  95. {
  96. return cpufreq_generic_init(policy, freq_table, transition_latency);
  97. }
  98. static struct cpufreq_driver cpu0_cpufreq_driver = {
  99. .flags = CPUFREQ_STICKY,
  100. .verify = cpufreq_generic_frequency_table_verify,
  101. .target_index = cpu0_set_target,
  102. .get = cpu0_get_speed,
  103. .init = cpu0_cpufreq_init,
  104. .exit = cpufreq_generic_exit,
  105. .name = "generic_cpu0",
  106. .attr = cpufreq_generic_attr,
  107. };
  108. static int cpu0_cpufreq_probe(struct platform_device *pdev)
  109. {
  110. struct device_node *np;
  111. int ret;
  112. cpu_dev = get_cpu_device(0);
  113. if (!cpu_dev) {
  114. pr_err("failed to get cpu0 device\n");
  115. return -ENODEV;
  116. }
  117. np = of_node_get(cpu_dev->of_node);
  118. if (!np) {
  119. pr_err("failed to find cpu0 node\n");
  120. return -ENOENT;
  121. }
  122. cpu_reg = devm_regulator_get_optional(cpu_dev, "cpu0");
  123. if (IS_ERR(cpu_reg)) {
  124. /*
  125. * If cpu0 regulator supply node is present, but regulator is
  126. * not yet registered, we should try defering probe.
  127. */
  128. if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
  129. dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
  130. ret = -EPROBE_DEFER;
  131. goto out_put_node;
  132. }
  133. pr_warn("failed to get cpu0 regulator: %ld\n",
  134. PTR_ERR(cpu_reg));
  135. }
  136. cpu_clk = devm_clk_get(cpu_dev, NULL);
  137. if (IS_ERR(cpu_clk)) {
  138. ret = PTR_ERR(cpu_clk);
  139. pr_err("failed to get cpu0 clock: %d\n", ret);
  140. goto out_put_node;
  141. }
  142. ret = of_init_opp_table(cpu_dev);
  143. if (ret) {
  144. pr_err("failed to init OPP table: %d\n", ret);
  145. goto out_put_node;
  146. }
  147. ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
  148. if (ret) {
  149. pr_err("failed to init cpufreq table: %d\n", ret);
  150. goto out_put_node;
  151. }
  152. of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
  153. if (of_property_read_u32(np, "clock-latency", &transition_latency))
  154. transition_latency = CPUFREQ_ETERNAL;
  155. if (!IS_ERR(cpu_reg)) {
  156. struct dev_pm_opp *opp;
  157. unsigned long min_uV, max_uV;
  158. int i;
  159. /*
  160. * OPP is maintained in order of increasing frequency, and
  161. * freq_table initialised from OPP is therefore sorted in the
  162. * same order.
  163. */
  164. for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
  165. ;
  166. rcu_read_lock();
  167. opp = dev_pm_opp_find_freq_exact(cpu_dev,
  168. freq_table[0].frequency * 1000, true);
  169. min_uV = dev_pm_opp_get_voltage(opp);
  170. opp = dev_pm_opp_find_freq_exact(cpu_dev,
  171. freq_table[i-1].frequency * 1000, true);
  172. max_uV = dev_pm_opp_get_voltage(opp);
  173. rcu_read_unlock();
  174. ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
  175. if (ret > 0)
  176. transition_latency += ret * 1000;
  177. }
  178. ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
  179. if (ret) {
  180. pr_err("failed register driver: %d\n", ret);
  181. goto out_free_table;
  182. }
  183. of_node_put(np);
  184. return 0;
  185. out_free_table:
  186. dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
  187. out_put_node:
  188. of_node_put(np);
  189. return ret;
  190. }
  191. static int cpu0_cpufreq_remove(struct platform_device *pdev)
  192. {
  193. cpufreq_unregister_driver(&cpu0_cpufreq_driver);
  194. dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
  195. return 0;
  196. }
  197. static struct platform_driver cpu0_cpufreq_platdrv = {
  198. .driver = {
  199. .name = "cpufreq-cpu0",
  200. .owner = THIS_MODULE,
  201. },
  202. .probe = cpu0_cpufreq_probe,
  203. .remove = cpu0_cpufreq_remove,
  204. };
  205. module_platform_driver(cpu0_cpufreq_platdrv);
  206. MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
  207. MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
  208. MODULE_LICENSE("GPL");