cx23885-dvb.c 29 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "tda10048.h"
  39. #include "tuner-xc2028.h"
  40. #include "tuner-simple.h"
  41. #include "dib7000p.h"
  42. #include "dibx000_common.h"
  43. #include "zl10353.h"
  44. #include "stv0900.h"
  45. #include "stv0900_reg.h"
  46. #include "stv6110.h"
  47. #include "lnbh24.h"
  48. #include "cx24116.h"
  49. #include "cimax2.h"
  50. #include "lgs8gxx.h"
  51. #include "netup-eeprom.h"
  52. #include "netup-init.h"
  53. #include "lgdt3305.h"
  54. static unsigned int debug;
  55. #define dprintk(level, fmt, arg...)\
  56. do { if (debug >= level)\
  57. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  58. } while (0)
  59. /* ------------------------------------------------------------------ */
  60. static unsigned int alt_tuner;
  61. module_param(alt_tuner, int, 0644);
  62. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  63. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  64. /* ------------------------------------------------------------------ */
  65. static int dvb_buf_setup(struct videobuf_queue *q,
  66. unsigned int *count, unsigned int *size)
  67. {
  68. struct cx23885_tsport *port = q->priv_data;
  69. port->ts_packet_size = 188 * 4;
  70. port->ts_packet_count = 32;
  71. *size = port->ts_packet_size * port->ts_packet_count;
  72. *count = 32;
  73. return 0;
  74. }
  75. static int dvb_buf_prepare(struct videobuf_queue *q,
  76. struct videobuf_buffer *vb, enum v4l2_field field)
  77. {
  78. struct cx23885_tsport *port = q->priv_data;
  79. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  80. }
  81. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  82. {
  83. struct cx23885_tsport *port = q->priv_data;
  84. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  85. }
  86. static void dvb_buf_release(struct videobuf_queue *q,
  87. struct videobuf_buffer *vb)
  88. {
  89. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  90. }
  91. static struct videobuf_queue_ops dvb_qops = {
  92. .buf_setup = dvb_buf_setup,
  93. .buf_prepare = dvb_buf_prepare,
  94. .buf_queue = dvb_buf_queue,
  95. .buf_release = dvb_buf_release,
  96. };
  97. static struct s5h1409_config hauppauge_generic_config = {
  98. .demod_address = 0x32 >> 1,
  99. .output_mode = S5H1409_SERIAL_OUTPUT,
  100. .gpio = S5H1409_GPIO_ON,
  101. .qam_if = 44000,
  102. .inversion = S5H1409_INVERSION_OFF,
  103. .status_mode = S5H1409_DEMODLOCKING,
  104. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  105. };
  106. static struct tda10048_config hauppauge_hvr1200_config = {
  107. .demod_address = 0x10 >> 1,
  108. .output_mode = TDA10048_SERIAL_OUTPUT,
  109. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  110. .inversion = TDA10048_INVERSION_ON,
  111. .dtv6_if_freq_khz = TDA10048_IF_3300,
  112. .dtv7_if_freq_khz = TDA10048_IF_3800,
  113. .dtv8_if_freq_khz = TDA10048_IF_4300,
  114. .clk_freq_khz = TDA10048_CLK_16000,
  115. };
  116. static struct tda10048_config hauppauge_hvr1210_config = {
  117. .demod_address = 0x10 >> 1,
  118. .output_mode = TDA10048_SERIAL_OUTPUT,
  119. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  120. .inversion = TDA10048_INVERSION_ON,
  121. .dtv6_if_freq_khz = TDA10048_IF_3300,
  122. .dtv7_if_freq_khz = TDA10048_IF_3500,
  123. .dtv8_if_freq_khz = TDA10048_IF_4000,
  124. .clk_freq_khz = TDA10048_CLK_16000,
  125. };
  126. static struct s5h1409_config hauppauge_ezqam_config = {
  127. .demod_address = 0x32 >> 1,
  128. .output_mode = S5H1409_SERIAL_OUTPUT,
  129. .gpio = S5H1409_GPIO_OFF,
  130. .qam_if = 4000,
  131. .inversion = S5H1409_INVERSION_ON,
  132. .status_mode = S5H1409_DEMODLOCKING,
  133. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  134. };
  135. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  136. .demod_address = 0x32 >> 1,
  137. .output_mode = S5H1409_SERIAL_OUTPUT,
  138. .gpio = S5H1409_GPIO_OFF,
  139. .qam_if = 44000,
  140. .inversion = S5H1409_INVERSION_OFF,
  141. .status_mode = S5H1409_DEMODLOCKING,
  142. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  143. };
  144. static struct s5h1409_config hauppauge_hvr1500_config = {
  145. .demod_address = 0x32 >> 1,
  146. .output_mode = S5H1409_SERIAL_OUTPUT,
  147. .gpio = S5H1409_GPIO_OFF,
  148. .inversion = S5H1409_INVERSION_OFF,
  149. .status_mode = S5H1409_DEMODLOCKING,
  150. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  151. };
  152. static struct mt2131_config hauppauge_generic_tunerconfig = {
  153. 0x61
  154. };
  155. static struct lgdt330x_config fusionhdtv_5_express = {
  156. .demod_address = 0x0e,
  157. .demod_chip = LGDT3303,
  158. .serial_mpeg = 0x40,
  159. };
  160. static struct s5h1409_config hauppauge_hvr1500q_config = {
  161. .demod_address = 0x32 >> 1,
  162. .output_mode = S5H1409_SERIAL_OUTPUT,
  163. .gpio = S5H1409_GPIO_ON,
  164. .qam_if = 44000,
  165. .inversion = S5H1409_INVERSION_OFF,
  166. .status_mode = S5H1409_DEMODLOCKING,
  167. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  168. };
  169. static struct s5h1409_config dvico_s5h1409_config = {
  170. .demod_address = 0x32 >> 1,
  171. .output_mode = S5H1409_SERIAL_OUTPUT,
  172. .gpio = S5H1409_GPIO_ON,
  173. .qam_if = 44000,
  174. .inversion = S5H1409_INVERSION_OFF,
  175. .status_mode = S5H1409_DEMODLOCKING,
  176. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  177. };
  178. static struct s5h1411_config dvico_s5h1411_config = {
  179. .output_mode = S5H1411_SERIAL_OUTPUT,
  180. .gpio = S5H1411_GPIO_ON,
  181. .qam_if = S5H1411_IF_44000,
  182. .vsb_if = S5H1411_IF_44000,
  183. .inversion = S5H1411_INVERSION_OFF,
  184. .status_mode = S5H1411_DEMODLOCKING,
  185. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  186. };
  187. static struct s5h1411_config hcw_s5h1411_config = {
  188. .output_mode = S5H1411_SERIAL_OUTPUT,
  189. .gpio = S5H1411_GPIO_OFF,
  190. .vsb_if = S5H1411_IF_44000,
  191. .qam_if = S5H1411_IF_4000,
  192. .inversion = S5H1411_INVERSION_ON,
  193. .status_mode = S5H1411_DEMODLOCKING,
  194. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  197. .i2c_address = 0x61,
  198. .if_khz = 5380,
  199. };
  200. static struct xc5000_config dvico_xc5000_tunerconfig = {
  201. .i2c_address = 0x64,
  202. .if_khz = 5380,
  203. };
  204. static struct tda829x_config tda829x_no_probe = {
  205. .probe_tuner = TDA829X_DONT_PROBE,
  206. };
  207. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  208. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  209. .if_lvl = 6, .rfagc_top = 0x37 },
  210. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  211. .if_lvl = 6, .rfagc_top = 0x37 },
  212. };
  213. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  214. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  215. .if_lvl = 1, .rfagc_top = 0x37, },
  216. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  217. .if_lvl = 1, .rfagc_top = 0x37, },
  218. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  219. .if_lvl = 1, .rfagc_top = 0x37, },
  220. };
  221. static struct tda18271_config hauppauge_tda18271_config = {
  222. .std_map = &hauppauge_tda18271_std_map,
  223. .gate = TDA18271_GATE_ANALOG,
  224. .output_opt = TDA18271_OUTPUT_LT_OFF,
  225. };
  226. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  227. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  228. .gate = TDA18271_GATE_ANALOG,
  229. .output_opt = TDA18271_OUTPUT_LT_OFF,
  230. };
  231. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  232. .gate = TDA18271_GATE_DIGITAL,
  233. .output_opt = TDA18271_OUTPUT_LT_OFF,
  234. };
  235. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  236. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  237. .if_lvl = 1, .rfagc_top = 0x58 },
  238. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  239. .if_lvl = 1, .rfagc_top = 0x58 },
  240. };
  241. static struct tda18271_config hauppauge_hvr127x_config = {
  242. .std_map = &hauppauge_hvr127x_std_map,
  243. .output_opt = TDA18271_OUTPUT_LT_OFF,
  244. };
  245. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  246. .i2c_addr = 0x0e,
  247. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  248. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  249. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  250. .deny_i2c_rptr = 1,
  251. .spectral_inversion = 1,
  252. .qam_if_khz = 4000,
  253. .vsb_if_khz = 3250,
  254. };
  255. static struct dibx000_agc_config xc3028_agc_config = {
  256. BAND_VHF | BAND_UHF, /* band_caps */
  257. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  258. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  259. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  260. * P_agc_nb_est=2, P_agc_write=0
  261. */
  262. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  263. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  264. 712, /* inv_gain */
  265. 21, /* time_stabiliz */
  266. 0, /* alpha_level */
  267. 118, /* thlock */
  268. 0, /* wbd_inv */
  269. 2867, /* wbd_ref */
  270. 0, /* wbd_sel */
  271. 2, /* wbd_alpha */
  272. 0, /* agc1_max */
  273. 0, /* agc1_min */
  274. 39718, /* agc2_max */
  275. 9930, /* agc2_min */
  276. 0, /* agc1_pt1 */
  277. 0, /* agc1_pt2 */
  278. 0, /* agc1_pt3 */
  279. 0, /* agc1_slope1 */
  280. 0, /* agc1_slope2 */
  281. 0, /* agc2_pt1 */
  282. 128, /* agc2_pt2 */
  283. 29, /* agc2_slope1 */
  284. 29, /* agc2_slope2 */
  285. 17, /* alpha_mant */
  286. 27, /* alpha_exp */
  287. 23, /* beta_mant */
  288. 51, /* beta_exp */
  289. 1, /* perform_agc_softsplit */
  290. };
  291. /* PLL Configuration for COFDM BW_MHz = 8.000000
  292. * With external clock = 30.000000 */
  293. static struct dibx000_bandwidth_config xc3028_bw_config = {
  294. 60000, /* internal */
  295. 30000, /* sampling */
  296. 1, /* pll_cfg: prediv */
  297. 8, /* pll_cfg: ratio */
  298. 3, /* pll_cfg: range */
  299. 1, /* pll_cfg: reset */
  300. 0, /* pll_cfg: bypass */
  301. 0, /* misc: refdiv */
  302. 0, /* misc: bypclk_div */
  303. 1, /* misc: IO_CLK_en_core */
  304. 1, /* misc: ADClkSrc */
  305. 0, /* misc: modulo */
  306. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  307. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  308. 20452225, /* timf */
  309. 30000000 /* xtal_hz */
  310. };
  311. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  312. .output_mpeg2_in_188_bytes = 1,
  313. .hostbus_diversity = 1,
  314. .tuner_is_baseband = 0,
  315. .update_lna = NULL,
  316. .agc_config_count = 1,
  317. .agc = &xc3028_agc_config,
  318. .bw = &xc3028_bw_config,
  319. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  320. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  321. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  322. .pwm_freq_div = 0,
  323. .agc_control = NULL,
  324. .spur_protect = 0,
  325. .output_mode = OUTMODE_MPEG2_SERIAL,
  326. };
  327. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  328. .demod_address = 0x0f,
  329. .if2 = 45600,
  330. .no_tuner = 1,
  331. .disable_i2c_gate_ctrl = 1,
  332. };
  333. static struct stv0900_reg stv0900_ts_regs[] = {
  334. { R0900_TSGENERAL, 0x00 },
  335. { R0900_P1_TSSPEED, 0x40 },
  336. { R0900_P2_TSSPEED, 0x40 },
  337. { R0900_P1_TSCFGM, 0xc0 },
  338. { R0900_P2_TSCFGM, 0xc0 },
  339. { R0900_P1_TSCFGH, 0xe0 },
  340. { R0900_P2_TSCFGH, 0xe0 },
  341. { R0900_P1_TSCFGL, 0x20 },
  342. { R0900_P2_TSCFGL, 0x20 },
  343. { 0xffff, 0xff }, /* terminate */
  344. };
  345. static struct stv0900_config netup_stv0900_config = {
  346. .demod_address = 0x68,
  347. .xtal = 8000000,
  348. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  349. .diseqc_mode = 2,/* 2/3 PWM */
  350. .ts_config_regs = stv0900_ts_regs,
  351. .tun1_maddress = 0,/* 0x60 */
  352. .tun2_maddress = 3,/* 0x63 */
  353. .tun1_adc = 1,/* 1 Vpp */
  354. .tun2_adc = 1,/* 1 Vpp */
  355. };
  356. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  357. .i2c_address = 0x60,
  358. .mclk = 16000000,
  359. .clk_div = 1,
  360. .gain = 8, /* +16 dB - maximum gain */
  361. };
  362. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  363. .i2c_address = 0x63,
  364. .mclk = 16000000,
  365. .clk_div = 1,
  366. .gain = 8, /* +16 dB - maximum gain */
  367. };
  368. static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  369. {
  370. struct cx23885_tsport *port = fe->dvb->priv;
  371. struct cx23885_dev *dev = port->dev;
  372. if (voltage == SEC_VOLTAGE_18)
  373. cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
  374. else if (voltage == SEC_VOLTAGE_13)
  375. cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
  376. else
  377. cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
  378. return 0;
  379. }
  380. static struct cx24116_config tbs_cx24116_config = {
  381. .demod_address = 0x05,
  382. };
  383. static struct cx24116_config tevii_cx24116_config = {
  384. .demod_address = 0x55,
  385. };
  386. static struct cx24116_config dvbworld_cx24116_config = {
  387. .demod_address = 0x05,
  388. };
  389. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  390. .prod = LGS8GXX_PROD_LGS8GL5,
  391. .demod_address = 0x19,
  392. .serial_ts = 0,
  393. .ts_clk_pol = 1,
  394. .ts_clk_gated = 1,
  395. .if_clk_freq = 30400, /* 30.4 MHz */
  396. .if_freq = 5380, /* 5.38 MHz */
  397. .if_neg_center = 1,
  398. .ext_adc = 0,
  399. .adc_signed = 0,
  400. .if_neg_edge = 0,
  401. };
  402. static struct xc5000_config mygica_x8506_xc5000_config = {
  403. .i2c_address = 0x61,
  404. .if_khz = 5380,
  405. };
  406. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
  407. struct dvb_frontend_parameters *param)
  408. {
  409. struct cx23885_tsport *port = fe->dvb->priv;
  410. struct cx23885_dev *dev = port->dev;
  411. switch (dev->board) {
  412. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  413. switch (param->u.vsb.modulation) {
  414. case VSB_8:
  415. cx23885_gpio_clear(dev, GPIO_5);
  416. break;
  417. case QAM_64:
  418. case QAM_256:
  419. default:
  420. cx23885_gpio_set(dev, GPIO_5);
  421. break;
  422. }
  423. break;
  424. case CX23885_BOARD_MYGICA_X8506:
  425. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  426. /* Select Digital TV */
  427. cx23885_gpio_set(dev, GPIO_0);
  428. break;
  429. }
  430. return 0;
  431. }
  432. static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
  433. unsigned int cmd, void *parg,
  434. unsigned int stage)
  435. {
  436. int err = 0;
  437. switch (stage) {
  438. case DVB_FE_IOCTL_PRE:
  439. switch (cmd) {
  440. case FE_SET_FRONTEND:
  441. err = cx23885_dvb_set_frontend(fe,
  442. (struct dvb_frontend_parameters *) parg);
  443. break;
  444. }
  445. break;
  446. case DVB_FE_IOCTL_POST:
  447. /* no post-ioctl handling required */
  448. break;
  449. }
  450. return err;
  451. };
  452. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  453. .prod = LGS8GXX_PROD_LGS8G75,
  454. .demod_address = 0x19,
  455. .serial_ts = 0,
  456. .ts_clk_pol = 1,
  457. .ts_clk_gated = 1,
  458. .if_clk_freq = 30400, /* 30.4 MHz */
  459. .if_freq = 6500, /* 6.50 MHz */
  460. .if_neg_center = 1,
  461. .ext_adc = 0,
  462. .adc_signed = 1,
  463. .adc_vpp = 2, /* 1.6 Vpp */
  464. .if_neg_edge = 1,
  465. };
  466. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  467. .i2c_address = 0x61,
  468. .if_khz = 6500,
  469. };
  470. static int dvb_register(struct cx23885_tsport *port)
  471. {
  472. struct cx23885_dev *dev = port->dev;
  473. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  474. struct videobuf_dvb_frontend *fe0;
  475. int ret;
  476. /* Get the first frontend */
  477. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  478. if (!fe0)
  479. return -EINVAL;
  480. /* init struct videobuf_dvb */
  481. fe0->dvb.name = dev->name;
  482. /* init frontend */
  483. switch (dev->board) {
  484. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  485. i2c_bus = &dev->i2c_bus[0];
  486. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  487. &hauppauge_generic_config,
  488. &i2c_bus->i2c_adap);
  489. if (fe0->dvb.frontend != NULL) {
  490. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  491. &i2c_bus->i2c_adap,
  492. &hauppauge_generic_tunerconfig, 0);
  493. }
  494. break;
  495. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  496. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  497. i2c_bus = &dev->i2c_bus[0];
  498. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  499. &hauppauge_lgdt3305_config,
  500. &i2c_bus->i2c_adap);
  501. if (fe0->dvb.frontend != NULL) {
  502. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  503. 0x60, &dev->i2c_bus[1].i2c_adap,
  504. &hauppauge_hvr127x_config);
  505. }
  506. break;
  507. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  508. i2c_bus = &dev->i2c_bus[0];
  509. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  510. &hcw_s5h1411_config,
  511. &i2c_bus->i2c_adap);
  512. if (fe0->dvb.frontend != NULL) {
  513. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  514. 0x60, &dev->i2c_bus[1].i2c_adap,
  515. &hauppauge_tda18271_config);
  516. }
  517. break;
  518. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  519. i2c_bus = &dev->i2c_bus[0];
  520. switch (alt_tuner) {
  521. case 1:
  522. fe0->dvb.frontend =
  523. dvb_attach(s5h1409_attach,
  524. &hauppauge_ezqam_config,
  525. &i2c_bus->i2c_adap);
  526. if (fe0->dvb.frontend != NULL) {
  527. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  528. &dev->i2c_bus[1].i2c_adap, 0x42,
  529. &tda829x_no_probe);
  530. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  531. 0x60, &dev->i2c_bus[1].i2c_adap,
  532. &hauppauge_tda18271_config);
  533. }
  534. break;
  535. case 0:
  536. default:
  537. fe0->dvb.frontend =
  538. dvb_attach(s5h1409_attach,
  539. &hauppauge_generic_config,
  540. &i2c_bus->i2c_adap);
  541. if (fe0->dvb.frontend != NULL)
  542. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  543. &i2c_bus->i2c_adap,
  544. &hauppauge_generic_tunerconfig, 0);
  545. break;
  546. }
  547. break;
  548. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  549. i2c_bus = &dev->i2c_bus[0];
  550. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  551. &hauppauge_hvr1800lp_config,
  552. &i2c_bus->i2c_adap);
  553. if (fe0->dvb.frontend != NULL) {
  554. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  555. &i2c_bus->i2c_adap,
  556. &hauppauge_generic_tunerconfig, 0);
  557. }
  558. break;
  559. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  560. i2c_bus = &dev->i2c_bus[0];
  561. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  562. &fusionhdtv_5_express,
  563. &i2c_bus->i2c_adap);
  564. if (fe0->dvb.frontend != NULL) {
  565. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  566. &i2c_bus->i2c_adap, 0x61,
  567. TUNER_LG_TDVS_H06XF);
  568. }
  569. break;
  570. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  571. i2c_bus = &dev->i2c_bus[1];
  572. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  573. &hauppauge_hvr1500q_config,
  574. &dev->i2c_bus[0].i2c_adap);
  575. if (fe0->dvb.frontend != NULL)
  576. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  577. &i2c_bus->i2c_adap,
  578. &hauppauge_hvr1500q_tunerconfig);
  579. break;
  580. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  581. i2c_bus = &dev->i2c_bus[1];
  582. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  583. &hauppauge_hvr1500_config,
  584. &dev->i2c_bus[0].i2c_adap);
  585. if (fe0->dvb.frontend != NULL) {
  586. struct dvb_frontend *fe;
  587. struct xc2028_config cfg = {
  588. .i2c_adap = &i2c_bus->i2c_adap,
  589. .i2c_addr = 0x61,
  590. };
  591. static struct xc2028_ctrl ctl = {
  592. .fname = XC2028_DEFAULT_FIRMWARE,
  593. .max_len = 64,
  594. .demod = XC3028_FE_OREN538,
  595. };
  596. fe = dvb_attach(xc2028_attach,
  597. fe0->dvb.frontend, &cfg);
  598. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  599. fe->ops.tuner_ops.set_config(fe, &ctl);
  600. }
  601. break;
  602. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  603. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  604. i2c_bus = &dev->i2c_bus[0];
  605. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  606. &hauppauge_hvr1200_config,
  607. &i2c_bus->i2c_adap);
  608. if (fe0->dvb.frontend != NULL) {
  609. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  610. &dev->i2c_bus[1].i2c_adap, 0x42,
  611. &tda829x_no_probe);
  612. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  613. 0x60, &dev->i2c_bus[1].i2c_adap,
  614. &hauppauge_hvr1200_tuner_config);
  615. }
  616. break;
  617. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  618. i2c_bus = &dev->i2c_bus[0];
  619. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  620. &hauppauge_hvr1210_config,
  621. &i2c_bus->i2c_adap);
  622. if (fe0->dvb.frontend != NULL) {
  623. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  624. 0x60, &dev->i2c_bus[1].i2c_adap,
  625. &hauppauge_hvr1210_tuner_config);
  626. }
  627. break;
  628. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  629. i2c_bus = &dev->i2c_bus[0];
  630. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  631. &i2c_bus->i2c_adap,
  632. 0x12, &hauppauge_hvr1400_dib7000_config);
  633. if (fe0->dvb.frontend != NULL) {
  634. struct dvb_frontend *fe;
  635. struct xc2028_config cfg = {
  636. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  637. .i2c_addr = 0x64,
  638. };
  639. static struct xc2028_ctrl ctl = {
  640. .fname = XC3028L_DEFAULT_FIRMWARE,
  641. .max_len = 64,
  642. .demod = 5000,
  643. /* This is true for all demods with
  644. v36 firmware? */
  645. .type = XC2028_D2633,
  646. };
  647. fe = dvb_attach(xc2028_attach,
  648. fe0->dvb.frontend, &cfg);
  649. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  650. fe->ops.tuner_ops.set_config(fe, &ctl);
  651. }
  652. break;
  653. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  654. i2c_bus = &dev->i2c_bus[port->nr - 1];
  655. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  656. &dvico_s5h1409_config,
  657. &i2c_bus->i2c_adap);
  658. if (fe0->dvb.frontend == NULL)
  659. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  660. &dvico_s5h1411_config,
  661. &i2c_bus->i2c_adap);
  662. if (fe0->dvb.frontend != NULL)
  663. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  664. &i2c_bus->i2c_adap,
  665. &dvico_xc5000_tunerconfig);
  666. break;
  667. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  668. i2c_bus = &dev->i2c_bus[port->nr - 1];
  669. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  670. &dvico_fusionhdtv_xc3028,
  671. &i2c_bus->i2c_adap);
  672. if (fe0->dvb.frontend != NULL) {
  673. struct dvb_frontend *fe;
  674. struct xc2028_config cfg = {
  675. .i2c_adap = &i2c_bus->i2c_adap,
  676. .i2c_addr = 0x61,
  677. };
  678. static struct xc2028_ctrl ctl = {
  679. .fname = XC2028_DEFAULT_FIRMWARE,
  680. .max_len = 64,
  681. .demod = XC3028_FE_ZARLINK456,
  682. };
  683. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  684. &cfg);
  685. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  686. fe->ops.tuner_ops.set_config(fe, &ctl);
  687. }
  688. break;
  689. }
  690. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  691. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  692. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  693. i2c_bus = &dev->i2c_bus[0];
  694. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  695. &dvico_fusionhdtv_xc3028,
  696. &i2c_bus->i2c_adap);
  697. if (fe0->dvb.frontend != NULL) {
  698. struct dvb_frontend *fe;
  699. struct xc2028_config cfg = {
  700. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  701. .i2c_addr = 0x61,
  702. };
  703. static struct xc2028_ctrl ctl = {
  704. .fname = XC2028_DEFAULT_FIRMWARE,
  705. .max_len = 64,
  706. .demod = XC3028_FE_ZARLINK456,
  707. };
  708. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  709. &cfg);
  710. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  711. fe->ops.tuner_ops.set_config(fe, &ctl);
  712. }
  713. break;
  714. case CX23885_BOARD_TBS_6920:
  715. i2c_bus = &dev->i2c_bus[0];
  716. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  717. &tbs_cx24116_config,
  718. &i2c_bus->i2c_adap);
  719. if (fe0->dvb.frontend != NULL)
  720. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  721. break;
  722. case CX23885_BOARD_TEVII_S470:
  723. i2c_bus = &dev->i2c_bus[1];
  724. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  725. &tevii_cx24116_config,
  726. &i2c_bus->i2c_adap);
  727. if (fe0->dvb.frontend != NULL)
  728. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  729. break;
  730. case CX23885_BOARD_DVBWORLD_2005:
  731. i2c_bus = &dev->i2c_bus[1];
  732. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  733. &dvbworld_cx24116_config,
  734. &i2c_bus->i2c_adap);
  735. break;
  736. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  737. i2c_bus = &dev->i2c_bus[0];
  738. switch (port->nr) {
  739. /* port B */
  740. case 1:
  741. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  742. &netup_stv0900_config,
  743. &i2c_bus->i2c_adap, 0);
  744. if (fe0->dvb.frontend != NULL) {
  745. if (dvb_attach(stv6110_attach,
  746. fe0->dvb.frontend,
  747. &netup_stv6110_tunerconfig_a,
  748. &i2c_bus->i2c_adap)) {
  749. if (!dvb_attach(lnbh24_attach,
  750. fe0->dvb.frontend,
  751. &i2c_bus->i2c_adap,
  752. LNBH24_PCL | LNBH24_TTX,
  753. LNBH24_TEN, 0x09))
  754. printk(KERN_ERR
  755. "No LNBH24 found!\n");
  756. }
  757. }
  758. break;
  759. /* port C */
  760. case 2:
  761. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  762. &netup_stv0900_config,
  763. &i2c_bus->i2c_adap, 1);
  764. if (fe0->dvb.frontend != NULL) {
  765. if (dvb_attach(stv6110_attach,
  766. fe0->dvb.frontend,
  767. &netup_stv6110_tunerconfig_b,
  768. &i2c_bus->i2c_adap)) {
  769. if (!dvb_attach(lnbh24_attach,
  770. fe0->dvb.frontend,
  771. &i2c_bus->i2c_adap,
  772. LNBH24_PCL | LNBH24_TTX,
  773. LNBH24_TEN, 0x0a))
  774. printk(KERN_ERR
  775. "No LNBH24 found!\n");
  776. }
  777. }
  778. break;
  779. }
  780. break;
  781. case CX23885_BOARD_MYGICA_X8506:
  782. i2c_bus = &dev->i2c_bus[0];
  783. i2c_bus2 = &dev->i2c_bus[1];
  784. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  785. &mygica_x8506_lgs8gl5_config,
  786. &i2c_bus->i2c_adap);
  787. if (fe0->dvb.frontend != NULL) {
  788. dvb_attach(xc5000_attach,
  789. fe0->dvb.frontend,
  790. &i2c_bus2->i2c_adap,
  791. &mygica_x8506_xc5000_config);
  792. }
  793. break;
  794. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  795. i2c_bus = &dev->i2c_bus[0];
  796. i2c_bus2 = &dev->i2c_bus[1];
  797. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  798. &magicpro_prohdtve2_lgs8g75_config,
  799. &i2c_bus->i2c_adap);
  800. if (fe0->dvb.frontend != NULL) {
  801. dvb_attach(xc5000_attach,
  802. fe0->dvb.frontend,
  803. &i2c_bus2->i2c_adap,
  804. &magicpro_prohdtve2_xc5000_config);
  805. }
  806. break;
  807. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  808. i2c_bus = &dev->i2c_bus[0];
  809. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  810. &hcw_s5h1411_config,
  811. &i2c_bus->i2c_adap);
  812. if (fe0->dvb.frontend != NULL)
  813. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  814. 0x60, &dev->i2c_bus[0].i2c_adap,
  815. &hauppauge_tda18271_config);
  816. break;
  817. default:
  818. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  819. " isn't supported yet\n",
  820. dev->name);
  821. break;
  822. }
  823. if (NULL == fe0->dvb.frontend) {
  824. printk(KERN_ERR "%s: frontend initialization failed\n",
  825. dev->name);
  826. return -1;
  827. }
  828. /* define general-purpose callback pointer */
  829. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  830. /* Put the analog decoder in standby to keep it quiet */
  831. call_all(dev, core, s_power, 0);
  832. if (fe0->dvb.frontend->ops.analog_ops.standby)
  833. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  834. /* register everything */
  835. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  836. &dev->pci->dev, adapter_nr, 0,
  837. cx23885_dvb_fe_ioctl_override);
  838. /* init CI & MAC */
  839. switch (dev->board) {
  840. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  841. static struct netup_card_info cinfo;
  842. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  843. memcpy(port->frontends.adapter.proposed_mac,
  844. cinfo.port[port->nr - 1].mac, 6);
  845. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
  846. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  847. port->nr,
  848. port->frontends.adapter.proposed_mac[0],
  849. port->frontends.adapter.proposed_mac[1],
  850. port->frontends.adapter.proposed_mac[2],
  851. port->frontends.adapter.proposed_mac[3],
  852. port->frontends.adapter.proposed_mac[4],
  853. port->frontends.adapter.proposed_mac[5]);
  854. netup_ci_init(port);
  855. break;
  856. }
  857. }
  858. return ret;
  859. }
  860. int cx23885_dvb_register(struct cx23885_tsport *port)
  861. {
  862. struct videobuf_dvb_frontend *fe0;
  863. struct cx23885_dev *dev = port->dev;
  864. int err, i;
  865. /* Here we need to allocate the correct number of frontends,
  866. * as reflected in the cards struct. The reality is that currrently
  867. * no cx23885 boards support this - yet. But, if we don't modify this
  868. * code then the second frontend would never be allocated (later)
  869. * and fail with error before the attach in dvb_register().
  870. * Without these changes we risk an OOPS later. The changes here
  871. * are for safety, and should provide a good foundation for the
  872. * future addition of any multi-frontend cx23885 based boards.
  873. */
  874. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  875. port->num_frontends);
  876. for (i = 1; i <= port->num_frontends; i++) {
  877. if (videobuf_dvb_alloc_frontend(
  878. &port->frontends, i) == NULL) {
  879. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  880. return -ENOMEM;
  881. }
  882. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  883. if (!fe0)
  884. err = -EINVAL;
  885. dprintk(1, "%s\n", __func__);
  886. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  887. dev->board,
  888. dev->name,
  889. dev->pci_bus,
  890. dev->pci_slot);
  891. err = -ENODEV;
  892. /* dvb stuff */
  893. /* We have to init the queue for each frontend on a port. */
  894. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  895. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  896. &dev->pci->dev, &port->slock,
  897. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  898. sizeof(struct cx23885_buffer), port);
  899. }
  900. err = dvb_register(port);
  901. if (err != 0)
  902. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  903. __func__, err);
  904. return err;
  905. }
  906. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  907. {
  908. struct videobuf_dvb_frontend *fe0;
  909. /* FIXME: in an error condition where the we have
  910. * an expected number of frontends (attach problem)
  911. * then this might not clean up correctly, if 1
  912. * is invalid.
  913. * This comment only applies to future boards IF they
  914. * implement MFE support.
  915. */
  916. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  917. if (fe0->dvb.frontend)
  918. videobuf_dvb_unregister_bus(&port->frontends);
  919. switch (port->dev->board) {
  920. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  921. netup_ci_exit(port);
  922. break;
  923. }
  924. return 0;
  925. }