at91sam9260.dtsi 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598
  1. /*
  2. * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  7. *
  8. * Licensed under GPLv2 or later.
  9. */
  10. #include "skeleton.dtsi"
  11. #include <dt-bindings/gpio/gpio.h>
  12. / {
  13. model = "Atmel AT91SAM9260 family SoC";
  14. compatible = "atmel,at91sam9260";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. serial5 = &uart0;
  23. serial6 = &uart1;
  24. gpio0 = &pioA;
  25. gpio1 = &pioB;
  26. gpio2 = &pioC;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. ssc0 = &ssc0;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x20000000 0x04000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <29 30 31>;
  56. };
  57. ramc0: ramc@ffffea00 {
  58. compatible = "atmel,at91sam9260-sdramc";
  59. reg = <0xffffea00 0x200>;
  60. };
  61. pmc: pmc@fffffc00 {
  62. compatible = "atmel,at91rm9200-pmc";
  63. reg = <0xfffffc00 0x100>;
  64. };
  65. rstc@fffffd00 {
  66. compatible = "atmel,at91sam9260-rstc";
  67. reg = <0xfffffd00 0x10>;
  68. };
  69. shdwc@fffffd10 {
  70. compatible = "atmel,at91sam9260-shdwc";
  71. reg = <0xfffffd10 0x10>;
  72. };
  73. pit: timer@fffffd30 {
  74. compatible = "atmel,at91sam9260-pit";
  75. reg = <0xfffffd30 0xf>;
  76. interrupts = <1 4 7>;
  77. };
  78. tcb0: timer@fffa0000 {
  79. compatible = "atmel,at91rm9200-tcb";
  80. reg = <0xfffa0000 0x100>;
  81. interrupts = <17 4 0 18 4 0 19 4 0>;
  82. };
  83. tcb1: timer@fffdc000 {
  84. compatible = "atmel,at91rm9200-tcb";
  85. reg = <0xfffdc000 0x100>;
  86. interrupts = <26 4 0 27 4 0 28 4 0>;
  87. };
  88. pinctrl@fffff400 {
  89. #address-cells = <1>;
  90. #size-cells = <1>;
  91. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  92. ranges = <0xfffff400 0xfffff400 0x600>;
  93. atmel,mux-mask = <
  94. /* A B */
  95. 0xffffffff 0xffc00c3b /* pioA */
  96. 0xffffffff 0x7fff3ccf /* pioB */
  97. 0xffffffff 0x007fffff /* pioC */
  98. >;
  99. /* shared pinctrl settings */
  100. dbgu {
  101. pinctrl_dbgu: dbgu-0 {
  102. atmel,pins =
  103. <1 14 0x1 0x0 /* PB14 periph A */
  104. 1 15 0x1 0x1>; /* PB15 periph with pullup */
  105. };
  106. };
  107. usart0 {
  108. pinctrl_usart0: usart0-0 {
  109. atmel,pins =
  110. <1 4 0x1 0x0 /* PB4 periph A */
  111. 1 5 0x1 0x0>; /* PB5 periph A */
  112. };
  113. pinctrl_usart0_rts: usart0_rts-0 {
  114. atmel,pins =
  115. <1 26 0x1 0x0>; /* PB26 periph A */
  116. };
  117. pinctrl_usart0_cts: usart0_cts-0 {
  118. atmel,pins =
  119. <1 27 0x1 0x0>; /* PB27 periph A */
  120. };
  121. pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
  122. atmel,pins =
  123. <1 24 0x1 0x0 /* PB24 periph A */
  124. 1 22 0x1 0x0>; /* PB22 periph A */
  125. };
  126. pinctrl_usart0_dcd: usart0_dcd-0 {
  127. atmel,pins =
  128. <1 23 0x1 0x0>; /* PB23 periph A */
  129. };
  130. pinctrl_usart0_ri: usart0_ri-0 {
  131. atmel,pins =
  132. <1 25 0x1 0x0>; /* PB25 periph A */
  133. };
  134. };
  135. usart1 {
  136. pinctrl_usart1: usart1-0 {
  137. atmel,pins =
  138. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  139. 1 7 0x1 0x0>; /* PB7 periph A */
  140. };
  141. pinctrl_usart1_rts: usart1_rts-0 {
  142. atmel,pins =
  143. <1 28 0x1 0x0>; /* PB28 periph A */
  144. };
  145. pinctrl_usart1_cts: usart1_cts-0 {
  146. atmel,pins =
  147. <1 29 0x1 0x0>; /* PB29 periph A */
  148. };
  149. };
  150. usart2 {
  151. pinctrl_usart2: usart2-0 {
  152. atmel,pins =
  153. <1 8 0x1 0x1 /* PB8 periph A with pullup */
  154. 1 9 0x1 0x0>; /* PB9 periph A */
  155. };
  156. pinctrl_usart2_rts: usart2_rts-0 {
  157. atmel,pins =
  158. <0 4 0x1 0x0>; /* PA4 periph A */
  159. };
  160. pinctrl_usart2_cts: usart2_cts-0 {
  161. atmel,pins =
  162. <0 5 0x1 0x0>; /* PA5 periph A */
  163. };
  164. };
  165. usart3 {
  166. pinctrl_usart3: usart3-0 {
  167. atmel,pins =
  168. <1 10 0x1 0x1 /* PB10 periph A with pullup */
  169. 1 11 0x1 0x0>; /* PB11 periph A */
  170. };
  171. pinctrl_usart3_rts: usart3_rts-0 {
  172. atmel,pins =
  173. <2 8 0x2 0x0>; /* PC8 periph B */
  174. };
  175. pinctrl_usart3_cts: usart3_cts-0 {
  176. atmel,pins =
  177. <2 10 0x2 0x0>; /* PC10 periph B */
  178. };
  179. };
  180. uart0 {
  181. pinctrl_uart0: uart0-0 {
  182. atmel,pins =
  183. <0 31 0x2 0x1 /* PA31 periph B with pullup */
  184. 0 30 0x2 0x0>; /* PA30 periph B */
  185. };
  186. };
  187. uart1 {
  188. pinctrl_uart1: uart1-0 {
  189. atmel,pins =
  190. <1 12 0x1 0x1 /* PB12 periph A with pullup */
  191. 1 13 0x1 0x0>; /* PB13 periph A */
  192. };
  193. };
  194. nand {
  195. pinctrl_nand: nand-0 {
  196. atmel,pins =
  197. <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
  198. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  199. };
  200. };
  201. macb {
  202. pinctrl_macb_rmii: macb_rmii-0 {
  203. atmel,pins =
  204. <0 12 0x1 0x0 /* PA12 periph A */
  205. 0 13 0x1 0x0 /* PA13 periph A */
  206. 0 14 0x1 0x0 /* PA14 periph A */
  207. 0 15 0x1 0x0 /* PA15 periph A */
  208. 0 16 0x1 0x0 /* PA16 periph A */
  209. 0 17 0x1 0x0 /* PA17 periph A */
  210. 0 18 0x1 0x0 /* PA18 periph A */
  211. 0 19 0x1 0x0 /* PA19 periph A */
  212. 0 20 0x1 0x0 /* PA20 periph A */
  213. 0 21 0x1 0x0>; /* PA21 periph A */
  214. };
  215. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  216. atmel,pins =
  217. <0 22 0x2 0x0 /* PA22 periph B */
  218. 0 23 0x2 0x0 /* PA23 periph B */
  219. 0 24 0x2 0x0 /* PA24 periph B */
  220. 0 25 0x2 0x0 /* PA25 periph B */
  221. 0 26 0x2 0x0 /* PA26 periph B */
  222. 0 27 0x2 0x0 /* PA27 periph B */
  223. 0 28 0x2 0x0 /* PA28 periph B */
  224. 0 29 0x2 0x0>; /* PA29 periph B */
  225. };
  226. pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
  227. atmel,pins =
  228. <0 10 0x2 0x0 /* PA10 periph B */
  229. 0 11 0x2 0x0 /* PA11 periph B */
  230. 0 24 0x2 0x0 /* PA24 periph B */
  231. 0 25 0x2 0x0 /* PA25 periph B */
  232. 0 26 0x2 0x0 /* PA26 periph B */
  233. 0 27 0x2 0x0 /* PA27 periph B */
  234. 0 28 0x2 0x0 /* PA28 periph B */
  235. 0 29 0x2 0x0>; /* PA29 periph B */
  236. };
  237. };
  238. mmc0 {
  239. pinctrl_mmc0_clk: mmc0_clk-0 {
  240. atmel,pins =
  241. <0 8 0x1 0x0>; /* PA8 periph A */
  242. };
  243. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  244. atmel,pins =
  245. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  246. 0 6 0x1 0x1>; /* PA6 periph A with pullup */
  247. };
  248. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  249. atmel,pins =
  250. <0 9 0x1 0x1 /* PA9 periph A with pullup */
  251. 0 10 0x1 0x1 /* PA10 periph A with pullup */
  252. 0 11 0x1 0x1>; /* PA11 periph A with pullup */
  253. };
  254. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  255. atmel,pins =
  256. <0 1 0x2 0x1 /* PA1 periph B with pullup */
  257. 0 0 0x2 0x1>; /* PA0 periph B with pullup */
  258. };
  259. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  260. atmel,pins =
  261. <0 5 0x2 0x1 /* PA5 periph B with pullup */
  262. 0 4 0x2 0x1 /* PA4 periph B with pullup */
  263. 0 3 0x2 0x1>; /* PA3 periph B with pullup */
  264. };
  265. };
  266. ssc0 {
  267. pinctrl_ssc0_tx: ssc0_tx-0 {
  268. atmel,pins =
  269. <1 16 0x1 0x0 /* PB16 periph A */
  270. 1 17 0x1 0x0 /* PB17 periph A */
  271. 1 18 0x1 0x0>; /* PB18 periph A */
  272. };
  273. pinctrl_ssc0_rx: ssc0_rx-0 {
  274. atmel,pins =
  275. <1 19 0x1 0x0 /* PB19 periph A */
  276. 1 20 0x1 0x0 /* PB20 periph A */
  277. 1 21 0x1 0x0>; /* PB21 periph A */
  278. };
  279. };
  280. spi0 {
  281. pinctrl_spi0: spi0-0 {
  282. atmel,pins =
  283. <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */
  284. 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */
  285. 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */
  286. };
  287. };
  288. spi1 {
  289. pinctrl_spi1: spi1-0 {
  290. atmel,pins =
  291. <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */
  292. 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */
  293. 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */
  294. };
  295. };
  296. pioA: gpio@fffff400 {
  297. compatible = "atmel,at91rm9200-gpio";
  298. reg = <0xfffff400 0x200>;
  299. interrupts = <2 4 1>;
  300. #gpio-cells = <2>;
  301. gpio-controller;
  302. interrupt-controller;
  303. #interrupt-cells = <2>;
  304. };
  305. pioB: gpio@fffff600 {
  306. compatible = "atmel,at91rm9200-gpio";
  307. reg = <0xfffff600 0x200>;
  308. interrupts = <3 4 1>;
  309. #gpio-cells = <2>;
  310. gpio-controller;
  311. interrupt-controller;
  312. #interrupt-cells = <2>;
  313. };
  314. pioC: gpio@fffff800 {
  315. compatible = "atmel,at91rm9200-gpio";
  316. reg = <0xfffff800 0x200>;
  317. interrupts = <4 4 1>;
  318. #gpio-cells = <2>;
  319. gpio-controller;
  320. interrupt-controller;
  321. #interrupt-cells = <2>;
  322. };
  323. };
  324. dbgu: serial@fffff200 {
  325. compatible = "atmel,at91sam9260-usart";
  326. reg = <0xfffff200 0x200>;
  327. interrupts = <1 4 7>;
  328. pinctrl-names = "default";
  329. pinctrl-0 = <&pinctrl_dbgu>;
  330. status = "disabled";
  331. };
  332. usart0: serial@fffb0000 {
  333. compatible = "atmel,at91sam9260-usart";
  334. reg = <0xfffb0000 0x200>;
  335. interrupts = <6 4 5>;
  336. atmel,use-dma-rx;
  337. atmel,use-dma-tx;
  338. pinctrl-names = "default";
  339. pinctrl-0 = <&pinctrl_usart0>;
  340. status = "disabled";
  341. };
  342. usart1: serial@fffb4000 {
  343. compatible = "atmel,at91sam9260-usart";
  344. reg = <0xfffb4000 0x200>;
  345. interrupts = <7 4 5>;
  346. atmel,use-dma-rx;
  347. atmel,use-dma-tx;
  348. pinctrl-names = "default";
  349. pinctrl-0 = <&pinctrl_usart1>;
  350. status = "disabled";
  351. };
  352. usart2: serial@fffb8000 {
  353. compatible = "atmel,at91sam9260-usart";
  354. reg = <0xfffb8000 0x200>;
  355. interrupts = <8 4 5>;
  356. atmel,use-dma-rx;
  357. atmel,use-dma-tx;
  358. pinctrl-names = "default";
  359. pinctrl-0 = <&pinctrl_usart2>;
  360. status = "disabled";
  361. };
  362. usart3: serial@fffd0000 {
  363. compatible = "atmel,at91sam9260-usart";
  364. reg = <0xfffd0000 0x200>;
  365. interrupts = <23 4 5>;
  366. atmel,use-dma-rx;
  367. atmel,use-dma-tx;
  368. pinctrl-names = "default";
  369. pinctrl-0 = <&pinctrl_usart3>;
  370. status = "disabled";
  371. };
  372. uart0: serial@fffd4000 {
  373. compatible = "atmel,at91sam9260-usart";
  374. reg = <0xfffd4000 0x200>;
  375. interrupts = <24 4 5>;
  376. atmel,use-dma-rx;
  377. atmel,use-dma-tx;
  378. pinctrl-names = "default";
  379. pinctrl-0 = <&pinctrl_uart0>;
  380. status = "disabled";
  381. };
  382. uart1: serial@fffd8000 {
  383. compatible = "atmel,at91sam9260-usart";
  384. reg = <0xfffd8000 0x200>;
  385. interrupts = <25 4 5>;
  386. atmel,use-dma-rx;
  387. atmel,use-dma-tx;
  388. pinctrl-names = "default";
  389. pinctrl-0 = <&pinctrl_uart1>;
  390. status = "disabled";
  391. };
  392. macb0: ethernet@fffc4000 {
  393. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  394. reg = <0xfffc4000 0x100>;
  395. interrupts = <21 4 3>;
  396. pinctrl-names = "default";
  397. pinctrl-0 = <&pinctrl_macb_rmii>;
  398. status = "disabled";
  399. };
  400. usb1: gadget@fffa4000 {
  401. compatible = "atmel,at91rm9200-udc";
  402. reg = <0xfffa4000 0x4000>;
  403. interrupts = <10 4 2>;
  404. status = "disabled";
  405. };
  406. i2c0: i2c@fffac000 {
  407. compatible = "atmel,at91sam9260-i2c";
  408. reg = <0xfffac000 0x100>;
  409. interrupts = <11 4 6>;
  410. #address-cells = <1>;
  411. #size-cells = <0>;
  412. status = "disabled";
  413. };
  414. mmc0: mmc@fffa8000 {
  415. compatible = "atmel,hsmci";
  416. reg = <0xfffa8000 0x600>;
  417. interrupts = <9 4 0>;
  418. #address-cells = <1>;
  419. #size-cells = <0>;
  420. status = "disabled";
  421. };
  422. ssc0: ssc@fffbc000 {
  423. compatible = "atmel,at91rm9200-ssc";
  424. reg = <0xfffbc000 0x4000>;
  425. interrupts = <14 4 5>;
  426. pinctrl-names = "default";
  427. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  428. status = "disabled";
  429. };
  430. spi0: spi@fffc8000 {
  431. #address-cells = <1>;
  432. #size-cells = <0>;
  433. compatible = "atmel,at91rm9200-spi";
  434. reg = <0xfffc8000 0x200>;
  435. interrupts = <12 4 3>;
  436. pinctrl-names = "default";
  437. pinctrl-0 = <&pinctrl_spi0>;
  438. status = "disabled";
  439. };
  440. spi1: spi@fffcc000 {
  441. #address-cells = <1>;
  442. #size-cells = <0>;
  443. compatible = "atmel,at91rm9200-spi";
  444. reg = <0xfffcc000 0x200>;
  445. interrupts = <13 4 3>;
  446. pinctrl-names = "default";
  447. pinctrl-0 = <&pinctrl_spi1>;
  448. status = "disabled";
  449. };
  450. adc0: adc@fffe0000 {
  451. compatible = "atmel,at91sam9260-adc";
  452. reg = <0xfffe0000 0x100>;
  453. interrupts = <5 4 0>;
  454. atmel,adc-use-external-triggers;
  455. atmel,adc-channels-used = <0xf>;
  456. atmel,adc-vref = <3300>;
  457. atmel,adc-num-channels = <4>;
  458. atmel,adc-startup-time = <15>;
  459. atmel,adc-channel-base = <0x30>;
  460. atmel,adc-drdy-mask = <0x10000>;
  461. atmel,adc-status-register = <0x1c>;
  462. atmel,adc-trigger-register = <0x04>;
  463. atmel,adc-res = <8 10>;
  464. atmel,adc-res-names = "lowres", "highres";
  465. atmel,adc-use-res = "highres";
  466. trigger@0 {
  467. trigger-name = "timer-counter-0";
  468. trigger-value = <0x1>;
  469. };
  470. trigger@1 {
  471. trigger-name = "timer-counter-1";
  472. trigger-value = <0x3>;
  473. };
  474. trigger@2 {
  475. trigger-name = "timer-counter-2";
  476. trigger-value = <0x5>;
  477. };
  478. trigger@3 {
  479. trigger-name = "external";
  480. trigger-value = <0x13>;
  481. trigger-external;
  482. };
  483. };
  484. watchdog@fffffd40 {
  485. compatible = "atmel,at91sam9260-wdt";
  486. reg = <0xfffffd40 0x10>;
  487. status = "disabled";
  488. };
  489. };
  490. nand0: nand@40000000 {
  491. compatible = "atmel,at91rm9200-nand";
  492. #address-cells = <1>;
  493. #size-cells = <1>;
  494. reg = <0x40000000 0x10000000
  495. 0xffffe800 0x200
  496. >;
  497. atmel,nand-addr-offset = <21>;
  498. atmel,nand-cmd-offset = <22>;
  499. pinctrl-names = "default";
  500. pinctrl-0 = <&pinctrl_nand>;
  501. gpios = <&pioC 13 GPIO_ACTIVE_HIGH
  502. &pioC 14 GPIO_ACTIVE_HIGH
  503. 0
  504. >;
  505. status = "disabled";
  506. };
  507. usb0: ohci@00500000 {
  508. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  509. reg = <0x00500000 0x100000>;
  510. interrupts = <20 4 2>;
  511. status = "disabled";
  512. };
  513. };
  514. i2c@0 {
  515. compatible = "i2c-gpio";
  516. gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
  517. &pioA 24 GPIO_ACTIVE_HIGH /* scl */
  518. >;
  519. i2c-gpio,sda-open-drain;
  520. i2c-gpio,scl-open-drain;
  521. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  522. #address-cells = <1>;
  523. #size-cells = <0>;
  524. status = "disabled";
  525. };
  526. };