at91rm9200.dtsi 13 KB

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  1. /*
  2. * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2012 Joachim Eastwood <manabian@gmail.com>
  7. *
  8. * Based on at91sam9260.dtsi
  9. *
  10. * Licensed under GPLv2 or later.
  11. */
  12. #include "skeleton.dtsi"
  13. #include <dt-bindings/gpio/gpio.h>
  14. / {
  15. model = "Atmel AT91RM9200 family SoC";
  16. compatible = "atmel,at91rm9200";
  17. interrupt-parent = <&aic>;
  18. aliases {
  19. serial0 = &dbgu;
  20. serial1 = &usart0;
  21. serial2 = &usart1;
  22. serial3 = &usart2;
  23. serial4 = &usart3;
  24. gpio0 = &pioA;
  25. gpio1 = &pioB;
  26. gpio2 = &pioC;
  27. gpio3 = &pioD;
  28. tcb0 = &tcb0;
  29. tcb1 = &tcb1;
  30. i2c0 = &i2c0;
  31. ssc0 = &ssc0;
  32. ssc1 = &ssc1;
  33. ssc2 = &ssc2;
  34. };
  35. cpus {
  36. cpu@0 {
  37. compatible = "arm,arm920t";
  38. };
  39. };
  40. memory {
  41. reg = <0x20000000 0x04000000>;
  42. };
  43. ahb {
  44. compatible = "simple-bus";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. ranges;
  48. apb {
  49. compatible = "simple-bus";
  50. #address-cells = <1>;
  51. #size-cells = <1>;
  52. ranges;
  53. aic: interrupt-controller@fffff000 {
  54. #interrupt-cells = <3>;
  55. compatible = "atmel,at91rm9200-aic";
  56. interrupt-controller;
  57. reg = <0xfffff000 0x200>;
  58. atmel,external-irqs = <25 26 27 28 29 30 31>;
  59. };
  60. ramc0: ramc@ffffff00 {
  61. compatible = "atmel,at91rm9200-sdramc";
  62. reg = <0xffffff00 0x100>;
  63. };
  64. pmc: pmc@fffffc00 {
  65. compatible = "atmel,at91rm9200-pmc";
  66. reg = <0xfffffc00 0x100>;
  67. };
  68. st: timer@fffffd00 {
  69. compatible = "atmel,at91rm9200-st";
  70. reg = <0xfffffd00 0x100>;
  71. interrupts = <1 4 7>;
  72. };
  73. tcb0: timer@fffa0000 {
  74. compatible = "atmel,at91rm9200-tcb";
  75. reg = <0xfffa0000 0x100>;
  76. interrupts = <17 4 0 18 4 0 19 4 0>;
  77. };
  78. tcb1: timer@fffa4000 {
  79. compatible = "atmel,at91rm9200-tcb";
  80. reg = <0xfffa4000 0x100>;
  81. interrupts = <20 4 0 21 4 0 22 4 0>;
  82. };
  83. i2c0: i2c@fffb8000 {
  84. compatible = "atmel,at91rm9200-i2c";
  85. reg = <0xfffb8000 0x4000>;
  86. interrupts = <12 4 6>;
  87. pinctrl-names = "default";
  88. pinctrl-0 = <&pinctrl_twi>;
  89. #address-cells = <1>;
  90. #size-cells = <0>;
  91. status = "disabled";
  92. };
  93. mmc0: mmc@fffb4000 {
  94. compatible = "atmel,hsmci";
  95. reg = <0xfffb4000 0x4000>;
  96. interrupts = <10 4 0>;
  97. #address-cells = <1>;
  98. #size-cells = <0>;
  99. status = "disabled";
  100. };
  101. ssc0: ssc@fffd0000 {
  102. compatible = "atmel,at91rm9200-ssc";
  103. reg = <0xfffd0000 0x4000>;
  104. interrupts = <14 4 5>;
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  107. status = "disable";
  108. };
  109. ssc1: ssc@fffd4000 {
  110. compatible = "atmel,at91rm9200-ssc";
  111. reg = <0xfffd4000 0x4000>;
  112. interrupts = <15 4 5>;
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  115. status = "disable";
  116. };
  117. ssc2: ssc@fffd8000 {
  118. compatible = "atmel,at91rm9200-ssc";
  119. reg = <0xfffd8000 0x4000>;
  120. interrupts = <16 4 5>;
  121. pinctrl-names = "default";
  122. pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
  123. status = "disable";
  124. };
  125. macb0: ethernet@fffbc000 {
  126. compatible = "cdns,at91rm9200-emac", "cdns,emac";
  127. reg = <0xfffbc000 0x4000>;
  128. interrupts = <24 4 3>;
  129. phy-mode = "rmii";
  130. pinctrl-names = "default";
  131. pinctrl-0 = <&pinctrl_macb_rmii>;
  132. status = "disabled";
  133. };
  134. pinctrl@fffff400 {
  135. #address-cells = <1>;
  136. #size-cells = <1>;
  137. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  138. ranges = <0xfffff400 0xfffff400 0x800>;
  139. atmel,mux-mask = <
  140. /* A B */
  141. 0xffffffff 0xffffffff /* pioA */
  142. 0xffffffff 0x083fffff /* pioB */
  143. 0xffff3fff 0x00000000 /* pioC */
  144. 0x03ff87ff 0x0fffff80 /* pioD */
  145. >;
  146. /* shared pinctrl settings */
  147. dbgu {
  148. pinctrl_dbgu: dbgu-0 {
  149. atmel,pins =
  150. <0 30 0x1 0x0 /* PA30 periph A */
  151. 0 31 0x1 0x1>; /* PA31 periph with pullup */
  152. };
  153. };
  154. uart0 {
  155. pinctrl_uart0: uart0-0 {
  156. atmel,pins =
  157. <0 17 0x1 0x0 /* PA17 periph A */
  158. 0 18 0x1 0x0>; /* PA18 periph A */
  159. };
  160. pinctrl_uart0_rts: uart0_rts-0 {
  161. atmel,pins =
  162. <0 20 0x1 0x0>; /* PA20 periph A */
  163. };
  164. pinctrl_uart0_cts: uart0_cts-0 {
  165. atmel,pins =
  166. <0 21 0x1 0x0>; /* PA21 periph A */
  167. };
  168. };
  169. uart1 {
  170. pinctrl_uart1: uart1-0 {
  171. atmel,pins =
  172. <1 20 0x1 0x1 /* PB20 periph A with pullup */
  173. 1 21 0x1 0x0>; /* PB21 periph A */
  174. };
  175. pinctrl_uart1_rts: uart1_rts-0 {
  176. atmel,pins =
  177. <1 24 0x1 0x0>; /* PB24 periph A */
  178. };
  179. pinctrl_uart1_cts: uart1_cts-0 {
  180. atmel,pins =
  181. <1 26 0x1 0x0>; /* PB26 periph A */
  182. };
  183. pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
  184. atmel,pins =
  185. <1 19 0x1 0x0 /* PB19 periph A */
  186. 1 25 0x1 0x0>; /* PB25 periph A */
  187. };
  188. pinctrl_uart1_dcd: uart1_dcd-0 {
  189. atmel,pins =
  190. <1 23 0x1 0x0>; /* PB23 periph A */
  191. };
  192. pinctrl_uart1_ri: uart1_ri-0 {
  193. atmel,pins =
  194. <1 18 0x1 0x0>; /* PB18 periph A */
  195. };
  196. };
  197. uart2 {
  198. pinctrl_uart2: uart2-0 {
  199. atmel,pins =
  200. <0 22 0x1 0x0 /* PA22 periph A */
  201. 0 23 0x1 0x1>; /* PA23 periph A with pullup */
  202. };
  203. pinctrl_uart2_rts: uart2_rts-0 {
  204. atmel,pins =
  205. <0 30 0x2 0x0>; /* PA30 periph B */
  206. };
  207. pinctrl_uart2_cts: uart2_cts-0 {
  208. atmel,pins =
  209. <0 31 0x2 0x0>; /* PA31 periph B */
  210. };
  211. };
  212. uart3 {
  213. pinctrl_uart3: uart3-0 {
  214. atmel,pins =
  215. <0 5 0x2 0x1 /* PA5 periph B with pullup */
  216. 0 6 0x2 0x0>; /* PA6 periph B */
  217. };
  218. pinctrl_uart3_rts: uart3_rts-0 {
  219. atmel,pins =
  220. <1 0 0x2 0x0>; /* PB0 periph B */
  221. };
  222. pinctrl_uart3_cts: uart3_cts-0 {
  223. atmel,pins =
  224. <1 1 0x2 0x0>; /* PB1 periph B */
  225. };
  226. };
  227. nand {
  228. pinctrl_nand: nand-0 {
  229. atmel,pins =
  230. <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */
  231. 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */
  232. };
  233. };
  234. macb {
  235. pinctrl_macb_rmii: macb_rmii-0 {
  236. atmel,pins =
  237. <0 7 0x1 0x0 /* PA7 periph A */
  238. 0 8 0x1 0x0 /* PA8 periph A */
  239. 0 9 0x1 0x0 /* PA9 periph A */
  240. 0 10 0x1 0x0 /* PA10 periph A */
  241. 0 11 0x1 0x0 /* PA11 periph A */
  242. 0 12 0x1 0x0 /* PA12 periph A */
  243. 0 13 0x1 0x0 /* PA13 periph A */
  244. 0 14 0x1 0x0 /* PA14 periph A */
  245. 0 15 0x1 0x0 /* PA15 periph A */
  246. 0 16 0x1 0x0>; /* PA16 periph A */
  247. };
  248. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  249. atmel,pins =
  250. <1 12 0x2 0x0 /* PB12 periph B */
  251. 1 13 0x2 0x0 /* PB13 periph B */
  252. 1 14 0x2 0x0 /* PB14 periph B */
  253. 1 15 0x2 0x0 /* PB15 periph B */
  254. 1 16 0x2 0x0 /* PB16 periph B */
  255. 1 17 0x2 0x0 /* PB17 periph B */
  256. 1 18 0x2 0x0 /* PB18 periph B */
  257. 1 19 0x2 0x0>; /* PB19 periph B */
  258. };
  259. };
  260. mmc0 {
  261. pinctrl_mmc0_clk: mmc0_clk-0 {
  262. atmel,pins =
  263. <0 27 0x1 0x0>; /* PA27 periph A */
  264. };
  265. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  266. atmel,pins =
  267. <0 28 0x1 0x1 /* PA28 periph A with pullup */
  268. 0 29 0x1 0x1>; /* PA29 periph A with pullup */
  269. };
  270. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  271. atmel,pins =
  272. <1 3 0x2 0x1 /* PB3 periph B with pullup */
  273. 1 4 0x2 0x1 /* PB4 periph B with pullup */
  274. 1 5 0x2 0x1>; /* PB5 periph B with pullup */
  275. };
  276. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  277. atmel,pins =
  278. <0 8 0x2 0x1 /* PA8 periph B with pullup */
  279. 0 9 0x2 0x1>; /* PA9 periph B with pullup */
  280. };
  281. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  282. atmel,pins =
  283. <0 10 0x2 0x1 /* PA10 periph B with pullup */
  284. 0 11 0x2 0x1 /* PA11 periph B with pullup */
  285. 0 12 0x2 0x1>; /* PA12 periph B with pullup */
  286. };
  287. };
  288. ssc0 {
  289. pinctrl_ssc0_tx: ssc0_tx-0 {
  290. atmel,pins =
  291. <1 0 0x1 0x0 /* PB0 periph A */
  292. 1 1 0x1 0x0 /* PB1 periph A */
  293. 1 2 0x1 0x0>; /* PB2 periph A */
  294. };
  295. pinctrl_ssc0_rx: ssc0_rx-0 {
  296. atmel,pins =
  297. <1 3 0x1 0x0 /* PB3 periph A */
  298. 1 4 0x1 0x0 /* PB4 periph A */
  299. 1 5 0x1 0x0>; /* PB5 periph A */
  300. };
  301. };
  302. ssc1 {
  303. pinctrl_ssc1_tx: ssc1_tx-0 {
  304. atmel,pins =
  305. <1 6 0x1 0x0 /* PB6 periph A */
  306. 1 7 0x1 0x0 /* PB7 periph A */
  307. 1 8 0x1 0x0>; /* PB8 periph A */
  308. };
  309. pinctrl_ssc1_rx: ssc1_rx-0 {
  310. atmel,pins =
  311. <1 9 0x1 0x0 /* PB9 periph A */
  312. 1 10 0x1 0x0 /* PB10 periph A */
  313. 1 11 0x1 0x0>; /* PB11 periph A */
  314. };
  315. };
  316. ssc2 {
  317. pinctrl_ssc2_tx: ssc2_tx-0 {
  318. atmel,pins =
  319. <1 12 0x1 0x0 /* PB12 periph A */
  320. 1 13 0x1 0x0 /* PB13 periph A */
  321. 1 14 0x1 0x0>; /* PB14 periph A */
  322. };
  323. pinctrl_ssc2_rx: ssc2_rx-0 {
  324. atmel,pins =
  325. <1 15 0x1 0x0 /* PB15 periph A */
  326. 1 16 0x1 0x0 /* PB16 periph A */
  327. 1 17 0x1 0x0>; /* PB17 periph A */
  328. };
  329. };
  330. twi {
  331. pinctrl_twi: twi-0 {
  332. atmel,pins =
  333. <0 25 0x1 0x2 /* PA25 periph A with multi drive */
  334. 0 26 0x1 0x2>; /* PA26 periph A with multi drive */
  335. };
  336. pinctrl_twi_gpio: twi_gpio-0 {
  337. atmel,pins =
  338. <0 25 0x0 0x2 /* PA25 GPIO with multi drive */
  339. 0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
  340. };
  341. };
  342. pioA: gpio@fffff400 {
  343. compatible = "atmel,at91rm9200-gpio";
  344. reg = <0xfffff400 0x200>;
  345. interrupts = <2 4 1>;
  346. #gpio-cells = <2>;
  347. gpio-controller;
  348. interrupt-controller;
  349. #interrupt-cells = <2>;
  350. };
  351. pioB: gpio@fffff600 {
  352. compatible = "atmel,at91rm9200-gpio";
  353. reg = <0xfffff600 0x200>;
  354. interrupts = <3 4 1>;
  355. #gpio-cells = <2>;
  356. gpio-controller;
  357. interrupt-controller;
  358. #interrupt-cells = <2>;
  359. };
  360. pioC: gpio@fffff800 {
  361. compatible = "atmel,at91rm9200-gpio";
  362. reg = <0xfffff800 0x200>;
  363. interrupts = <4 4 1>;
  364. #gpio-cells = <2>;
  365. gpio-controller;
  366. interrupt-controller;
  367. #interrupt-cells = <2>;
  368. };
  369. pioD: gpio@fffffa00 {
  370. compatible = "atmel,at91rm9200-gpio";
  371. reg = <0xfffffa00 0x200>;
  372. interrupts = <5 4 1>;
  373. #gpio-cells = <2>;
  374. gpio-controller;
  375. interrupt-controller;
  376. #interrupt-cells = <2>;
  377. };
  378. };
  379. dbgu: serial@fffff200 {
  380. compatible = "atmel,at91rm9200-usart";
  381. reg = <0xfffff200 0x200>;
  382. interrupts = <1 4 7>;
  383. pinctrl-names = "default";
  384. pinctrl-0 = <&pinctrl_dbgu>;
  385. status = "disabled";
  386. };
  387. usart0: serial@fffc0000 {
  388. compatible = "atmel,at91rm9200-usart";
  389. reg = <0xfffc0000 0x200>;
  390. interrupts = <6 4 5>;
  391. atmel,use-dma-rx;
  392. atmel,use-dma-tx;
  393. pinctrl-names = "default";
  394. pinctrl-0 = <&pinctrl_uart0>;
  395. status = "disabled";
  396. };
  397. usart1: serial@fffc4000 {
  398. compatible = "atmel,at91rm9200-usart";
  399. reg = <0xfffc4000 0x200>;
  400. interrupts = <7 4 5>;
  401. atmel,use-dma-rx;
  402. atmel,use-dma-tx;
  403. pinctrl-names = "default";
  404. pinctrl-0 = <&pinctrl_uart1>;
  405. status = "disabled";
  406. };
  407. usart2: serial@fffc8000 {
  408. compatible = "atmel,at91rm9200-usart";
  409. reg = <0xfffc8000 0x200>;
  410. interrupts = <8 4 5>;
  411. atmel,use-dma-rx;
  412. atmel,use-dma-tx;
  413. pinctrl-names = "default";
  414. pinctrl-0 = <&pinctrl_uart2>;
  415. status = "disabled";
  416. };
  417. usart3: serial@fffcc000 {
  418. compatible = "atmel,at91rm9200-usart";
  419. reg = <0xfffcc000 0x200>;
  420. interrupts = <23 4 5>;
  421. atmel,use-dma-rx;
  422. atmel,use-dma-tx;
  423. pinctrl-names = "default";
  424. pinctrl-0 = <&pinctrl_uart3>;
  425. status = "disabled";
  426. };
  427. usb1: gadget@fffb0000 {
  428. compatible = "atmel,at91rm9200-udc";
  429. reg = <0xfffb0000 0x4000>;
  430. interrupts = <11 4 2>;
  431. status = "disabled";
  432. };
  433. };
  434. nand0: nand@40000000 {
  435. compatible = "atmel,at91rm9200-nand";
  436. #address-cells = <1>;
  437. #size-cells = <1>;
  438. reg = <0x40000000 0x10000000>;
  439. atmel,nand-addr-offset = <21>;
  440. atmel,nand-cmd-offset = <22>;
  441. pinctrl-names = "default";
  442. pinctrl-0 = <&pinctrl_nand>;
  443. nand-ecc-mode = "soft";
  444. gpios = <&pioC 2 GPIO_ACTIVE_HIGH
  445. 0
  446. &pioB 1 GPIO_ACTIVE_HIGH
  447. >;
  448. status = "disabled";
  449. };
  450. usb0: ohci@00300000 {
  451. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  452. reg = <0x00300000 0x100000>;
  453. interrupts = <23 4 2>;
  454. status = "disabled";
  455. };
  456. };
  457. i2c@0 {
  458. compatible = "i2c-gpio";
  459. gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
  460. &pioA 26 GPIO_ACTIVE_HIGH /* scl */
  461. >;
  462. i2c-gpio,sda-open-drain;
  463. i2c-gpio,scl-open-drain;
  464. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  465. pinctrl-names = "default";
  466. pinctrl-0 = <&pinctrl_twi_gpio>;
  467. #address-cells = <1>;
  468. #size-cells = <0>;
  469. status = "disabled";
  470. };
  471. };