at91sam9g45.dtsi 6.9 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. ssc0 = &ssc0;
  32. ssc1 = &ssc1;
  33. };
  34. cpus {
  35. cpu@0 {
  36. compatible = "arm,arm926ejs";
  37. };
  38. };
  39. memory {
  40. reg = <0x70000000 0x10000000>;
  41. };
  42. ahb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. apb {
  48. compatible = "simple-bus";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. aic: interrupt-controller@fffff000 {
  53. #interrupt-cells = <3>;
  54. compatible = "atmel,at91rm9200-aic";
  55. interrupt-controller;
  56. reg = <0xfffff000 0x200>;
  57. atmel,external-irqs = <31>;
  58. };
  59. ramc0: ramc@ffffe400 {
  60. compatible = "atmel,at91sam9g45-ddramc";
  61. reg = <0xffffe400 0x200
  62. 0xffffe600 0x200>;
  63. };
  64. pmc: pmc@fffffc00 {
  65. compatible = "atmel,at91rm9200-pmc";
  66. reg = <0xfffffc00 0x100>;
  67. };
  68. rstc@fffffd00 {
  69. compatible = "atmel,at91sam9g45-rstc";
  70. reg = <0xfffffd00 0x10>;
  71. };
  72. pit: timer@fffffd30 {
  73. compatible = "atmel,at91sam9260-pit";
  74. reg = <0xfffffd30 0xf>;
  75. interrupts = <1 4 7>;
  76. };
  77. shdwc@fffffd10 {
  78. compatible = "atmel,at91sam9rl-shdwc";
  79. reg = <0xfffffd10 0x10>;
  80. };
  81. tcb0: timer@fff7c000 {
  82. compatible = "atmel,at91rm9200-tcb";
  83. reg = <0xfff7c000 0x100>;
  84. interrupts = <18 4 0>;
  85. };
  86. tcb1: timer@fffd4000 {
  87. compatible = "atmel,at91rm9200-tcb";
  88. reg = <0xfffd4000 0x100>;
  89. interrupts = <18 4 0>;
  90. };
  91. dma: dma-controller@ffffec00 {
  92. compatible = "atmel,at91sam9g45-dma";
  93. reg = <0xffffec00 0x200>;
  94. interrupts = <21 4 0>;
  95. };
  96. pioA: gpio@fffff200 {
  97. compatible = "atmel,at91rm9200-gpio";
  98. reg = <0xfffff200 0x100>;
  99. interrupts = <2 4 1>;
  100. #gpio-cells = <2>;
  101. gpio-controller;
  102. interrupt-controller;
  103. #interrupt-cells = <2>;
  104. };
  105. pioB: gpio@fffff400 {
  106. compatible = "atmel,at91rm9200-gpio";
  107. reg = <0xfffff400 0x100>;
  108. interrupts = <3 4 1>;
  109. #gpio-cells = <2>;
  110. gpio-controller;
  111. interrupt-controller;
  112. #interrupt-cells = <2>;
  113. };
  114. pioC: gpio@fffff600 {
  115. compatible = "atmel,at91rm9200-gpio";
  116. reg = <0xfffff600 0x100>;
  117. interrupts = <4 4 1>;
  118. #gpio-cells = <2>;
  119. gpio-controller;
  120. interrupt-controller;
  121. #interrupt-cells = <2>;
  122. };
  123. pioD: gpio@fffff800 {
  124. compatible = "atmel,at91rm9200-gpio";
  125. reg = <0xfffff800 0x100>;
  126. interrupts = <5 4 1>;
  127. #gpio-cells = <2>;
  128. gpio-controller;
  129. interrupt-controller;
  130. #interrupt-cells = <2>;
  131. };
  132. pioE: gpio@fffffa00 {
  133. compatible = "atmel,at91rm9200-gpio";
  134. reg = <0xfffffa00 0x100>;
  135. interrupts = <5 4 1>;
  136. #gpio-cells = <2>;
  137. gpio-controller;
  138. interrupt-controller;
  139. #interrupt-cells = <2>;
  140. };
  141. dbgu: serial@ffffee00 {
  142. compatible = "atmel,at91sam9260-usart";
  143. reg = <0xffffee00 0x200>;
  144. interrupts = <1 4 7>;
  145. status = "disabled";
  146. };
  147. usart0: serial@fff8c000 {
  148. compatible = "atmel,at91sam9260-usart";
  149. reg = <0xfff8c000 0x200>;
  150. interrupts = <7 4 5>;
  151. atmel,use-dma-rx;
  152. atmel,use-dma-tx;
  153. status = "disabled";
  154. };
  155. usart1: serial@fff90000 {
  156. compatible = "atmel,at91sam9260-usart";
  157. reg = <0xfff90000 0x200>;
  158. interrupts = <8 4 5>;
  159. atmel,use-dma-rx;
  160. atmel,use-dma-tx;
  161. status = "disabled";
  162. };
  163. usart2: serial@fff94000 {
  164. compatible = "atmel,at91sam9260-usart";
  165. reg = <0xfff94000 0x200>;
  166. interrupts = <9 4 5>;
  167. atmel,use-dma-rx;
  168. atmel,use-dma-tx;
  169. status = "disabled";
  170. };
  171. usart3: serial@fff98000 {
  172. compatible = "atmel,at91sam9260-usart";
  173. reg = <0xfff98000 0x200>;
  174. interrupts = <10 4 5>;
  175. atmel,use-dma-rx;
  176. atmel,use-dma-tx;
  177. status = "disabled";
  178. };
  179. macb0: ethernet@fffbc000 {
  180. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  181. reg = <0xfffbc000 0x100>;
  182. interrupts = <25 4 3>;
  183. status = "disabled";
  184. };
  185. i2c0: i2c@fff84000 {
  186. compatible = "atmel,at91sam9g10-i2c";
  187. reg = <0xfff84000 0x100>;
  188. interrupts = <12 4 6>;
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. status = "disabled";
  192. };
  193. i2c1: i2c@fff88000 {
  194. compatible = "atmel,at91sam9g10-i2c";
  195. reg = <0xfff88000 0x100>;
  196. interrupts = <13 4 6>;
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. status = "disabled";
  200. };
  201. ssc0: ssc@fff9c000 {
  202. compatible = "atmel,at91sam9g45-ssc";
  203. reg = <0xfff9c000 0x4000>;
  204. interrupts = <16 4 5>;
  205. status = "disabled";
  206. };
  207. ssc1: ssc@fffa0000 {
  208. compatible = "atmel,at91sam9g45-ssc";
  209. reg = <0xfffa0000 0x4000>;
  210. interrupts = <17 4 5>;
  211. status = "disabled";
  212. };
  213. adc0: adc@fffb0000 {
  214. compatible = "atmel,at91sam9260-adc";
  215. reg = <0xfffb0000 0x100>;
  216. interrupts = <20 4 0>;
  217. atmel,adc-use-external-triggers;
  218. atmel,adc-channels-used = <0xff>;
  219. atmel,adc-vref = <3300>;
  220. atmel,adc-num-channels = <8>;
  221. atmel,adc-startup-time = <40>;
  222. atmel,adc-channel-base = <0x30>;
  223. atmel,adc-drdy-mask = <0x10000>;
  224. atmel,adc-status-register = <0x1c>;
  225. atmel,adc-trigger-register = <0x08>;
  226. trigger@0 {
  227. trigger-name = "external-rising";
  228. trigger-value = <0x1>;
  229. trigger-external;
  230. };
  231. trigger@1 {
  232. trigger-name = "external-falling";
  233. trigger-value = <0x2>;
  234. trigger-external;
  235. };
  236. trigger@2 {
  237. trigger-name = "external-any";
  238. trigger-value = <0x3>;
  239. trigger-external;
  240. };
  241. trigger@3 {
  242. trigger-name = "continuous";
  243. trigger-value = <0x6>;
  244. };
  245. };
  246. };
  247. nand0: nand@40000000 {
  248. compatible = "atmel,at91rm9200-nand";
  249. #address-cells = <1>;
  250. #size-cells = <1>;
  251. reg = <0x40000000 0x10000000
  252. 0xffffe200 0x200
  253. >;
  254. atmel,nand-addr-offset = <21>;
  255. atmel,nand-cmd-offset = <22>;
  256. gpios = <&pioC 8 0
  257. &pioC 14 0
  258. 0
  259. >;
  260. status = "disabled";
  261. };
  262. usb0: ohci@00700000 {
  263. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  264. reg = <0x00700000 0x100000>;
  265. interrupts = <22 4 2>;
  266. status = "disabled";
  267. };
  268. usb1: ehci@00800000 {
  269. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  270. reg = <0x00800000 0x100000>;
  271. interrupts = <22 4 2>;
  272. status = "disabled";
  273. };
  274. };
  275. i2c@0 {
  276. compatible = "i2c-gpio";
  277. gpios = <&pioA 20 0 /* sda */
  278. &pioA 21 0 /* scl */
  279. >;
  280. i2c-gpio,sda-open-drain;
  281. i2c-gpio,scl-open-drain;
  282. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  283. #address-cells = <1>;
  284. #size-cells = <0>;
  285. status = "disabled";
  286. };
  287. };