qeth_core_main.c 124 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541
  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/ipv6.h>
  17. #include <linux/tcp.h>
  18. #include <linux/mii.h>
  19. #include <linux/kthread.h>
  20. #include <asm-s390/ebcdic.h>
  21. #include <asm-s390/io.h>
  22. #include <asm/s390_rdev.h>
  23. #include "qeth_core.h"
  24. #include "qeth_core_offl.h"
  25. #define QETH_DBF_TEXT_(name, level, text...) \
  26. do { \
  27. if (qeth_dbf_passes(qeth_dbf_##name, level)) { \
  28. char *dbf_txt_buf = \
  29. get_cpu_var(qeth_core_dbf_txt_buf); \
  30. sprintf(dbf_txt_buf, text); \
  31. debug_text_event(qeth_dbf_##name, level, dbf_txt_buf); \
  32. put_cpu_var(qeth_core_dbf_txt_buf); \
  33. } \
  34. } while (0)
  35. struct qeth_card_list_struct qeth_core_card_list;
  36. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  37. debug_info_t *qeth_dbf_setup;
  38. EXPORT_SYMBOL_GPL(qeth_dbf_setup);
  39. debug_info_t *qeth_dbf_data;
  40. EXPORT_SYMBOL_GPL(qeth_dbf_data);
  41. debug_info_t *qeth_dbf_misc;
  42. EXPORT_SYMBOL_GPL(qeth_dbf_misc);
  43. debug_info_t *qeth_dbf_control;
  44. EXPORT_SYMBOL_GPL(qeth_dbf_control);
  45. debug_info_t *qeth_dbf_trace;
  46. EXPORT_SYMBOL_GPL(qeth_dbf_trace);
  47. debug_info_t *qeth_dbf_sense;
  48. EXPORT_SYMBOL_GPL(qeth_dbf_sense);
  49. debug_info_t *qeth_dbf_qerr;
  50. EXPORT_SYMBOL_GPL(qeth_dbf_qerr);
  51. static struct device *qeth_core_root_dev;
  52. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  53. static struct lock_class_key qdio_out_skb_queue_key;
  54. static DEFINE_PER_CPU(char[256], qeth_core_dbf_txt_buf);
  55. static void qeth_send_control_data_cb(struct qeth_channel *,
  56. struct qeth_cmd_buffer *);
  57. static int qeth_issue_next_read(struct qeth_card *);
  58. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  59. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  60. static void qeth_free_buffer_pool(struct qeth_card *);
  61. static int qeth_qdio_establish(struct qeth_card *);
  62. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  63. struct qdio_buffer *buffer, int is_tso,
  64. int *next_element_to_fill)
  65. {
  66. struct skb_frag_struct *frag;
  67. int fragno;
  68. unsigned long addr;
  69. int element, cnt, dlen;
  70. fragno = skb_shinfo(skb)->nr_frags;
  71. element = *next_element_to_fill;
  72. dlen = 0;
  73. if (is_tso)
  74. buffer->element[element].flags =
  75. SBAL_FLAGS_MIDDLE_FRAG;
  76. else
  77. buffer->element[element].flags =
  78. SBAL_FLAGS_FIRST_FRAG;
  79. dlen = skb->len - skb->data_len;
  80. if (dlen) {
  81. buffer->element[element].addr = skb->data;
  82. buffer->element[element].length = dlen;
  83. element++;
  84. }
  85. for (cnt = 0; cnt < fragno; cnt++) {
  86. frag = &skb_shinfo(skb)->frags[cnt];
  87. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  88. frag->page_offset;
  89. buffer->element[element].addr = (char *)addr;
  90. buffer->element[element].length = frag->size;
  91. if (cnt < (fragno - 1))
  92. buffer->element[element].flags =
  93. SBAL_FLAGS_MIDDLE_FRAG;
  94. else
  95. buffer->element[element].flags =
  96. SBAL_FLAGS_LAST_FRAG;
  97. element++;
  98. }
  99. *next_element_to_fill = element;
  100. }
  101. static inline const char *qeth_get_cardname(struct qeth_card *card)
  102. {
  103. if (card->info.guestlan) {
  104. switch (card->info.type) {
  105. case QETH_CARD_TYPE_OSAE:
  106. return " Guest LAN QDIO";
  107. case QETH_CARD_TYPE_IQD:
  108. return " Guest LAN Hiper";
  109. default:
  110. return " unknown";
  111. }
  112. } else {
  113. switch (card->info.type) {
  114. case QETH_CARD_TYPE_OSAE:
  115. return " OSD Express";
  116. case QETH_CARD_TYPE_IQD:
  117. return " HiperSockets";
  118. case QETH_CARD_TYPE_OSN:
  119. return " OSN QDIO";
  120. default:
  121. return " unknown";
  122. }
  123. }
  124. return " n/a";
  125. }
  126. /* max length to be returned: 14 */
  127. const char *qeth_get_cardname_short(struct qeth_card *card)
  128. {
  129. if (card->info.guestlan) {
  130. switch (card->info.type) {
  131. case QETH_CARD_TYPE_OSAE:
  132. return "GuestLAN QDIO";
  133. case QETH_CARD_TYPE_IQD:
  134. return "GuestLAN Hiper";
  135. default:
  136. return "unknown";
  137. }
  138. } else {
  139. switch (card->info.type) {
  140. case QETH_CARD_TYPE_OSAE:
  141. switch (card->info.link_type) {
  142. case QETH_LINK_TYPE_FAST_ETH:
  143. return "OSD_100";
  144. case QETH_LINK_TYPE_HSTR:
  145. return "HSTR";
  146. case QETH_LINK_TYPE_GBIT_ETH:
  147. return "OSD_1000";
  148. case QETH_LINK_TYPE_10GBIT_ETH:
  149. return "OSD_10GIG";
  150. case QETH_LINK_TYPE_LANE_ETH100:
  151. return "OSD_FE_LANE";
  152. case QETH_LINK_TYPE_LANE_TR:
  153. return "OSD_TR_LANE";
  154. case QETH_LINK_TYPE_LANE_ETH1000:
  155. return "OSD_GbE_LANE";
  156. case QETH_LINK_TYPE_LANE:
  157. return "OSD_ATM_LANE";
  158. default:
  159. return "OSD_Express";
  160. }
  161. case QETH_CARD_TYPE_IQD:
  162. return "HiperSockets";
  163. case QETH_CARD_TYPE_OSN:
  164. return "OSN";
  165. default:
  166. return "unknown";
  167. }
  168. }
  169. return "n/a";
  170. }
  171. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  172. int clear_start_mask)
  173. {
  174. unsigned long flags;
  175. spin_lock_irqsave(&card->thread_mask_lock, flags);
  176. card->thread_allowed_mask = threads;
  177. if (clear_start_mask)
  178. card->thread_start_mask &= threads;
  179. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  180. wake_up(&card->wait_q);
  181. }
  182. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  183. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  184. {
  185. unsigned long flags;
  186. int rc = 0;
  187. spin_lock_irqsave(&card->thread_mask_lock, flags);
  188. rc = (card->thread_running_mask & threads);
  189. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  190. return rc;
  191. }
  192. EXPORT_SYMBOL_GPL(qeth_threads_running);
  193. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  194. {
  195. return wait_event_interruptible(card->wait_q,
  196. qeth_threads_running(card, threads) == 0);
  197. }
  198. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  199. void qeth_clear_working_pool_list(struct qeth_card *card)
  200. {
  201. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  202. QETH_DBF_TEXT(trace, 5, "clwrklst");
  203. list_for_each_entry_safe(pool_entry, tmp,
  204. &card->qdio.in_buf_pool.entry_list, list){
  205. list_del(&pool_entry->list);
  206. }
  207. }
  208. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  209. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  210. {
  211. struct qeth_buffer_pool_entry *pool_entry;
  212. void *ptr;
  213. int i, j;
  214. QETH_DBF_TEXT(trace, 5, "alocpool");
  215. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  216. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  217. if (!pool_entry) {
  218. qeth_free_buffer_pool(card);
  219. return -ENOMEM;
  220. }
  221. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  222. ptr = (void *) __get_free_page(GFP_KERNEL);
  223. if (!ptr) {
  224. while (j > 0)
  225. free_page((unsigned long)
  226. pool_entry->elements[--j]);
  227. kfree(pool_entry);
  228. qeth_free_buffer_pool(card);
  229. return -ENOMEM;
  230. }
  231. pool_entry->elements[j] = ptr;
  232. }
  233. list_add(&pool_entry->init_list,
  234. &card->qdio.init_pool.entry_list);
  235. }
  236. return 0;
  237. }
  238. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  239. {
  240. QETH_DBF_TEXT(trace, 2, "realcbp");
  241. if ((card->state != CARD_STATE_DOWN) &&
  242. (card->state != CARD_STATE_RECOVER))
  243. return -EPERM;
  244. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  245. qeth_clear_working_pool_list(card);
  246. qeth_free_buffer_pool(card);
  247. card->qdio.in_buf_pool.buf_count = bufcnt;
  248. card->qdio.init_pool.buf_count = bufcnt;
  249. return qeth_alloc_buffer_pool(card);
  250. }
  251. int qeth_set_large_send(struct qeth_card *card,
  252. enum qeth_large_send_types type)
  253. {
  254. int rc = 0;
  255. if (card->dev == NULL) {
  256. card->options.large_send = type;
  257. return 0;
  258. }
  259. if (card->state == CARD_STATE_UP)
  260. netif_tx_disable(card->dev);
  261. card->options.large_send = type;
  262. switch (card->options.large_send) {
  263. case QETH_LARGE_SEND_EDDP:
  264. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  265. NETIF_F_HW_CSUM;
  266. break;
  267. case QETH_LARGE_SEND_TSO:
  268. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  269. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  270. NETIF_F_HW_CSUM;
  271. } else {
  272. PRINT_WARN("TSO not supported on %s. "
  273. "large_send set to 'no'.\n",
  274. card->dev->name);
  275. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  276. NETIF_F_HW_CSUM);
  277. card->options.large_send = QETH_LARGE_SEND_NO;
  278. rc = -EOPNOTSUPP;
  279. }
  280. break;
  281. default: /* includes QETH_LARGE_SEND_NO */
  282. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  283. NETIF_F_HW_CSUM);
  284. break;
  285. }
  286. if (card->state == CARD_STATE_UP)
  287. netif_wake_queue(card->dev);
  288. return rc;
  289. }
  290. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  291. static int qeth_issue_next_read(struct qeth_card *card)
  292. {
  293. int rc;
  294. struct qeth_cmd_buffer *iob;
  295. QETH_DBF_TEXT(trace, 5, "issnxrd");
  296. if (card->read.state != CH_STATE_UP)
  297. return -EIO;
  298. iob = qeth_get_buffer(&card->read);
  299. if (!iob) {
  300. PRINT_WARN("issue_next_read failed: no iob available!\n");
  301. return -ENOMEM;
  302. }
  303. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  304. QETH_DBF_TEXT(trace, 6, "noirqpnd");
  305. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  306. (addr_t) iob, 0, 0);
  307. if (rc) {
  308. PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
  309. atomic_set(&card->read.irq_pending, 0);
  310. qeth_schedule_recovery(card);
  311. wake_up(&card->wait_q);
  312. }
  313. return rc;
  314. }
  315. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  316. {
  317. struct qeth_reply *reply;
  318. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  319. if (reply) {
  320. atomic_set(&reply->refcnt, 1);
  321. atomic_set(&reply->received, 0);
  322. reply->card = card;
  323. };
  324. return reply;
  325. }
  326. static void qeth_get_reply(struct qeth_reply *reply)
  327. {
  328. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  329. atomic_inc(&reply->refcnt);
  330. }
  331. static void qeth_put_reply(struct qeth_reply *reply)
  332. {
  333. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  334. if (atomic_dec_and_test(&reply->refcnt))
  335. kfree(reply);
  336. }
  337. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd,
  338. struct qeth_card *card)
  339. {
  340. int rc;
  341. int com;
  342. char *ipa_name;
  343. com = cmd->hdr.command;
  344. rc = cmd->hdr.return_code;
  345. ipa_name = qeth_get_ipa_cmd_name(com);
  346. PRINT_ERR("%s(x%X) for %s returned x%X \"%s\"\n", ipa_name, com,
  347. QETH_CARD_IFNAME(card), rc, qeth_get_ipa_msg(rc));
  348. }
  349. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  350. struct qeth_cmd_buffer *iob)
  351. {
  352. struct qeth_ipa_cmd *cmd = NULL;
  353. QETH_DBF_TEXT(trace, 5, "chkipad");
  354. if (IS_IPA(iob->data)) {
  355. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  356. if (IS_IPA_REPLY(cmd)) {
  357. if (cmd->hdr.return_code &&
  358. (cmd->hdr.command < IPA_CMD_SETCCID ||
  359. cmd->hdr.command > IPA_CMD_MODCCID))
  360. qeth_issue_ipa_msg(cmd, card);
  361. return cmd;
  362. } else {
  363. switch (cmd->hdr.command) {
  364. case IPA_CMD_STOPLAN:
  365. PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
  366. "there is a network problem or "
  367. "someone pulled the cable or "
  368. "disabled the port.\n",
  369. QETH_CARD_IFNAME(card),
  370. card->info.chpid);
  371. card->lan_online = 0;
  372. if (card->dev && netif_carrier_ok(card->dev))
  373. netif_carrier_off(card->dev);
  374. return NULL;
  375. case IPA_CMD_STARTLAN:
  376. PRINT_INFO("Link reestablished on %s "
  377. "(CHPID 0x%X). Scheduling "
  378. "IP address reset.\n",
  379. QETH_CARD_IFNAME(card),
  380. card->info.chpid);
  381. netif_carrier_on(card->dev);
  382. card->lan_online = 1;
  383. qeth_schedule_recovery(card);
  384. return NULL;
  385. case IPA_CMD_MODCCID:
  386. return cmd;
  387. case IPA_CMD_REGISTER_LOCAL_ADDR:
  388. QETH_DBF_TEXT(trace, 3, "irla");
  389. break;
  390. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  391. QETH_DBF_TEXT(trace, 3, "urla");
  392. break;
  393. default:
  394. PRINT_WARN("Received data is IPA "
  395. "but not a reply!\n");
  396. break;
  397. }
  398. }
  399. }
  400. return cmd;
  401. }
  402. void qeth_clear_ipacmd_list(struct qeth_card *card)
  403. {
  404. struct qeth_reply *reply, *r;
  405. unsigned long flags;
  406. QETH_DBF_TEXT(trace, 4, "clipalst");
  407. spin_lock_irqsave(&card->lock, flags);
  408. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  409. qeth_get_reply(reply);
  410. reply->rc = -EIO;
  411. atomic_inc(&reply->received);
  412. list_del_init(&reply->list);
  413. wake_up(&reply->wait_q);
  414. qeth_put_reply(reply);
  415. }
  416. spin_unlock_irqrestore(&card->lock, flags);
  417. }
  418. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  419. static int qeth_check_idx_response(unsigned char *buffer)
  420. {
  421. if (!buffer)
  422. return 0;
  423. QETH_DBF_HEX(control, 2, buffer, QETH_DBF_CONTROL_LEN);
  424. if ((buffer[2] & 0xc0) == 0xc0) {
  425. PRINT_WARN("received an IDX TERMINATE "
  426. "with cause code 0x%02x%s\n",
  427. buffer[4],
  428. ((buffer[4] == 0x22) ?
  429. " -- try another portname" : ""));
  430. QETH_DBF_TEXT(trace, 2, "ckidxres");
  431. QETH_DBF_TEXT(trace, 2, " idxterm");
  432. QETH_DBF_TEXT_(trace, 2, " rc%d", -EIO);
  433. return -EIO;
  434. }
  435. return 0;
  436. }
  437. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  438. __u32 len)
  439. {
  440. struct qeth_card *card;
  441. QETH_DBF_TEXT(trace, 4, "setupccw");
  442. card = CARD_FROM_CDEV(channel->ccwdev);
  443. if (channel == &card->read)
  444. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  445. else
  446. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  447. channel->ccw.count = len;
  448. channel->ccw.cda = (__u32) __pa(iob);
  449. }
  450. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  451. {
  452. __u8 index;
  453. QETH_DBF_TEXT(trace, 6, "getbuff");
  454. index = channel->io_buf_no;
  455. do {
  456. if (channel->iob[index].state == BUF_STATE_FREE) {
  457. channel->iob[index].state = BUF_STATE_LOCKED;
  458. channel->io_buf_no = (channel->io_buf_no + 1) %
  459. QETH_CMD_BUFFER_NO;
  460. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  461. return channel->iob + index;
  462. }
  463. index = (index + 1) % QETH_CMD_BUFFER_NO;
  464. } while (index != channel->io_buf_no);
  465. return NULL;
  466. }
  467. void qeth_release_buffer(struct qeth_channel *channel,
  468. struct qeth_cmd_buffer *iob)
  469. {
  470. unsigned long flags;
  471. QETH_DBF_TEXT(trace, 6, "relbuff");
  472. spin_lock_irqsave(&channel->iob_lock, flags);
  473. memset(iob->data, 0, QETH_BUFSIZE);
  474. iob->state = BUF_STATE_FREE;
  475. iob->callback = qeth_send_control_data_cb;
  476. iob->rc = 0;
  477. spin_unlock_irqrestore(&channel->iob_lock, flags);
  478. }
  479. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  480. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  481. {
  482. struct qeth_cmd_buffer *buffer = NULL;
  483. unsigned long flags;
  484. spin_lock_irqsave(&channel->iob_lock, flags);
  485. buffer = __qeth_get_buffer(channel);
  486. spin_unlock_irqrestore(&channel->iob_lock, flags);
  487. return buffer;
  488. }
  489. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  490. {
  491. struct qeth_cmd_buffer *buffer;
  492. wait_event(channel->wait_q,
  493. ((buffer = qeth_get_buffer(channel)) != NULL));
  494. return buffer;
  495. }
  496. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  497. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  498. {
  499. int cnt;
  500. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  501. qeth_release_buffer(channel, &channel->iob[cnt]);
  502. channel->buf_no = 0;
  503. channel->io_buf_no = 0;
  504. }
  505. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  506. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  507. struct qeth_cmd_buffer *iob)
  508. {
  509. struct qeth_card *card;
  510. struct qeth_reply *reply, *r;
  511. struct qeth_ipa_cmd *cmd;
  512. unsigned long flags;
  513. int keep_reply;
  514. QETH_DBF_TEXT(trace, 4, "sndctlcb");
  515. card = CARD_FROM_CDEV(channel->ccwdev);
  516. if (qeth_check_idx_response(iob->data)) {
  517. qeth_clear_ipacmd_list(card);
  518. qeth_schedule_recovery(card);
  519. goto out;
  520. }
  521. cmd = qeth_check_ipa_data(card, iob);
  522. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  523. goto out;
  524. /*in case of OSN : check if cmd is set */
  525. if (card->info.type == QETH_CARD_TYPE_OSN &&
  526. cmd &&
  527. cmd->hdr.command != IPA_CMD_STARTLAN &&
  528. card->osn_info.assist_cb != NULL) {
  529. card->osn_info.assist_cb(card->dev, cmd);
  530. goto out;
  531. }
  532. spin_lock_irqsave(&card->lock, flags);
  533. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  534. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  535. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  536. qeth_get_reply(reply);
  537. list_del_init(&reply->list);
  538. spin_unlock_irqrestore(&card->lock, flags);
  539. keep_reply = 0;
  540. if (reply->callback != NULL) {
  541. if (cmd) {
  542. reply->offset = (__u16)((char *)cmd -
  543. (char *)iob->data);
  544. keep_reply = reply->callback(card,
  545. reply,
  546. (unsigned long)cmd);
  547. } else
  548. keep_reply = reply->callback(card,
  549. reply,
  550. (unsigned long)iob);
  551. }
  552. if (cmd)
  553. reply->rc = (u16) cmd->hdr.return_code;
  554. else if (iob->rc)
  555. reply->rc = iob->rc;
  556. if (keep_reply) {
  557. spin_lock_irqsave(&card->lock, flags);
  558. list_add_tail(&reply->list,
  559. &card->cmd_waiter_list);
  560. spin_unlock_irqrestore(&card->lock, flags);
  561. } else {
  562. atomic_inc(&reply->received);
  563. wake_up(&reply->wait_q);
  564. }
  565. qeth_put_reply(reply);
  566. goto out;
  567. }
  568. }
  569. spin_unlock_irqrestore(&card->lock, flags);
  570. out:
  571. memcpy(&card->seqno.pdu_hdr_ack,
  572. QETH_PDU_HEADER_SEQ_NO(iob->data),
  573. QETH_SEQ_NO_LENGTH);
  574. qeth_release_buffer(channel, iob);
  575. }
  576. static int qeth_setup_channel(struct qeth_channel *channel)
  577. {
  578. int cnt;
  579. QETH_DBF_TEXT(setup, 2, "setupch");
  580. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  581. channel->iob[cnt].data = (char *)
  582. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  583. if (channel->iob[cnt].data == NULL)
  584. break;
  585. channel->iob[cnt].state = BUF_STATE_FREE;
  586. channel->iob[cnt].channel = channel;
  587. channel->iob[cnt].callback = qeth_send_control_data_cb;
  588. channel->iob[cnt].rc = 0;
  589. }
  590. if (cnt < QETH_CMD_BUFFER_NO) {
  591. while (cnt-- > 0)
  592. kfree(channel->iob[cnt].data);
  593. return -ENOMEM;
  594. }
  595. channel->buf_no = 0;
  596. channel->io_buf_no = 0;
  597. atomic_set(&channel->irq_pending, 0);
  598. spin_lock_init(&channel->iob_lock);
  599. init_waitqueue_head(&channel->wait_q);
  600. return 0;
  601. }
  602. static int qeth_set_thread_start_bit(struct qeth_card *card,
  603. unsigned long thread)
  604. {
  605. unsigned long flags;
  606. spin_lock_irqsave(&card->thread_mask_lock, flags);
  607. if (!(card->thread_allowed_mask & thread) ||
  608. (card->thread_start_mask & thread)) {
  609. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  610. return -EPERM;
  611. }
  612. card->thread_start_mask |= thread;
  613. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  614. return 0;
  615. }
  616. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  617. {
  618. unsigned long flags;
  619. spin_lock_irqsave(&card->thread_mask_lock, flags);
  620. card->thread_start_mask &= ~thread;
  621. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  622. wake_up(&card->wait_q);
  623. }
  624. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  625. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  626. {
  627. unsigned long flags;
  628. spin_lock_irqsave(&card->thread_mask_lock, flags);
  629. card->thread_running_mask &= ~thread;
  630. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  631. wake_up(&card->wait_q);
  632. }
  633. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  634. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  635. {
  636. unsigned long flags;
  637. int rc = 0;
  638. spin_lock_irqsave(&card->thread_mask_lock, flags);
  639. if (card->thread_start_mask & thread) {
  640. if ((card->thread_allowed_mask & thread) &&
  641. !(card->thread_running_mask & thread)) {
  642. rc = 1;
  643. card->thread_start_mask &= ~thread;
  644. card->thread_running_mask |= thread;
  645. } else
  646. rc = -EPERM;
  647. }
  648. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  649. return rc;
  650. }
  651. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  652. {
  653. int rc = 0;
  654. wait_event(card->wait_q,
  655. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  656. return rc;
  657. }
  658. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  659. void qeth_schedule_recovery(struct qeth_card *card)
  660. {
  661. QETH_DBF_TEXT(trace, 2, "startrec");
  662. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  663. schedule_work(&card->kernel_thread_starter);
  664. }
  665. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  666. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  667. {
  668. int dstat, cstat;
  669. char *sense;
  670. sense = (char *) irb->ecw;
  671. cstat = irb->scsw.cstat;
  672. dstat = irb->scsw.dstat;
  673. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  674. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  675. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  676. QETH_DBF_TEXT(trace, 2, "CGENCHK");
  677. PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
  678. cdev->dev.bus_id, dstat, cstat);
  679. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  680. 16, 1, irb, 64, 1);
  681. return 1;
  682. }
  683. if (dstat & DEV_STAT_UNIT_CHECK) {
  684. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  685. SENSE_RESETTING_EVENT_FLAG) {
  686. QETH_DBF_TEXT(trace, 2, "REVIND");
  687. return 1;
  688. }
  689. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  690. SENSE_COMMAND_REJECT_FLAG) {
  691. QETH_DBF_TEXT(trace, 2, "CMDREJi");
  692. return 0;
  693. }
  694. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  695. QETH_DBF_TEXT(trace, 2, "AFFE");
  696. return 1;
  697. }
  698. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  699. QETH_DBF_TEXT(trace, 2, "ZEROSEN");
  700. return 0;
  701. }
  702. QETH_DBF_TEXT(trace, 2, "DGENCHK");
  703. return 1;
  704. }
  705. return 0;
  706. }
  707. static long __qeth_check_irb_error(struct ccw_device *cdev,
  708. unsigned long intparm, struct irb *irb)
  709. {
  710. if (!IS_ERR(irb))
  711. return 0;
  712. switch (PTR_ERR(irb)) {
  713. case -EIO:
  714. PRINT_WARN("i/o-error on device %s\n", cdev->dev.bus_id);
  715. QETH_DBF_TEXT(trace, 2, "ckirberr");
  716. QETH_DBF_TEXT_(trace, 2, " rc%d", -EIO);
  717. break;
  718. case -ETIMEDOUT:
  719. PRINT_WARN("timeout on device %s\n", cdev->dev.bus_id);
  720. QETH_DBF_TEXT(trace, 2, "ckirberr");
  721. QETH_DBF_TEXT_(trace, 2, " rc%d", -ETIMEDOUT);
  722. if (intparm == QETH_RCD_PARM) {
  723. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  724. if (card && (card->data.ccwdev == cdev)) {
  725. card->data.state = CH_STATE_DOWN;
  726. wake_up(&card->wait_q);
  727. }
  728. }
  729. break;
  730. default:
  731. PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
  732. cdev->dev.bus_id);
  733. QETH_DBF_TEXT(trace, 2, "ckirberr");
  734. QETH_DBF_TEXT(trace, 2, " rc???");
  735. }
  736. return PTR_ERR(irb);
  737. }
  738. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  739. struct irb *irb)
  740. {
  741. int rc;
  742. int cstat, dstat;
  743. struct qeth_cmd_buffer *buffer;
  744. struct qeth_channel *channel;
  745. struct qeth_card *card;
  746. struct qeth_cmd_buffer *iob;
  747. __u8 index;
  748. QETH_DBF_TEXT(trace, 5, "irq");
  749. if (__qeth_check_irb_error(cdev, intparm, irb))
  750. return;
  751. cstat = irb->scsw.cstat;
  752. dstat = irb->scsw.dstat;
  753. card = CARD_FROM_CDEV(cdev);
  754. if (!card)
  755. return;
  756. if (card->read.ccwdev == cdev) {
  757. channel = &card->read;
  758. QETH_DBF_TEXT(trace, 5, "read");
  759. } else if (card->write.ccwdev == cdev) {
  760. channel = &card->write;
  761. QETH_DBF_TEXT(trace, 5, "write");
  762. } else {
  763. channel = &card->data;
  764. QETH_DBF_TEXT(trace, 5, "data");
  765. }
  766. atomic_set(&channel->irq_pending, 0);
  767. if (irb->scsw.fctl & (SCSW_FCTL_CLEAR_FUNC))
  768. channel->state = CH_STATE_STOPPED;
  769. if (irb->scsw.fctl & (SCSW_FCTL_HALT_FUNC))
  770. channel->state = CH_STATE_HALTED;
  771. /*let's wake up immediately on data channel*/
  772. if ((channel == &card->data) && (intparm != 0) &&
  773. (intparm != QETH_RCD_PARM))
  774. goto out;
  775. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  776. QETH_DBF_TEXT(trace, 6, "clrchpar");
  777. /* we don't have to handle this further */
  778. intparm = 0;
  779. }
  780. if (intparm == QETH_HALT_CHANNEL_PARM) {
  781. QETH_DBF_TEXT(trace, 6, "hltchpar");
  782. /* we don't have to handle this further */
  783. intparm = 0;
  784. }
  785. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  786. (dstat & DEV_STAT_UNIT_CHECK) ||
  787. (cstat)) {
  788. if (irb->esw.esw0.erw.cons) {
  789. /* TODO: we should make this s390dbf */
  790. PRINT_WARN("sense data available on channel %s.\n",
  791. CHANNEL_ID(channel));
  792. PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
  793. print_hex_dump(KERN_WARNING, "qeth: irb ",
  794. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  795. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  796. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  797. }
  798. if (intparm == QETH_RCD_PARM) {
  799. channel->state = CH_STATE_DOWN;
  800. goto out;
  801. }
  802. rc = qeth_get_problem(cdev, irb);
  803. if (rc) {
  804. qeth_schedule_recovery(card);
  805. goto out;
  806. }
  807. }
  808. if (intparm == QETH_RCD_PARM) {
  809. channel->state = CH_STATE_RCD_DONE;
  810. goto out;
  811. }
  812. if (intparm) {
  813. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  814. buffer->state = BUF_STATE_PROCESSED;
  815. }
  816. if (channel == &card->data)
  817. return;
  818. if (channel == &card->read &&
  819. channel->state == CH_STATE_UP)
  820. qeth_issue_next_read(card);
  821. iob = channel->iob;
  822. index = channel->buf_no;
  823. while (iob[index].state == BUF_STATE_PROCESSED) {
  824. if (iob[index].callback != NULL)
  825. iob[index].callback(channel, iob + index);
  826. index = (index + 1) % QETH_CMD_BUFFER_NO;
  827. }
  828. channel->buf_no = index;
  829. out:
  830. wake_up(&card->wait_q);
  831. return;
  832. }
  833. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  834. struct qeth_qdio_out_buffer *buf)
  835. {
  836. int i;
  837. struct sk_buff *skb;
  838. /* is PCI flag set on buffer? */
  839. if (buf->buffer->element[0].flags & 0x40)
  840. atomic_dec(&queue->set_pci_flags_count);
  841. skb = skb_dequeue(&buf->skb_list);
  842. while (skb) {
  843. atomic_dec(&skb->users);
  844. dev_kfree_skb_any(skb);
  845. skb = skb_dequeue(&buf->skb_list);
  846. }
  847. qeth_eddp_buf_release_contexts(buf);
  848. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  849. buf->buffer->element[i].length = 0;
  850. buf->buffer->element[i].addr = NULL;
  851. buf->buffer->element[i].flags = 0;
  852. }
  853. buf->next_element_to_fill = 0;
  854. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  855. }
  856. void qeth_clear_qdio_buffers(struct qeth_card *card)
  857. {
  858. int i, j;
  859. QETH_DBF_TEXT(trace, 2, "clearqdbf");
  860. /* clear outbound buffers to free skbs */
  861. for (i = 0; i < card->qdio.no_out_queues; ++i)
  862. if (card->qdio.out_qs[i]) {
  863. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  864. qeth_clear_output_buffer(card->qdio.out_qs[i],
  865. &card->qdio.out_qs[i]->bufs[j]);
  866. }
  867. }
  868. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  869. static void qeth_free_buffer_pool(struct qeth_card *card)
  870. {
  871. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  872. int i = 0;
  873. QETH_DBF_TEXT(trace, 5, "freepool");
  874. list_for_each_entry_safe(pool_entry, tmp,
  875. &card->qdio.init_pool.entry_list, init_list){
  876. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  877. free_page((unsigned long)pool_entry->elements[i]);
  878. list_del(&pool_entry->init_list);
  879. kfree(pool_entry);
  880. }
  881. }
  882. static void qeth_free_qdio_buffers(struct qeth_card *card)
  883. {
  884. int i, j;
  885. QETH_DBF_TEXT(trace, 2, "freeqdbf");
  886. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  887. QETH_QDIO_UNINITIALIZED)
  888. return;
  889. kfree(card->qdio.in_q);
  890. card->qdio.in_q = NULL;
  891. /* inbound buffer pool */
  892. qeth_free_buffer_pool(card);
  893. /* free outbound qdio_qs */
  894. if (card->qdio.out_qs) {
  895. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  896. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  897. qeth_clear_output_buffer(card->qdio.out_qs[i],
  898. &card->qdio.out_qs[i]->bufs[j]);
  899. kfree(card->qdio.out_qs[i]);
  900. }
  901. kfree(card->qdio.out_qs);
  902. card->qdio.out_qs = NULL;
  903. }
  904. }
  905. static void qeth_clean_channel(struct qeth_channel *channel)
  906. {
  907. int cnt;
  908. QETH_DBF_TEXT(setup, 2, "freech");
  909. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  910. kfree(channel->iob[cnt].data);
  911. }
  912. static int qeth_is_1920_device(struct qeth_card *card)
  913. {
  914. int single_queue = 0;
  915. struct ccw_device *ccwdev;
  916. struct channelPath_dsc {
  917. u8 flags;
  918. u8 lsn;
  919. u8 desc;
  920. u8 chpid;
  921. u8 swla;
  922. u8 zeroes;
  923. u8 chla;
  924. u8 chpp;
  925. } *chp_dsc;
  926. QETH_DBF_TEXT(setup, 2, "chk_1920");
  927. ccwdev = card->data.ccwdev;
  928. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  929. if (chp_dsc != NULL) {
  930. /* CHPP field bit 6 == 1 -> single queue */
  931. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  932. kfree(chp_dsc);
  933. }
  934. QETH_DBF_TEXT_(setup, 2, "rc:%x", single_queue);
  935. return single_queue;
  936. }
  937. static void qeth_init_qdio_info(struct qeth_card *card)
  938. {
  939. QETH_DBF_TEXT(setup, 4, "intqdinf");
  940. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  941. /* inbound */
  942. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  943. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  944. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  945. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  946. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  947. }
  948. static void qeth_set_intial_options(struct qeth_card *card)
  949. {
  950. card->options.route4.type = NO_ROUTER;
  951. card->options.route6.type = NO_ROUTER;
  952. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  953. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  954. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  955. card->options.fake_broadcast = 0;
  956. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  957. card->options.fake_ll = 0;
  958. card->options.performance_stats = 0;
  959. card->options.rx_sg_cb = QETH_RX_SG_CB;
  960. }
  961. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  962. {
  963. unsigned long flags;
  964. int rc = 0;
  965. spin_lock_irqsave(&card->thread_mask_lock, flags);
  966. QETH_DBF_TEXT_(trace, 4, " %02x%02x%02x",
  967. (u8) card->thread_start_mask,
  968. (u8) card->thread_allowed_mask,
  969. (u8) card->thread_running_mask);
  970. rc = (card->thread_start_mask & thread);
  971. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  972. return rc;
  973. }
  974. static void qeth_start_kernel_thread(struct work_struct *work)
  975. {
  976. struct qeth_card *card = container_of(work, struct qeth_card,
  977. kernel_thread_starter);
  978. QETH_DBF_TEXT(trace , 2, "strthrd");
  979. if (card->read.state != CH_STATE_UP &&
  980. card->write.state != CH_STATE_UP)
  981. return;
  982. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  983. kthread_run(card->discipline.recover, (void *) card,
  984. "qeth_recover");
  985. }
  986. static int qeth_setup_card(struct qeth_card *card)
  987. {
  988. QETH_DBF_TEXT(setup, 2, "setupcrd");
  989. QETH_DBF_HEX(setup, 2, &card, sizeof(void *));
  990. card->read.state = CH_STATE_DOWN;
  991. card->write.state = CH_STATE_DOWN;
  992. card->data.state = CH_STATE_DOWN;
  993. card->state = CARD_STATE_DOWN;
  994. card->lan_online = 0;
  995. card->use_hard_stop = 0;
  996. card->dev = NULL;
  997. spin_lock_init(&card->vlanlock);
  998. spin_lock_init(&card->mclock);
  999. card->vlangrp = NULL;
  1000. spin_lock_init(&card->lock);
  1001. spin_lock_init(&card->ip_lock);
  1002. spin_lock_init(&card->thread_mask_lock);
  1003. card->thread_start_mask = 0;
  1004. card->thread_allowed_mask = 0;
  1005. card->thread_running_mask = 0;
  1006. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1007. INIT_LIST_HEAD(&card->ip_list);
  1008. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1009. if (!card->ip_tbd_list) {
  1010. QETH_DBF_TEXT(setup, 0, "iptbdnom");
  1011. return -ENOMEM;
  1012. }
  1013. INIT_LIST_HEAD(card->ip_tbd_list);
  1014. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1015. init_waitqueue_head(&card->wait_q);
  1016. /* intial options */
  1017. qeth_set_intial_options(card);
  1018. /* IP address takeover */
  1019. INIT_LIST_HEAD(&card->ipato.entries);
  1020. card->ipato.enabled = 0;
  1021. card->ipato.invert4 = 0;
  1022. card->ipato.invert6 = 0;
  1023. /* init QDIO stuff */
  1024. qeth_init_qdio_info(card);
  1025. return 0;
  1026. }
  1027. static struct qeth_card *qeth_alloc_card(void)
  1028. {
  1029. struct qeth_card *card;
  1030. QETH_DBF_TEXT(setup, 2, "alloccrd");
  1031. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1032. if (!card)
  1033. return NULL;
  1034. QETH_DBF_HEX(setup, 2, &card, sizeof(void *));
  1035. if (qeth_setup_channel(&card->read)) {
  1036. kfree(card);
  1037. return NULL;
  1038. }
  1039. if (qeth_setup_channel(&card->write)) {
  1040. qeth_clean_channel(&card->read);
  1041. kfree(card);
  1042. return NULL;
  1043. }
  1044. card->options.layer2 = -1;
  1045. return card;
  1046. }
  1047. static int qeth_determine_card_type(struct qeth_card *card)
  1048. {
  1049. int i = 0;
  1050. QETH_DBF_TEXT(setup, 2, "detcdtyp");
  1051. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1052. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1053. while (known_devices[i][4]) {
  1054. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1055. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1056. card->info.type = known_devices[i][4];
  1057. card->qdio.no_out_queues = known_devices[i][8];
  1058. card->info.is_multicast_different = known_devices[i][9];
  1059. if (qeth_is_1920_device(card)) {
  1060. PRINT_INFO("Priority Queueing not able "
  1061. "due to hardware limitations!\n");
  1062. card->qdio.no_out_queues = 1;
  1063. card->qdio.default_out_queue = 0;
  1064. }
  1065. return 0;
  1066. }
  1067. i++;
  1068. }
  1069. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1070. PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
  1071. return -ENOENT;
  1072. }
  1073. static int qeth_clear_channel(struct qeth_channel *channel)
  1074. {
  1075. unsigned long flags;
  1076. struct qeth_card *card;
  1077. int rc;
  1078. QETH_DBF_TEXT(trace, 3, "clearch");
  1079. card = CARD_FROM_CDEV(channel->ccwdev);
  1080. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1081. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1082. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1083. if (rc)
  1084. return rc;
  1085. rc = wait_event_interruptible_timeout(card->wait_q,
  1086. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1087. if (rc == -ERESTARTSYS)
  1088. return rc;
  1089. if (channel->state != CH_STATE_STOPPED)
  1090. return -ETIME;
  1091. channel->state = CH_STATE_DOWN;
  1092. return 0;
  1093. }
  1094. static int qeth_halt_channel(struct qeth_channel *channel)
  1095. {
  1096. unsigned long flags;
  1097. struct qeth_card *card;
  1098. int rc;
  1099. QETH_DBF_TEXT(trace, 3, "haltch");
  1100. card = CARD_FROM_CDEV(channel->ccwdev);
  1101. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1102. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1103. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1104. if (rc)
  1105. return rc;
  1106. rc = wait_event_interruptible_timeout(card->wait_q,
  1107. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1108. if (rc == -ERESTARTSYS)
  1109. return rc;
  1110. if (channel->state != CH_STATE_HALTED)
  1111. return -ETIME;
  1112. return 0;
  1113. }
  1114. static int qeth_halt_channels(struct qeth_card *card)
  1115. {
  1116. int rc1 = 0, rc2 = 0, rc3 = 0;
  1117. QETH_DBF_TEXT(trace, 3, "haltchs");
  1118. rc1 = qeth_halt_channel(&card->read);
  1119. rc2 = qeth_halt_channel(&card->write);
  1120. rc3 = qeth_halt_channel(&card->data);
  1121. if (rc1)
  1122. return rc1;
  1123. if (rc2)
  1124. return rc2;
  1125. return rc3;
  1126. }
  1127. static int qeth_clear_channels(struct qeth_card *card)
  1128. {
  1129. int rc1 = 0, rc2 = 0, rc3 = 0;
  1130. QETH_DBF_TEXT(trace, 3, "clearchs");
  1131. rc1 = qeth_clear_channel(&card->read);
  1132. rc2 = qeth_clear_channel(&card->write);
  1133. rc3 = qeth_clear_channel(&card->data);
  1134. if (rc1)
  1135. return rc1;
  1136. if (rc2)
  1137. return rc2;
  1138. return rc3;
  1139. }
  1140. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1141. {
  1142. int rc = 0;
  1143. QETH_DBF_TEXT(trace, 3, "clhacrd");
  1144. QETH_DBF_HEX(trace, 3, &card, sizeof(void *));
  1145. if (halt)
  1146. rc = qeth_halt_channels(card);
  1147. if (rc)
  1148. return rc;
  1149. return qeth_clear_channels(card);
  1150. }
  1151. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1152. {
  1153. int rc = 0;
  1154. QETH_DBF_TEXT(trace, 3, "qdioclr");
  1155. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1156. QETH_QDIO_CLEANING)) {
  1157. case QETH_QDIO_ESTABLISHED:
  1158. if (card->info.type == QETH_CARD_TYPE_IQD)
  1159. rc = qdio_cleanup(CARD_DDEV(card),
  1160. QDIO_FLAG_CLEANUP_USING_HALT);
  1161. else
  1162. rc = qdio_cleanup(CARD_DDEV(card),
  1163. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1164. if (rc)
  1165. QETH_DBF_TEXT_(trace, 3, "1err%d", rc);
  1166. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1167. break;
  1168. case QETH_QDIO_CLEANING:
  1169. return rc;
  1170. default:
  1171. break;
  1172. }
  1173. rc = qeth_clear_halt_card(card, use_halt);
  1174. if (rc)
  1175. QETH_DBF_TEXT_(trace, 3, "2err%d", rc);
  1176. card->state = CARD_STATE_DOWN;
  1177. return rc;
  1178. }
  1179. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1180. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1181. int *length)
  1182. {
  1183. struct ciw *ciw;
  1184. char *rcd_buf;
  1185. int ret;
  1186. struct qeth_channel *channel = &card->data;
  1187. unsigned long flags;
  1188. /*
  1189. * scan for RCD command in extended SenseID data
  1190. */
  1191. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1192. if (!ciw || ciw->cmd == 0)
  1193. return -EOPNOTSUPP;
  1194. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1195. if (!rcd_buf)
  1196. return -ENOMEM;
  1197. channel->ccw.cmd_code = ciw->cmd;
  1198. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1199. channel->ccw.count = ciw->count;
  1200. channel->ccw.flags = CCW_FLAG_SLI;
  1201. channel->state = CH_STATE_RCD;
  1202. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1203. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1204. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1205. QETH_RCD_TIMEOUT);
  1206. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1207. if (!ret)
  1208. wait_event(card->wait_q,
  1209. (channel->state == CH_STATE_RCD_DONE ||
  1210. channel->state == CH_STATE_DOWN));
  1211. if (channel->state == CH_STATE_DOWN)
  1212. ret = -EIO;
  1213. else
  1214. channel->state = CH_STATE_DOWN;
  1215. if (ret) {
  1216. kfree(rcd_buf);
  1217. *buffer = NULL;
  1218. *length = 0;
  1219. } else {
  1220. *length = ciw->count;
  1221. *buffer = rcd_buf;
  1222. }
  1223. return ret;
  1224. }
  1225. static int qeth_get_unitaddr(struct qeth_card *card)
  1226. {
  1227. int length;
  1228. char *prcd;
  1229. int rc;
  1230. QETH_DBF_TEXT(setup, 2, "getunit");
  1231. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1232. if (rc) {
  1233. PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
  1234. CARD_DDEV_ID(card), rc);
  1235. return rc;
  1236. }
  1237. card->info.chpid = prcd[30];
  1238. card->info.unit_addr2 = prcd[31];
  1239. card->info.cula = prcd[63];
  1240. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1241. (prcd[0x11] == _ascebc['M']));
  1242. kfree(prcd);
  1243. return 0;
  1244. }
  1245. static void qeth_init_tokens(struct qeth_card *card)
  1246. {
  1247. card->token.issuer_rm_w = 0x00010103UL;
  1248. card->token.cm_filter_w = 0x00010108UL;
  1249. card->token.cm_connection_w = 0x0001010aUL;
  1250. card->token.ulp_filter_w = 0x0001010bUL;
  1251. card->token.ulp_connection_w = 0x0001010dUL;
  1252. }
  1253. static void qeth_init_func_level(struct qeth_card *card)
  1254. {
  1255. if (card->ipato.enabled) {
  1256. if (card->info.type == QETH_CARD_TYPE_IQD)
  1257. card->info.func_level =
  1258. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1259. else
  1260. card->info.func_level =
  1261. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1262. } else {
  1263. if (card->info.type == QETH_CARD_TYPE_IQD)
  1264. /*FIXME:why do we have same values for dis and ena for
  1265. osae??? */
  1266. card->info.func_level =
  1267. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1268. else
  1269. card->info.func_level =
  1270. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1271. }
  1272. }
  1273. static inline __u16 qeth_raw_devno_from_bus_id(char *id)
  1274. {
  1275. id += (strlen(id) - 4);
  1276. return (__u16) simple_strtoul(id, &id, 16);
  1277. }
  1278. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1279. void (*idx_reply_cb)(struct qeth_channel *,
  1280. struct qeth_cmd_buffer *))
  1281. {
  1282. struct qeth_cmd_buffer *iob;
  1283. unsigned long flags;
  1284. int rc;
  1285. struct qeth_card *card;
  1286. QETH_DBF_TEXT(setup, 2, "idxanswr");
  1287. card = CARD_FROM_CDEV(channel->ccwdev);
  1288. iob = qeth_get_buffer(channel);
  1289. iob->callback = idx_reply_cb;
  1290. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1291. channel->ccw.count = QETH_BUFSIZE;
  1292. channel->ccw.cda = (__u32) __pa(iob->data);
  1293. wait_event(card->wait_q,
  1294. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1295. QETH_DBF_TEXT(setup, 6, "noirqpnd");
  1296. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1297. rc = ccw_device_start(channel->ccwdev,
  1298. &channel->ccw, (addr_t) iob, 0, 0);
  1299. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1300. if (rc) {
  1301. PRINT_ERR("Error2 in activating channel rc=%d\n", rc);
  1302. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  1303. atomic_set(&channel->irq_pending, 0);
  1304. wake_up(&card->wait_q);
  1305. return rc;
  1306. }
  1307. rc = wait_event_interruptible_timeout(card->wait_q,
  1308. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1309. if (rc == -ERESTARTSYS)
  1310. return rc;
  1311. if (channel->state != CH_STATE_UP) {
  1312. rc = -ETIME;
  1313. QETH_DBF_TEXT_(setup, 2, "3err%d", rc);
  1314. qeth_clear_cmd_buffers(channel);
  1315. } else
  1316. rc = 0;
  1317. return rc;
  1318. }
  1319. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1320. void (*idx_reply_cb)(struct qeth_channel *,
  1321. struct qeth_cmd_buffer *))
  1322. {
  1323. struct qeth_card *card;
  1324. struct qeth_cmd_buffer *iob;
  1325. unsigned long flags;
  1326. __u16 temp;
  1327. __u8 tmp;
  1328. int rc;
  1329. card = CARD_FROM_CDEV(channel->ccwdev);
  1330. QETH_DBF_TEXT(setup, 2, "idxactch");
  1331. iob = qeth_get_buffer(channel);
  1332. iob->callback = idx_reply_cb;
  1333. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1334. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1335. channel->ccw.cda = (__u32) __pa(iob->data);
  1336. if (channel == &card->write) {
  1337. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1338. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1339. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1340. card->seqno.trans_hdr++;
  1341. } else {
  1342. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1343. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1344. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1345. }
  1346. tmp = ((__u8)card->info.portno) | 0x80;
  1347. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1348. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1349. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1350. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1351. &card->info.func_level, sizeof(__u16));
  1352. temp = qeth_raw_devno_from_bus_id(CARD_DDEV_ID(card));
  1353. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp, 2);
  1354. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1355. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1356. wait_event(card->wait_q,
  1357. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1358. QETH_DBF_TEXT(setup, 6, "noirqpnd");
  1359. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1360. rc = ccw_device_start(channel->ccwdev,
  1361. &channel->ccw, (addr_t) iob, 0, 0);
  1362. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1363. if (rc) {
  1364. PRINT_ERR("Error1 in activating channel. rc=%d\n", rc);
  1365. QETH_DBF_TEXT_(setup, 2, "1err%d", rc);
  1366. atomic_set(&channel->irq_pending, 0);
  1367. wake_up(&card->wait_q);
  1368. return rc;
  1369. }
  1370. rc = wait_event_interruptible_timeout(card->wait_q,
  1371. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1372. if (rc == -ERESTARTSYS)
  1373. return rc;
  1374. if (channel->state != CH_STATE_ACTIVATING) {
  1375. PRINT_WARN("IDX activate timed out!\n");
  1376. QETH_DBF_TEXT_(setup, 2, "2err%d", -ETIME);
  1377. qeth_clear_cmd_buffers(channel);
  1378. return -ETIME;
  1379. }
  1380. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1381. }
  1382. static int qeth_peer_func_level(int level)
  1383. {
  1384. if ((level & 0xff) == 8)
  1385. return (level & 0xff) + 0x400;
  1386. if (((level >> 8) & 3) == 1)
  1387. return (level & 0xff) + 0x200;
  1388. return level;
  1389. }
  1390. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1391. struct qeth_cmd_buffer *iob)
  1392. {
  1393. struct qeth_card *card;
  1394. __u16 temp;
  1395. QETH_DBF_TEXT(setup , 2, "idxwrcb");
  1396. if (channel->state == CH_STATE_DOWN) {
  1397. channel->state = CH_STATE_ACTIVATING;
  1398. goto out;
  1399. }
  1400. card = CARD_FROM_CDEV(channel->ccwdev);
  1401. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1402. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1403. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1404. "adapter exclusively used by another host\n",
  1405. CARD_WDEV_ID(card));
  1406. else
  1407. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1408. "negative reply\n", CARD_WDEV_ID(card));
  1409. goto out;
  1410. }
  1411. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1412. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1413. PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
  1414. "function level mismatch "
  1415. "(sent: 0x%x, received: 0x%x)\n",
  1416. CARD_WDEV_ID(card), card->info.func_level, temp);
  1417. goto out;
  1418. }
  1419. channel->state = CH_STATE_UP;
  1420. out:
  1421. qeth_release_buffer(channel, iob);
  1422. }
  1423. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1424. struct qeth_cmd_buffer *iob)
  1425. {
  1426. struct qeth_card *card;
  1427. __u16 temp;
  1428. QETH_DBF_TEXT(setup , 2, "idxrdcb");
  1429. if (channel->state == CH_STATE_DOWN) {
  1430. channel->state = CH_STATE_ACTIVATING;
  1431. goto out;
  1432. }
  1433. card = CARD_FROM_CDEV(channel->ccwdev);
  1434. if (qeth_check_idx_response(iob->data))
  1435. goto out;
  1436. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1437. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1438. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1439. "adapter exclusively used by another host\n",
  1440. CARD_RDEV_ID(card));
  1441. else
  1442. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1443. "negative reply\n", CARD_RDEV_ID(card));
  1444. goto out;
  1445. }
  1446. /**
  1447. * temporary fix for microcode bug
  1448. * to revert it,replace OR by AND
  1449. */
  1450. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1451. (card->info.type == QETH_CARD_TYPE_OSAE))
  1452. card->info.portname_required = 1;
  1453. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1454. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1455. PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
  1456. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1457. CARD_RDEV_ID(card), card->info.func_level, temp);
  1458. goto out;
  1459. }
  1460. memcpy(&card->token.issuer_rm_r,
  1461. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1462. QETH_MPC_TOKEN_LENGTH);
  1463. memcpy(&card->info.mcl_level[0],
  1464. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1465. channel->state = CH_STATE_UP;
  1466. out:
  1467. qeth_release_buffer(channel, iob);
  1468. }
  1469. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1470. struct qeth_cmd_buffer *iob)
  1471. {
  1472. qeth_setup_ccw(&card->write, iob->data, len);
  1473. iob->callback = qeth_release_buffer;
  1474. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1475. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1476. card->seqno.trans_hdr++;
  1477. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1478. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1479. card->seqno.pdu_hdr++;
  1480. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1481. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1482. QETH_DBF_HEX(control, 2, iob->data, QETH_DBF_CONTROL_LEN);
  1483. }
  1484. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1485. int qeth_send_control_data(struct qeth_card *card, int len,
  1486. struct qeth_cmd_buffer *iob,
  1487. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1488. unsigned long),
  1489. void *reply_param)
  1490. {
  1491. int rc;
  1492. unsigned long flags;
  1493. struct qeth_reply *reply = NULL;
  1494. unsigned long timeout;
  1495. QETH_DBF_TEXT(trace, 2, "sendctl");
  1496. reply = qeth_alloc_reply(card);
  1497. if (!reply) {
  1498. PRINT_WARN("Could no alloc qeth_reply!\n");
  1499. return -ENOMEM;
  1500. }
  1501. reply->callback = reply_cb;
  1502. reply->param = reply_param;
  1503. if (card->state == CARD_STATE_DOWN)
  1504. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1505. else
  1506. reply->seqno = card->seqno.ipa++;
  1507. init_waitqueue_head(&reply->wait_q);
  1508. spin_lock_irqsave(&card->lock, flags);
  1509. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1510. spin_unlock_irqrestore(&card->lock, flags);
  1511. QETH_DBF_HEX(control, 2, iob->data, QETH_DBF_CONTROL_LEN);
  1512. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1513. qeth_prepare_control_data(card, len, iob);
  1514. if (IS_IPA(iob->data))
  1515. timeout = jiffies + QETH_IPA_TIMEOUT;
  1516. else
  1517. timeout = jiffies + QETH_TIMEOUT;
  1518. QETH_DBF_TEXT(trace, 6, "noirqpnd");
  1519. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1520. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1521. (addr_t) iob, 0, 0);
  1522. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1523. if (rc) {
  1524. PRINT_WARN("qeth_send_control_data: "
  1525. "ccw_device_start rc = %i\n", rc);
  1526. QETH_DBF_TEXT_(trace, 2, " err%d", rc);
  1527. spin_lock_irqsave(&card->lock, flags);
  1528. list_del_init(&reply->list);
  1529. qeth_put_reply(reply);
  1530. spin_unlock_irqrestore(&card->lock, flags);
  1531. qeth_release_buffer(iob->channel, iob);
  1532. atomic_set(&card->write.irq_pending, 0);
  1533. wake_up(&card->wait_q);
  1534. return rc;
  1535. }
  1536. while (!atomic_read(&reply->received)) {
  1537. if (time_after(jiffies, timeout)) {
  1538. spin_lock_irqsave(&reply->card->lock, flags);
  1539. list_del_init(&reply->list);
  1540. spin_unlock_irqrestore(&reply->card->lock, flags);
  1541. reply->rc = -ETIME;
  1542. atomic_inc(&reply->received);
  1543. wake_up(&reply->wait_q);
  1544. }
  1545. cpu_relax();
  1546. };
  1547. rc = reply->rc;
  1548. qeth_put_reply(reply);
  1549. return rc;
  1550. }
  1551. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1552. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1553. unsigned long data)
  1554. {
  1555. struct qeth_cmd_buffer *iob;
  1556. QETH_DBF_TEXT(setup, 2, "cmenblcb");
  1557. iob = (struct qeth_cmd_buffer *) data;
  1558. memcpy(&card->token.cm_filter_r,
  1559. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1560. QETH_MPC_TOKEN_LENGTH);
  1561. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1562. return 0;
  1563. }
  1564. static int qeth_cm_enable(struct qeth_card *card)
  1565. {
  1566. int rc;
  1567. struct qeth_cmd_buffer *iob;
  1568. QETH_DBF_TEXT(setup, 2, "cmenable");
  1569. iob = qeth_wait_for_buffer(&card->write);
  1570. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1571. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1572. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1573. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1574. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1575. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1576. qeth_cm_enable_cb, NULL);
  1577. return rc;
  1578. }
  1579. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1580. unsigned long data)
  1581. {
  1582. struct qeth_cmd_buffer *iob;
  1583. QETH_DBF_TEXT(setup, 2, "cmsetpcb");
  1584. iob = (struct qeth_cmd_buffer *) data;
  1585. memcpy(&card->token.cm_connection_r,
  1586. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1587. QETH_MPC_TOKEN_LENGTH);
  1588. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1589. return 0;
  1590. }
  1591. static int qeth_cm_setup(struct qeth_card *card)
  1592. {
  1593. int rc;
  1594. struct qeth_cmd_buffer *iob;
  1595. QETH_DBF_TEXT(setup, 2, "cmsetup");
  1596. iob = qeth_wait_for_buffer(&card->write);
  1597. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1598. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1599. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1600. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1601. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1602. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1603. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1604. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1605. qeth_cm_setup_cb, NULL);
  1606. return rc;
  1607. }
  1608. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1609. {
  1610. switch (card->info.type) {
  1611. case QETH_CARD_TYPE_UNKNOWN:
  1612. return 1500;
  1613. case QETH_CARD_TYPE_IQD:
  1614. return card->info.max_mtu;
  1615. case QETH_CARD_TYPE_OSAE:
  1616. switch (card->info.link_type) {
  1617. case QETH_LINK_TYPE_HSTR:
  1618. case QETH_LINK_TYPE_LANE_TR:
  1619. return 2000;
  1620. default:
  1621. return 1492;
  1622. }
  1623. default:
  1624. return 1500;
  1625. }
  1626. }
  1627. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1628. {
  1629. switch (cardtype) {
  1630. case QETH_CARD_TYPE_UNKNOWN:
  1631. case QETH_CARD_TYPE_OSAE:
  1632. case QETH_CARD_TYPE_OSN:
  1633. return 61440;
  1634. case QETH_CARD_TYPE_IQD:
  1635. return 57344;
  1636. default:
  1637. return 1500;
  1638. }
  1639. }
  1640. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1641. {
  1642. switch (cardtype) {
  1643. case QETH_CARD_TYPE_IQD:
  1644. return 1;
  1645. default:
  1646. return 0;
  1647. }
  1648. }
  1649. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1650. {
  1651. switch (framesize) {
  1652. case 0x4000:
  1653. return 8192;
  1654. case 0x6000:
  1655. return 16384;
  1656. case 0xa000:
  1657. return 32768;
  1658. case 0xffff:
  1659. return 57344;
  1660. default:
  1661. return 0;
  1662. }
  1663. }
  1664. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1665. {
  1666. switch (card->info.type) {
  1667. case QETH_CARD_TYPE_OSAE:
  1668. return ((mtu >= 576) && (mtu <= 61440));
  1669. case QETH_CARD_TYPE_IQD:
  1670. return ((mtu >= 576) &&
  1671. (mtu <= card->info.max_mtu + 4096 - 32));
  1672. case QETH_CARD_TYPE_OSN:
  1673. case QETH_CARD_TYPE_UNKNOWN:
  1674. default:
  1675. return 1;
  1676. }
  1677. }
  1678. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1679. unsigned long data)
  1680. {
  1681. __u16 mtu, framesize;
  1682. __u16 len;
  1683. __u8 link_type;
  1684. struct qeth_cmd_buffer *iob;
  1685. QETH_DBF_TEXT(setup, 2, "ulpenacb");
  1686. iob = (struct qeth_cmd_buffer *) data;
  1687. memcpy(&card->token.ulp_filter_r,
  1688. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1689. QETH_MPC_TOKEN_LENGTH);
  1690. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1691. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1692. mtu = qeth_get_mtu_outof_framesize(framesize);
  1693. if (!mtu) {
  1694. iob->rc = -EINVAL;
  1695. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1696. return 0;
  1697. }
  1698. card->info.max_mtu = mtu;
  1699. card->info.initial_mtu = mtu;
  1700. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1701. } else {
  1702. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1703. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1704. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1705. }
  1706. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1707. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1708. memcpy(&link_type,
  1709. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1710. card->info.link_type = link_type;
  1711. } else
  1712. card->info.link_type = 0;
  1713. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1714. return 0;
  1715. }
  1716. static int qeth_ulp_enable(struct qeth_card *card)
  1717. {
  1718. int rc;
  1719. char prot_type;
  1720. struct qeth_cmd_buffer *iob;
  1721. /*FIXME: trace view callbacks*/
  1722. QETH_DBF_TEXT(setup, 2, "ulpenabl");
  1723. iob = qeth_wait_for_buffer(&card->write);
  1724. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1725. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1726. (__u8) card->info.portno;
  1727. if (card->options.layer2)
  1728. if (card->info.type == QETH_CARD_TYPE_OSN)
  1729. prot_type = QETH_PROT_OSN2;
  1730. else
  1731. prot_type = QETH_PROT_LAYER2;
  1732. else
  1733. prot_type = QETH_PROT_TCPIP;
  1734. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1735. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1736. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1737. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1738. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1739. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1740. card->info.portname, 9);
  1741. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1742. qeth_ulp_enable_cb, NULL);
  1743. return rc;
  1744. }
  1745. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1746. unsigned long data)
  1747. {
  1748. struct qeth_cmd_buffer *iob;
  1749. QETH_DBF_TEXT(setup, 2, "ulpstpcb");
  1750. iob = (struct qeth_cmd_buffer *) data;
  1751. memcpy(&card->token.ulp_connection_r,
  1752. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1753. QETH_MPC_TOKEN_LENGTH);
  1754. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1755. return 0;
  1756. }
  1757. static int qeth_ulp_setup(struct qeth_card *card)
  1758. {
  1759. int rc;
  1760. __u16 temp;
  1761. struct qeth_cmd_buffer *iob;
  1762. struct ccw_dev_id dev_id;
  1763. QETH_DBF_TEXT(setup, 2, "ulpsetup");
  1764. iob = qeth_wait_for_buffer(&card->write);
  1765. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1766. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1767. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1768. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1769. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1770. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1771. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1772. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1773. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1774. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1775. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1776. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1777. qeth_ulp_setup_cb, NULL);
  1778. return rc;
  1779. }
  1780. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1781. {
  1782. int i, j;
  1783. QETH_DBF_TEXT(setup, 2, "allcqdbf");
  1784. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1785. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1786. return 0;
  1787. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1788. GFP_KERNEL);
  1789. if (!card->qdio.in_q)
  1790. goto out_nomem;
  1791. QETH_DBF_TEXT(setup, 2, "inq");
  1792. QETH_DBF_HEX(setup, 2, &card->qdio.in_q, sizeof(void *));
  1793. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1794. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1795. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1796. card->qdio.in_q->bufs[i].buffer =
  1797. &card->qdio.in_q->qdio_bufs[i];
  1798. /* inbound buffer pool */
  1799. if (qeth_alloc_buffer_pool(card))
  1800. goto out_freeinq;
  1801. /* outbound */
  1802. card->qdio.out_qs =
  1803. kmalloc(card->qdio.no_out_queues *
  1804. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1805. if (!card->qdio.out_qs)
  1806. goto out_freepool;
  1807. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1808. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1809. GFP_KERNEL);
  1810. if (!card->qdio.out_qs[i])
  1811. goto out_freeoutq;
  1812. QETH_DBF_TEXT_(setup, 2, "outq %i", i);
  1813. QETH_DBF_HEX(setup, 2, &card->qdio.out_qs[i], sizeof(void *));
  1814. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1815. card->qdio.out_qs[i]->queue_no = i;
  1816. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1817. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1818. card->qdio.out_qs[i]->bufs[j].buffer =
  1819. &card->qdio.out_qs[i]->qdio_bufs[j];
  1820. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1821. skb_list);
  1822. lockdep_set_class(
  1823. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1824. &qdio_out_skb_queue_key);
  1825. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1826. }
  1827. }
  1828. return 0;
  1829. out_freeoutq:
  1830. while (i > 0)
  1831. kfree(card->qdio.out_qs[--i]);
  1832. kfree(card->qdio.out_qs);
  1833. card->qdio.out_qs = NULL;
  1834. out_freepool:
  1835. qeth_free_buffer_pool(card);
  1836. out_freeinq:
  1837. kfree(card->qdio.in_q);
  1838. card->qdio.in_q = NULL;
  1839. out_nomem:
  1840. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1841. return -ENOMEM;
  1842. }
  1843. static void qeth_create_qib_param_field(struct qeth_card *card,
  1844. char *param_field)
  1845. {
  1846. param_field[0] = _ascebc['P'];
  1847. param_field[1] = _ascebc['C'];
  1848. param_field[2] = _ascebc['I'];
  1849. param_field[3] = _ascebc['T'];
  1850. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1851. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1852. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1853. }
  1854. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1855. char *param_field)
  1856. {
  1857. param_field[16] = _ascebc['B'];
  1858. param_field[17] = _ascebc['L'];
  1859. param_field[18] = _ascebc['K'];
  1860. param_field[19] = _ascebc['T'];
  1861. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1862. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1863. *((unsigned int *) (&param_field[28])) =
  1864. card->info.blkt.inter_packet_jumbo;
  1865. }
  1866. static int qeth_qdio_activate(struct qeth_card *card)
  1867. {
  1868. QETH_DBF_TEXT(setup, 3, "qdioact");
  1869. return qdio_activate(CARD_DDEV(card), 0);
  1870. }
  1871. static int qeth_dm_act(struct qeth_card *card)
  1872. {
  1873. int rc;
  1874. struct qeth_cmd_buffer *iob;
  1875. QETH_DBF_TEXT(setup, 2, "dmact");
  1876. iob = qeth_wait_for_buffer(&card->write);
  1877. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1878. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1879. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1880. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1881. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1882. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1883. return rc;
  1884. }
  1885. static int qeth_mpc_initialize(struct qeth_card *card)
  1886. {
  1887. int rc;
  1888. QETH_DBF_TEXT(setup, 2, "mpcinit");
  1889. rc = qeth_issue_next_read(card);
  1890. if (rc) {
  1891. QETH_DBF_TEXT_(setup, 2, "1err%d", rc);
  1892. return rc;
  1893. }
  1894. rc = qeth_cm_enable(card);
  1895. if (rc) {
  1896. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  1897. goto out_qdio;
  1898. }
  1899. rc = qeth_cm_setup(card);
  1900. if (rc) {
  1901. QETH_DBF_TEXT_(setup, 2, "3err%d", rc);
  1902. goto out_qdio;
  1903. }
  1904. rc = qeth_ulp_enable(card);
  1905. if (rc) {
  1906. QETH_DBF_TEXT_(setup, 2, "4err%d", rc);
  1907. goto out_qdio;
  1908. }
  1909. rc = qeth_ulp_setup(card);
  1910. if (rc) {
  1911. QETH_DBF_TEXT_(setup, 2, "5err%d", rc);
  1912. goto out_qdio;
  1913. }
  1914. rc = qeth_alloc_qdio_buffers(card);
  1915. if (rc) {
  1916. QETH_DBF_TEXT_(setup, 2, "5err%d", rc);
  1917. goto out_qdio;
  1918. }
  1919. rc = qeth_qdio_establish(card);
  1920. if (rc) {
  1921. QETH_DBF_TEXT_(setup, 2, "6err%d", rc);
  1922. qeth_free_qdio_buffers(card);
  1923. goto out_qdio;
  1924. }
  1925. rc = qeth_qdio_activate(card);
  1926. if (rc) {
  1927. QETH_DBF_TEXT_(setup, 2, "7err%d", rc);
  1928. goto out_qdio;
  1929. }
  1930. rc = qeth_dm_act(card);
  1931. if (rc) {
  1932. QETH_DBF_TEXT_(setup, 2, "8err%d", rc);
  1933. goto out_qdio;
  1934. }
  1935. return 0;
  1936. out_qdio:
  1937. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1938. return rc;
  1939. }
  1940. static void qeth_print_status_with_portname(struct qeth_card *card)
  1941. {
  1942. char dbf_text[15];
  1943. int i;
  1944. sprintf(dbf_text, "%s", card->info.portname + 1);
  1945. for (i = 0; i < 8; i++)
  1946. dbf_text[i] =
  1947. (char) _ebcasc[(__u8) dbf_text[i]];
  1948. dbf_text[8] = 0;
  1949. PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
  1950. "with link type %s (portname: %s)\n",
  1951. CARD_RDEV_ID(card),
  1952. CARD_WDEV_ID(card),
  1953. CARD_DDEV_ID(card),
  1954. qeth_get_cardname(card),
  1955. (card->info.mcl_level[0]) ? " (level: " : "",
  1956. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1957. (card->info.mcl_level[0]) ? ")" : "",
  1958. qeth_get_cardname_short(card),
  1959. dbf_text);
  1960. }
  1961. static void qeth_print_status_no_portname(struct qeth_card *card)
  1962. {
  1963. if (card->info.portname[0])
  1964. PRINT_INFO("Device %s/%s/%s is a%s "
  1965. "card%s%s%s\nwith link type %s "
  1966. "(no portname needed by interface).\n",
  1967. CARD_RDEV_ID(card),
  1968. CARD_WDEV_ID(card),
  1969. CARD_DDEV_ID(card),
  1970. qeth_get_cardname(card),
  1971. (card->info.mcl_level[0]) ? " (level: " : "",
  1972. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1973. (card->info.mcl_level[0]) ? ")" : "",
  1974. qeth_get_cardname_short(card));
  1975. else
  1976. PRINT_INFO("Device %s/%s/%s is a%s "
  1977. "card%s%s%s\nwith link type %s.\n",
  1978. CARD_RDEV_ID(card),
  1979. CARD_WDEV_ID(card),
  1980. CARD_DDEV_ID(card),
  1981. qeth_get_cardname(card),
  1982. (card->info.mcl_level[0]) ? " (level: " : "",
  1983. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1984. (card->info.mcl_level[0]) ? ")" : "",
  1985. qeth_get_cardname_short(card));
  1986. }
  1987. void qeth_print_status_message(struct qeth_card *card)
  1988. {
  1989. switch (card->info.type) {
  1990. case QETH_CARD_TYPE_OSAE:
  1991. /* VM will use a non-zero first character
  1992. * to indicate a HiperSockets like reporting
  1993. * of the level OSA sets the first character to zero
  1994. * */
  1995. if (!card->info.mcl_level[0]) {
  1996. sprintf(card->info.mcl_level, "%02x%02x",
  1997. card->info.mcl_level[2],
  1998. card->info.mcl_level[3]);
  1999. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2000. break;
  2001. }
  2002. /* fallthrough */
  2003. case QETH_CARD_TYPE_IQD:
  2004. if (card->info.guestlan) {
  2005. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2006. card->info.mcl_level[0]];
  2007. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2008. card->info.mcl_level[1]];
  2009. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2010. card->info.mcl_level[2]];
  2011. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2012. card->info.mcl_level[3]];
  2013. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2014. }
  2015. break;
  2016. default:
  2017. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2018. }
  2019. if (card->info.portname_required)
  2020. qeth_print_status_with_portname(card);
  2021. else
  2022. qeth_print_status_no_portname(card);
  2023. }
  2024. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2025. void qeth_put_buffer_pool_entry(struct qeth_card *card,
  2026. struct qeth_buffer_pool_entry *entry)
  2027. {
  2028. QETH_DBF_TEXT(trace, 6, "ptbfplen");
  2029. list_add_tail(&entry->list, &card->qdio.in_buf_pool.entry_list);
  2030. }
  2031. EXPORT_SYMBOL_GPL(qeth_put_buffer_pool_entry);
  2032. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2033. {
  2034. struct qeth_buffer_pool_entry *entry;
  2035. QETH_DBF_TEXT(trace, 5, "inwrklst");
  2036. list_for_each_entry(entry,
  2037. &card->qdio.init_pool.entry_list, init_list) {
  2038. qeth_put_buffer_pool_entry(card, entry);
  2039. }
  2040. }
  2041. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2042. struct qeth_card *card)
  2043. {
  2044. struct list_head *plh;
  2045. struct qeth_buffer_pool_entry *entry;
  2046. int i, free;
  2047. struct page *page;
  2048. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2049. return NULL;
  2050. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2051. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2052. free = 1;
  2053. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2054. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2055. free = 0;
  2056. break;
  2057. }
  2058. }
  2059. if (free) {
  2060. list_del_init(&entry->list);
  2061. return entry;
  2062. }
  2063. }
  2064. /* no free buffer in pool so take first one and swap pages */
  2065. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2066. struct qeth_buffer_pool_entry, list);
  2067. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2068. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2069. page = alloc_page(GFP_ATOMIC);
  2070. if (!page) {
  2071. return NULL;
  2072. } else {
  2073. free_page((unsigned long)entry->elements[i]);
  2074. entry->elements[i] = page_address(page);
  2075. if (card->options.performance_stats)
  2076. card->perf_stats.sg_alloc_page_rx++;
  2077. }
  2078. }
  2079. }
  2080. list_del_init(&entry->list);
  2081. return entry;
  2082. }
  2083. static int qeth_init_input_buffer(struct qeth_card *card,
  2084. struct qeth_qdio_buffer *buf)
  2085. {
  2086. struct qeth_buffer_pool_entry *pool_entry;
  2087. int i;
  2088. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2089. if (!pool_entry)
  2090. return 1;
  2091. /*
  2092. * since the buffer is accessed only from the input_tasklet
  2093. * there shouldn't be a need to synchronize; also, since we use
  2094. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2095. * buffers
  2096. */
  2097. BUG_ON(!pool_entry);
  2098. buf->pool_entry = pool_entry;
  2099. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2100. buf->buffer->element[i].length = PAGE_SIZE;
  2101. buf->buffer->element[i].addr = pool_entry->elements[i];
  2102. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2103. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2104. else
  2105. buf->buffer->element[i].flags = 0;
  2106. }
  2107. return 0;
  2108. }
  2109. int qeth_init_qdio_queues(struct qeth_card *card)
  2110. {
  2111. int i, j;
  2112. int rc;
  2113. QETH_DBF_TEXT(setup, 2, "initqdqs");
  2114. /* inbound queue */
  2115. memset(card->qdio.in_q->qdio_bufs, 0,
  2116. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2117. qeth_initialize_working_pool_list(card);
  2118. /*give only as many buffers to hardware as we have buffer pool entries*/
  2119. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2120. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2121. card->qdio.in_q->next_buf_to_init =
  2122. card->qdio.in_buf_pool.buf_count - 1;
  2123. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2124. card->qdio.in_buf_pool.buf_count - 1, NULL);
  2125. if (rc) {
  2126. QETH_DBF_TEXT_(setup, 2, "1err%d", rc);
  2127. return rc;
  2128. }
  2129. rc = qdio_synchronize(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0);
  2130. if (rc) {
  2131. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  2132. return rc;
  2133. }
  2134. /* outbound queue */
  2135. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2136. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2137. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2138. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2139. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2140. &card->qdio.out_qs[i]->bufs[j]);
  2141. }
  2142. card->qdio.out_qs[i]->card = card;
  2143. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2144. card->qdio.out_qs[i]->do_pack = 0;
  2145. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2146. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2147. atomic_set(&card->qdio.out_qs[i]->state,
  2148. QETH_OUT_Q_UNLOCKED);
  2149. }
  2150. return 0;
  2151. }
  2152. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2153. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2154. {
  2155. switch (link_type) {
  2156. case QETH_LINK_TYPE_HSTR:
  2157. return 2;
  2158. default:
  2159. return 1;
  2160. }
  2161. }
  2162. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2163. struct qeth_ipa_cmd *cmd, __u8 command,
  2164. enum qeth_prot_versions prot)
  2165. {
  2166. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2167. cmd->hdr.command = command;
  2168. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2169. cmd->hdr.seqno = card->seqno.ipa;
  2170. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2171. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2172. if (card->options.layer2)
  2173. cmd->hdr.prim_version_no = 2;
  2174. else
  2175. cmd->hdr.prim_version_no = 1;
  2176. cmd->hdr.param_count = 1;
  2177. cmd->hdr.prot_version = prot;
  2178. cmd->hdr.ipa_supported = 0;
  2179. cmd->hdr.ipa_enabled = 0;
  2180. }
  2181. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2182. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2183. {
  2184. struct qeth_cmd_buffer *iob;
  2185. struct qeth_ipa_cmd *cmd;
  2186. iob = qeth_wait_for_buffer(&card->write);
  2187. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2188. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2189. return iob;
  2190. }
  2191. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2192. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2193. char prot_type)
  2194. {
  2195. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2196. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2197. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2198. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2199. }
  2200. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2201. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2202. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2203. unsigned long),
  2204. void *reply_param)
  2205. {
  2206. int rc;
  2207. char prot_type;
  2208. int cmd;
  2209. cmd = ((struct qeth_ipa_cmd *)
  2210. (iob->data+IPA_PDU_HEADER_SIZE))->hdr.command;
  2211. QETH_DBF_TEXT(trace, 4, "sendipa");
  2212. if (card->options.layer2)
  2213. if (card->info.type == QETH_CARD_TYPE_OSN)
  2214. prot_type = QETH_PROT_OSN2;
  2215. else
  2216. prot_type = QETH_PROT_LAYER2;
  2217. else
  2218. prot_type = QETH_PROT_TCPIP;
  2219. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2220. rc = qeth_send_control_data(card, IPA_CMD_LENGTH, iob,
  2221. reply_cb, reply_param);
  2222. if (rc != 0) {
  2223. char *ipa_cmd_name;
  2224. ipa_cmd_name = qeth_get_ipa_cmd_name(cmd);
  2225. PRINT_ERR("%s %s(%x) returned %s(%x)\n", __FUNCTION__,
  2226. ipa_cmd_name, cmd, qeth_get_ipa_msg(rc), rc);
  2227. }
  2228. return rc;
  2229. }
  2230. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2231. static int qeth_send_startstoplan(struct qeth_card *card,
  2232. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2233. {
  2234. int rc;
  2235. struct qeth_cmd_buffer *iob;
  2236. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2237. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2238. return rc;
  2239. }
  2240. int qeth_send_startlan(struct qeth_card *card)
  2241. {
  2242. int rc;
  2243. QETH_DBF_TEXT(setup, 2, "strtlan");
  2244. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2245. return rc;
  2246. }
  2247. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2248. int qeth_send_stoplan(struct qeth_card *card)
  2249. {
  2250. int rc = 0;
  2251. /*
  2252. * TODO: according to the IPA format document page 14,
  2253. * TCP/IP (we!) never issue a STOPLAN
  2254. * is this right ?!?
  2255. */
  2256. QETH_DBF_TEXT(setup, 2, "stoplan");
  2257. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2258. return rc;
  2259. }
  2260. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2261. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2262. struct qeth_reply *reply, unsigned long data)
  2263. {
  2264. struct qeth_ipa_cmd *cmd;
  2265. QETH_DBF_TEXT(trace, 4, "defadpcb");
  2266. cmd = (struct qeth_ipa_cmd *) data;
  2267. if (cmd->hdr.return_code == 0)
  2268. cmd->hdr.return_code =
  2269. cmd->data.setadapterparms.hdr.return_code;
  2270. return 0;
  2271. }
  2272. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2273. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2274. struct qeth_reply *reply, unsigned long data)
  2275. {
  2276. struct qeth_ipa_cmd *cmd;
  2277. QETH_DBF_TEXT(trace, 3, "quyadpcb");
  2278. cmd = (struct qeth_ipa_cmd *) data;
  2279. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2280. card->info.link_type =
  2281. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2282. card->options.adp.supported_funcs =
  2283. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2284. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2285. }
  2286. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2287. __u32 command, __u32 cmdlen)
  2288. {
  2289. struct qeth_cmd_buffer *iob;
  2290. struct qeth_ipa_cmd *cmd;
  2291. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2292. QETH_PROT_IPV4);
  2293. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2294. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2295. cmd->data.setadapterparms.hdr.command_code = command;
  2296. cmd->data.setadapterparms.hdr.used_total = 1;
  2297. cmd->data.setadapterparms.hdr.seq_no = 1;
  2298. return iob;
  2299. }
  2300. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2301. int qeth_query_setadapterparms(struct qeth_card *card)
  2302. {
  2303. int rc;
  2304. struct qeth_cmd_buffer *iob;
  2305. QETH_DBF_TEXT(trace, 3, "queryadp");
  2306. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2307. sizeof(struct qeth_ipacmd_setadpparms));
  2308. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2309. return rc;
  2310. }
  2311. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2312. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2313. unsigned int siga_error, const char *dbftext)
  2314. {
  2315. if (qdio_error || siga_error) {
  2316. QETH_DBF_TEXT(trace, 2, dbftext);
  2317. QETH_DBF_TEXT(qerr, 2, dbftext);
  2318. QETH_DBF_TEXT_(qerr, 2, " F15=%02X",
  2319. buf->element[15].flags & 0xff);
  2320. QETH_DBF_TEXT_(qerr, 2, " F14=%02X",
  2321. buf->element[14].flags & 0xff);
  2322. QETH_DBF_TEXT_(qerr, 2, " qerr=%X", qdio_error);
  2323. QETH_DBF_TEXT_(qerr, 2, " serr=%X", siga_error);
  2324. return 1;
  2325. }
  2326. return 0;
  2327. }
  2328. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2329. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2330. {
  2331. struct qeth_qdio_q *queue = card->qdio.in_q;
  2332. int count;
  2333. int i;
  2334. int rc;
  2335. int newcount = 0;
  2336. QETH_DBF_TEXT(trace, 6, "queinbuf");
  2337. count = (index < queue->next_buf_to_init)?
  2338. card->qdio.in_buf_pool.buf_count -
  2339. (queue->next_buf_to_init - index) :
  2340. card->qdio.in_buf_pool.buf_count -
  2341. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2342. /* only requeue at a certain threshold to avoid SIGAs */
  2343. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2344. for (i = queue->next_buf_to_init;
  2345. i < queue->next_buf_to_init + count; ++i) {
  2346. if (qeth_init_input_buffer(card,
  2347. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2348. break;
  2349. } else {
  2350. newcount++;
  2351. }
  2352. }
  2353. if (newcount < count) {
  2354. /* we are in memory shortage so we switch back to
  2355. traditional skb allocation and drop packages */
  2356. if (!atomic_read(&card->force_alloc_skb) &&
  2357. net_ratelimit())
  2358. PRINT_WARN("Switch to alloc skb\n");
  2359. atomic_set(&card->force_alloc_skb, 3);
  2360. count = newcount;
  2361. } else {
  2362. if ((atomic_read(&card->force_alloc_skb) == 1) &&
  2363. net_ratelimit())
  2364. PRINT_WARN("Switch to sg\n");
  2365. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2366. }
  2367. /*
  2368. * according to old code it should be avoided to requeue all
  2369. * 128 buffers in order to benefit from PCI avoidance.
  2370. * this function keeps at least one buffer (the buffer at
  2371. * 'index') un-requeued -> this buffer is the first buffer that
  2372. * will be requeued the next time
  2373. */
  2374. if (card->options.performance_stats) {
  2375. card->perf_stats.inbound_do_qdio_cnt++;
  2376. card->perf_stats.inbound_do_qdio_start_time =
  2377. qeth_get_micros();
  2378. }
  2379. rc = do_QDIO(CARD_DDEV(card),
  2380. QDIO_FLAG_SYNC_INPUT | QDIO_FLAG_UNDER_INTERRUPT,
  2381. 0, queue->next_buf_to_init, count, NULL);
  2382. if (card->options.performance_stats)
  2383. card->perf_stats.inbound_do_qdio_time +=
  2384. qeth_get_micros() -
  2385. card->perf_stats.inbound_do_qdio_start_time;
  2386. if (rc) {
  2387. PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
  2388. "return %i (device %s).\n",
  2389. rc, CARD_DDEV_ID(card));
  2390. QETH_DBF_TEXT(trace, 2, "qinberr");
  2391. QETH_DBF_TEXT_(trace, 2, "%s", CARD_BUS_ID(card));
  2392. }
  2393. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2394. QDIO_MAX_BUFFERS_PER_Q;
  2395. }
  2396. }
  2397. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2398. static int qeth_handle_send_error(struct qeth_card *card,
  2399. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err,
  2400. unsigned int siga_err)
  2401. {
  2402. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2403. int cc = siga_err & 3;
  2404. QETH_DBF_TEXT(trace, 6, "hdsnderr");
  2405. qeth_check_qdio_errors(buffer->buffer, qdio_err, siga_err, "qouterr");
  2406. switch (cc) {
  2407. case 0:
  2408. if (qdio_err) {
  2409. QETH_DBF_TEXT(trace, 1, "lnkfail");
  2410. QETH_DBF_TEXT_(trace, 1, "%s", CARD_BUS_ID(card));
  2411. QETH_DBF_TEXT_(trace, 1, "%04x %02x",
  2412. (u16)qdio_err, (u8)sbalf15);
  2413. return QETH_SEND_ERROR_LINK_FAILURE;
  2414. }
  2415. return QETH_SEND_ERROR_NONE;
  2416. case 2:
  2417. if (siga_err & QDIO_SIGA_ERROR_B_BIT_SET) {
  2418. QETH_DBF_TEXT(trace, 1, "SIGAcc2B");
  2419. QETH_DBF_TEXT_(trace, 1, "%s", CARD_BUS_ID(card));
  2420. return QETH_SEND_ERROR_KICK_IT;
  2421. }
  2422. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2423. return QETH_SEND_ERROR_RETRY;
  2424. return QETH_SEND_ERROR_LINK_FAILURE;
  2425. /* look at qdio_error and sbalf 15 */
  2426. case 1:
  2427. QETH_DBF_TEXT(trace, 1, "SIGAcc1");
  2428. QETH_DBF_TEXT_(trace, 1, "%s", CARD_BUS_ID(card));
  2429. return QETH_SEND_ERROR_LINK_FAILURE;
  2430. case 3:
  2431. default:
  2432. QETH_DBF_TEXT(trace, 1, "SIGAcc3");
  2433. QETH_DBF_TEXT_(trace, 1, "%s", CARD_BUS_ID(card));
  2434. return QETH_SEND_ERROR_KICK_IT;
  2435. }
  2436. }
  2437. /*
  2438. * Switched to packing state if the number of used buffers on a queue
  2439. * reaches a certain limit.
  2440. */
  2441. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2442. {
  2443. if (!queue->do_pack) {
  2444. if (atomic_read(&queue->used_buffers)
  2445. >= QETH_HIGH_WATERMARK_PACK){
  2446. /* switch non-PACKING -> PACKING */
  2447. QETH_DBF_TEXT(trace, 6, "np->pack");
  2448. if (queue->card->options.performance_stats)
  2449. queue->card->perf_stats.sc_dp_p++;
  2450. queue->do_pack = 1;
  2451. }
  2452. }
  2453. }
  2454. /*
  2455. * Switches from packing to non-packing mode. If there is a packing
  2456. * buffer on the queue this buffer will be prepared to be flushed.
  2457. * In that case 1 is returned to inform the caller. If no buffer
  2458. * has to be flushed, zero is returned.
  2459. */
  2460. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2461. {
  2462. struct qeth_qdio_out_buffer *buffer;
  2463. int flush_count = 0;
  2464. if (queue->do_pack) {
  2465. if (atomic_read(&queue->used_buffers)
  2466. <= QETH_LOW_WATERMARK_PACK) {
  2467. /* switch PACKING -> non-PACKING */
  2468. QETH_DBF_TEXT(trace, 6, "pack->np");
  2469. if (queue->card->options.performance_stats)
  2470. queue->card->perf_stats.sc_p_dp++;
  2471. queue->do_pack = 0;
  2472. /* flush packing buffers */
  2473. buffer = &queue->bufs[queue->next_buf_to_fill];
  2474. if ((atomic_read(&buffer->state) ==
  2475. QETH_QDIO_BUF_EMPTY) &&
  2476. (buffer->next_element_to_fill > 0)) {
  2477. atomic_set(&buffer->state,
  2478. QETH_QDIO_BUF_PRIMED);
  2479. flush_count++;
  2480. queue->next_buf_to_fill =
  2481. (queue->next_buf_to_fill + 1) %
  2482. QDIO_MAX_BUFFERS_PER_Q;
  2483. }
  2484. }
  2485. }
  2486. return flush_count;
  2487. }
  2488. /*
  2489. * Called to flush a packing buffer if no more pci flags are on the queue.
  2490. * Checks if there is a packing buffer and prepares it to be flushed.
  2491. * In that case returns 1, otherwise zero.
  2492. */
  2493. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2494. {
  2495. struct qeth_qdio_out_buffer *buffer;
  2496. buffer = &queue->bufs[queue->next_buf_to_fill];
  2497. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2498. (buffer->next_element_to_fill > 0)) {
  2499. /* it's a packing buffer */
  2500. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2501. queue->next_buf_to_fill =
  2502. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2503. return 1;
  2504. }
  2505. return 0;
  2506. }
  2507. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int under_int,
  2508. int index, int count)
  2509. {
  2510. struct qeth_qdio_out_buffer *buf;
  2511. int rc;
  2512. int i;
  2513. unsigned int qdio_flags;
  2514. QETH_DBF_TEXT(trace, 6, "flushbuf");
  2515. for (i = index; i < index + count; ++i) {
  2516. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2517. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2518. SBAL_FLAGS_LAST_ENTRY;
  2519. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2520. continue;
  2521. if (!queue->do_pack) {
  2522. if ((atomic_read(&queue->used_buffers) >=
  2523. (QETH_HIGH_WATERMARK_PACK -
  2524. QETH_WATERMARK_PACK_FUZZ)) &&
  2525. !atomic_read(&queue->set_pci_flags_count)) {
  2526. /* it's likely that we'll go to packing
  2527. * mode soon */
  2528. atomic_inc(&queue->set_pci_flags_count);
  2529. buf->buffer->element[0].flags |= 0x40;
  2530. }
  2531. } else {
  2532. if (!atomic_read(&queue->set_pci_flags_count)) {
  2533. /*
  2534. * there's no outstanding PCI any more, so we
  2535. * have to request a PCI to be sure the the PCI
  2536. * will wake at some time in the future then we
  2537. * can flush packed buffers that might still be
  2538. * hanging around, which can happen if no
  2539. * further send was requested by the stack
  2540. */
  2541. atomic_inc(&queue->set_pci_flags_count);
  2542. buf->buffer->element[0].flags |= 0x40;
  2543. }
  2544. }
  2545. }
  2546. queue->card->dev->trans_start = jiffies;
  2547. if (queue->card->options.performance_stats) {
  2548. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2549. queue->card->perf_stats.outbound_do_qdio_start_time =
  2550. qeth_get_micros();
  2551. }
  2552. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2553. if (under_int)
  2554. qdio_flags |= QDIO_FLAG_UNDER_INTERRUPT;
  2555. if (atomic_read(&queue->set_pci_flags_count))
  2556. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2557. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2558. queue->queue_no, index, count, NULL);
  2559. if (queue->card->options.performance_stats)
  2560. queue->card->perf_stats.outbound_do_qdio_time +=
  2561. qeth_get_micros() -
  2562. queue->card->perf_stats.outbound_do_qdio_start_time;
  2563. if (rc) {
  2564. QETH_DBF_TEXT(trace, 2, "flushbuf");
  2565. QETH_DBF_TEXT_(trace, 2, " err%d", rc);
  2566. QETH_DBF_TEXT_(trace, 2, "%s", CARD_DDEV_ID(queue->card));
  2567. queue->card->stats.tx_errors += count;
  2568. /* this must not happen under normal circumstances. if it
  2569. * happens something is really wrong -> recover */
  2570. qeth_schedule_recovery(queue->card);
  2571. return;
  2572. }
  2573. atomic_add(count, &queue->used_buffers);
  2574. if (queue->card->options.performance_stats)
  2575. queue->card->perf_stats.bufs_sent += count;
  2576. }
  2577. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2578. {
  2579. int index;
  2580. int flush_cnt = 0;
  2581. int q_was_packing = 0;
  2582. /*
  2583. * check if weed have to switch to non-packing mode or if
  2584. * we have to get a pci flag out on the queue
  2585. */
  2586. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2587. !atomic_read(&queue->set_pci_flags_count)) {
  2588. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2589. QETH_OUT_Q_UNLOCKED) {
  2590. /*
  2591. * If we get in here, there was no action in
  2592. * do_send_packet. So, we check if there is a
  2593. * packing buffer to be flushed here.
  2594. */
  2595. netif_stop_queue(queue->card->dev);
  2596. index = queue->next_buf_to_fill;
  2597. q_was_packing = queue->do_pack;
  2598. /* queue->do_pack may change */
  2599. barrier();
  2600. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2601. if (!flush_cnt &&
  2602. !atomic_read(&queue->set_pci_flags_count))
  2603. flush_cnt +=
  2604. qeth_flush_buffers_on_no_pci(queue);
  2605. if (queue->card->options.performance_stats &&
  2606. q_was_packing)
  2607. queue->card->perf_stats.bufs_sent_pack +=
  2608. flush_cnt;
  2609. if (flush_cnt)
  2610. qeth_flush_buffers(queue, 1, index, flush_cnt);
  2611. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2612. }
  2613. }
  2614. }
  2615. void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status,
  2616. unsigned int qdio_error, unsigned int siga_error,
  2617. unsigned int __queue, int first_element, int count,
  2618. unsigned long card_ptr)
  2619. {
  2620. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2621. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2622. struct qeth_qdio_out_buffer *buffer;
  2623. int i;
  2624. QETH_DBF_TEXT(trace, 6, "qdouhdl");
  2625. if (status & QDIO_STATUS_LOOK_FOR_ERROR) {
  2626. if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) {
  2627. QETH_DBF_TEXT(trace, 2, "achkcond");
  2628. QETH_DBF_TEXT_(trace, 2, "%s", CARD_BUS_ID(card));
  2629. QETH_DBF_TEXT_(trace, 2, "%08x", status);
  2630. netif_stop_queue(card->dev);
  2631. qeth_schedule_recovery(card);
  2632. return;
  2633. }
  2634. }
  2635. if (card->options.performance_stats) {
  2636. card->perf_stats.outbound_handler_cnt++;
  2637. card->perf_stats.outbound_handler_start_time =
  2638. qeth_get_micros();
  2639. }
  2640. for (i = first_element; i < (first_element + count); ++i) {
  2641. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2642. /*we only handle the KICK_IT error by doing a recovery */
  2643. if (qeth_handle_send_error(card, buffer,
  2644. qdio_error, siga_error)
  2645. == QETH_SEND_ERROR_KICK_IT){
  2646. netif_stop_queue(card->dev);
  2647. qeth_schedule_recovery(card);
  2648. return;
  2649. }
  2650. qeth_clear_output_buffer(queue, buffer);
  2651. }
  2652. atomic_sub(count, &queue->used_buffers);
  2653. /* check if we need to do something on this outbound queue */
  2654. if (card->info.type != QETH_CARD_TYPE_IQD)
  2655. qeth_check_outbound_queue(queue);
  2656. netif_wake_queue(queue->card->dev);
  2657. if (card->options.performance_stats)
  2658. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2659. card->perf_stats.outbound_handler_start_time;
  2660. }
  2661. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2662. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2663. {
  2664. int cast_type = RTN_UNSPEC;
  2665. if (card->info.type == QETH_CARD_TYPE_OSN)
  2666. return cast_type;
  2667. if (skb->dst && skb->dst->neighbour) {
  2668. cast_type = skb->dst->neighbour->type;
  2669. if ((cast_type == RTN_BROADCAST) ||
  2670. (cast_type == RTN_MULTICAST) ||
  2671. (cast_type == RTN_ANYCAST))
  2672. return cast_type;
  2673. else
  2674. return RTN_UNSPEC;
  2675. }
  2676. /* try something else */
  2677. if (skb->protocol == ETH_P_IPV6)
  2678. return (skb_network_header(skb)[24] == 0xff) ?
  2679. RTN_MULTICAST : 0;
  2680. else if (skb->protocol == ETH_P_IP)
  2681. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2682. RTN_MULTICAST : 0;
  2683. /* ... */
  2684. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2685. return RTN_BROADCAST;
  2686. else {
  2687. u16 hdr_mac;
  2688. hdr_mac = *((u16 *)skb->data);
  2689. /* tr multicast? */
  2690. switch (card->info.link_type) {
  2691. case QETH_LINK_TYPE_HSTR:
  2692. case QETH_LINK_TYPE_LANE_TR:
  2693. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2694. (hdr_mac == QETH_TR_MAC_C))
  2695. return RTN_MULTICAST;
  2696. break;
  2697. /* eth or so multicast? */
  2698. default:
  2699. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2700. (hdr_mac == QETH_ETH_MAC_V6))
  2701. return RTN_MULTICAST;
  2702. }
  2703. }
  2704. return cast_type;
  2705. }
  2706. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2707. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2708. int ipv, int cast_type)
  2709. {
  2710. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2711. return card->qdio.default_out_queue;
  2712. switch (card->qdio.no_out_queues) {
  2713. case 4:
  2714. if (cast_type && card->info.is_multicast_different)
  2715. return card->info.is_multicast_different &
  2716. (card->qdio.no_out_queues - 1);
  2717. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2718. const u8 tos = ip_hdr(skb)->tos;
  2719. if (card->qdio.do_prio_queueing ==
  2720. QETH_PRIO_Q_ING_TOS) {
  2721. if (tos & IP_TOS_NOTIMPORTANT)
  2722. return 3;
  2723. if (tos & IP_TOS_HIGHRELIABILITY)
  2724. return 2;
  2725. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2726. return 1;
  2727. if (tos & IP_TOS_LOWDELAY)
  2728. return 0;
  2729. }
  2730. if (card->qdio.do_prio_queueing ==
  2731. QETH_PRIO_Q_ING_PREC)
  2732. return 3 - (tos >> 6);
  2733. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2734. /* TODO: IPv6!!! */
  2735. }
  2736. return card->qdio.default_out_queue;
  2737. case 1: /* fallthrough for single-out-queue 1920-device */
  2738. default:
  2739. return card->qdio.default_out_queue;
  2740. }
  2741. }
  2742. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2743. static void __qeth_free_new_skb(struct sk_buff *orig_skb,
  2744. struct sk_buff *new_skb)
  2745. {
  2746. if (orig_skb != new_skb)
  2747. dev_kfree_skb_any(new_skb);
  2748. }
  2749. static inline struct sk_buff *qeth_realloc_headroom(struct qeth_card *card,
  2750. struct sk_buff *skb, int size)
  2751. {
  2752. struct sk_buff *new_skb = skb;
  2753. if (skb_headroom(skb) >= size)
  2754. return skb;
  2755. new_skb = skb_realloc_headroom(skb, size);
  2756. if (!new_skb)
  2757. PRINT_ERR("Could not realloc headroom for qeth_hdr "
  2758. "on interface %s", QETH_CARD_IFNAME(card));
  2759. return new_skb;
  2760. }
  2761. struct sk_buff *qeth_prepare_skb(struct qeth_card *card, struct sk_buff *skb,
  2762. struct qeth_hdr **hdr)
  2763. {
  2764. struct sk_buff *new_skb;
  2765. QETH_DBF_TEXT(trace, 6, "prepskb");
  2766. new_skb = qeth_realloc_headroom(card, skb,
  2767. sizeof(struct qeth_hdr));
  2768. if (!new_skb)
  2769. return NULL;
  2770. *hdr = ((struct qeth_hdr *)qeth_push_skb(card, new_skb,
  2771. sizeof(struct qeth_hdr)));
  2772. if (*hdr == NULL) {
  2773. __qeth_free_new_skb(skb, new_skb);
  2774. return NULL;
  2775. }
  2776. return new_skb;
  2777. }
  2778. EXPORT_SYMBOL_GPL(qeth_prepare_skb);
  2779. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2780. struct sk_buff *skb, int elems)
  2781. {
  2782. int elements_needed = 0;
  2783. if (skb_shinfo(skb)->nr_frags > 0)
  2784. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2785. if (elements_needed == 0)
  2786. elements_needed = 1 + (((((unsigned long) hdr) % PAGE_SIZE)
  2787. + skb->len) >> PAGE_SHIFT);
  2788. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2789. PRINT_ERR("Invalid size of IP packet "
  2790. "(Number=%d / Length=%d). Discarded.\n",
  2791. (elements_needed+elems), skb->len);
  2792. return 0;
  2793. }
  2794. return elements_needed;
  2795. }
  2796. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2797. static void __qeth_fill_buffer(struct sk_buff *skb, struct qdio_buffer *buffer,
  2798. int is_tso, int *next_element_to_fill)
  2799. {
  2800. int length = skb->len;
  2801. int length_here;
  2802. int element;
  2803. char *data;
  2804. int first_lap ;
  2805. element = *next_element_to_fill;
  2806. data = skb->data;
  2807. first_lap = (is_tso == 0 ? 1 : 0);
  2808. while (length > 0) {
  2809. /* length_here is the remaining amount of data in this page */
  2810. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2811. if (length < length_here)
  2812. length_here = length;
  2813. buffer->element[element].addr = data;
  2814. buffer->element[element].length = length_here;
  2815. length -= length_here;
  2816. if (!length) {
  2817. if (first_lap)
  2818. buffer->element[element].flags = 0;
  2819. else
  2820. buffer->element[element].flags =
  2821. SBAL_FLAGS_LAST_FRAG;
  2822. } else {
  2823. if (first_lap)
  2824. buffer->element[element].flags =
  2825. SBAL_FLAGS_FIRST_FRAG;
  2826. else
  2827. buffer->element[element].flags =
  2828. SBAL_FLAGS_MIDDLE_FRAG;
  2829. }
  2830. data += length_here;
  2831. element++;
  2832. first_lap = 0;
  2833. }
  2834. *next_element_to_fill = element;
  2835. }
  2836. static int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2837. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb)
  2838. {
  2839. struct qdio_buffer *buffer;
  2840. struct qeth_hdr_tso *hdr;
  2841. int flush_cnt = 0, hdr_len, large_send = 0;
  2842. QETH_DBF_TEXT(trace, 6, "qdfillbf");
  2843. buffer = buf->buffer;
  2844. atomic_inc(&skb->users);
  2845. skb_queue_tail(&buf->skb_list, skb);
  2846. hdr = (struct qeth_hdr_tso *) skb->data;
  2847. /*check first on TSO ....*/
  2848. if (hdr->hdr.hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2849. int element = buf->next_element_to_fill;
  2850. hdr_len = sizeof(struct qeth_hdr_tso) + hdr->ext.dg_hdr_len;
  2851. /*fill first buffer entry only with header information */
  2852. buffer->element[element].addr = skb->data;
  2853. buffer->element[element].length = hdr_len;
  2854. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2855. buf->next_element_to_fill++;
  2856. skb->data += hdr_len;
  2857. skb->len -= hdr_len;
  2858. large_send = 1;
  2859. }
  2860. if (skb_shinfo(skb)->nr_frags == 0)
  2861. __qeth_fill_buffer(skb, buffer, large_send,
  2862. (int *)&buf->next_element_to_fill);
  2863. else
  2864. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2865. (int *)&buf->next_element_to_fill);
  2866. if (!queue->do_pack) {
  2867. QETH_DBF_TEXT(trace, 6, "fillbfnp");
  2868. /* set state to PRIMED -> will be flushed */
  2869. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2870. flush_cnt = 1;
  2871. } else {
  2872. QETH_DBF_TEXT(trace, 6, "fillbfpa");
  2873. if (queue->card->options.performance_stats)
  2874. queue->card->perf_stats.skbs_sent_pack++;
  2875. if (buf->next_element_to_fill >=
  2876. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2877. /*
  2878. * packed buffer if full -> set state PRIMED
  2879. * -> will be flushed
  2880. */
  2881. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2882. flush_cnt = 1;
  2883. }
  2884. }
  2885. return flush_cnt;
  2886. }
  2887. int qeth_do_send_packet_fast(struct qeth_card *card,
  2888. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2889. struct qeth_hdr *hdr, int elements_needed,
  2890. struct qeth_eddp_context *ctx)
  2891. {
  2892. struct qeth_qdio_out_buffer *buffer;
  2893. int buffers_needed = 0;
  2894. int flush_cnt = 0;
  2895. int index;
  2896. QETH_DBF_TEXT(trace, 6, "dosndpfa");
  2897. /* spin until we get the queue ... */
  2898. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2899. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2900. /* ... now we've got the queue */
  2901. index = queue->next_buf_to_fill;
  2902. buffer = &queue->bufs[queue->next_buf_to_fill];
  2903. /*
  2904. * check if buffer is empty to make sure that we do not 'overtake'
  2905. * ourselves and try to fill a buffer that is already primed
  2906. */
  2907. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2908. goto out;
  2909. if (ctx == NULL)
  2910. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2911. QDIO_MAX_BUFFERS_PER_Q;
  2912. else {
  2913. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2914. ctx);
  2915. if (buffers_needed < 0)
  2916. goto out;
  2917. queue->next_buf_to_fill =
  2918. (queue->next_buf_to_fill + buffers_needed) %
  2919. QDIO_MAX_BUFFERS_PER_Q;
  2920. }
  2921. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2922. if (ctx == NULL) {
  2923. qeth_fill_buffer(queue, buffer, skb);
  2924. qeth_flush_buffers(queue, 0, index, 1);
  2925. } else {
  2926. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2927. WARN_ON(buffers_needed != flush_cnt);
  2928. qeth_flush_buffers(queue, 0, index, flush_cnt);
  2929. }
  2930. return 0;
  2931. out:
  2932. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2933. return -EBUSY;
  2934. }
  2935. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2936. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2937. struct sk_buff *skb, struct qeth_hdr *hdr,
  2938. int elements_needed, struct qeth_eddp_context *ctx)
  2939. {
  2940. struct qeth_qdio_out_buffer *buffer;
  2941. int start_index;
  2942. int flush_count = 0;
  2943. int do_pack = 0;
  2944. int tmp;
  2945. int rc = 0;
  2946. QETH_DBF_TEXT(trace, 6, "dosndpkt");
  2947. /* spin until we get the queue ... */
  2948. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2949. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2950. start_index = queue->next_buf_to_fill;
  2951. buffer = &queue->bufs[queue->next_buf_to_fill];
  2952. /*
  2953. * check if buffer is empty to make sure that we do not 'overtake'
  2954. * ourselves and try to fill a buffer that is already primed
  2955. */
  2956. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2957. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2958. return -EBUSY;
  2959. }
  2960. /* check if we need to switch packing state of this queue */
  2961. qeth_switch_to_packing_if_needed(queue);
  2962. if (queue->do_pack) {
  2963. do_pack = 1;
  2964. if (ctx == NULL) {
  2965. /* does packet fit in current buffer? */
  2966. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2967. buffer->next_element_to_fill) < elements_needed) {
  2968. /* ... no -> set state PRIMED */
  2969. atomic_set(&buffer->state,
  2970. QETH_QDIO_BUF_PRIMED);
  2971. flush_count++;
  2972. queue->next_buf_to_fill =
  2973. (queue->next_buf_to_fill + 1) %
  2974. QDIO_MAX_BUFFERS_PER_Q;
  2975. buffer = &queue->bufs[queue->next_buf_to_fill];
  2976. /* we did a step forward, so check buffer state
  2977. * again */
  2978. if (atomic_read(&buffer->state) !=
  2979. QETH_QDIO_BUF_EMPTY){
  2980. qeth_flush_buffers(queue, 0,
  2981. start_index, flush_count);
  2982. atomic_set(&queue->state,
  2983. QETH_OUT_Q_UNLOCKED);
  2984. return -EBUSY;
  2985. }
  2986. }
  2987. } else {
  2988. /* check if we have enough elements (including following
  2989. * free buffers) to handle eddp context */
  2990. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2991. < 0) {
  2992. if (net_ratelimit())
  2993. PRINT_WARN("eddp tx_dropped 1\n");
  2994. rc = -EBUSY;
  2995. goto out;
  2996. }
  2997. }
  2998. }
  2999. if (ctx == NULL)
  3000. tmp = qeth_fill_buffer(queue, buffer, skb);
  3001. else {
  3002. tmp = qeth_eddp_fill_buffer(queue, ctx,
  3003. queue->next_buf_to_fill);
  3004. if (tmp < 0) {
  3005. PRINT_ERR("eddp tx_dropped 2\n");
  3006. rc = -EBUSY;
  3007. goto out;
  3008. }
  3009. }
  3010. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3011. QDIO_MAX_BUFFERS_PER_Q;
  3012. flush_count += tmp;
  3013. out:
  3014. if (flush_count)
  3015. qeth_flush_buffers(queue, 0, start_index, flush_count);
  3016. else if (!atomic_read(&queue->set_pci_flags_count))
  3017. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3018. /*
  3019. * queue->state will go from LOCKED -> UNLOCKED or from
  3020. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3021. * (switch packing state or flush buffer to get another pci flag out).
  3022. * In that case we will enter this loop
  3023. */
  3024. while (atomic_dec_return(&queue->state)) {
  3025. flush_count = 0;
  3026. start_index = queue->next_buf_to_fill;
  3027. /* check if we can go back to non-packing state */
  3028. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3029. /*
  3030. * check if we need to flush a packing buffer to get a pci
  3031. * flag out on the queue
  3032. */
  3033. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3034. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3035. if (flush_count)
  3036. qeth_flush_buffers(queue, 0, start_index, flush_count);
  3037. }
  3038. /* at this point the queue is UNLOCKED again */
  3039. if (queue->card->options.performance_stats && do_pack)
  3040. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3041. return rc;
  3042. }
  3043. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3044. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3045. struct qeth_reply *reply, unsigned long data)
  3046. {
  3047. struct qeth_ipa_cmd *cmd;
  3048. struct qeth_ipacmd_setadpparms *setparms;
  3049. QETH_DBF_TEXT(trace, 4, "prmadpcb");
  3050. cmd = (struct qeth_ipa_cmd *) data;
  3051. setparms = &(cmd->data.setadapterparms);
  3052. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3053. if (cmd->hdr.return_code) {
  3054. QETH_DBF_TEXT_(trace, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3055. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3056. }
  3057. card->info.promisc_mode = setparms->data.mode;
  3058. return 0;
  3059. }
  3060. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3061. {
  3062. enum qeth_ipa_promisc_modes mode;
  3063. struct net_device *dev = card->dev;
  3064. struct qeth_cmd_buffer *iob;
  3065. struct qeth_ipa_cmd *cmd;
  3066. QETH_DBF_TEXT(trace, 4, "setprom");
  3067. if (((dev->flags & IFF_PROMISC) &&
  3068. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3069. (!(dev->flags & IFF_PROMISC) &&
  3070. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3071. return;
  3072. mode = SET_PROMISC_MODE_OFF;
  3073. if (dev->flags & IFF_PROMISC)
  3074. mode = SET_PROMISC_MODE_ON;
  3075. QETH_DBF_TEXT_(trace, 4, "mode:%x", mode);
  3076. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3077. sizeof(struct qeth_ipacmd_setadpparms));
  3078. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3079. cmd->data.setadapterparms.data.mode = mode;
  3080. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3081. }
  3082. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3083. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3084. {
  3085. struct qeth_card *card;
  3086. char dbf_text[15];
  3087. card = netdev_priv(dev);
  3088. QETH_DBF_TEXT(trace, 4, "chgmtu");
  3089. sprintf(dbf_text, "%8x", new_mtu);
  3090. QETH_DBF_TEXT(trace, 4, dbf_text);
  3091. if (new_mtu < 64)
  3092. return -EINVAL;
  3093. if (new_mtu > 65535)
  3094. return -EINVAL;
  3095. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3096. (!qeth_mtu_is_valid(card, new_mtu)))
  3097. return -EINVAL;
  3098. dev->mtu = new_mtu;
  3099. return 0;
  3100. }
  3101. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3102. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3103. {
  3104. struct qeth_card *card;
  3105. card = netdev_priv(dev);
  3106. QETH_DBF_TEXT(trace, 5, "getstat");
  3107. return &card->stats;
  3108. }
  3109. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3110. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3111. struct qeth_reply *reply, unsigned long data)
  3112. {
  3113. struct qeth_ipa_cmd *cmd;
  3114. QETH_DBF_TEXT(trace, 4, "chgmaccb");
  3115. cmd = (struct qeth_ipa_cmd *) data;
  3116. if (!card->options.layer2 ||
  3117. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3118. memcpy(card->dev->dev_addr,
  3119. &cmd->data.setadapterparms.data.change_addr.addr,
  3120. OSA_ADDR_LEN);
  3121. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3122. }
  3123. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3124. return 0;
  3125. }
  3126. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3127. {
  3128. int rc;
  3129. struct qeth_cmd_buffer *iob;
  3130. struct qeth_ipa_cmd *cmd;
  3131. QETH_DBF_TEXT(trace, 4, "chgmac");
  3132. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3133. sizeof(struct qeth_ipacmd_setadpparms));
  3134. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3135. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3136. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3137. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3138. card->dev->dev_addr, OSA_ADDR_LEN);
  3139. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3140. NULL);
  3141. return rc;
  3142. }
  3143. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3144. void qeth_tx_timeout(struct net_device *dev)
  3145. {
  3146. struct qeth_card *card;
  3147. card = netdev_priv(dev);
  3148. card->stats.tx_errors++;
  3149. qeth_schedule_recovery(card);
  3150. }
  3151. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3152. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3153. {
  3154. struct qeth_card *card = netdev_priv(dev);
  3155. int rc = 0;
  3156. switch (regnum) {
  3157. case MII_BMCR: /* Basic mode control register */
  3158. rc = BMCR_FULLDPLX;
  3159. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3160. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3161. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3162. rc |= BMCR_SPEED100;
  3163. break;
  3164. case MII_BMSR: /* Basic mode status register */
  3165. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3166. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3167. BMSR_100BASE4;
  3168. break;
  3169. case MII_PHYSID1: /* PHYS ID 1 */
  3170. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3171. dev->dev_addr[2];
  3172. rc = (rc >> 5) & 0xFFFF;
  3173. break;
  3174. case MII_PHYSID2: /* PHYS ID 2 */
  3175. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3176. break;
  3177. case MII_ADVERTISE: /* Advertisement control reg */
  3178. rc = ADVERTISE_ALL;
  3179. break;
  3180. case MII_LPA: /* Link partner ability reg */
  3181. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3182. LPA_100BASE4 | LPA_LPACK;
  3183. break;
  3184. case MII_EXPANSION: /* Expansion register */
  3185. break;
  3186. case MII_DCOUNTER: /* disconnect counter */
  3187. break;
  3188. case MII_FCSCOUNTER: /* false carrier counter */
  3189. break;
  3190. case MII_NWAYTEST: /* N-way auto-neg test register */
  3191. break;
  3192. case MII_RERRCOUNTER: /* rx error counter */
  3193. rc = card->stats.rx_errors;
  3194. break;
  3195. case MII_SREVISION: /* silicon revision */
  3196. break;
  3197. case MII_RESV1: /* reserved 1 */
  3198. break;
  3199. case MII_LBRERROR: /* loopback, rx, bypass error */
  3200. break;
  3201. case MII_PHYADDR: /* physical address */
  3202. break;
  3203. case MII_RESV2: /* reserved 2 */
  3204. break;
  3205. case MII_TPISTATUS: /* TPI status for 10mbps */
  3206. break;
  3207. case MII_NCONFIG: /* network interface config */
  3208. break;
  3209. default:
  3210. break;
  3211. }
  3212. return rc;
  3213. }
  3214. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3215. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3216. struct qeth_cmd_buffer *iob, int len,
  3217. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3218. unsigned long),
  3219. void *reply_param)
  3220. {
  3221. u16 s1, s2;
  3222. QETH_DBF_TEXT(trace, 4, "sendsnmp");
  3223. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3224. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3225. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3226. /* adjust PDU length fields in IPA_PDU_HEADER */
  3227. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3228. s2 = (u32) len;
  3229. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3230. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3231. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3232. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3233. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3234. reply_cb, reply_param);
  3235. }
  3236. static int qeth_snmp_command_cb(struct qeth_card *card,
  3237. struct qeth_reply *reply, unsigned long sdata)
  3238. {
  3239. struct qeth_ipa_cmd *cmd;
  3240. struct qeth_arp_query_info *qinfo;
  3241. struct qeth_snmp_cmd *snmp;
  3242. unsigned char *data;
  3243. __u16 data_len;
  3244. QETH_DBF_TEXT(trace, 3, "snpcmdcb");
  3245. cmd = (struct qeth_ipa_cmd *) sdata;
  3246. data = (unsigned char *)((char *)cmd - reply->offset);
  3247. qinfo = (struct qeth_arp_query_info *) reply->param;
  3248. snmp = &cmd->data.setadapterparms.data.snmp;
  3249. if (cmd->hdr.return_code) {
  3250. QETH_DBF_TEXT_(trace, 4, "scer1%i", cmd->hdr.return_code);
  3251. return 0;
  3252. }
  3253. if (cmd->data.setadapterparms.hdr.return_code) {
  3254. cmd->hdr.return_code =
  3255. cmd->data.setadapterparms.hdr.return_code;
  3256. QETH_DBF_TEXT_(trace, 4, "scer2%i", cmd->hdr.return_code);
  3257. return 0;
  3258. }
  3259. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3260. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3261. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3262. else
  3263. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3264. /* check if there is enough room in userspace */
  3265. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3266. QETH_DBF_TEXT_(trace, 4, "scer3%i", -ENOMEM);
  3267. cmd->hdr.return_code = -ENOMEM;
  3268. return 0;
  3269. }
  3270. QETH_DBF_TEXT_(trace, 4, "snore%i",
  3271. cmd->data.setadapterparms.hdr.used_total);
  3272. QETH_DBF_TEXT_(trace, 4, "sseqn%i",
  3273. cmd->data.setadapterparms.hdr.seq_no);
  3274. /*copy entries to user buffer*/
  3275. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3276. memcpy(qinfo->udata + qinfo->udata_offset,
  3277. (char *)snmp,
  3278. data_len + offsetof(struct qeth_snmp_cmd, data));
  3279. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3280. } else {
  3281. memcpy(qinfo->udata + qinfo->udata_offset,
  3282. (char *)&snmp->request, data_len);
  3283. }
  3284. qinfo->udata_offset += data_len;
  3285. /* check if all replies received ... */
  3286. QETH_DBF_TEXT_(trace, 4, "srtot%i",
  3287. cmd->data.setadapterparms.hdr.used_total);
  3288. QETH_DBF_TEXT_(trace, 4, "srseq%i",
  3289. cmd->data.setadapterparms.hdr.seq_no);
  3290. if (cmd->data.setadapterparms.hdr.seq_no <
  3291. cmd->data.setadapterparms.hdr.used_total)
  3292. return 1;
  3293. return 0;
  3294. }
  3295. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3296. {
  3297. struct qeth_cmd_buffer *iob;
  3298. struct qeth_ipa_cmd *cmd;
  3299. struct qeth_snmp_ureq *ureq;
  3300. int req_len;
  3301. struct qeth_arp_query_info qinfo = {0, };
  3302. int rc = 0;
  3303. QETH_DBF_TEXT(trace, 3, "snmpcmd");
  3304. if (card->info.guestlan)
  3305. return -EOPNOTSUPP;
  3306. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3307. (!card->options.layer2)) {
  3308. PRINT_WARN("SNMP Query MIBS not supported "
  3309. "on %s!\n", QETH_CARD_IFNAME(card));
  3310. return -EOPNOTSUPP;
  3311. }
  3312. /* skip 4 bytes (data_len struct member) to get req_len */
  3313. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3314. return -EFAULT;
  3315. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3316. if (!ureq) {
  3317. QETH_DBF_TEXT(trace, 2, "snmpnome");
  3318. return -ENOMEM;
  3319. }
  3320. if (copy_from_user(ureq, udata,
  3321. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3322. kfree(ureq);
  3323. return -EFAULT;
  3324. }
  3325. qinfo.udata_len = ureq->hdr.data_len;
  3326. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3327. if (!qinfo.udata) {
  3328. kfree(ureq);
  3329. return -ENOMEM;
  3330. }
  3331. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3332. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3333. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3334. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3335. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3336. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3337. qeth_snmp_command_cb, (void *)&qinfo);
  3338. if (rc)
  3339. PRINT_WARN("SNMP command failed on %s: (0x%x)\n",
  3340. QETH_CARD_IFNAME(card), rc);
  3341. else {
  3342. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3343. rc = -EFAULT;
  3344. }
  3345. kfree(ureq);
  3346. kfree(qinfo.udata);
  3347. return rc;
  3348. }
  3349. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3350. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3351. {
  3352. switch (card->info.type) {
  3353. case QETH_CARD_TYPE_IQD:
  3354. return 2;
  3355. default:
  3356. return 0;
  3357. }
  3358. }
  3359. static int qeth_qdio_establish(struct qeth_card *card)
  3360. {
  3361. struct qdio_initialize init_data;
  3362. char *qib_param_field;
  3363. struct qdio_buffer **in_sbal_ptrs;
  3364. struct qdio_buffer **out_sbal_ptrs;
  3365. int i, j, k;
  3366. int rc = 0;
  3367. QETH_DBF_TEXT(setup, 2, "qdioest");
  3368. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3369. GFP_KERNEL);
  3370. if (!qib_param_field)
  3371. return -ENOMEM;
  3372. qeth_create_qib_param_field(card, qib_param_field);
  3373. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3374. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3375. GFP_KERNEL);
  3376. if (!in_sbal_ptrs) {
  3377. kfree(qib_param_field);
  3378. return -ENOMEM;
  3379. }
  3380. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3381. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3382. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3383. out_sbal_ptrs =
  3384. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3385. sizeof(void *), GFP_KERNEL);
  3386. if (!out_sbal_ptrs) {
  3387. kfree(in_sbal_ptrs);
  3388. kfree(qib_param_field);
  3389. return -ENOMEM;
  3390. }
  3391. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3392. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3393. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3394. card->qdio.out_qs[i]->bufs[j].buffer);
  3395. }
  3396. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3397. init_data.cdev = CARD_DDEV(card);
  3398. init_data.q_format = qeth_get_qdio_q_format(card);
  3399. init_data.qib_param_field_format = 0;
  3400. init_data.qib_param_field = qib_param_field;
  3401. init_data.min_input_threshold = QETH_MIN_INPUT_THRESHOLD;
  3402. init_data.max_input_threshold = QETH_MAX_INPUT_THRESHOLD;
  3403. init_data.min_output_threshold = QETH_MIN_OUTPUT_THRESHOLD;
  3404. init_data.max_output_threshold = QETH_MAX_OUTPUT_THRESHOLD;
  3405. init_data.no_input_qs = 1;
  3406. init_data.no_output_qs = card->qdio.no_out_queues;
  3407. init_data.input_handler = card->discipline.input_handler;
  3408. init_data.output_handler = card->discipline.output_handler;
  3409. init_data.int_parm = (unsigned long) card;
  3410. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3411. QDIO_OUTBOUND_0COPY_SBALS |
  3412. QDIO_USE_OUTBOUND_PCIS;
  3413. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3414. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3415. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3416. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3417. rc = qdio_initialize(&init_data);
  3418. if (rc)
  3419. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3420. }
  3421. kfree(out_sbal_ptrs);
  3422. kfree(in_sbal_ptrs);
  3423. kfree(qib_param_field);
  3424. return rc;
  3425. }
  3426. static void qeth_core_free_card(struct qeth_card *card)
  3427. {
  3428. QETH_DBF_TEXT(setup, 2, "freecrd");
  3429. QETH_DBF_HEX(setup, 2, &card, sizeof(void *));
  3430. qeth_clean_channel(&card->read);
  3431. qeth_clean_channel(&card->write);
  3432. if (card->dev)
  3433. free_netdev(card->dev);
  3434. kfree(card->ip_tbd_list);
  3435. qeth_free_qdio_buffers(card);
  3436. kfree(card);
  3437. }
  3438. static struct ccw_device_id qeth_ids[] = {
  3439. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3440. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3441. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3442. {},
  3443. };
  3444. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3445. static struct ccw_driver qeth_ccw_driver = {
  3446. .name = "qeth",
  3447. .ids = qeth_ids,
  3448. .probe = ccwgroup_probe_ccwdev,
  3449. .remove = ccwgroup_remove_ccwdev,
  3450. };
  3451. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3452. unsigned long driver_id)
  3453. {
  3454. const char *start, *end;
  3455. char bus_ids[3][BUS_ID_SIZE], *argv[3];
  3456. int i;
  3457. start = buf;
  3458. for (i = 0; i < 3; i++) {
  3459. static const char delim[] = { ',', ',', '\n' };
  3460. int len;
  3461. end = strchr(start, delim[i]);
  3462. if (!end)
  3463. return -EINVAL;
  3464. len = min_t(ptrdiff_t, BUS_ID_SIZE, end - start);
  3465. strncpy(bus_ids[i], start, len);
  3466. bus_ids[i][len] = '\0';
  3467. start = end + 1;
  3468. argv[i] = bus_ids[i];
  3469. }
  3470. return (ccwgroup_create(root_dev, driver_id,
  3471. &qeth_ccw_driver, 3, argv));
  3472. }
  3473. int qeth_core_hardsetup_card(struct qeth_card *card)
  3474. {
  3475. int retries = 3;
  3476. int mpno;
  3477. int rc;
  3478. QETH_DBF_TEXT(setup, 2, "hrdsetup");
  3479. atomic_set(&card->force_alloc_skb, 0);
  3480. retry:
  3481. if (retries < 3) {
  3482. PRINT_WARN("Retrying to do IDX activates.\n");
  3483. ccw_device_set_offline(CARD_DDEV(card));
  3484. ccw_device_set_offline(CARD_WDEV(card));
  3485. ccw_device_set_offline(CARD_RDEV(card));
  3486. ccw_device_set_online(CARD_RDEV(card));
  3487. ccw_device_set_online(CARD_WDEV(card));
  3488. ccw_device_set_online(CARD_DDEV(card));
  3489. }
  3490. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3491. if (rc == -ERESTARTSYS) {
  3492. QETH_DBF_TEXT(setup, 2, "break1");
  3493. return rc;
  3494. } else if (rc) {
  3495. QETH_DBF_TEXT_(setup, 2, "1err%d", rc);
  3496. if (--retries < 0)
  3497. goto out;
  3498. else
  3499. goto retry;
  3500. }
  3501. rc = qeth_get_unitaddr(card);
  3502. if (rc) {
  3503. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  3504. return rc;
  3505. }
  3506. mpno = QETH_MAX_PORTNO;
  3507. if (card->info.portno > mpno) {
  3508. PRINT_ERR("Device %s does not offer port number %d \n.",
  3509. CARD_BUS_ID(card), card->info.portno);
  3510. rc = -ENODEV;
  3511. goto out;
  3512. }
  3513. qeth_init_tokens(card);
  3514. qeth_init_func_level(card);
  3515. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3516. if (rc == -ERESTARTSYS) {
  3517. QETH_DBF_TEXT(setup, 2, "break2");
  3518. return rc;
  3519. } else if (rc) {
  3520. QETH_DBF_TEXT_(setup, 2, "3err%d", rc);
  3521. if (--retries < 0)
  3522. goto out;
  3523. else
  3524. goto retry;
  3525. }
  3526. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3527. if (rc == -ERESTARTSYS) {
  3528. QETH_DBF_TEXT(setup, 2, "break3");
  3529. return rc;
  3530. } else if (rc) {
  3531. QETH_DBF_TEXT_(setup, 2, "4err%d", rc);
  3532. if (--retries < 0)
  3533. goto out;
  3534. else
  3535. goto retry;
  3536. }
  3537. rc = qeth_mpc_initialize(card);
  3538. if (rc) {
  3539. QETH_DBF_TEXT_(setup, 2, "5err%d", rc);
  3540. goto out;
  3541. }
  3542. return 0;
  3543. out:
  3544. PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
  3545. return rc;
  3546. }
  3547. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3548. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3549. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3550. {
  3551. struct page *page = virt_to_page(element->addr);
  3552. if (*pskb == NULL) {
  3553. /* the upper protocol layers assume that there is data in the
  3554. * skb itself. Copy a small amount (64 bytes) to make them
  3555. * happy. */
  3556. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3557. if (!(*pskb))
  3558. return -ENOMEM;
  3559. skb_reserve(*pskb, ETH_HLEN);
  3560. if (data_len <= 64) {
  3561. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3562. data_len);
  3563. } else {
  3564. get_page(page);
  3565. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3566. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3567. data_len - 64);
  3568. (*pskb)->data_len += data_len - 64;
  3569. (*pskb)->len += data_len - 64;
  3570. (*pskb)->truesize += data_len - 64;
  3571. (*pfrag)++;
  3572. }
  3573. } else {
  3574. get_page(page);
  3575. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3576. (*pskb)->data_len += data_len;
  3577. (*pskb)->len += data_len;
  3578. (*pskb)->truesize += data_len;
  3579. (*pfrag)++;
  3580. }
  3581. return 0;
  3582. }
  3583. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3584. struct qdio_buffer *buffer,
  3585. struct qdio_buffer_element **__element, int *__offset,
  3586. struct qeth_hdr **hdr)
  3587. {
  3588. struct qdio_buffer_element *element = *__element;
  3589. int offset = *__offset;
  3590. struct sk_buff *skb = NULL;
  3591. int skb_len;
  3592. void *data_ptr;
  3593. int data_len;
  3594. int headroom = 0;
  3595. int use_rx_sg = 0;
  3596. int frag = 0;
  3597. QETH_DBF_TEXT(trace, 6, "nextskb");
  3598. /* qeth_hdr must not cross element boundaries */
  3599. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3600. if (qeth_is_last_sbale(element))
  3601. return NULL;
  3602. element++;
  3603. offset = 0;
  3604. if (element->length < sizeof(struct qeth_hdr))
  3605. return NULL;
  3606. }
  3607. *hdr = element->addr + offset;
  3608. offset += sizeof(struct qeth_hdr);
  3609. if (card->options.layer2) {
  3610. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3611. skb_len = (*hdr)->hdr.osn.pdu_length;
  3612. headroom = sizeof(struct qeth_hdr);
  3613. } else {
  3614. skb_len = (*hdr)->hdr.l2.pkt_length;
  3615. }
  3616. } else {
  3617. skb_len = (*hdr)->hdr.l3.length;
  3618. headroom = max((int)ETH_HLEN, (int)TR_HLEN);
  3619. }
  3620. if (!skb_len)
  3621. return NULL;
  3622. if ((skb_len >= card->options.rx_sg_cb) &&
  3623. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3624. (!atomic_read(&card->force_alloc_skb))) {
  3625. use_rx_sg = 1;
  3626. } else {
  3627. skb = dev_alloc_skb(skb_len + headroom);
  3628. if (!skb)
  3629. goto no_mem;
  3630. if (headroom)
  3631. skb_reserve(skb, headroom);
  3632. }
  3633. data_ptr = element->addr + offset;
  3634. while (skb_len) {
  3635. data_len = min(skb_len, (int)(element->length - offset));
  3636. if (data_len) {
  3637. if (use_rx_sg) {
  3638. if (qeth_create_skb_frag(element, &skb, offset,
  3639. &frag, data_len))
  3640. goto no_mem;
  3641. } else {
  3642. memcpy(skb_put(skb, data_len), data_ptr,
  3643. data_len);
  3644. }
  3645. }
  3646. skb_len -= data_len;
  3647. if (skb_len) {
  3648. if (qeth_is_last_sbale(element)) {
  3649. QETH_DBF_TEXT(trace, 4, "unexeob");
  3650. QETH_DBF_TEXT_(trace, 4, "%s",
  3651. CARD_BUS_ID(card));
  3652. QETH_DBF_TEXT(qerr, 2, "unexeob");
  3653. QETH_DBF_TEXT_(qerr, 2, "%s",
  3654. CARD_BUS_ID(card));
  3655. QETH_DBF_HEX(misc, 4, buffer, sizeof(*buffer));
  3656. dev_kfree_skb_any(skb);
  3657. card->stats.rx_errors++;
  3658. return NULL;
  3659. }
  3660. element++;
  3661. offset = 0;
  3662. data_ptr = element->addr;
  3663. } else {
  3664. offset += data_len;
  3665. }
  3666. }
  3667. *__element = element;
  3668. *__offset = offset;
  3669. if (use_rx_sg && card->options.performance_stats) {
  3670. card->perf_stats.sg_skbs_rx++;
  3671. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3672. }
  3673. return skb;
  3674. no_mem:
  3675. if (net_ratelimit()) {
  3676. PRINT_WARN("No memory for packet received on %s.\n",
  3677. QETH_CARD_IFNAME(card));
  3678. QETH_DBF_TEXT(trace, 2, "noskbmem");
  3679. QETH_DBF_TEXT_(trace, 2, "%s", CARD_BUS_ID(card));
  3680. }
  3681. card->stats.rx_dropped++;
  3682. return NULL;
  3683. }
  3684. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3685. static void qeth_unregister_dbf_views(void)
  3686. {
  3687. if (qeth_dbf_setup)
  3688. debug_unregister(qeth_dbf_setup);
  3689. if (qeth_dbf_qerr)
  3690. debug_unregister(qeth_dbf_qerr);
  3691. if (qeth_dbf_sense)
  3692. debug_unregister(qeth_dbf_sense);
  3693. if (qeth_dbf_misc)
  3694. debug_unregister(qeth_dbf_misc);
  3695. if (qeth_dbf_data)
  3696. debug_unregister(qeth_dbf_data);
  3697. if (qeth_dbf_control)
  3698. debug_unregister(qeth_dbf_control);
  3699. if (qeth_dbf_trace)
  3700. debug_unregister(qeth_dbf_trace);
  3701. }
  3702. static int qeth_register_dbf_views(void)
  3703. {
  3704. qeth_dbf_setup = debug_register(QETH_DBF_SETUP_NAME,
  3705. QETH_DBF_SETUP_PAGES,
  3706. QETH_DBF_SETUP_NR_AREAS,
  3707. QETH_DBF_SETUP_LEN);
  3708. qeth_dbf_misc = debug_register(QETH_DBF_MISC_NAME,
  3709. QETH_DBF_MISC_PAGES,
  3710. QETH_DBF_MISC_NR_AREAS,
  3711. QETH_DBF_MISC_LEN);
  3712. qeth_dbf_data = debug_register(QETH_DBF_DATA_NAME,
  3713. QETH_DBF_DATA_PAGES,
  3714. QETH_DBF_DATA_NR_AREAS,
  3715. QETH_DBF_DATA_LEN);
  3716. qeth_dbf_control = debug_register(QETH_DBF_CONTROL_NAME,
  3717. QETH_DBF_CONTROL_PAGES,
  3718. QETH_DBF_CONTROL_NR_AREAS,
  3719. QETH_DBF_CONTROL_LEN);
  3720. qeth_dbf_sense = debug_register(QETH_DBF_SENSE_NAME,
  3721. QETH_DBF_SENSE_PAGES,
  3722. QETH_DBF_SENSE_NR_AREAS,
  3723. QETH_DBF_SENSE_LEN);
  3724. qeth_dbf_qerr = debug_register(QETH_DBF_QERR_NAME,
  3725. QETH_DBF_QERR_PAGES,
  3726. QETH_DBF_QERR_NR_AREAS,
  3727. QETH_DBF_QERR_LEN);
  3728. qeth_dbf_trace = debug_register(QETH_DBF_TRACE_NAME,
  3729. QETH_DBF_TRACE_PAGES,
  3730. QETH_DBF_TRACE_NR_AREAS,
  3731. QETH_DBF_TRACE_LEN);
  3732. if ((qeth_dbf_setup == NULL) || (qeth_dbf_misc == NULL) ||
  3733. (qeth_dbf_data == NULL) || (qeth_dbf_control == NULL) ||
  3734. (qeth_dbf_sense == NULL) || (qeth_dbf_qerr == NULL) ||
  3735. (qeth_dbf_trace == NULL)) {
  3736. qeth_unregister_dbf_views();
  3737. return -ENOMEM;
  3738. }
  3739. debug_register_view(qeth_dbf_setup, &debug_hex_ascii_view);
  3740. debug_set_level(qeth_dbf_setup, QETH_DBF_SETUP_LEVEL);
  3741. debug_register_view(qeth_dbf_misc, &debug_hex_ascii_view);
  3742. debug_set_level(qeth_dbf_misc, QETH_DBF_MISC_LEVEL);
  3743. debug_register_view(qeth_dbf_data, &debug_hex_ascii_view);
  3744. debug_set_level(qeth_dbf_data, QETH_DBF_DATA_LEVEL);
  3745. debug_register_view(qeth_dbf_control, &debug_hex_ascii_view);
  3746. debug_set_level(qeth_dbf_control, QETH_DBF_CONTROL_LEVEL);
  3747. debug_register_view(qeth_dbf_sense, &debug_hex_ascii_view);
  3748. debug_set_level(qeth_dbf_sense, QETH_DBF_SENSE_LEVEL);
  3749. debug_register_view(qeth_dbf_qerr, &debug_hex_ascii_view);
  3750. debug_set_level(qeth_dbf_qerr, QETH_DBF_QERR_LEVEL);
  3751. debug_register_view(qeth_dbf_trace, &debug_hex_ascii_view);
  3752. debug_set_level(qeth_dbf_trace, QETH_DBF_TRACE_LEVEL);
  3753. return 0;
  3754. }
  3755. int qeth_core_load_discipline(struct qeth_card *card,
  3756. enum qeth_discipline_id discipline)
  3757. {
  3758. int rc = 0;
  3759. switch (discipline) {
  3760. case QETH_DISCIPLINE_LAYER3:
  3761. card->discipline.ccwgdriver = try_then_request_module(
  3762. symbol_get(qeth_l3_ccwgroup_driver),
  3763. "qeth_l3");
  3764. break;
  3765. case QETH_DISCIPLINE_LAYER2:
  3766. card->discipline.ccwgdriver = try_then_request_module(
  3767. symbol_get(qeth_l2_ccwgroup_driver),
  3768. "qeth_l2");
  3769. break;
  3770. }
  3771. if (!card->discipline.ccwgdriver) {
  3772. PRINT_ERR("Support for discipline %d not present\n",
  3773. discipline);
  3774. rc = -EINVAL;
  3775. }
  3776. return rc;
  3777. }
  3778. void qeth_core_free_discipline(struct qeth_card *card)
  3779. {
  3780. if (card->options.layer2)
  3781. symbol_put(qeth_l2_ccwgroup_driver);
  3782. else
  3783. symbol_put(qeth_l3_ccwgroup_driver);
  3784. card->discipline.ccwgdriver = NULL;
  3785. }
  3786. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3787. {
  3788. struct qeth_card *card;
  3789. struct device *dev;
  3790. int rc;
  3791. unsigned long flags;
  3792. QETH_DBF_TEXT(setup, 2, "probedev");
  3793. dev = &gdev->dev;
  3794. if (!get_device(dev))
  3795. return -ENODEV;
  3796. QETH_DBF_TEXT_(setup, 2, "%s", gdev->dev.bus_id);
  3797. card = qeth_alloc_card();
  3798. if (!card) {
  3799. QETH_DBF_TEXT_(setup, 2, "1err%d", -ENOMEM);
  3800. rc = -ENOMEM;
  3801. goto err_dev;
  3802. }
  3803. card->read.ccwdev = gdev->cdev[0];
  3804. card->write.ccwdev = gdev->cdev[1];
  3805. card->data.ccwdev = gdev->cdev[2];
  3806. dev_set_drvdata(&gdev->dev, card);
  3807. card->gdev = gdev;
  3808. gdev->cdev[0]->handler = qeth_irq;
  3809. gdev->cdev[1]->handler = qeth_irq;
  3810. gdev->cdev[2]->handler = qeth_irq;
  3811. rc = qeth_determine_card_type(card);
  3812. if (rc) {
  3813. PRINT_WARN("%s: not a valid card type\n", __func__);
  3814. QETH_DBF_TEXT_(setup, 2, "3err%d", rc);
  3815. goto err_card;
  3816. }
  3817. rc = qeth_setup_card(card);
  3818. if (rc) {
  3819. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  3820. goto err_card;
  3821. }
  3822. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3823. rc = qeth_core_create_osn_attributes(dev);
  3824. if (rc)
  3825. goto err_card;
  3826. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3827. if (rc) {
  3828. qeth_core_remove_osn_attributes(dev);
  3829. goto err_card;
  3830. }
  3831. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3832. if (rc) {
  3833. qeth_core_free_discipline(card);
  3834. qeth_core_remove_osn_attributes(dev);
  3835. goto err_card;
  3836. }
  3837. } else {
  3838. rc = qeth_core_create_device_attributes(dev);
  3839. if (rc)
  3840. goto err_card;
  3841. }
  3842. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3843. list_add_tail(&card->list, &qeth_core_card_list.list);
  3844. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3845. return 0;
  3846. err_card:
  3847. qeth_core_free_card(card);
  3848. err_dev:
  3849. put_device(dev);
  3850. return rc;
  3851. }
  3852. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3853. {
  3854. unsigned long flags;
  3855. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3856. if (card->discipline.ccwgdriver) {
  3857. card->discipline.ccwgdriver->remove(gdev);
  3858. qeth_core_free_discipline(card);
  3859. }
  3860. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3861. qeth_core_remove_osn_attributes(&gdev->dev);
  3862. } else {
  3863. qeth_core_remove_device_attributes(&gdev->dev);
  3864. }
  3865. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3866. list_del(&card->list);
  3867. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3868. qeth_core_free_card(card);
  3869. dev_set_drvdata(&gdev->dev, NULL);
  3870. put_device(&gdev->dev);
  3871. return;
  3872. }
  3873. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3874. {
  3875. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3876. int rc = 0;
  3877. int def_discipline;
  3878. if (!card->discipline.ccwgdriver) {
  3879. if (card->info.type == QETH_CARD_TYPE_IQD)
  3880. def_discipline = QETH_DISCIPLINE_LAYER3;
  3881. else
  3882. def_discipline = QETH_DISCIPLINE_LAYER2;
  3883. rc = qeth_core_load_discipline(card, def_discipline);
  3884. if (rc)
  3885. goto err;
  3886. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3887. if (rc)
  3888. goto err;
  3889. }
  3890. rc = card->discipline.ccwgdriver->set_online(gdev);
  3891. err:
  3892. return rc;
  3893. }
  3894. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3895. {
  3896. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3897. return card->discipline.ccwgdriver->set_offline(gdev);
  3898. }
  3899. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3900. {
  3901. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3902. if (card->discipline.ccwgdriver &&
  3903. card->discipline.ccwgdriver->shutdown)
  3904. card->discipline.ccwgdriver->shutdown(gdev);
  3905. }
  3906. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3907. .owner = THIS_MODULE,
  3908. .name = "qeth",
  3909. .driver_id = 0xD8C5E3C8,
  3910. .probe = qeth_core_probe_device,
  3911. .remove = qeth_core_remove_device,
  3912. .set_online = qeth_core_set_online,
  3913. .set_offline = qeth_core_set_offline,
  3914. .shutdown = qeth_core_shutdown,
  3915. };
  3916. static ssize_t
  3917. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3918. size_t count)
  3919. {
  3920. int err;
  3921. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3922. qeth_core_ccwgroup_driver.driver_id);
  3923. if (err)
  3924. return err;
  3925. else
  3926. return count;
  3927. }
  3928. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3929. static struct {
  3930. const char str[ETH_GSTRING_LEN];
  3931. } qeth_ethtool_stats_keys[] = {
  3932. /* 0 */{"rx skbs"},
  3933. {"rx buffers"},
  3934. {"tx skbs"},
  3935. {"tx buffers"},
  3936. {"tx skbs no packing"},
  3937. {"tx buffers no packing"},
  3938. {"tx skbs packing"},
  3939. {"tx buffers packing"},
  3940. {"tx sg skbs"},
  3941. {"tx sg frags"},
  3942. /* 10 */{"rx sg skbs"},
  3943. {"rx sg frags"},
  3944. {"rx sg page allocs"},
  3945. {"tx large kbytes"},
  3946. {"tx large count"},
  3947. {"tx pk state ch n->p"},
  3948. {"tx pk state ch p->n"},
  3949. {"tx pk watermark low"},
  3950. {"tx pk watermark high"},
  3951. {"queue 0 buffer usage"},
  3952. /* 20 */{"queue 1 buffer usage"},
  3953. {"queue 2 buffer usage"},
  3954. {"queue 3 buffer usage"},
  3955. {"rx handler time"},
  3956. {"rx handler count"},
  3957. {"rx do_QDIO time"},
  3958. {"rx do_QDIO count"},
  3959. {"tx handler time"},
  3960. {"tx handler count"},
  3961. {"tx time"},
  3962. /* 30 */{"tx count"},
  3963. {"tx do_QDIO time"},
  3964. {"tx do_QDIO count"},
  3965. };
  3966. int qeth_core_get_stats_count(struct net_device *dev)
  3967. {
  3968. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3969. }
  3970. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3971. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3972. struct ethtool_stats *stats, u64 *data)
  3973. {
  3974. struct qeth_card *card = netdev_priv(dev);
  3975. data[0] = card->stats.rx_packets -
  3976. card->perf_stats.initial_rx_packets;
  3977. data[1] = card->perf_stats.bufs_rec;
  3978. data[2] = card->stats.tx_packets -
  3979. card->perf_stats.initial_tx_packets;
  3980. data[3] = card->perf_stats.bufs_sent;
  3981. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3982. - card->perf_stats.skbs_sent_pack;
  3983. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3984. data[6] = card->perf_stats.skbs_sent_pack;
  3985. data[7] = card->perf_stats.bufs_sent_pack;
  3986. data[8] = card->perf_stats.sg_skbs_sent;
  3987. data[9] = card->perf_stats.sg_frags_sent;
  3988. data[10] = card->perf_stats.sg_skbs_rx;
  3989. data[11] = card->perf_stats.sg_frags_rx;
  3990. data[12] = card->perf_stats.sg_alloc_page_rx;
  3991. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3992. data[14] = card->perf_stats.large_send_cnt;
  3993. data[15] = card->perf_stats.sc_dp_p;
  3994. data[16] = card->perf_stats.sc_p_dp;
  3995. data[17] = QETH_LOW_WATERMARK_PACK;
  3996. data[18] = QETH_HIGH_WATERMARK_PACK;
  3997. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3998. data[20] = (card->qdio.no_out_queues > 1) ?
  3999. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4000. data[21] = (card->qdio.no_out_queues > 2) ?
  4001. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4002. data[22] = (card->qdio.no_out_queues > 3) ?
  4003. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4004. data[23] = card->perf_stats.inbound_time;
  4005. data[24] = card->perf_stats.inbound_cnt;
  4006. data[25] = card->perf_stats.inbound_do_qdio_time;
  4007. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4008. data[27] = card->perf_stats.outbound_handler_time;
  4009. data[28] = card->perf_stats.outbound_handler_cnt;
  4010. data[29] = card->perf_stats.outbound_time;
  4011. data[30] = card->perf_stats.outbound_cnt;
  4012. data[31] = card->perf_stats.outbound_do_qdio_time;
  4013. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4014. }
  4015. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4016. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4017. {
  4018. switch (stringset) {
  4019. case ETH_SS_STATS:
  4020. memcpy(data, &qeth_ethtool_stats_keys,
  4021. sizeof(qeth_ethtool_stats_keys));
  4022. break;
  4023. default:
  4024. WARN_ON(1);
  4025. break;
  4026. }
  4027. }
  4028. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4029. void qeth_core_get_drvinfo(struct net_device *dev,
  4030. struct ethtool_drvinfo *info)
  4031. {
  4032. struct qeth_card *card = netdev_priv(dev);
  4033. if (card->options.layer2)
  4034. strcpy(info->driver, "qeth_l2");
  4035. else
  4036. strcpy(info->driver, "qeth_l3");
  4037. strcpy(info->version, "1.0");
  4038. strcpy(info->fw_version, card->info.mcl_level);
  4039. sprintf(info->bus_info, "%s/%s/%s",
  4040. CARD_RDEV_ID(card),
  4041. CARD_WDEV_ID(card),
  4042. CARD_DDEV_ID(card));
  4043. }
  4044. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4045. static int __init qeth_core_init(void)
  4046. {
  4047. int rc;
  4048. PRINT_INFO("loading core functions\n");
  4049. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4050. rwlock_init(&qeth_core_card_list.rwlock);
  4051. rc = qeth_register_dbf_views();
  4052. if (rc)
  4053. goto out_err;
  4054. rc = ccw_driver_register(&qeth_ccw_driver);
  4055. if (rc)
  4056. goto ccw_err;
  4057. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4058. if (rc)
  4059. goto ccwgroup_err;
  4060. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4061. &driver_attr_group);
  4062. if (rc)
  4063. goto driver_err;
  4064. qeth_core_root_dev = s390_root_dev_register("qeth");
  4065. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4066. if (rc)
  4067. goto register_err;
  4068. return 0;
  4069. register_err:
  4070. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4071. &driver_attr_group);
  4072. driver_err:
  4073. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4074. ccwgroup_err:
  4075. ccw_driver_unregister(&qeth_ccw_driver);
  4076. ccw_err:
  4077. qeth_unregister_dbf_views();
  4078. out_err:
  4079. PRINT_ERR("Initialization failed with code %d\n", rc);
  4080. return rc;
  4081. }
  4082. static void __exit qeth_core_exit(void)
  4083. {
  4084. s390_root_dev_unregister(qeth_core_root_dev);
  4085. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4086. &driver_attr_group);
  4087. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4088. ccw_driver_unregister(&qeth_ccw_driver);
  4089. qeth_unregister_dbf_views();
  4090. PRINT_INFO("core functions removed\n");
  4091. }
  4092. module_init(qeth_core_init);
  4093. module_exit(qeth_core_exit);
  4094. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4095. MODULE_DESCRIPTION("qeth core functions");
  4096. MODULE_LICENSE("GPL");