netxen_nic_init.c 31 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  47. uint32_t ctx, uint32_t ringid);
  48. static void crb_addr_transform_setup(void)
  49. {
  50. crb_addr_transform(XDMA);
  51. crb_addr_transform(TIMR);
  52. crb_addr_transform(SRE);
  53. crb_addr_transform(SQN3);
  54. crb_addr_transform(SQN2);
  55. crb_addr_transform(SQN1);
  56. crb_addr_transform(SQN0);
  57. crb_addr_transform(SQS3);
  58. crb_addr_transform(SQS2);
  59. crb_addr_transform(SQS1);
  60. crb_addr_transform(SQS0);
  61. crb_addr_transform(RPMX7);
  62. crb_addr_transform(RPMX6);
  63. crb_addr_transform(RPMX5);
  64. crb_addr_transform(RPMX4);
  65. crb_addr_transform(RPMX3);
  66. crb_addr_transform(RPMX2);
  67. crb_addr_transform(RPMX1);
  68. crb_addr_transform(RPMX0);
  69. crb_addr_transform(ROMUSB);
  70. crb_addr_transform(SN);
  71. crb_addr_transform(QMN);
  72. crb_addr_transform(QMS);
  73. crb_addr_transform(PGNI);
  74. crb_addr_transform(PGND);
  75. crb_addr_transform(PGN3);
  76. crb_addr_transform(PGN2);
  77. crb_addr_transform(PGN1);
  78. crb_addr_transform(PGN0);
  79. crb_addr_transform(PGSI);
  80. crb_addr_transform(PGSD);
  81. crb_addr_transform(PGS3);
  82. crb_addr_transform(PGS2);
  83. crb_addr_transform(PGS1);
  84. crb_addr_transform(PGS0);
  85. crb_addr_transform(PS);
  86. crb_addr_transform(PH);
  87. crb_addr_transform(NIU);
  88. crb_addr_transform(I2Q);
  89. crb_addr_transform(EG);
  90. crb_addr_transform(MN);
  91. crb_addr_transform(MS);
  92. crb_addr_transform(CAS2);
  93. crb_addr_transform(CAS1);
  94. crb_addr_transform(CAS0);
  95. crb_addr_transform(CAM);
  96. crb_addr_transform(C2C1);
  97. crb_addr_transform(C2C0);
  98. crb_addr_transform(SMB);
  99. crb_addr_transform(OCM0);
  100. crb_addr_transform(I2C0);
  101. }
  102. int netxen_init_firmware(struct netxen_adapter *adapter)
  103. {
  104. u32 state = 0, loops = 0, err = 0;
  105. /* Window 1 call */
  106. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  107. if (state == PHAN_INITIALIZE_ACK)
  108. return 0;
  109. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  110. msleep(1);
  111. /* Window 1 call */
  112. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  113. loops++;
  114. }
  115. if (loops >= 2000) {
  116. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  117. state);
  118. err = -EIO;
  119. return err;
  120. }
  121. /* Window 1 call */
  122. adapter->pci_write_normalize(adapter,
  123. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  124. adapter->pci_write_normalize(adapter,
  125. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  126. adapter->pci_write_normalize(adapter,
  127. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  128. adapter->pci_write_normalize(adapter,
  129. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  130. return err;
  131. }
  132. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  133. {
  134. struct netxen_recv_context *recv_ctx;
  135. struct nx_host_rds_ring *rds_ring;
  136. struct netxen_rx_buffer *rx_buf;
  137. int i, ctxid, ring;
  138. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  139. recv_ctx = &adapter->recv_ctx[ctxid];
  140. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  141. rds_ring = &recv_ctx->rds_rings[ring];
  142. for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
  143. rx_buf = &(rds_ring->rx_buf_arr[i]);
  144. if (rx_buf->state == NETXEN_BUFFER_FREE)
  145. continue;
  146. pci_unmap_single(adapter->pdev,
  147. rx_buf->dma,
  148. rds_ring->dma_size,
  149. PCI_DMA_FROMDEVICE);
  150. if (rx_buf->skb != NULL)
  151. dev_kfree_skb_any(rx_buf->skb);
  152. }
  153. }
  154. }
  155. }
  156. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  157. {
  158. struct netxen_cmd_buffer *cmd_buf;
  159. struct netxen_skb_frag *buffrag;
  160. int i, j;
  161. cmd_buf = adapter->cmd_buf_arr;
  162. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  163. buffrag = cmd_buf->frag_array;
  164. if (buffrag->dma) {
  165. pci_unmap_single(adapter->pdev, buffrag->dma,
  166. buffrag->length, PCI_DMA_TODEVICE);
  167. buffrag->dma = 0ULL;
  168. }
  169. for (j = 0; j < cmd_buf->frag_count; j++) {
  170. buffrag++;
  171. if (buffrag->dma) {
  172. pci_unmap_page(adapter->pdev, buffrag->dma,
  173. buffrag->length,
  174. PCI_DMA_TODEVICE);
  175. buffrag->dma = 0ULL;
  176. }
  177. }
  178. /* Free the skb we received in netxen_nic_xmit_frame */
  179. if (cmd_buf->skb) {
  180. dev_kfree_skb_any(cmd_buf->skb);
  181. cmd_buf->skb = NULL;
  182. }
  183. cmd_buf++;
  184. }
  185. }
  186. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  187. {
  188. struct netxen_recv_context *recv_ctx;
  189. struct nx_host_rds_ring *rds_ring;
  190. int ctx, ring;
  191. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  192. recv_ctx = &adapter->recv_ctx[ctx];
  193. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  194. rds_ring = &recv_ctx->rds_rings[ring];
  195. if (rds_ring->rx_buf_arr) {
  196. vfree(rds_ring->rx_buf_arr);
  197. rds_ring->rx_buf_arr = NULL;
  198. }
  199. }
  200. }
  201. if (adapter->cmd_buf_arr)
  202. vfree(adapter->cmd_buf_arr);
  203. return;
  204. }
  205. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  206. {
  207. struct netxen_recv_context *recv_ctx;
  208. struct nx_host_rds_ring *rds_ring;
  209. struct netxen_rx_buffer *rx_buf;
  210. int ctx, ring, i, num_rx_bufs;
  211. struct netxen_cmd_buffer *cmd_buf_arr;
  212. struct net_device *netdev = adapter->netdev;
  213. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  214. if (cmd_buf_arr == NULL) {
  215. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  216. netdev->name);
  217. return -ENOMEM;
  218. }
  219. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  220. adapter->cmd_buf_arr = cmd_buf_arr;
  221. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  222. recv_ctx = &adapter->recv_ctx[ctx];
  223. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  224. rds_ring = &recv_ctx->rds_rings[ring];
  225. switch (RCV_DESC_TYPE(ring)) {
  226. case RCV_DESC_NORMAL:
  227. rds_ring->max_rx_desc_count =
  228. adapter->max_rx_desc_count;
  229. rds_ring->flags = RCV_DESC_NORMAL;
  230. if (adapter->ahw.cut_through) {
  231. rds_ring->dma_size =
  232. NX_CT_DEFAULT_RX_BUF_LEN;
  233. rds_ring->skb_size =
  234. NX_CT_DEFAULT_RX_BUF_LEN;
  235. } else {
  236. rds_ring->dma_size = RX_DMA_MAP_LEN;
  237. rds_ring->skb_size =
  238. MAX_RX_BUFFER_LENGTH;
  239. }
  240. break;
  241. case RCV_DESC_JUMBO:
  242. rds_ring->max_rx_desc_count =
  243. adapter->max_jumbo_rx_desc_count;
  244. rds_ring->flags = RCV_DESC_JUMBO;
  245. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  246. rds_ring->dma_size =
  247. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  248. else
  249. rds_ring->dma_size =
  250. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  251. rds_ring->skb_size =
  252. rds_ring->dma_size + NET_IP_ALIGN;
  253. break;
  254. case RCV_RING_LRO:
  255. rds_ring->max_rx_desc_count =
  256. adapter->max_lro_rx_desc_count;
  257. rds_ring->flags = RCV_DESC_LRO;
  258. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  259. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  260. break;
  261. }
  262. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  263. vmalloc(RCV_BUFFSIZE);
  264. if (rds_ring->rx_buf_arr == NULL) {
  265. printk(KERN_ERR "%s: Failed to allocate "
  266. "rx buffer ring %d\n",
  267. netdev->name, ring);
  268. /* free whatever was already allocated */
  269. goto err_out;
  270. }
  271. memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
  272. INIT_LIST_HEAD(&rds_ring->free_list);
  273. /*
  274. * Now go through all of them, set reference handles
  275. * and put them in the queues.
  276. */
  277. num_rx_bufs = rds_ring->max_rx_desc_count;
  278. rx_buf = rds_ring->rx_buf_arr;
  279. for (i = 0; i < num_rx_bufs; i++) {
  280. list_add_tail(&rx_buf->list,
  281. &rds_ring->free_list);
  282. rx_buf->ref_handle = i;
  283. rx_buf->state = NETXEN_BUFFER_FREE;
  284. rx_buf++;
  285. }
  286. }
  287. }
  288. return 0;
  289. err_out:
  290. netxen_free_sw_resources(adapter);
  291. return -ENOMEM;
  292. }
  293. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  294. {
  295. switch (adapter->ahw.board_type) {
  296. case NETXEN_NIC_GBE:
  297. adapter->enable_phy_interrupts =
  298. netxen_niu_gbe_enable_phy_interrupts;
  299. adapter->disable_phy_interrupts =
  300. netxen_niu_gbe_disable_phy_interrupts;
  301. adapter->macaddr_set = netxen_niu_macaddr_set;
  302. adapter->set_mtu = netxen_nic_set_mtu_gb;
  303. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  304. adapter->phy_read = netxen_niu_gbe_phy_read;
  305. adapter->phy_write = netxen_niu_gbe_phy_write;
  306. adapter->init_port = netxen_niu_gbe_init_port;
  307. adapter->stop_port = netxen_niu_disable_gbe_port;
  308. break;
  309. case NETXEN_NIC_XGBE:
  310. adapter->enable_phy_interrupts =
  311. netxen_niu_xgbe_enable_phy_interrupts;
  312. adapter->disable_phy_interrupts =
  313. netxen_niu_xgbe_disable_phy_interrupts;
  314. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  315. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  316. adapter->init_port = netxen_niu_xg_init_port;
  317. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  318. adapter->stop_port = netxen_niu_disable_xg_port;
  319. break;
  320. default:
  321. break;
  322. }
  323. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  324. adapter->set_mtu = nx_fw_cmd_set_mtu;
  325. adapter->set_promisc = netxen_p3_nic_set_promisc;
  326. }
  327. }
  328. /*
  329. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  330. * address to external PCI CRB address.
  331. */
  332. static u32 netxen_decode_crb_addr(u32 addr)
  333. {
  334. int i;
  335. u32 base_addr, offset, pci_base;
  336. crb_addr_transform_setup();
  337. pci_base = NETXEN_ADDR_ERROR;
  338. base_addr = addr & 0xfff00000;
  339. offset = addr & 0x000fffff;
  340. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  341. if (crb_addr_xform[i] == base_addr) {
  342. pci_base = i << 20;
  343. break;
  344. }
  345. }
  346. if (pci_base == NETXEN_ADDR_ERROR)
  347. return pci_base;
  348. else
  349. return (pci_base + offset);
  350. }
  351. static long rom_max_timeout = 100;
  352. static long rom_lock_timeout = 10000;
  353. static int rom_lock(struct netxen_adapter *adapter)
  354. {
  355. int iter;
  356. u32 done = 0;
  357. int timeout = 0;
  358. while (!done) {
  359. /* acquire semaphore2 from PCI HW block */
  360. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  361. &done);
  362. if (done == 1)
  363. break;
  364. if (timeout >= rom_lock_timeout)
  365. return -EIO;
  366. timeout++;
  367. /*
  368. * Yield CPU
  369. */
  370. if (!in_atomic())
  371. schedule();
  372. else {
  373. for (iter = 0; iter < 20; iter++)
  374. cpu_relax(); /*This a nop instr on i386 */
  375. }
  376. }
  377. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  378. return 0;
  379. }
  380. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  381. {
  382. long timeout = 0;
  383. long done = 0;
  384. cond_resched();
  385. while (done == 0) {
  386. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  387. done &= 2;
  388. timeout++;
  389. if (timeout >= rom_max_timeout) {
  390. printk("Timeout reached waiting for rom done");
  391. return -EIO;
  392. }
  393. }
  394. return 0;
  395. }
  396. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  397. {
  398. u32 val;
  399. /* release semaphore2 */
  400. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  401. }
  402. static int do_rom_fast_read(struct netxen_adapter *adapter,
  403. int addr, int *valp)
  404. {
  405. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  406. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  407. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  408. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  409. if (netxen_wait_rom_done(adapter)) {
  410. printk("Error waiting for rom done\n");
  411. return -EIO;
  412. }
  413. /* reset abyte_cnt and dummy_byte_cnt */
  414. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  415. udelay(10);
  416. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  417. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  418. return 0;
  419. }
  420. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  421. u8 *bytes, size_t size)
  422. {
  423. int addridx;
  424. int ret = 0;
  425. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  426. int v;
  427. ret = do_rom_fast_read(adapter, addridx, &v);
  428. if (ret != 0)
  429. break;
  430. *(__le32 *)bytes = cpu_to_le32(v);
  431. bytes += 4;
  432. }
  433. return ret;
  434. }
  435. int
  436. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  437. u8 *bytes, size_t size)
  438. {
  439. int ret;
  440. ret = rom_lock(adapter);
  441. if (ret < 0)
  442. return ret;
  443. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  444. netxen_rom_unlock(adapter);
  445. return ret;
  446. }
  447. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  448. {
  449. int ret;
  450. if (rom_lock(adapter) != 0)
  451. return -EIO;
  452. ret = do_rom_fast_read(adapter, addr, valp);
  453. netxen_rom_unlock(adapter);
  454. return ret;
  455. }
  456. #define NETXEN_BOARDTYPE 0x4008
  457. #define NETXEN_BOARDNUM 0x400c
  458. #define NETXEN_CHIPNUM 0x4010
  459. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  460. {
  461. int addr, val;
  462. int i, n, init_delay = 0;
  463. struct crb_addr_pair *buf;
  464. unsigned offset;
  465. u32 off;
  466. /* resetall */
  467. rom_lock(adapter);
  468. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  469. 0xffffffff);
  470. netxen_rom_unlock(adapter);
  471. if (verbose) {
  472. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  473. printk("P2 ROM board type: 0x%08x\n", val);
  474. else
  475. printk("Could not read board type\n");
  476. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  477. printk("P2 ROM board num: 0x%08x\n", val);
  478. else
  479. printk("Could not read board number\n");
  480. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  481. printk("P2 ROM chip num: 0x%08x\n", val);
  482. else
  483. printk("Could not read chip number\n");
  484. }
  485. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  486. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  487. (n != 0xcafecafe) ||
  488. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  489. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  490. "n: %08x\n", netxen_nic_driver_name, n);
  491. return -EIO;
  492. }
  493. offset = n & 0xffffU;
  494. n = (n >> 16) & 0xffffU;
  495. } else {
  496. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  497. !(n & 0x80000000)) {
  498. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  499. "n: %08x\n", netxen_nic_driver_name, n);
  500. return -EIO;
  501. }
  502. offset = 1;
  503. n &= ~0x80000000;
  504. }
  505. if (n < 1024) {
  506. if (verbose)
  507. printk(KERN_DEBUG "%s: %d CRB init values found"
  508. " in ROM.\n", netxen_nic_driver_name, n);
  509. } else {
  510. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  511. " initialized.\n", __func__, n);
  512. return -EIO;
  513. }
  514. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  515. if (buf == NULL) {
  516. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  517. netxen_nic_driver_name);
  518. return -ENOMEM;
  519. }
  520. for (i = 0; i < n; i++) {
  521. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  522. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  523. kfree(buf);
  524. return -EIO;
  525. }
  526. buf[i].addr = addr;
  527. buf[i].data = val;
  528. if (verbose)
  529. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  530. netxen_nic_driver_name,
  531. (u32)netxen_decode_crb_addr(addr), val);
  532. }
  533. for (i = 0; i < n; i++) {
  534. off = netxen_decode_crb_addr(buf[i].addr);
  535. if (off == NETXEN_ADDR_ERROR) {
  536. printk(KERN_ERR"CRB init value out of range %x\n",
  537. buf[i].addr);
  538. continue;
  539. }
  540. off += NETXEN_PCI_CRBSPACE;
  541. /* skipping cold reboot MAGIC */
  542. if (off == NETXEN_CAM_RAM(0x1fc))
  543. continue;
  544. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  545. /* do not reset PCI */
  546. if (off == (ROMUSB_GLB + 0xbc))
  547. continue;
  548. if (off == (ROMUSB_GLB + 0xa8))
  549. continue;
  550. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  551. continue;
  552. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  553. continue;
  554. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  555. continue;
  556. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  557. buf[i].data = 0x1020;
  558. /* skip the function enable register */
  559. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  560. continue;
  561. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  562. continue;
  563. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  564. continue;
  565. }
  566. if (off == NETXEN_ADDR_ERROR) {
  567. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  568. netxen_nic_driver_name, buf[i].addr);
  569. continue;
  570. }
  571. init_delay = 1;
  572. /* After writing this register, HW needs time for CRB */
  573. /* to quiet down (else crb_window returns 0xffffffff) */
  574. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  575. init_delay = 1000;
  576. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  577. /* hold xdma in reset also */
  578. buf[i].data = NETXEN_NIC_XDMA_RESET;
  579. buf[i].data = 0x8000ff;
  580. }
  581. }
  582. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  583. msleep(init_delay);
  584. }
  585. kfree(buf);
  586. /* disable_peg_cache_all */
  587. /* unreset_net_cache */
  588. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  589. adapter->hw_read_wx(adapter,
  590. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  591. netxen_crb_writelit_adapter(adapter,
  592. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  593. }
  594. /* p2dn replyCount */
  595. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  596. /* disable_peg_cache 0 */
  597. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  598. /* disable_peg_cache 1 */
  599. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  600. /* peg_clr_all */
  601. /* peg_clr 0 */
  602. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  603. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  604. /* peg_clr 1 */
  605. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  606. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  607. /* peg_clr 2 */
  608. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  609. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  610. /* peg_clr 3 */
  611. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  612. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  613. return 0;
  614. }
  615. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  616. {
  617. uint64_t addr;
  618. uint32_t hi;
  619. uint32_t lo;
  620. adapter->dummy_dma.addr =
  621. pci_alloc_consistent(adapter->pdev,
  622. NETXEN_HOST_DUMMY_DMA_SIZE,
  623. &adapter->dummy_dma.phys_addr);
  624. if (adapter->dummy_dma.addr == NULL) {
  625. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  626. __func__);
  627. return -ENOMEM;
  628. }
  629. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  630. hi = (addr >> 32) & 0xffffffff;
  631. lo = addr & 0xffffffff;
  632. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  633. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  634. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  635. uint32_t temp = 0;
  636. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  637. }
  638. return 0;
  639. }
  640. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  641. {
  642. int i = 100;
  643. if (!adapter->dummy_dma.addr)
  644. return;
  645. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  646. do {
  647. if (dma_watchdog_shutdown_request(adapter) == 1)
  648. break;
  649. msleep(50);
  650. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  651. break;
  652. } while (--i);
  653. }
  654. if (i) {
  655. pci_free_consistent(adapter->pdev,
  656. NETXEN_HOST_DUMMY_DMA_SIZE,
  657. adapter->dummy_dma.addr,
  658. adapter->dummy_dma.phys_addr);
  659. adapter->dummy_dma.addr = NULL;
  660. } else {
  661. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  662. adapter->netdev->name);
  663. }
  664. }
  665. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  666. {
  667. u32 val = 0;
  668. int retries = 60;
  669. if (!pegtune_val) {
  670. do {
  671. val = adapter->pci_read_normalize(adapter,
  672. CRB_CMDPEG_STATE);
  673. if (val == PHAN_INITIALIZE_COMPLETE ||
  674. val == PHAN_INITIALIZE_ACK)
  675. return 0;
  676. msleep(500);
  677. } while (--retries);
  678. if (!retries) {
  679. pegtune_val = adapter->pci_read_normalize(adapter,
  680. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  681. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  682. "pegtune_val=%x\n", pegtune_val);
  683. return -1;
  684. }
  685. }
  686. return 0;
  687. }
  688. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  689. {
  690. u32 val = 0;
  691. int retries = 2000;
  692. do {
  693. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  694. if (val == PHAN_PEG_RCV_INITIALIZED)
  695. return 0;
  696. msleep(10);
  697. } while (--retries);
  698. if (!retries) {
  699. printk(KERN_ERR "Receive Peg initialization not "
  700. "complete, state: 0x%x.\n", val);
  701. return -EIO;
  702. }
  703. return 0;
  704. }
  705. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  706. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  707. {
  708. struct netxen_rx_buffer *buffer;
  709. struct sk_buff *skb;
  710. buffer = &rds_ring->rx_buf_arr[index];
  711. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  712. PCI_DMA_FROMDEVICE);
  713. skb = buffer->skb;
  714. if (!skb)
  715. goto no_skb;
  716. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  717. adapter->stats.csummed++;
  718. skb->ip_summed = CHECKSUM_UNNECESSARY;
  719. } else
  720. skb->ip_summed = CHECKSUM_NONE;
  721. skb->dev = adapter->netdev;
  722. buffer->skb = NULL;
  723. no_skb:
  724. buffer->state = NETXEN_BUFFER_FREE;
  725. buffer->lro_current_frags = 0;
  726. buffer->lro_expected_frags = 0;
  727. list_add_tail(&buffer->list, &rds_ring->free_list);
  728. return skb;
  729. }
  730. /*
  731. * netxen_process_rcv() send the received packet to the protocol stack.
  732. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  733. * invoke the routine to send more rx buffers to the Phantom...
  734. */
  735. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  736. struct status_desc *desc, struct status_desc *frag_desc)
  737. {
  738. struct net_device *netdev = adapter->netdev;
  739. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  740. int index = netxen_get_sts_refhandle(sts_data);
  741. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  742. struct netxen_rx_buffer *buffer;
  743. struct sk_buff *skb;
  744. u32 length = netxen_get_sts_totallength(sts_data);
  745. u32 desc_ctx;
  746. u16 pkt_offset = 0, cksum;
  747. struct nx_host_rds_ring *rds_ring;
  748. desc_ctx = netxen_get_sts_type(sts_data);
  749. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  750. printk("%s: %s Bad Rcv descriptor ring\n",
  751. netxen_nic_driver_name, netdev->name);
  752. return;
  753. }
  754. rds_ring = &recv_ctx->rds_rings[desc_ctx];
  755. if (unlikely(index > rds_ring->max_rx_desc_count)) {
  756. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  757. index, rds_ring->max_rx_desc_count);
  758. return;
  759. }
  760. buffer = &rds_ring->rx_buf_arr[index];
  761. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  762. buffer->lro_current_frags++;
  763. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  764. buffer->lro_expected_frags =
  765. netxen_get_sts_desc_lro_cnt(desc);
  766. buffer->lro_length = length;
  767. }
  768. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  769. if (buffer->lro_expected_frags != 0) {
  770. printk("LRO: (refhandle:%x) recv frag. "
  771. "wait for last. flags: %x expected:%d "
  772. "have:%d\n", index,
  773. netxen_get_sts_desc_lro_last_frag(desc),
  774. buffer->lro_expected_frags,
  775. buffer->lro_current_frags);
  776. }
  777. return;
  778. }
  779. }
  780. cksum = netxen_get_sts_status(sts_data);
  781. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  782. if (!skb)
  783. return;
  784. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  785. /* True length was only available on the last pkt */
  786. skb_put(skb, buffer->lro_length);
  787. } else {
  788. if (length > rds_ring->skb_size)
  789. skb_put(skb, rds_ring->skb_size);
  790. else
  791. skb_put(skb, length);
  792. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  793. if (pkt_offset)
  794. skb_pull(skb, pkt_offset);
  795. }
  796. skb->protocol = eth_type_trans(skb, netdev);
  797. /*
  798. * rx buffer chaining is disabled, walk and free
  799. * any spurious rx buffer chain.
  800. */
  801. if (frag_desc) {
  802. u16 i, nr_frags = desc->nr_frags;
  803. dev_kfree_skb_any(skb);
  804. for (i = 0; i < nr_frags; i++) {
  805. index = le16_to_cpu(frag_desc->frag_handles[i]);
  806. skb = netxen_process_rxbuf(adapter,
  807. rds_ring, index, cksum);
  808. if (skb)
  809. dev_kfree_skb_any(skb);
  810. }
  811. adapter->stats.rxdropped++;
  812. } else {
  813. netif_receive_skb(skb);
  814. adapter->stats.no_rcv++;
  815. adapter->stats.rxbytes += length;
  816. }
  817. }
  818. /* Process Receive status ring */
  819. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  820. {
  821. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  822. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  823. struct status_desc *desc, *frag_desc;
  824. u32 consumer = recv_ctx->status_rx_consumer;
  825. int count = 0, ring;
  826. u64 sts_data;
  827. u16 opcode;
  828. while (count < max) {
  829. desc = &desc_head[consumer];
  830. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  831. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  832. netxen_get_sts_owner(desc));
  833. break;
  834. }
  835. sts_data = le64_to_cpu(desc->status_desc_data);
  836. opcode = netxen_get_sts_opcode(sts_data);
  837. frag_desc = NULL;
  838. if (opcode == NETXEN_NIC_RXPKT_DESC) {
  839. if (desc->nr_frags) {
  840. consumer = get_next_index(consumer,
  841. adapter->max_rx_desc_count);
  842. frag_desc = &desc_head[consumer];
  843. netxen_set_sts_owner(frag_desc,
  844. STATUS_OWNER_PHANTOM);
  845. }
  846. }
  847. netxen_process_rcv(adapter, ctxid, desc, frag_desc);
  848. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  849. consumer = get_next_index(consumer,
  850. adapter->max_rx_desc_count);
  851. count++;
  852. }
  853. for (ring = 0; ring < adapter->max_rds_rings; ring++)
  854. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  855. /* update the consumer index in phantom */
  856. if (count) {
  857. recv_ctx->status_rx_consumer = consumer;
  858. /* Window = 1 */
  859. adapter->pci_write_normalize(adapter,
  860. recv_ctx->crb_sts_consumer, consumer);
  861. }
  862. return count;
  863. }
  864. /* Process Command status ring */
  865. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  866. {
  867. u32 last_consumer, consumer;
  868. int count = 0, i;
  869. struct netxen_cmd_buffer *buffer;
  870. struct pci_dev *pdev = adapter->pdev;
  871. struct net_device *netdev = adapter->netdev;
  872. struct netxen_skb_frag *frag;
  873. int done = 0;
  874. last_consumer = adapter->last_cmd_consumer;
  875. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  876. while (last_consumer != consumer) {
  877. buffer = &adapter->cmd_buf_arr[last_consumer];
  878. if (buffer->skb) {
  879. frag = &buffer->frag_array[0];
  880. pci_unmap_single(pdev, frag->dma, frag->length,
  881. PCI_DMA_TODEVICE);
  882. frag->dma = 0ULL;
  883. for (i = 1; i < buffer->frag_count; i++) {
  884. frag++; /* Get the next frag */
  885. pci_unmap_page(pdev, frag->dma, frag->length,
  886. PCI_DMA_TODEVICE);
  887. frag->dma = 0ULL;
  888. }
  889. adapter->stats.xmitfinished++;
  890. dev_kfree_skb_any(buffer->skb);
  891. buffer->skb = NULL;
  892. }
  893. last_consumer = get_next_index(last_consumer,
  894. adapter->max_tx_desc_count);
  895. if (++count >= MAX_STATUS_HANDLE)
  896. break;
  897. }
  898. if (count) {
  899. adapter->last_cmd_consumer = last_consumer;
  900. smp_mb();
  901. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  902. netif_tx_lock(netdev);
  903. netif_wake_queue(netdev);
  904. smp_mb();
  905. netif_tx_unlock(netdev);
  906. }
  907. }
  908. /*
  909. * If everything is freed up to consumer then check if the ring is full
  910. * If the ring is full then check if more needs to be freed and
  911. * schedule the call back again.
  912. *
  913. * This happens when there are 2 CPUs. One could be freeing and the
  914. * other filling it. If the ring is full when we get out of here and
  915. * the card has already interrupted the host then the host can miss the
  916. * interrupt.
  917. *
  918. * There is still a possible race condition and the host could miss an
  919. * interrupt. The card has to take care of this.
  920. */
  921. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  922. done = (last_consumer == consumer);
  923. return (done);
  924. }
  925. /*
  926. * netxen_post_rx_buffers puts buffer in the Phantom memory
  927. */
  928. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  929. {
  930. struct pci_dev *pdev = adapter->pdev;
  931. struct sk_buff *skb;
  932. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  933. struct nx_host_rds_ring *rds_ring = NULL;
  934. uint producer;
  935. struct rcv_desc *pdesc;
  936. struct netxen_rx_buffer *buffer;
  937. int count = 0;
  938. netxen_ctx_msg msg = 0;
  939. dma_addr_t dma;
  940. struct list_head *head;
  941. rds_ring = &recv_ctx->rds_rings[ringid];
  942. producer = rds_ring->producer;
  943. head = &rds_ring->free_list;
  944. /* We can start writing rx descriptors into the phantom memory. */
  945. while (!list_empty(head)) {
  946. skb = dev_alloc_skb(rds_ring->skb_size);
  947. if (unlikely(!skb)) {
  948. break;
  949. }
  950. if (!adapter->ahw.cut_through)
  951. skb_reserve(skb, 2);
  952. dma = pci_map_single(pdev, skb->data,
  953. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  954. if (pci_dma_mapping_error(pdev, dma)) {
  955. dev_kfree_skb_any(skb);
  956. break;
  957. }
  958. count++;
  959. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  960. list_del(&buffer->list);
  961. buffer->skb = skb;
  962. buffer->state = NETXEN_BUFFER_BUSY;
  963. buffer->dma = dma;
  964. /* make a rcv descriptor */
  965. pdesc = &rds_ring->desc_head[producer];
  966. pdesc->addr_buffer = cpu_to_le64(dma);
  967. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  968. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  969. producer = get_next_index(producer, rds_ring->max_rx_desc_count);
  970. }
  971. /* if we did allocate buffers, then write the count to Phantom */
  972. if (count) {
  973. rds_ring->producer = producer;
  974. /* Window = 1 */
  975. adapter->pci_write_normalize(adapter,
  976. rds_ring->crb_rcv_producer,
  977. (producer-1) & (rds_ring->max_rx_desc_count-1));
  978. if (adapter->fw_major < 4) {
  979. /*
  980. * Write a doorbell msg to tell phanmon of change in
  981. * receive ring producer
  982. * Only for firmware version < 4.0.0
  983. */
  984. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  985. netxen_set_msg_privid(msg);
  986. netxen_set_msg_count(msg,
  987. ((producer -
  988. 1) & (rds_ring->
  989. max_rx_desc_count - 1)));
  990. netxen_set_msg_ctxid(msg, adapter->portnum);
  991. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  992. writel(msg,
  993. DB_NORMALIZE(adapter,
  994. NETXEN_RCV_PRODUCER_OFFSET));
  995. }
  996. }
  997. }
  998. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  999. uint32_t ctx, uint32_t ringid)
  1000. {
  1001. struct pci_dev *pdev = adapter->pdev;
  1002. struct sk_buff *skb;
  1003. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1004. struct nx_host_rds_ring *rds_ring = NULL;
  1005. u32 producer;
  1006. struct rcv_desc *pdesc;
  1007. struct netxen_rx_buffer *buffer;
  1008. int count = 0;
  1009. struct list_head *head;
  1010. dma_addr_t dma;
  1011. rds_ring = &recv_ctx->rds_rings[ringid];
  1012. producer = rds_ring->producer;
  1013. head = &rds_ring->free_list;
  1014. /* We can start writing rx descriptors into the phantom memory. */
  1015. while (!list_empty(head)) {
  1016. skb = dev_alloc_skb(rds_ring->skb_size);
  1017. if (unlikely(!skb)) {
  1018. break;
  1019. }
  1020. if (!adapter->ahw.cut_through)
  1021. skb_reserve(skb, 2);
  1022. dma = pci_map_single(pdev, skb->data,
  1023. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1024. if (pci_dma_mapping_error(pdev, dma)) {
  1025. dev_kfree_skb_any(skb);
  1026. break;
  1027. }
  1028. count++;
  1029. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1030. list_del(&buffer->list);
  1031. buffer->skb = skb;
  1032. buffer->state = NETXEN_BUFFER_BUSY;
  1033. buffer->dma = dma;
  1034. /* make a rcv descriptor */
  1035. pdesc = &rds_ring->desc_head[producer];
  1036. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1037. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1038. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1039. producer = get_next_index(producer, rds_ring->max_rx_desc_count);
  1040. }
  1041. /* if we did allocate buffers, then write the count to Phantom */
  1042. if (count) {
  1043. rds_ring->producer = producer;
  1044. /* Window = 1 */
  1045. adapter->pci_write_normalize(adapter,
  1046. rds_ring->crb_rcv_producer,
  1047. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1048. wmb();
  1049. }
  1050. }
  1051. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1052. {
  1053. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1054. return;
  1055. }