yam.c 31 KB

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  1. /*****************************************************************************/
  2. /*
  3. * yam.c -- YAM radio modem driver.
  4. *
  5. * Copyright (C) 1998 Frederic Rible F1OAT (frible@teaser.fr)
  6. * Adapted from baycom.c driver written by Thomas Sailer (sailer@ife.ee.ethz.ch)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * Please note that the GPL allows you to use the driver, NOT the radio.
  23. * In order to use the radio, you need a license from the communications
  24. * authority of your country.
  25. *
  26. *
  27. * History:
  28. * 0.0 F1OAT 06.06.98 Begin of work with baycom.c source code V 0.3
  29. * 0.1 F1OAT 07.06.98 Add timer polling routine for channel arbitration
  30. * 0.2 F6FBB 08.06.98 Added delay after FPGA programming
  31. * 0.3 F6FBB 29.07.98 Delayed PTT implementation for dupmode=2
  32. * 0.4 F6FBB 30.07.98 Added TxTail, Slottime and Persistance
  33. * 0.5 F6FBB 01.08.98 Shared IRQs, /proc/net and network statistics
  34. * 0.6 F6FBB 25.08.98 Added 1200Bds format
  35. * 0.7 F6FBB 12.09.98 Added to the kernel configuration
  36. * 0.8 F6FBB 14.10.98 Fixed slottime/persistence timing bug
  37. * OK1ZIA 2.09.01 Fixed "kfree_skb on hard IRQ"
  38. * using dev_kfree_skb_any(). (important in 2.4 kernel)
  39. *
  40. */
  41. /*****************************************************************************/
  42. #include <linux/module.h>
  43. #include <linux/types.h>
  44. #include <linux/net.h>
  45. #include <linux/in.h>
  46. #include <linux/if.h>
  47. #include <linux/slab.h>
  48. #include <linux/errno.h>
  49. #include <linux/bitops.h>
  50. #include <linux/random.h>
  51. #include <asm/io.h>
  52. #include <asm/system.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/ioport.h>
  55. #include <linux/netdevice.h>
  56. #include <linux/if_arp.h>
  57. #include <linux/etherdevice.h>
  58. #include <linux/skbuff.h>
  59. #include <net/ax25.h>
  60. #include <linux/kernel.h>
  61. #include <linux/proc_fs.h>
  62. #include <linux/seq_file.h>
  63. #include <net/net_namespace.h>
  64. #include <asm/uaccess.h>
  65. #include <linux/init.h>
  66. #include <linux/yam.h>
  67. #include "yam9600.h"
  68. #include "yam1200.h"
  69. /* --------------------------------------------------------------------- */
  70. static const char yam_drvname[] = "yam";
  71. static const char yam_drvinfo[] __initdata = KERN_INFO \
  72. "YAM driver version 0.8 by F1OAT/F6FBB\n";
  73. /* --------------------------------------------------------------------- */
  74. #define YAM_9600 1
  75. #define YAM_1200 2
  76. #define NR_PORTS 4
  77. #define YAM_MAGIC 0xF10A7654
  78. /* Transmitter states */
  79. #define TX_OFF 0
  80. #define TX_HEAD 1
  81. #define TX_DATA 2
  82. #define TX_CRC1 3
  83. #define TX_CRC2 4
  84. #define TX_TAIL 5
  85. #define YAM_MAX_FRAME 1024
  86. #define DEFAULT_BITRATE 9600 /* bps */
  87. #define DEFAULT_HOLDD 10 /* sec */
  88. #define DEFAULT_TXD 300 /* ms */
  89. #define DEFAULT_TXTAIL 10 /* ms */
  90. #define DEFAULT_SLOT 100 /* ms */
  91. #define DEFAULT_PERS 64 /* 0->255 */
  92. struct yam_port {
  93. int magic;
  94. int bitrate;
  95. int baudrate;
  96. int iobase;
  97. int irq;
  98. int dupmode;
  99. struct net_device *dev;
  100. int nb_rxint;
  101. int nb_mdint;
  102. /* Parameters section */
  103. int txd; /* tx delay */
  104. int holdd; /* duplex ptt delay */
  105. int txtail; /* txtail delay */
  106. int slot; /* slottime */
  107. int pers; /* persistence */
  108. /* Tx section */
  109. int tx_state;
  110. int tx_count;
  111. int slotcnt;
  112. unsigned char tx_buf[YAM_MAX_FRAME];
  113. int tx_len;
  114. int tx_crcl, tx_crch;
  115. struct sk_buff_head send_queue; /* Packets awaiting transmission */
  116. /* Rx section */
  117. int dcd;
  118. unsigned char rx_buf[YAM_MAX_FRAME];
  119. int rx_len;
  120. int rx_crcl, rx_crch;
  121. };
  122. struct yam_mcs {
  123. unsigned char bits[YAM_FPGA_SIZE];
  124. int bitrate;
  125. struct yam_mcs *next;
  126. };
  127. static struct net_device *yam_devs[NR_PORTS];
  128. static struct yam_mcs *yam_data;
  129. static DEFINE_TIMER(yam_timer, NULL, 0, 0);
  130. /* --------------------------------------------------------------------- */
  131. #define RBR(iobase) (iobase+0)
  132. #define THR(iobase) (iobase+0)
  133. #define IER(iobase) (iobase+1)
  134. #define IIR(iobase) (iobase+2)
  135. #define FCR(iobase) (iobase+2)
  136. #define LCR(iobase) (iobase+3)
  137. #define MCR(iobase) (iobase+4)
  138. #define LSR(iobase) (iobase+5)
  139. #define MSR(iobase) (iobase+6)
  140. #define SCR(iobase) (iobase+7)
  141. #define DLL(iobase) (iobase+0)
  142. #define DLM(iobase) (iobase+1)
  143. #define YAM_EXTENT 8
  144. /* Interrupt Identification Register Bit Masks */
  145. #define IIR_NOPEND 1
  146. #define IIR_MSR 0
  147. #define IIR_TX 2
  148. #define IIR_RX 4
  149. #define IIR_LSR 6
  150. #define IIR_TIMEOUT 12 /* Fifo mode only */
  151. #define IIR_MASK 0x0F
  152. /* Interrupt Enable Register Bit Masks */
  153. #define IER_RX 1 /* enable rx interrupt */
  154. #define IER_TX 2 /* enable tx interrupt */
  155. #define IER_LSR 4 /* enable line status interrupts */
  156. #define IER_MSR 8 /* enable modem status interrupts */
  157. /* Modem Control Register Bit Masks */
  158. #define MCR_DTR 0x01 /* DTR output */
  159. #define MCR_RTS 0x02 /* RTS output */
  160. #define MCR_OUT1 0x04 /* OUT1 output (not accessible in RS232) */
  161. #define MCR_OUT2 0x08 /* Master Interrupt enable (must be set on PCs) */
  162. #define MCR_LOOP 0x10 /* Loopback enable */
  163. /* Modem Status Register Bit Masks */
  164. #define MSR_DCTS 0x01 /* Delta CTS input */
  165. #define MSR_DDSR 0x02 /* Delta DSR */
  166. #define MSR_DRIN 0x04 /* Delta RI */
  167. #define MSR_DDCD 0x08 /* Delta DCD */
  168. #define MSR_CTS 0x10 /* CTS input */
  169. #define MSR_DSR 0x20 /* DSR input */
  170. #define MSR_RING 0x40 /* RI input */
  171. #define MSR_DCD 0x80 /* DCD input */
  172. /* line status register bit mask */
  173. #define LSR_RXC 0x01
  174. #define LSR_OE 0x02
  175. #define LSR_PE 0x04
  176. #define LSR_FE 0x08
  177. #define LSR_BREAK 0x10
  178. #define LSR_THRE 0x20
  179. #define LSR_TSRE 0x40
  180. /* Line Control Register Bit Masks */
  181. #define LCR_DLAB 0x80
  182. #define LCR_BREAK 0x40
  183. #define LCR_PZERO 0x28
  184. #define LCR_PEVEN 0x18
  185. #define LCR_PODD 0x08
  186. #define LCR_STOP1 0x00
  187. #define LCR_STOP2 0x04
  188. #define LCR_BIT5 0x00
  189. #define LCR_BIT6 0x02
  190. #define LCR_BIT7 0x01
  191. #define LCR_BIT8 0x03
  192. /* YAM Modem <-> UART Port mapping */
  193. #define TX_RDY MSR_DCTS /* transmitter ready to send */
  194. #define RX_DCD MSR_DCD /* carrier detect */
  195. #define RX_FLAG MSR_RING /* hdlc flag received */
  196. #define FPGA_DONE MSR_DSR /* FPGA is configured */
  197. #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */
  198. #define PTT_OFF (MCR_DTR|MCR_OUT2) /* release PTT */
  199. #define ENABLE_RXINT IER_RX /* enable uart rx interrupt during rx */
  200. #define ENABLE_TXINT IER_MSR /* enable uart ms interrupt during tx */
  201. #define ENABLE_RTXINT (IER_RX|IER_MSR) /* full duplex operations */
  202. /*************************************************************************
  203. * CRC Tables
  204. ************************************************************************/
  205. static const unsigned char chktabl[256] =
  206. {0x00, 0x89, 0x12, 0x9b, 0x24, 0xad, 0x36, 0xbf, 0x48, 0xc1, 0x5a, 0xd3, 0x6c, 0xe5, 0x7e,
  207. 0xf7, 0x81, 0x08, 0x93, 0x1a, 0xa5, 0x2c, 0xb7, 0x3e, 0xc9, 0x40, 0xdb, 0x52, 0xed, 0x64,
  208. 0xff, 0x76, 0x02, 0x8b, 0x10, 0x99, 0x26, 0xaf, 0x34, 0xbd, 0x4a, 0xc3, 0x58, 0xd1, 0x6e,
  209. 0xe7, 0x7c, 0xf5, 0x83, 0x0a, 0x91, 0x18, 0xa7, 0x2e, 0xb5, 0x3c, 0xcb, 0x42, 0xd9, 0x50,
  210. 0xef, 0x66, 0xfd, 0x74, 0x04, 0x8d, 0x16, 0x9f, 0x20, 0xa9, 0x32, 0xbb, 0x4c, 0xc5, 0x5e,
  211. 0xd7, 0x68, 0xe1, 0x7a, 0xf3, 0x85, 0x0c, 0x97, 0x1e, 0xa1, 0x28, 0xb3, 0x3a, 0xcd, 0x44,
  212. 0xdf, 0x56, 0xe9, 0x60, 0xfb, 0x72, 0x06, 0x8f, 0x14, 0x9d, 0x22, 0xab, 0x30, 0xb9, 0x4e,
  213. 0xc7, 0x5c, 0xd5, 0x6a, 0xe3, 0x78, 0xf1, 0x87, 0x0e, 0x95, 0x1c, 0xa3, 0x2a, 0xb1, 0x38,
  214. 0xcf, 0x46, 0xdd, 0x54, 0xeb, 0x62, 0xf9, 0x70, 0x08, 0x81, 0x1a, 0x93, 0x2c, 0xa5, 0x3e,
  215. 0xb7, 0x40, 0xc9, 0x52, 0xdb, 0x64, 0xed, 0x76, 0xff, 0x89, 0x00, 0x9b, 0x12, 0xad, 0x24,
  216. 0xbf, 0x36, 0xc1, 0x48, 0xd3, 0x5a, 0xe5, 0x6c, 0xf7, 0x7e, 0x0a, 0x83, 0x18, 0x91, 0x2e,
  217. 0xa7, 0x3c, 0xb5, 0x42, 0xcb, 0x50, 0xd9, 0x66, 0xef, 0x74, 0xfd, 0x8b, 0x02, 0x99, 0x10,
  218. 0xaf, 0x26, 0xbd, 0x34, 0xc3, 0x4a, 0xd1, 0x58, 0xe7, 0x6e, 0xf5, 0x7c, 0x0c, 0x85, 0x1e,
  219. 0x97, 0x28, 0xa1, 0x3a, 0xb3, 0x44, 0xcd, 0x56, 0xdf, 0x60, 0xe9, 0x72, 0xfb, 0x8d, 0x04,
  220. 0x9f, 0x16, 0xa9, 0x20, 0xbb, 0x32, 0xc5, 0x4c, 0xd7, 0x5e, 0xe1, 0x68, 0xf3, 0x7a, 0x0e,
  221. 0x87, 0x1c, 0x95, 0x2a, 0xa3, 0x38, 0xb1, 0x46, 0xcf, 0x54, 0xdd, 0x62, 0xeb, 0x70, 0xf9,
  222. 0x8f, 0x06, 0x9d, 0x14, 0xab, 0x22, 0xb9, 0x30, 0xc7, 0x4e, 0xd5, 0x5c, 0xe3, 0x6a, 0xf1,
  223. 0x78};
  224. static const unsigned char chktabh[256] =
  225. {0x00, 0x11, 0x23, 0x32, 0x46, 0x57, 0x65, 0x74, 0x8c, 0x9d, 0xaf, 0xbe, 0xca, 0xdb, 0xe9,
  226. 0xf8, 0x10, 0x01, 0x33, 0x22, 0x56, 0x47, 0x75, 0x64, 0x9c, 0x8d, 0xbf, 0xae, 0xda, 0xcb,
  227. 0xf9, 0xe8, 0x21, 0x30, 0x02, 0x13, 0x67, 0x76, 0x44, 0x55, 0xad, 0xbc, 0x8e, 0x9f, 0xeb,
  228. 0xfa, 0xc8, 0xd9, 0x31, 0x20, 0x12, 0x03, 0x77, 0x66, 0x54, 0x45, 0xbd, 0xac, 0x9e, 0x8f,
  229. 0xfb, 0xea, 0xd8, 0xc9, 0x42, 0x53, 0x61, 0x70, 0x04, 0x15, 0x27, 0x36, 0xce, 0xdf, 0xed,
  230. 0xfc, 0x88, 0x99, 0xab, 0xba, 0x52, 0x43, 0x71, 0x60, 0x14, 0x05, 0x37, 0x26, 0xde, 0xcf,
  231. 0xfd, 0xec, 0x98, 0x89, 0xbb, 0xaa, 0x63, 0x72, 0x40, 0x51, 0x25, 0x34, 0x06, 0x17, 0xef,
  232. 0xfe, 0xcc, 0xdd, 0xa9, 0xb8, 0x8a, 0x9b, 0x73, 0x62, 0x50, 0x41, 0x35, 0x24, 0x16, 0x07,
  233. 0xff, 0xee, 0xdc, 0xcd, 0xb9, 0xa8, 0x9a, 0x8b, 0x84, 0x95, 0xa7, 0xb6, 0xc2, 0xd3, 0xe1,
  234. 0xf0, 0x08, 0x19, 0x2b, 0x3a, 0x4e, 0x5f, 0x6d, 0x7c, 0x94, 0x85, 0xb7, 0xa6, 0xd2, 0xc3,
  235. 0xf1, 0xe0, 0x18, 0x09, 0x3b, 0x2a, 0x5e, 0x4f, 0x7d, 0x6c, 0xa5, 0xb4, 0x86, 0x97, 0xe3,
  236. 0xf2, 0xc0, 0xd1, 0x29, 0x38, 0x0a, 0x1b, 0x6f, 0x7e, 0x4c, 0x5d, 0xb5, 0xa4, 0x96, 0x87,
  237. 0xf3, 0xe2, 0xd0, 0xc1, 0x39, 0x28, 0x1a, 0x0b, 0x7f, 0x6e, 0x5c, 0x4d, 0xc6, 0xd7, 0xe5,
  238. 0xf4, 0x80, 0x91, 0xa3, 0xb2, 0x4a, 0x5b, 0x69, 0x78, 0x0c, 0x1d, 0x2f, 0x3e, 0xd6, 0xc7,
  239. 0xf5, 0xe4, 0x90, 0x81, 0xb3, 0xa2, 0x5a, 0x4b, 0x79, 0x68, 0x1c, 0x0d, 0x3f, 0x2e, 0xe7,
  240. 0xf6, 0xc4, 0xd5, 0xa1, 0xb0, 0x82, 0x93, 0x6b, 0x7a, 0x48, 0x59, 0x2d, 0x3c, 0x0e, 0x1f,
  241. 0xf7, 0xe6, 0xd4, 0xc5, 0xb1, 0xa0, 0x92, 0x83, 0x7b, 0x6a, 0x58, 0x49, 0x3d, 0x2c, 0x1e,
  242. 0x0f};
  243. /*************************************************************************
  244. * FPGA functions
  245. ************************************************************************/
  246. static void delay(int ms)
  247. {
  248. unsigned long timeout = jiffies + ((ms * HZ) / 1000);
  249. while (time_before(jiffies, timeout))
  250. cpu_relax();
  251. }
  252. /*
  253. * reset FPGA
  254. */
  255. static void fpga_reset(int iobase)
  256. {
  257. outb(0, IER(iobase));
  258. outb(LCR_DLAB | LCR_BIT5, LCR(iobase));
  259. outb(1, DLL(iobase));
  260. outb(0, DLM(iobase));
  261. outb(LCR_BIT5, LCR(iobase));
  262. inb(LSR(iobase));
  263. inb(MSR(iobase));
  264. /* turn off FPGA supply voltage */
  265. outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));
  266. delay(100);
  267. /* turn on FPGA supply voltage again */
  268. outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));
  269. delay(100);
  270. }
  271. /*
  272. * send one byte to FPGA
  273. */
  274. static int fpga_write(int iobase, unsigned char wrd)
  275. {
  276. unsigned char bit;
  277. int k;
  278. unsigned long timeout = jiffies + HZ / 10;
  279. for (k = 0; k < 8; k++) {
  280. bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR;
  281. outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));
  282. wrd <<= 1;
  283. outb(0xfc, THR(iobase));
  284. while ((inb(LSR(iobase)) & LSR_TSRE) == 0)
  285. if (time_after(jiffies, timeout))
  286. return -1;
  287. }
  288. return 0;
  289. }
  290. static unsigned char *add_mcs(unsigned char *bits, int bitrate)
  291. {
  292. struct yam_mcs *p;
  293. /* If it already exists, replace the bit data */
  294. p = yam_data;
  295. while (p) {
  296. if (p->bitrate == bitrate) {
  297. memcpy(p->bits, bits, YAM_FPGA_SIZE);
  298. return p->bits;
  299. }
  300. p = p->next;
  301. }
  302. /* Allocate a new mcs */
  303. if ((p = kmalloc(sizeof(struct yam_mcs), GFP_KERNEL)) == NULL) {
  304. printk(KERN_WARNING "YAM: no memory to allocate mcs\n");
  305. return NULL;
  306. }
  307. memcpy(p->bits, bits, YAM_FPGA_SIZE);
  308. p->bitrate = bitrate;
  309. p->next = yam_data;
  310. yam_data = p;
  311. return p->bits;
  312. }
  313. static unsigned char *get_mcs(int bitrate)
  314. {
  315. struct yam_mcs *p;
  316. p = yam_data;
  317. while (p) {
  318. if (p->bitrate == bitrate)
  319. return p->bits;
  320. p = p->next;
  321. }
  322. /* Load predefined mcs data */
  323. switch (bitrate) {
  324. case 1200:
  325. return add_mcs(bits_1200, bitrate);
  326. default:
  327. return add_mcs(bits_9600, bitrate);
  328. }
  329. }
  330. /*
  331. * download bitstream to FPGA
  332. * data is contained in bits[] array in yam1200.h resp. yam9600.h
  333. */
  334. static int fpga_download(int iobase, int bitrate)
  335. {
  336. int i, rc;
  337. unsigned char *pbits;
  338. pbits = get_mcs(bitrate);
  339. if (pbits == NULL)
  340. return -1;
  341. fpga_reset(iobase);
  342. for (i = 0; i < YAM_FPGA_SIZE; i++) {
  343. if (fpga_write(iobase, pbits[i])) {
  344. printk(KERN_ERR "yam: error in write cycle\n");
  345. return -1; /* write... */
  346. }
  347. }
  348. fpga_write(iobase, 0xFF);
  349. rc = inb(MSR(iobase)); /* check DONE signal */
  350. /* Needed for some hardwares */
  351. delay(50);
  352. return (rc & MSR_DSR) ? 0 : -1;
  353. }
  354. /************************************************************************
  355. * Serial port init
  356. ************************************************************************/
  357. static void yam_set_uart(struct net_device *dev)
  358. {
  359. struct yam_port *yp = netdev_priv(dev);
  360. int divisor = 115200 / yp->baudrate;
  361. outb(0, IER(dev->base_addr));
  362. outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));
  363. outb(divisor, DLL(dev->base_addr));
  364. outb(0, DLM(dev->base_addr));
  365. outb(LCR_BIT8, LCR(dev->base_addr));
  366. outb(PTT_OFF, MCR(dev->base_addr));
  367. outb(0x00, FCR(dev->base_addr));
  368. /* Flush pending irq */
  369. inb(RBR(dev->base_addr));
  370. inb(MSR(dev->base_addr));
  371. /* Enable rx irq */
  372. outb(ENABLE_RTXINT, IER(dev->base_addr));
  373. }
  374. /* --------------------------------------------------------------------- */
  375. enum uart {
  376. c_uart_unknown, c_uart_8250,
  377. c_uart_16450, c_uart_16550, c_uart_16550A
  378. };
  379. static const char *uart_str[] =
  380. {"unknown", "8250", "16450", "16550", "16550A"};
  381. static enum uart yam_check_uart(unsigned int iobase)
  382. {
  383. unsigned char b1, b2, b3;
  384. enum uart u;
  385. enum uart uart_tab[] =
  386. {c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A};
  387. b1 = inb(MCR(iobase));
  388. outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
  389. b2 = inb(MSR(iobase));
  390. outb(0x1a, MCR(iobase));
  391. b3 = inb(MSR(iobase)) & 0xf0;
  392. outb(b1, MCR(iobase)); /* restore old values */
  393. outb(b2, MSR(iobase));
  394. if (b3 != 0x90)
  395. return c_uart_unknown;
  396. inb(RBR(iobase));
  397. inb(RBR(iobase));
  398. outb(0x01, FCR(iobase)); /* enable FIFOs */
  399. u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
  400. if (u == c_uart_16450) {
  401. outb(0x5a, SCR(iobase));
  402. b1 = inb(SCR(iobase));
  403. outb(0xa5, SCR(iobase));
  404. b2 = inb(SCR(iobase));
  405. if ((b1 != 0x5a) || (b2 != 0xa5))
  406. u = c_uart_8250;
  407. }
  408. return u;
  409. }
  410. /******************************************************************************
  411. * Rx Section
  412. ******************************************************************************/
  413. static inline void yam_rx_flag(struct net_device *dev, struct yam_port *yp)
  414. {
  415. if (yp->dcd && yp->rx_len >= 3 && yp->rx_len < YAM_MAX_FRAME) {
  416. int pkt_len = yp->rx_len - 2 + 1; /* -CRC + kiss */
  417. struct sk_buff *skb;
  418. if ((yp->rx_crch & yp->rx_crcl) != 0xFF) {
  419. /* Bad crc */
  420. } else {
  421. if (!(skb = dev_alloc_skb(pkt_len))) {
  422. printk(KERN_WARNING "%s: memory squeeze, dropping packet\n", dev->name);
  423. ++dev->stats.rx_dropped;
  424. } else {
  425. unsigned char *cp;
  426. cp = skb_put(skb, pkt_len);
  427. *cp++ = 0; /* KISS kludge */
  428. memcpy(cp, yp->rx_buf, pkt_len - 1);
  429. skb->protocol = ax25_type_trans(skb, dev);
  430. netif_rx(skb);
  431. ++dev->stats.rx_packets;
  432. }
  433. }
  434. }
  435. yp->rx_len = 0;
  436. yp->rx_crcl = 0x21;
  437. yp->rx_crch = 0xf3;
  438. }
  439. static inline void yam_rx_byte(struct net_device *dev, struct yam_port *yp, unsigned char rxb)
  440. {
  441. if (yp->rx_len < YAM_MAX_FRAME) {
  442. unsigned char c = yp->rx_crcl;
  443. yp->rx_crcl = (chktabl[c] ^ yp->rx_crch);
  444. yp->rx_crch = (chktabh[c] ^ rxb);
  445. yp->rx_buf[yp->rx_len++] = rxb;
  446. }
  447. }
  448. /********************************************************************************
  449. * TX Section
  450. ********************************************************************************/
  451. static void ptt_on(struct net_device *dev)
  452. {
  453. outb(PTT_ON, MCR(dev->base_addr));
  454. }
  455. static void ptt_off(struct net_device *dev)
  456. {
  457. outb(PTT_OFF, MCR(dev->base_addr));
  458. }
  459. static int yam_send_packet(struct sk_buff *skb, struct net_device *dev)
  460. {
  461. struct yam_port *yp = netdev_priv(dev);
  462. skb_queue_tail(&yp->send_queue, skb);
  463. dev->trans_start = jiffies;
  464. return 0;
  465. }
  466. static void yam_start_tx(struct net_device *dev, struct yam_port *yp)
  467. {
  468. if ((yp->tx_state == TX_TAIL) || (yp->txd == 0))
  469. yp->tx_count = 1;
  470. else
  471. yp->tx_count = (yp->bitrate * yp->txd) / 8000;
  472. yp->tx_state = TX_HEAD;
  473. ptt_on(dev);
  474. }
  475. static void yam_arbitrate(struct net_device *dev)
  476. {
  477. struct yam_port *yp = netdev_priv(dev);
  478. if (yp->magic != YAM_MAGIC || yp->tx_state != TX_OFF ||
  479. skb_queue_empty(&yp->send_queue))
  480. return;
  481. /* tx_state is TX_OFF and there is data to send */
  482. if (yp->dupmode) {
  483. /* Full duplex mode, don't wait */
  484. yam_start_tx(dev, yp);
  485. return;
  486. }
  487. if (yp->dcd) {
  488. /* DCD on, wait slotime ... */
  489. yp->slotcnt = yp->slot / 10;
  490. return;
  491. }
  492. /* Is slottime passed ? */
  493. if ((--yp->slotcnt) > 0)
  494. return;
  495. yp->slotcnt = yp->slot / 10;
  496. /* is random > persist ? */
  497. if ((random32() % 256) > yp->pers)
  498. return;
  499. yam_start_tx(dev, yp);
  500. }
  501. static void yam_dotimer(unsigned long dummy)
  502. {
  503. int i;
  504. for (i = 0; i < NR_PORTS; i++) {
  505. struct net_device *dev = yam_devs[i];
  506. if (dev && netif_running(dev))
  507. yam_arbitrate(dev);
  508. }
  509. yam_timer.expires = jiffies + HZ / 100;
  510. add_timer(&yam_timer);
  511. }
  512. static void yam_tx_byte(struct net_device *dev, struct yam_port *yp)
  513. {
  514. struct sk_buff *skb;
  515. unsigned char b, temp;
  516. switch (yp->tx_state) {
  517. case TX_OFF:
  518. break;
  519. case TX_HEAD:
  520. if (--yp->tx_count <= 0) {
  521. if (!(skb = skb_dequeue(&yp->send_queue))) {
  522. ptt_off(dev);
  523. yp->tx_state = TX_OFF;
  524. break;
  525. }
  526. yp->tx_state = TX_DATA;
  527. if (skb->data[0] != 0) {
  528. /* do_kiss_params(s, skb->data, skb->len); */
  529. dev_kfree_skb_any(skb);
  530. break;
  531. }
  532. yp->tx_len = skb->len - 1; /* strip KISS byte */
  533. if (yp->tx_len >= YAM_MAX_FRAME || yp->tx_len < 2) {
  534. dev_kfree_skb_any(skb);
  535. break;
  536. }
  537. skb_copy_from_linear_data_offset(skb, 1,
  538. yp->tx_buf,
  539. yp->tx_len);
  540. dev_kfree_skb_any(skb);
  541. yp->tx_count = 0;
  542. yp->tx_crcl = 0x21;
  543. yp->tx_crch = 0xf3;
  544. yp->tx_state = TX_DATA;
  545. }
  546. break;
  547. case TX_DATA:
  548. b = yp->tx_buf[yp->tx_count++];
  549. outb(b, THR(dev->base_addr));
  550. temp = yp->tx_crcl;
  551. yp->tx_crcl = chktabl[temp] ^ yp->tx_crch;
  552. yp->tx_crch = chktabh[temp] ^ b;
  553. if (yp->tx_count >= yp->tx_len) {
  554. yp->tx_state = TX_CRC1;
  555. }
  556. break;
  557. case TX_CRC1:
  558. yp->tx_crch = chktabl[yp->tx_crcl] ^ yp->tx_crch;
  559. yp->tx_crcl = chktabh[yp->tx_crcl] ^ chktabl[yp->tx_crch] ^ 0xff;
  560. outb(yp->tx_crcl, THR(dev->base_addr));
  561. yp->tx_state = TX_CRC2;
  562. break;
  563. case TX_CRC2:
  564. outb(chktabh[yp->tx_crch] ^ 0xFF, THR(dev->base_addr));
  565. if (skb_queue_empty(&yp->send_queue)) {
  566. yp->tx_count = (yp->bitrate * yp->txtail) / 8000;
  567. if (yp->dupmode == 2)
  568. yp->tx_count += (yp->bitrate * yp->holdd) / 8;
  569. if (yp->tx_count == 0)
  570. yp->tx_count = 1;
  571. yp->tx_state = TX_TAIL;
  572. } else {
  573. yp->tx_count = 1;
  574. yp->tx_state = TX_HEAD;
  575. }
  576. ++dev->stats.tx_packets;
  577. break;
  578. case TX_TAIL:
  579. if (--yp->tx_count <= 0) {
  580. yp->tx_state = TX_OFF;
  581. ptt_off(dev);
  582. }
  583. break;
  584. }
  585. }
  586. /***********************************************************************************
  587. * ISR routine
  588. ************************************************************************************/
  589. static irqreturn_t yam_interrupt(int irq, void *dev_id)
  590. {
  591. struct net_device *dev;
  592. struct yam_port *yp;
  593. unsigned char iir;
  594. int counter = 100;
  595. int i;
  596. int handled = 0;
  597. for (i = 0; i < NR_PORTS; i++) {
  598. dev = yam_devs[i];
  599. yp = netdev_priv(dev);
  600. if (!netif_running(dev))
  601. continue;
  602. while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) {
  603. unsigned char msr = inb(MSR(dev->base_addr));
  604. unsigned char lsr = inb(LSR(dev->base_addr));
  605. unsigned char rxb;
  606. handled = 1;
  607. if (lsr & LSR_OE)
  608. ++dev->stats.rx_fifo_errors;
  609. yp->dcd = (msr & RX_DCD) ? 1 : 0;
  610. if (--counter <= 0) {
  611. printk(KERN_ERR "%s: too many irq iir=%d\n",
  612. dev->name, iir);
  613. goto out;
  614. }
  615. if (msr & TX_RDY) {
  616. ++yp->nb_mdint;
  617. yam_tx_byte(dev, yp);
  618. }
  619. if (lsr & LSR_RXC) {
  620. ++yp->nb_rxint;
  621. rxb = inb(RBR(dev->base_addr));
  622. if (msr & RX_FLAG)
  623. yam_rx_flag(dev, yp);
  624. else
  625. yam_rx_byte(dev, yp, rxb);
  626. }
  627. }
  628. }
  629. out:
  630. return IRQ_RETVAL(handled);
  631. }
  632. #ifdef CONFIG_PROC_FS
  633. static void *yam_seq_start(struct seq_file *seq, loff_t *pos)
  634. {
  635. return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
  636. }
  637. static void *yam_seq_next(struct seq_file *seq, void *v, loff_t *pos)
  638. {
  639. ++*pos;
  640. return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
  641. }
  642. static void yam_seq_stop(struct seq_file *seq, void *v)
  643. {
  644. }
  645. static int yam_seq_show(struct seq_file *seq, void *v)
  646. {
  647. struct net_device *dev = v;
  648. const struct yam_port *yp = netdev_priv(dev);
  649. seq_printf(seq, "Device %s\n", dev->name);
  650. seq_printf(seq, " Up %d\n", netif_running(dev));
  651. seq_printf(seq, " Speed %u\n", yp->bitrate);
  652. seq_printf(seq, " IoBase 0x%x\n", yp->iobase);
  653. seq_printf(seq, " BaudRate %u\n", yp->baudrate);
  654. seq_printf(seq, " IRQ %u\n", yp->irq);
  655. seq_printf(seq, " TxState %u\n", yp->tx_state);
  656. seq_printf(seq, " Duplex %u\n", yp->dupmode);
  657. seq_printf(seq, " HoldDly %u\n", yp->holdd);
  658. seq_printf(seq, " TxDelay %u\n", yp->txd);
  659. seq_printf(seq, " TxTail %u\n", yp->txtail);
  660. seq_printf(seq, " SlotTime %u\n", yp->slot);
  661. seq_printf(seq, " Persist %u\n", yp->pers);
  662. seq_printf(seq, " TxFrames %lu\n", dev->stats.tx_packets);
  663. seq_printf(seq, " RxFrames %lu\n", dev->stats.rx_packets);
  664. seq_printf(seq, " TxInt %u\n", yp->nb_mdint);
  665. seq_printf(seq, " RxInt %u\n", yp->nb_rxint);
  666. seq_printf(seq, " RxOver %lu\n", dev->stats.rx_fifo_errors);
  667. seq_printf(seq, "\n");
  668. return 0;
  669. }
  670. static const struct seq_operations yam_seqops = {
  671. .start = yam_seq_start,
  672. .next = yam_seq_next,
  673. .stop = yam_seq_stop,
  674. .show = yam_seq_show,
  675. };
  676. static int yam_info_open(struct inode *inode, struct file *file)
  677. {
  678. return seq_open(file, &yam_seqops);
  679. }
  680. static const struct file_operations yam_info_fops = {
  681. .owner = THIS_MODULE,
  682. .open = yam_info_open,
  683. .read = seq_read,
  684. .llseek = seq_lseek,
  685. .release = seq_release,
  686. };
  687. #endif
  688. /* --------------------------------------------------------------------- */
  689. static int yam_open(struct net_device *dev)
  690. {
  691. struct yam_port *yp = netdev_priv(dev);
  692. enum uart u;
  693. int i;
  694. int ret=0;
  695. printk(KERN_INFO "Trying %s at iobase 0x%lx irq %u\n", dev->name, dev->base_addr, dev->irq);
  696. if (!dev || !yp->bitrate)
  697. return -ENXIO;
  698. if (!dev->base_addr || dev->base_addr > 0x1000 - YAM_EXTENT ||
  699. dev->irq < 2 || dev->irq > 15) {
  700. return -ENXIO;
  701. }
  702. if (!request_region(dev->base_addr, YAM_EXTENT, dev->name))
  703. {
  704. printk(KERN_ERR "%s: cannot 0x%lx busy\n", dev->name, dev->base_addr);
  705. return -EACCES;
  706. }
  707. if ((u = yam_check_uart(dev->base_addr)) == c_uart_unknown) {
  708. printk(KERN_ERR "%s: cannot find uart type\n", dev->name);
  709. ret = -EIO;
  710. goto out_release_base;
  711. }
  712. if (fpga_download(dev->base_addr, yp->bitrate)) {
  713. printk(KERN_ERR "%s: cannot init FPGA\n", dev->name);
  714. ret = -EIO;
  715. goto out_release_base;
  716. }
  717. outb(0, IER(dev->base_addr));
  718. if (request_irq(dev->irq, yam_interrupt, IRQF_DISABLED | IRQF_SHARED, dev->name, dev)) {
  719. printk(KERN_ERR "%s: irq %d busy\n", dev->name, dev->irq);
  720. ret = -EBUSY;
  721. goto out_release_base;
  722. }
  723. yam_set_uart(dev);
  724. netif_start_queue(dev);
  725. yp->slotcnt = yp->slot / 10;
  726. /* Reset overruns for all ports - FPGA programming makes overruns */
  727. for (i = 0; i < NR_PORTS; i++) {
  728. struct net_device *yam_dev = yam_devs[i];
  729. inb(LSR(yam_dev->base_addr));
  730. yam_dev->stats.rx_fifo_errors = 0;
  731. }
  732. printk(KERN_INFO "%s at iobase 0x%lx irq %u uart %s\n", dev->name, dev->base_addr, dev->irq,
  733. uart_str[u]);
  734. return 0;
  735. out_release_base:
  736. release_region(dev->base_addr, YAM_EXTENT);
  737. return ret;
  738. }
  739. /* --------------------------------------------------------------------- */
  740. static int yam_close(struct net_device *dev)
  741. {
  742. struct sk_buff *skb;
  743. struct yam_port *yp = netdev_priv(dev);
  744. if (!dev)
  745. return -EINVAL;
  746. /*
  747. * disable interrupts
  748. */
  749. outb(0, IER(dev->base_addr));
  750. outb(1, MCR(dev->base_addr));
  751. /* Remove IRQ handler if last */
  752. free_irq(dev->irq,dev);
  753. release_region(dev->base_addr, YAM_EXTENT);
  754. netif_stop_queue(dev);
  755. while ((skb = skb_dequeue(&yp->send_queue)))
  756. dev_kfree_skb(skb);
  757. printk(KERN_INFO "%s: close yam at iobase 0x%lx irq %u\n",
  758. yam_drvname, dev->base_addr, dev->irq);
  759. return 0;
  760. }
  761. /* --------------------------------------------------------------------- */
  762. static int yam_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  763. {
  764. struct yam_port *yp = netdev_priv(dev);
  765. struct yamdrv_ioctl_cfg yi;
  766. struct yamdrv_ioctl_mcs *ym;
  767. int ioctl_cmd;
  768. if (copy_from_user(&ioctl_cmd, ifr->ifr_data, sizeof(int)))
  769. return -EFAULT;
  770. if (yp->magic != YAM_MAGIC)
  771. return -EINVAL;
  772. if (!capable(CAP_NET_ADMIN))
  773. return -EPERM;
  774. if (cmd != SIOCDEVPRIVATE)
  775. return -EINVAL;
  776. switch (ioctl_cmd) {
  777. case SIOCYAMRESERVED:
  778. return -EINVAL; /* unused */
  779. case SIOCYAMSMCS:
  780. if (netif_running(dev))
  781. return -EINVAL; /* Cannot change this parameter when up */
  782. if ((ym = kmalloc(sizeof(struct yamdrv_ioctl_mcs), GFP_KERNEL)) == NULL)
  783. return -ENOBUFS;
  784. ym->bitrate = 9600;
  785. if (copy_from_user(ym, ifr->ifr_data, sizeof(struct yamdrv_ioctl_mcs))) {
  786. kfree(ym);
  787. return -EFAULT;
  788. }
  789. if (ym->bitrate > YAM_MAXBITRATE) {
  790. kfree(ym);
  791. return -EINVAL;
  792. }
  793. add_mcs(ym->bits, ym->bitrate);
  794. kfree(ym);
  795. break;
  796. case SIOCYAMSCFG:
  797. if (!capable(CAP_SYS_RAWIO))
  798. return -EPERM;
  799. if (copy_from_user(&yi, ifr->ifr_data, sizeof(struct yamdrv_ioctl_cfg)))
  800. return -EFAULT;
  801. if ((yi.cfg.mask & YAM_IOBASE) && netif_running(dev))
  802. return -EINVAL; /* Cannot change this parameter when up */
  803. if ((yi.cfg.mask & YAM_IRQ) && netif_running(dev))
  804. return -EINVAL; /* Cannot change this parameter when up */
  805. if ((yi.cfg.mask & YAM_BITRATE) && netif_running(dev))
  806. return -EINVAL; /* Cannot change this parameter when up */
  807. if ((yi.cfg.mask & YAM_BAUDRATE) && netif_running(dev))
  808. return -EINVAL; /* Cannot change this parameter when up */
  809. if (yi.cfg.mask & YAM_IOBASE) {
  810. yp->iobase = yi.cfg.iobase;
  811. dev->base_addr = yi.cfg.iobase;
  812. }
  813. if (yi.cfg.mask & YAM_IRQ) {
  814. if (yi.cfg.irq > 15)
  815. return -EINVAL;
  816. yp->irq = yi.cfg.irq;
  817. dev->irq = yi.cfg.irq;
  818. }
  819. if (yi.cfg.mask & YAM_BITRATE) {
  820. if (yi.cfg.bitrate > YAM_MAXBITRATE)
  821. return -EINVAL;
  822. yp->bitrate = yi.cfg.bitrate;
  823. }
  824. if (yi.cfg.mask & YAM_BAUDRATE) {
  825. if (yi.cfg.baudrate > YAM_MAXBAUDRATE)
  826. return -EINVAL;
  827. yp->baudrate = yi.cfg.baudrate;
  828. }
  829. if (yi.cfg.mask & YAM_MODE) {
  830. if (yi.cfg.mode > YAM_MAXMODE)
  831. return -EINVAL;
  832. yp->dupmode = yi.cfg.mode;
  833. }
  834. if (yi.cfg.mask & YAM_HOLDDLY) {
  835. if (yi.cfg.holddly > YAM_MAXHOLDDLY)
  836. return -EINVAL;
  837. yp->holdd = yi.cfg.holddly;
  838. }
  839. if (yi.cfg.mask & YAM_TXDELAY) {
  840. if (yi.cfg.txdelay > YAM_MAXTXDELAY)
  841. return -EINVAL;
  842. yp->txd = yi.cfg.txdelay;
  843. }
  844. if (yi.cfg.mask & YAM_TXTAIL) {
  845. if (yi.cfg.txtail > YAM_MAXTXTAIL)
  846. return -EINVAL;
  847. yp->txtail = yi.cfg.txtail;
  848. }
  849. if (yi.cfg.mask & YAM_PERSIST) {
  850. if (yi.cfg.persist > YAM_MAXPERSIST)
  851. return -EINVAL;
  852. yp->pers = yi.cfg.persist;
  853. }
  854. if (yi.cfg.mask & YAM_SLOTTIME) {
  855. if (yi.cfg.slottime > YAM_MAXSLOTTIME)
  856. return -EINVAL;
  857. yp->slot = yi.cfg.slottime;
  858. yp->slotcnt = yp->slot / 10;
  859. }
  860. break;
  861. case SIOCYAMGCFG:
  862. yi.cfg.mask = 0xffffffff;
  863. yi.cfg.iobase = yp->iobase;
  864. yi.cfg.irq = yp->irq;
  865. yi.cfg.bitrate = yp->bitrate;
  866. yi.cfg.baudrate = yp->baudrate;
  867. yi.cfg.mode = yp->dupmode;
  868. yi.cfg.txdelay = yp->txd;
  869. yi.cfg.holddly = yp->holdd;
  870. yi.cfg.txtail = yp->txtail;
  871. yi.cfg.persist = yp->pers;
  872. yi.cfg.slottime = yp->slot;
  873. if (copy_to_user(ifr->ifr_data, &yi, sizeof(struct yamdrv_ioctl_cfg)))
  874. return -EFAULT;
  875. break;
  876. default:
  877. return -EINVAL;
  878. }
  879. return 0;
  880. }
  881. /* --------------------------------------------------------------------- */
  882. static int yam_set_mac_address(struct net_device *dev, void *addr)
  883. {
  884. struct sockaddr *sa = (struct sockaddr *) addr;
  885. /* addr is an AX.25 shifted ASCII mac address */
  886. memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
  887. return 0;
  888. }
  889. /* --------------------------------------------------------------------- */
  890. static const struct net_device_ops yam_netdev_ops = {
  891. .ndo_open = yam_open,
  892. .ndo_stop = yam_close,
  893. .ndo_start_xmit = yam_send_packet,
  894. .ndo_do_ioctl = yam_ioctl,
  895. .ndo_set_mac_address = yam_set_mac_address,
  896. };
  897. static void yam_setup(struct net_device *dev)
  898. {
  899. struct yam_port *yp = netdev_priv(dev);
  900. yp->magic = YAM_MAGIC;
  901. yp->bitrate = DEFAULT_BITRATE;
  902. yp->baudrate = DEFAULT_BITRATE * 2;
  903. yp->iobase = 0;
  904. yp->irq = 0;
  905. yp->dupmode = 0;
  906. yp->holdd = DEFAULT_HOLDD;
  907. yp->txd = DEFAULT_TXD;
  908. yp->txtail = DEFAULT_TXTAIL;
  909. yp->slot = DEFAULT_SLOT;
  910. yp->pers = DEFAULT_PERS;
  911. yp->dev = dev;
  912. dev->base_addr = yp->iobase;
  913. dev->irq = yp->irq;
  914. skb_queue_head_init(&yp->send_queue);
  915. dev->netdev_ops = &yam_netdev_ops;
  916. dev->header_ops = &ax25_header_ops;
  917. dev->type = ARPHRD_AX25;
  918. dev->hard_header_len = AX25_MAX_HEADER_LEN;
  919. dev->mtu = AX25_MTU;
  920. dev->addr_len = AX25_ADDR_LEN;
  921. memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
  922. memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
  923. }
  924. static int __init yam_init_driver(void)
  925. {
  926. struct net_device *dev;
  927. int i, err;
  928. char name[IFNAMSIZ];
  929. printk(yam_drvinfo);
  930. for (i = 0; i < NR_PORTS; i++) {
  931. sprintf(name, "yam%d", i);
  932. dev = alloc_netdev(sizeof(struct yam_port), name,
  933. yam_setup);
  934. if (!dev) {
  935. printk(KERN_ERR "yam: cannot allocate net device %s\n",
  936. dev->name);
  937. err = -ENOMEM;
  938. goto error;
  939. }
  940. err = register_netdev(dev);
  941. if (err) {
  942. printk(KERN_WARNING "yam: cannot register net device %s\n", dev->name);
  943. goto error;
  944. }
  945. yam_devs[i] = dev;
  946. }
  947. yam_timer.function = yam_dotimer;
  948. yam_timer.expires = jiffies + HZ / 100;
  949. add_timer(&yam_timer);
  950. proc_net_fops_create(&init_net, "yam", S_IRUGO, &yam_info_fops);
  951. return 0;
  952. error:
  953. while (--i >= 0) {
  954. unregister_netdev(yam_devs[i]);
  955. free_netdev(yam_devs[i]);
  956. }
  957. return err;
  958. }
  959. /* --------------------------------------------------------------------- */
  960. static void __exit yam_cleanup_driver(void)
  961. {
  962. struct yam_mcs *p;
  963. int i;
  964. del_timer(&yam_timer);
  965. for (i = 0; i < NR_PORTS; i++) {
  966. struct net_device *dev = yam_devs[i];
  967. if (dev) {
  968. unregister_netdev(dev);
  969. free_netdev(dev);
  970. }
  971. }
  972. while (yam_data) {
  973. p = yam_data;
  974. yam_data = yam_data->next;
  975. kfree(p);
  976. }
  977. proc_net_remove(&init_net, "yam");
  978. }
  979. /* --------------------------------------------------------------------- */
  980. MODULE_AUTHOR("Frederic Rible F1OAT frible@teaser.fr");
  981. MODULE_DESCRIPTION("Yam amateur radio modem driver");
  982. MODULE_LICENSE("GPL");
  983. module_init(yam_init_driver);
  984. module_exit(yam_cleanup_driver);
  985. /* --------------------------------------------------------------------- */