i915_drv.h 39 KB

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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #ifndef _I915_DRV_H_
  30. #define _I915_DRV_H_
  31. #include "i915_reg.h"
  32. #include "intel_bios.h"
  33. #include "intel_ringbuffer.h"
  34. #include <linux/io-mapping.h>
  35. #include <linux/i2c.h>
  36. #include <drm/intel-gtt.h>
  37. /* General customization:
  38. */
  39. #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
  40. #define DRIVER_NAME "i915"
  41. #define DRIVER_DESC "Intel Graphics"
  42. #define DRIVER_DATE "20080730"
  43. enum pipe {
  44. PIPE_A = 0,
  45. PIPE_B,
  46. };
  47. enum plane {
  48. PLANE_A = 0,
  49. PLANE_B,
  50. };
  51. #define I915_NUM_PIPE 2
  52. #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  53. /* Interface history:
  54. *
  55. * 1.1: Original.
  56. * 1.2: Add Power Management
  57. * 1.3: Add vblank support
  58. * 1.4: Fix cmdbuffer path, add heap destroy
  59. * 1.5: Add vblank pipe configuration
  60. * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  61. * - Support vertical blank on secondary display pipe
  62. */
  63. #define DRIVER_MAJOR 1
  64. #define DRIVER_MINOR 6
  65. #define DRIVER_PATCHLEVEL 0
  66. #define WATCH_COHERENCY 0
  67. #define WATCH_EXEC 0
  68. #define WATCH_RELOC 0
  69. #define WATCH_LISTS 0
  70. #define WATCH_PWRITE 0
  71. #define I915_GEM_PHYS_CURSOR_0 1
  72. #define I915_GEM_PHYS_CURSOR_1 2
  73. #define I915_GEM_PHYS_OVERLAY_REGS 3
  74. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  75. struct drm_i915_gem_phys_object {
  76. int id;
  77. struct page **page_list;
  78. drm_dma_handle_t *handle;
  79. struct drm_gem_object *cur_obj;
  80. };
  81. struct mem_block {
  82. struct mem_block *next;
  83. struct mem_block *prev;
  84. int start;
  85. int size;
  86. struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  87. };
  88. struct opregion_header;
  89. struct opregion_acpi;
  90. struct opregion_swsci;
  91. struct opregion_asle;
  92. struct intel_opregion {
  93. struct opregion_header *header;
  94. struct opregion_acpi *acpi;
  95. struct opregion_swsci *swsci;
  96. struct opregion_asle *asle;
  97. void *vbt;
  98. };
  99. #define OPREGION_SIZE (8*1024)
  100. struct intel_overlay;
  101. struct intel_overlay_error_state;
  102. struct drm_i915_master_private {
  103. drm_local_map_t *sarea;
  104. struct _drm_i915_sarea *sarea_priv;
  105. };
  106. #define I915_FENCE_REG_NONE -1
  107. struct drm_i915_fence_reg {
  108. struct drm_gem_object *obj;
  109. struct list_head lru_list;
  110. bool gpu;
  111. };
  112. struct sdvo_device_mapping {
  113. u8 initialized;
  114. u8 dvo_port;
  115. u8 slave_addr;
  116. u8 dvo_wiring;
  117. u8 i2c_pin;
  118. u8 i2c_speed;
  119. u8 ddc_pin;
  120. };
  121. struct drm_i915_error_state {
  122. u32 eir;
  123. u32 pgtbl_er;
  124. u32 pipeastat;
  125. u32 pipebstat;
  126. u32 ipeir;
  127. u32 ipehr;
  128. u32 instdone;
  129. u32 acthd;
  130. u32 instpm;
  131. u32 instps;
  132. u32 instdone1;
  133. u32 seqno;
  134. u64 bbaddr;
  135. struct timeval time;
  136. struct drm_i915_error_object {
  137. int page_count;
  138. u32 gtt_offset;
  139. u32 *pages[0];
  140. } *ringbuffer, *batchbuffer[2];
  141. struct drm_i915_error_buffer {
  142. size_t size;
  143. u32 name;
  144. u32 seqno;
  145. u32 gtt_offset;
  146. u32 read_domains;
  147. u32 write_domain;
  148. u32 fence_reg;
  149. s32 pinned:2;
  150. u32 tiling:2;
  151. u32 dirty:1;
  152. u32 purgeable:1;
  153. } *active_bo;
  154. u32 active_bo_count;
  155. struct intel_overlay_error_state *overlay;
  156. };
  157. struct drm_i915_display_funcs {
  158. void (*dpms)(struct drm_crtc *crtc, int mode);
  159. bool (*fbc_enabled)(struct drm_device *dev);
  160. void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  161. void (*disable_fbc)(struct drm_device *dev);
  162. int (*get_display_clock_speed)(struct drm_device *dev);
  163. int (*get_fifo_size)(struct drm_device *dev, int plane);
  164. void (*update_wm)(struct drm_device *dev, int planea_clock,
  165. int planeb_clock, int sr_hdisplay, int sr_htotal,
  166. int pixel_size);
  167. /* clock updates for mode set */
  168. /* cursor updates */
  169. /* render clock increase/decrease */
  170. /* display clock increase/decrease */
  171. /* pll clock increase/decrease */
  172. /* clock gating init */
  173. };
  174. struct intel_device_info {
  175. u8 gen;
  176. u8 is_mobile : 1;
  177. u8 is_i85x : 1;
  178. u8 is_i915g : 1;
  179. u8 is_i945gm : 1;
  180. u8 is_g33 : 1;
  181. u8 need_gfx_hws : 1;
  182. u8 is_g4x : 1;
  183. u8 is_pineview : 1;
  184. u8 is_broadwater : 1;
  185. u8 is_crestline : 1;
  186. u8 has_fbc : 1;
  187. u8 has_rc6 : 1;
  188. u8 has_pipe_cxsr : 1;
  189. u8 has_hotplug : 1;
  190. u8 cursor_needs_physical : 1;
  191. u8 has_overlay : 1;
  192. u8 overlay_needs_physical : 1;
  193. u8 supports_tv : 1;
  194. u8 has_bsd_ring : 1;
  195. u8 has_blt_ring : 1;
  196. };
  197. enum no_fbc_reason {
  198. FBC_NO_OUTPUT, /* no outputs enabled to compress */
  199. FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
  200. FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  201. FBC_MODE_TOO_LARGE, /* mode too large for compression */
  202. FBC_BAD_PLANE, /* fbc not supported on plane */
  203. FBC_NOT_TILED, /* buffer not tiled */
  204. FBC_MULTIPLE_PIPES, /* more than one pipe active */
  205. };
  206. enum intel_pch {
  207. PCH_IBX, /* Ibexpeak PCH */
  208. PCH_CPT, /* Cougarpoint PCH */
  209. };
  210. #define QUIRK_PIPEA_FORCE (1<<0)
  211. struct intel_fbdev;
  212. typedef struct drm_i915_private {
  213. struct drm_device *dev;
  214. const struct intel_device_info *info;
  215. int has_gem;
  216. void __iomem *regs;
  217. struct intel_gmbus {
  218. struct i2c_adapter adapter;
  219. struct i2c_adapter *force_bit;
  220. u32 reg0;
  221. } *gmbus;
  222. struct pci_dev *bridge_dev;
  223. struct intel_ring_buffer render_ring;
  224. struct intel_ring_buffer bsd_ring;
  225. struct intel_ring_buffer blt_ring;
  226. uint32_t next_seqno;
  227. drm_dma_handle_t *status_page_dmah;
  228. void *seqno_page;
  229. dma_addr_t dma_status_page;
  230. uint32_t counter;
  231. unsigned int seqno_gfx_addr;
  232. drm_local_map_t hws_map;
  233. struct drm_gem_object *seqno_obj;
  234. struct drm_gem_object *pwrctx;
  235. struct drm_gem_object *renderctx;
  236. struct resource mch_res;
  237. unsigned int cpp;
  238. int back_offset;
  239. int front_offset;
  240. int current_page;
  241. int page_flipping;
  242. #define I915_DEBUG_READ (1<<0)
  243. #define I915_DEBUG_WRITE (1<<1)
  244. unsigned long debug_flags;
  245. wait_queue_head_t irq_queue;
  246. atomic_t irq_received;
  247. /** Protects user_irq_refcount and irq_mask_reg */
  248. spinlock_t user_irq_lock;
  249. u32 trace_irq_seqno;
  250. /** Cached value of IMR to avoid reads in updating the bitfield */
  251. u32 irq_mask_reg;
  252. u32 pipestat[2];
  253. /** splitted irq regs for graphics and display engine on Ironlake,
  254. irq_mask_reg is still used for display irq. */
  255. u32 gt_irq_mask_reg;
  256. u32 gt_irq_enable_reg;
  257. u32 de_irq_enable_reg;
  258. u32 pch_irq_mask_reg;
  259. u32 pch_irq_enable_reg;
  260. u32 hotplug_supported_mask;
  261. struct work_struct hotplug_work;
  262. int tex_lru_log_granularity;
  263. int allow_batchbuffer;
  264. struct mem_block *agp_heap;
  265. unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
  266. int vblank_pipe;
  267. int num_pipe;
  268. /* For hangcheck timer */
  269. #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
  270. struct timer_list hangcheck_timer;
  271. int hangcheck_count;
  272. uint32_t last_acthd;
  273. uint32_t last_instdone;
  274. uint32_t last_instdone1;
  275. unsigned long cfb_size;
  276. unsigned long cfb_pitch;
  277. unsigned long cfb_offset;
  278. int cfb_fence;
  279. int cfb_plane;
  280. int cfb_y;
  281. int irq_enabled;
  282. struct intel_opregion opregion;
  283. /* overlay */
  284. struct intel_overlay *overlay;
  285. /* LVDS info */
  286. int backlight_level; /* restore backlight to this value */
  287. struct drm_display_mode *panel_fixed_mode;
  288. struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  289. struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  290. /* Feature bits from the VBIOS */
  291. unsigned int int_tv_support:1;
  292. unsigned int lvds_dither:1;
  293. unsigned int lvds_vbt:1;
  294. unsigned int int_crt_support:1;
  295. unsigned int lvds_use_ssc:1;
  296. int lvds_ssc_freq;
  297. struct {
  298. int rate;
  299. int lanes;
  300. int preemphasis;
  301. int vswing;
  302. bool initialized;
  303. bool support;
  304. int bpp;
  305. struct edp_power_seq pps;
  306. } edp;
  307. bool no_aux_handshake;
  308. struct notifier_block lid_notifier;
  309. int crt_ddc_pin;
  310. struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
  311. int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  312. int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  313. unsigned int fsb_freq, mem_freq, is_ddr3;
  314. spinlock_t error_lock;
  315. struct drm_i915_error_state *first_error;
  316. struct work_struct error_work;
  317. struct completion error_completion;
  318. struct workqueue_struct *wq;
  319. /* Display functions */
  320. struct drm_i915_display_funcs display;
  321. /* PCH chipset type */
  322. enum intel_pch pch_type;
  323. unsigned long quirks;
  324. /* Register state */
  325. bool modeset_on_lid;
  326. u8 saveLBB;
  327. u32 saveDSPACNTR;
  328. u32 saveDSPBCNTR;
  329. u32 saveDSPARB;
  330. u32 saveHWS;
  331. u32 savePIPEACONF;
  332. u32 savePIPEBCONF;
  333. u32 savePIPEASRC;
  334. u32 savePIPEBSRC;
  335. u32 saveFPA0;
  336. u32 saveFPA1;
  337. u32 saveDPLL_A;
  338. u32 saveDPLL_A_MD;
  339. u32 saveHTOTAL_A;
  340. u32 saveHBLANK_A;
  341. u32 saveHSYNC_A;
  342. u32 saveVTOTAL_A;
  343. u32 saveVBLANK_A;
  344. u32 saveVSYNC_A;
  345. u32 saveBCLRPAT_A;
  346. u32 saveTRANSACONF;
  347. u32 saveTRANS_HTOTAL_A;
  348. u32 saveTRANS_HBLANK_A;
  349. u32 saveTRANS_HSYNC_A;
  350. u32 saveTRANS_VTOTAL_A;
  351. u32 saveTRANS_VBLANK_A;
  352. u32 saveTRANS_VSYNC_A;
  353. u32 savePIPEASTAT;
  354. u32 saveDSPASTRIDE;
  355. u32 saveDSPASIZE;
  356. u32 saveDSPAPOS;
  357. u32 saveDSPAADDR;
  358. u32 saveDSPASURF;
  359. u32 saveDSPATILEOFF;
  360. u32 savePFIT_PGM_RATIOS;
  361. u32 saveBLC_HIST_CTL;
  362. u32 saveBLC_PWM_CTL;
  363. u32 saveBLC_PWM_CTL2;
  364. u32 saveBLC_CPU_PWM_CTL;
  365. u32 saveBLC_CPU_PWM_CTL2;
  366. u32 saveFPB0;
  367. u32 saveFPB1;
  368. u32 saveDPLL_B;
  369. u32 saveDPLL_B_MD;
  370. u32 saveHTOTAL_B;
  371. u32 saveHBLANK_B;
  372. u32 saveHSYNC_B;
  373. u32 saveVTOTAL_B;
  374. u32 saveVBLANK_B;
  375. u32 saveVSYNC_B;
  376. u32 saveBCLRPAT_B;
  377. u32 saveTRANSBCONF;
  378. u32 saveTRANS_HTOTAL_B;
  379. u32 saveTRANS_HBLANK_B;
  380. u32 saveTRANS_HSYNC_B;
  381. u32 saveTRANS_VTOTAL_B;
  382. u32 saveTRANS_VBLANK_B;
  383. u32 saveTRANS_VSYNC_B;
  384. u32 savePIPEBSTAT;
  385. u32 saveDSPBSTRIDE;
  386. u32 saveDSPBSIZE;
  387. u32 saveDSPBPOS;
  388. u32 saveDSPBADDR;
  389. u32 saveDSPBSURF;
  390. u32 saveDSPBTILEOFF;
  391. u32 saveVGA0;
  392. u32 saveVGA1;
  393. u32 saveVGA_PD;
  394. u32 saveVGACNTRL;
  395. u32 saveADPA;
  396. u32 saveLVDS;
  397. u32 savePP_ON_DELAYS;
  398. u32 savePP_OFF_DELAYS;
  399. u32 saveDVOA;
  400. u32 saveDVOB;
  401. u32 saveDVOC;
  402. u32 savePP_ON;
  403. u32 savePP_OFF;
  404. u32 savePP_CONTROL;
  405. u32 savePP_DIVISOR;
  406. u32 savePFIT_CONTROL;
  407. u32 save_palette_a[256];
  408. u32 save_palette_b[256];
  409. u32 saveDPFC_CB_BASE;
  410. u32 saveFBC_CFB_BASE;
  411. u32 saveFBC_LL_BASE;
  412. u32 saveFBC_CONTROL;
  413. u32 saveFBC_CONTROL2;
  414. u32 saveIER;
  415. u32 saveIIR;
  416. u32 saveIMR;
  417. u32 saveDEIER;
  418. u32 saveDEIMR;
  419. u32 saveGTIER;
  420. u32 saveGTIMR;
  421. u32 saveFDI_RXA_IMR;
  422. u32 saveFDI_RXB_IMR;
  423. u32 saveCACHE_MODE_0;
  424. u32 saveMI_ARB_STATE;
  425. u32 saveSWF0[16];
  426. u32 saveSWF1[16];
  427. u32 saveSWF2[3];
  428. u8 saveMSR;
  429. u8 saveSR[8];
  430. u8 saveGR[25];
  431. u8 saveAR_INDEX;
  432. u8 saveAR[21];
  433. u8 saveDACMASK;
  434. u8 saveCR[37];
  435. uint64_t saveFENCE[16];
  436. u32 saveCURACNTR;
  437. u32 saveCURAPOS;
  438. u32 saveCURABASE;
  439. u32 saveCURBCNTR;
  440. u32 saveCURBPOS;
  441. u32 saveCURBBASE;
  442. u32 saveCURSIZE;
  443. u32 saveDP_B;
  444. u32 saveDP_C;
  445. u32 saveDP_D;
  446. u32 savePIPEA_GMCH_DATA_M;
  447. u32 savePIPEB_GMCH_DATA_M;
  448. u32 savePIPEA_GMCH_DATA_N;
  449. u32 savePIPEB_GMCH_DATA_N;
  450. u32 savePIPEA_DP_LINK_M;
  451. u32 savePIPEB_DP_LINK_M;
  452. u32 savePIPEA_DP_LINK_N;
  453. u32 savePIPEB_DP_LINK_N;
  454. u32 saveFDI_RXA_CTL;
  455. u32 saveFDI_TXA_CTL;
  456. u32 saveFDI_RXB_CTL;
  457. u32 saveFDI_TXB_CTL;
  458. u32 savePFA_CTL_1;
  459. u32 savePFB_CTL_1;
  460. u32 savePFA_WIN_SZ;
  461. u32 savePFB_WIN_SZ;
  462. u32 savePFA_WIN_POS;
  463. u32 savePFB_WIN_POS;
  464. u32 savePCH_DREF_CONTROL;
  465. u32 saveDISP_ARB_CTL;
  466. u32 savePIPEA_DATA_M1;
  467. u32 savePIPEA_DATA_N1;
  468. u32 savePIPEA_LINK_M1;
  469. u32 savePIPEA_LINK_N1;
  470. u32 savePIPEB_DATA_M1;
  471. u32 savePIPEB_DATA_N1;
  472. u32 savePIPEB_LINK_M1;
  473. u32 savePIPEB_LINK_N1;
  474. u32 saveMCHBAR_RENDER_STANDBY;
  475. struct {
  476. /** Bridge to intel-gtt-ko */
  477. struct intel_gtt *gtt;
  478. /** Memory allocator for GTT stolen memory */
  479. struct drm_mm vram;
  480. /** Memory allocator for GTT */
  481. struct drm_mm gtt_space;
  482. /** End of mappable part of GTT */
  483. unsigned long gtt_mappable_end;
  484. struct io_mapping *gtt_mapping;
  485. int gtt_mtrr;
  486. /**
  487. * Membership on list of all loaded devices, used to evict
  488. * inactive buffers under memory pressure.
  489. *
  490. * Modifications should only be done whilst holding the
  491. * shrink_list_lock spinlock.
  492. */
  493. struct list_head shrink_list;
  494. /**
  495. * List of objects currently involved in rendering.
  496. *
  497. * Includes buffers having the contents of their GPU caches
  498. * flushed, not necessarily primitives. last_rendering_seqno
  499. * represents when the rendering involved will be completed.
  500. *
  501. * A reference is held on the buffer while on this list.
  502. */
  503. struct list_head active_list;
  504. /**
  505. * List of objects which are not in the ringbuffer but which
  506. * still have a write_domain which needs to be flushed before
  507. * unbinding.
  508. *
  509. * last_rendering_seqno is 0 while an object is in this list.
  510. *
  511. * A reference is held on the buffer while on this list.
  512. */
  513. struct list_head flushing_list;
  514. /**
  515. * LRU list of objects which are not in the ringbuffer and
  516. * are ready to unbind, but are still in the GTT.
  517. *
  518. * last_rendering_seqno is 0 while an object is in this list.
  519. *
  520. * A reference is not held on the buffer while on this list,
  521. * as merely being GTT-bound shouldn't prevent its being
  522. * freed, and we'll pull it off the list in the free path.
  523. */
  524. struct list_head inactive_list;
  525. /**
  526. * LRU list of objects which are not in the ringbuffer but
  527. * are still pinned in the GTT.
  528. */
  529. struct list_head pinned_list;
  530. /** LRU list of objects with fence regs on them. */
  531. struct list_head fence_list;
  532. /**
  533. * List of objects currently pending being freed.
  534. *
  535. * These objects are no longer in use, but due to a signal
  536. * we were prevented from freeing them at the appointed time.
  537. */
  538. struct list_head deferred_free_list;
  539. /**
  540. * We leave the user IRQ off as much as possible,
  541. * but this means that requests will finish and never
  542. * be retired once the system goes idle. Set a timer to
  543. * fire periodically while the ring is running. When it
  544. * fires, go retire requests.
  545. */
  546. struct delayed_work retire_work;
  547. /**
  548. * Flag if the X Server, and thus DRM, is not currently in
  549. * control of the device.
  550. *
  551. * This is set between LeaveVT and EnterVT. It needs to be
  552. * replaced with a semaphore. It also needs to be
  553. * transitioned away from for kernel modesetting.
  554. */
  555. int suspended;
  556. /**
  557. * Flag if the hardware appears to be wedged.
  558. *
  559. * This is set when attempts to idle the device timeout.
  560. * It prevents command submission from occuring and makes
  561. * every pending request fail
  562. */
  563. atomic_t wedged;
  564. /** Bit 6 swizzling required for X tiling */
  565. uint32_t bit_6_swizzle_x;
  566. /** Bit 6 swizzling required for Y tiling */
  567. uint32_t bit_6_swizzle_y;
  568. /* storage for physical objects */
  569. struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  570. uint32_t flush_rings;
  571. /* accounting, useful for userland debugging */
  572. size_t object_memory;
  573. size_t pin_memory;
  574. size_t gtt_memory;
  575. size_t gtt_total;
  576. u32 object_count;
  577. u32 pin_count;
  578. u32 gtt_count;
  579. } mm;
  580. struct sdvo_device_mapping sdvo_mappings[2];
  581. /* indicate whether the LVDS_BORDER should be enabled or not */
  582. unsigned int lvds_border_bits;
  583. /* Panel fitter placement and size for Ironlake+ */
  584. u32 pch_pf_pos, pch_pf_size;
  585. struct drm_crtc *plane_to_crtc_mapping[2];
  586. struct drm_crtc *pipe_to_crtc_mapping[2];
  587. wait_queue_head_t pending_flip_queue;
  588. bool flip_pending_is_done;
  589. /* Reclocking support */
  590. bool render_reclock_avail;
  591. bool lvds_downclock_avail;
  592. /* indicates the reduced downclock for LVDS*/
  593. int lvds_downclock;
  594. struct work_struct idle_work;
  595. struct timer_list idle_timer;
  596. bool busy;
  597. u16 orig_clock;
  598. int child_dev_num;
  599. struct child_device_config *child_dev;
  600. struct drm_connector *int_lvds_connector;
  601. bool mchbar_need_disable;
  602. u8 cur_delay;
  603. u8 min_delay;
  604. u8 max_delay;
  605. u8 fmax;
  606. u8 fstart;
  607. u64 last_count1;
  608. unsigned long last_time1;
  609. u64 last_count2;
  610. struct timespec last_time2;
  611. unsigned long gfx_power;
  612. int c_m;
  613. int r_t;
  614. u8 corr;
  615. spinlock_t *mchdev_lock;
  616. enum no_fbc_reason no_fbc_reason;
  617. struct drm_mm_node *compressed_fb;
  618. struct drm_mm_node *compressed_llb;
  619. unsigned long last_gpu_reset;
  620. /* list of fbdev register on this device */
  621. struct intel_fbdev *fbdev;
  622. } drm_i915_private_t;
  623. /** driver private structure attached to each drm_gem_object */
  624. struct drm_i915_gem_object {
  625. struct drm_gem_object base;
  626. /** Current space allocated to this object in the GTT, if any. */
  627. struct drm_mm_node *gtt_space;
  628. /** This object's place on the active/flushing/inactive lists */
  629. struct list_head ring_list;
  630. struct list_head mm_list;
  631. /** This object's place on GPU write list */
  632. struct list_head gpu_write_list;
  633. /** This object's place on eviction list */
  634. struct list_head evict_list;
  635. /**
  636. * This is set if the object is on the active or flushing lists
  637. * (has pending rendering), and is not set if it's on inactive (ready
  638. * to be unbound).
  639. */
  640. unsigned int active : 1;
  641. /**
  642. * This is set if the object has been written to since last bound
  643. * to the GTT
  644. */
  645. unsigned int dirty : 1;
  646. /**
  647. * Fence register bits (if any) for this object. Will be set
  648. * as needed when mapped into the GTT.
  649. * Protected by dev->struct_mutex.
  650. *
  651. * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
  652. */
  653. signed int fence_reg : 5;
  654. /**
  655. * Used for checking the object doesn't appear more than once
  656. * in an execbuffer object list.
  657. */
  658. unsigned int in_execbuffer : 1;
  659. /**
  660. * Advice: are the backing pages purgeable?
  661. */
  662. unsigned int madv : 2;
  663. /**
  664. * Refcount for the pages array. With the current locking scheme, there
  665. * are at most two concurrent users: Binding a bo to the gtt and
  666. * pwrite/pread using physical addresses. So two bits for a maximum
  667. * of two users are enough.
  668. */
  669. unsigned int pages_refcount : 2;
  670. #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
  671. /**
  672. * Current tiling mode for the object.
  673. */
  674. unsigned int tiling_mode : 2;
  675. /** How many users have pinned this object in GTT space. The following
  676. * users can each hold at most one reference: pwrite/pread, pin_ioctl
  677. * (via user_pin_count), execbuffer (objects are not allowed multiple
  678. * times for the same batchbuffer), and the framebuffer code. When
  679. * switching/pageflipping, the framebuffer code has at most two buffers
  680. * pinned per crtc.
  681. *
  682. * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  683. * bits with absolutely no headroom. So use 4 bits. */
  684. unsigned int pin_count : 4;
  685. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  686. /** AGP memory structure for our GTT binding. */
  687. DRM_AGP_MEM *agp_mem;
  688. struct page **pages;
  689. /**
  690. * Current offset of the object in GTT space.
  691. *
  692. * This is the same as gtt_space->start
  693. */
  694. uint32_t gtt_offset;
  695. /* Which ring is refering to is this object */
  696. struct intel_ring_buffer *ring;
  697. /**
  698. * Fake offset for use by mmap(2)
  699. */
  700. uint64_t mmap_offset;
  701. /** Breadcrumb of last rendering to the buffer. */
  702. uint32_t last_rendering_seqno;
  703. /** Current tiling stride for the object, if it's tiled. */
  704. uint32_t stride;
  705. /** Record of address bit 17 of each page at last unbind. */
  706. unsigned long *bit_17;
  707. /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
  708. uint32_t agp_type;
  709. /**
  710. * If present, while GEM_DOMAIN_CPU is in the read domain this array
  711. * flags which individual pages are valid.
  712. */
  713. uint8_t *page_cpu_valid;
  714. /** User space pin count and filp owning the pin */
  715. uint32_t user_pin_count;
  716. struct drm_file *pin_filp;
  717. /** for phy allocated objects */
  718. struct drm_i915_gem_phys_object *phys_obj;
  719. /**
  720. * Number of crtcs where this object is currently the fb, but
  721. * will be page flipped away on the next vblank. When it
  722. * reaches 0, dev_priv->pending_flip_queue will be woken up.
  723. */
  724. atomic_t pending_flip;
  725. };
  726. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  727. /**
  728. * Request queue structure.
  729. *
  730. * The request queue allows us to note sequence numbers that have been emitted
  731. * and may be associated with active buffers to be retired.
  732. *
  733. * By keeping this list, we can avoid having to do questionable
  734. * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  735. * an emission time with seqnos for tracking how far ahead of the GPU we are.
  736. */
  737. struct drm_i915_gem_request {
  738. /** On Which ring this request was generated */
  739. struct intel_ring_buffer *ring;
  740. /** GEM sequence number associated with this request. */
  741. uint32_t seqno;
  742. /** Time at which this request was emitted, in jiffies. */
  743. unsigned long emitted_jiffies;
  744. /** global list entry for this request */
  745. struct list_head list;
  746. struct drm_i915_file_private *file_priv;
  747. /** file_priv list entry for this request */
  748. struct list_head client_list;
  749. };
  750. struct drm_i915_file_private {
  751. struct {
  752. struct spinlock lock;
  753. struct list_head request_list;
  754. } mm;
  755. };
  756. enum intel_chip_family {
  757. CHIP_I8XX = 0x01,
  758. CHIP_I9XX = 0x02,
  759. CHIP_I915 = 0x04,
  760. CHIP_I965 = 0x08,
  761. };
  762. extern struct drm_ioctl_desc i915_ioctls[];
  763. extern int i915_max_ioctl;
  764. extern unsigned int i915_fbpercrtc;
  765. extern unsigned int i915_powersave;
  766. extern unsigned int i915_lvds_downclock;
  767. extern int i915_suspend(struct drm_device *dev, pm_message_t state);
  768. extern int i915_resume(struct drm_device *dev);
  769. extern void i915_save_display(struct drm_device *dev);
  770. extern void i915_restore_display(struct drm_device *dev);
  771. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  772. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  773. /* i915_dma.c */
  774. extern void i915_kernel_lost_context(struct drm_device * dev);
  775. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  776. extern int i915_driver_unload(struct drm_device *);
  777. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  778. extern void i915_driver_lastclose(struct drm_device * dev);
  779. extern void i915_driver_preclose(struct drm_device *dev,
  780. struct drm_file *file_priv);
  781. extern void i915_driver_postclose(struct drm_device *dev,
  782. struct drm_file *file_priv);
  783. extern int i915_driver_device_is_agp(struct drm_device * dev);
  784. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  785. unsigned long arg);
  786. extern int i915_emit_box(struct drm_device *dev,
  787. struct drm_clip_rect *boxes,
  788. int i, int DR1, int DR4);
  789. extern int i915_reset(struct drm_device *dev, u8 flags);
  790. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  791. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  792. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  793. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  794. /* i915_irq.c */
  795. void i915_hangcheck_elapsed(unsigned long data);
  796. extern int i915_irq_emit(struct drm_device *dev, void *data,
  797. struct drm_file *file_priv);
  798. extern int i915_irq_wait(struct drm_device *dev, void *data,
  799. struct drm_file *file_priv);
  800. void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
  801. extern void i915_enable_interrupt (struct drm_device *dev);
  802. extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
  803. extern void i915_driver_irq_preinstall(struct drm_device * dev);
  804. extern int i915_driver_irq_postinstall(struct drm_device *dev);
  805. extern void i915_driver_irq_uninstall(struct drm_device * dev);
  806. extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  807. struct drm_file *file_priv);
  808. extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  809. struct drm_file *file_priv);
  810. extern int i915_enable_vblank(struct drm_device *dev, int crtc);
  811. extern void i915_disable_vblank(struct drm_device *dev, int crtc);
  812. extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
  813. extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
  814. extern int i915_vblank_swap(struct drm_device *dev, void *data,
  815. struct drm_file *file_priv);
  816. extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
  817. extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
  818. extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
  819. u32 mask);
  820. extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
  821. u32 mask);
  822. void
  823. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  824. void
  825. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  826. void intel_enable_asle (struct drm_device *dev);
  827. #ifdef CONFIG_DEBUG_FS
  828. extern void i915_destroy_error_state(struct drm_device *dev);
  829. #else
  830. #define i915_destroy_error_state(x)
  831. #endif
  832. /* i915_mem.c */
  833. extern int i915_mem_alloc(struct drm_device *dev, void *data,
  834. struct drm_file *file_priv);
  835. extern int i915_mem_free(struct drm_device *dev, void *data,
  836. struct drm_file *file_priv);
  837. extern int i915_mem_init_heap(struct drm_device *dev, void *data,
  838. struct drm_file *file_priv);
  839. extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
  840. struct drm_file *file_priv);
  841. extern void i915_mem_takedown(struct mem_block **heap);
  842. extern void i915_mem_release(struct drm_device * dev,
  843. struct drm_file *file_priv, struct mem_block *heap);
  844. /* i915_gem.c */
  845. int i915_gem_check_is_wedged(struct drm_device *dev);
  846. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  847. struct drm_file *file_priv);
  848. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  849. struct drm_file *file_priv);
  850. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  851. struct drm_file *file_priv);
  852. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  853. struct drm_file *file_priv);
  854. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  855. struct drm_file *file_priv);
  856. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  857. struct drm_file *file_priv);
  858. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  859. struct drm_file *file_priv);
  860. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  861. struct drm_file *file_priv);
  862. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  863. struct drm_file *file_priv);
  864. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  865. struct drm_file *file_priv);
  866. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  867. struct drm_file *file_priv);
  868. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  869. struct drm_file *file_priv);
  870. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  871. struct drm_file *file_priv);
  872. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  873. struct drm_file *file_priv);
  874. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  875. struct drm_file *file_priv);
  876. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  877. struct drm_file *file_priv);
  878. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  879. struct drm_file *file_priv);
  880. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  881. struct drm_file *file_priv);
  882. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  883. struct drm_file *file_priv);
  884. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  885. struct drm_file *file_priv);
  886. void i915_gem_load(struct drm_device *dev);
  887. int i915_gem_init_object(struct drm_gem_object *obj);
  888. struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
  889. size_t size);
  890. void i915_gem_free_object(struct drm_gem_object *obj);
  891. int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment,
  892. bool mappable);
  893. void i915_gem_object_unpin(struct drm_gem_object *obj);
  894. int i915_gem_object_unbind(struct drm_gem_object *obj);
  895. void i915_gem_release_mmap(struct drm_gem_object *obj);
  896. void i915_gem_lastclose(struct drm_device *dev);
  897. /**
  898. * Returns true if seq1 is later than seq2.
  899. */
  900. static inline bool
  901. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  902. {
  903. return (int32_t)(seq1 - seq2) >= 0;
  904. }
  905. int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
  906. bool interruptible);
  907. int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
  908. bool interruptible);
  909. void i915_gem_retire_requests(struct drm_device *dev);
  910. void i915_gem_reset(struct drm_device *dev);
  911. void i915_gem_clflush_object(struct drm_gem_object *obj);
  912. int i915_gem_object_set_domain(struct drm_gem_object *obj,
  913. uint32_t read_domains,
  914. uint32_t write_domain);
  915. int i915_gem_init_ringbuffer(struct drm_device *dev);
  916. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  917. int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  918. unsigned long end);
  919. int i915_gpu_idle(struct drm_device *dev);
  920. int i915_gem_idle(struct drm_device *dev);
  921. int i915_add_request(struct drm_device *dev,
  922. struct drm_file *file_priv,
  923. struct drm_i915_gem_request *request,
  924. struct intel_ring_buffer *ring);
  925. int i915_do_wait_request(struct drm_device *dev,
  926. uint32_t seqno,
  927. bool interruptible,
  928. struct intel_ring_buffer *ring);
  929. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  930. int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
  931. int write);
  932. int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
  933. bool pipelined);
  934. int i915_gem_attach_phys_object(struct drm_device *dev,
  935. struct drm_gem_object *obj,
  936. int id,
  937. int align);
  938. void i915_gem_detach_phys_object(struct drm_device *dev,
  939. struct drm_gem_object *obj);
  940. void i915_gem_free_all_phys_object(struct drm_device *dev);
  941. void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
  942. void i915_gem_shrinker_init(void);
  943. void i915_gem_shrinker_exit(void);
  944. /* i915_gem_evict.c */
  945. int i915_gem_evict_something(struct drm_device *dev, int min_size,
  946. unsigned alignment, bool mappable);
  947. int i915_gem_evict_everything(struct drm_device *dev);
  948. int i915_gem_evict_inactive(struct drm_device *dev);
  949. /* i915_gem_tiling.c */
  950. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  951. void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
  952. void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
  953. bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
  954. int tiling_mode);
  955. bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
  956. int tiling_mode);
  957. /* i915_gem_debug.c */
  958. void i915_gem_dump_object(struct drm_gem_object *obj, int len,
  959. const char *where, uint32_t mark);
  960. #if WATCH_LISTS
  961. int i915_verify_lists(struct drm_device *dev);
  962. #else
  963. #define i915_verify_lists(dev) 0
  964. #endif
  965. void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
  966. void i915_gem_dump_object(struct drm_gem_object *obj, int len,
  967. const char *where, uint32_t mark);
  968. /* i915_debugfs.c */
  969. int i915_debugfs_init(struct drm_minor *minor);
  970. void i915_debugfs_cleanup(struct drm_minor *minor);
  971. /* i915_suspend.c */
  972. extern int i915_save_state(struct drm_device *dev);
  973. extern int i915_restore_state(struct drm_device *dev);
  974. /* i915_suspend.c */
  975. extern int i915_save_state(struct drm_device *dev);
  976. extern int i915_restore_state(struct drm_device *dev);
  977. /* intel_i2c.c */
  978. extern int intel_setup_gmbus(struct drm_device *dev);
  979. extern void intel_teardown_gmbus(struct drm_device *dev);
  980. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  981. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  982. extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  983. {
  984. return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  985. }
  986. extern void intel_i2c_reset(struct drm_device *dev);
  987. /* intel_opregion.c */
  988. extern int intel_opregion_setup(struct drm_device *dev);
  989. #ifdef CONFIG_ACPI
  990. extern void intel_opregion_init(struct drm_device *dev);
  991. extern void intel_opregion_fini(struct drm_device *dev);
  992. extern void intel_opregion_asle_intr(struct drm_device *dev);
  993. extern void intel_opregion_gse_intr(struct drm_device *dev);
  994. extern void intel_opregion_enable_asle(struct drm_device *dev);
  995. #else
  996. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  997. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  998. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  999. static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
  1000. static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
  1001. #endif
  1002. /* intel_acpi.c */
  1003. #ifdef CONFIG_ACPI
  1004. extern void intel_register_dsm_handler(void);
  1005. extern void intel_unregister_dsm_handler(void);
  1006. #else
  1007. static inline void intel_register_dsm_handler(void) { return; }
  1008. static inline void intel_unregister_dsm_handler(void) { return; }
  1009. #endif /* CONFIG_ACPI */
  1010. /* modesetting */
  1011. extern void intel_modeset_init(struct drm_device *dev);
  1012. extern void intel_modeset_cleanup(struct drm_device *dev);
  1013. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  1014. extern void i8xx_disable_fbc(struct drm_device *dev);
  1015. extern void g4x_disable_fbc(struct drm_device *dev);
  1016. extern void ironlake_disable_fbc(struct drm_device *dev);
  1017. extern void intel_disable_fbc(struct drm_device *dev);
  1018. extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
  1019. extern bool intel_fbc_enabled(struct drm_device *dev);
  1020. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  1021. extern void intel_detect_pch (struct drm_device *dev);
  1022. extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
  1023. /* overlay */
  1024. #ifdef CONFIG_DEBUG_FS
  1025. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  1026. extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
  1027. #endif
  1028. /**
  1029. * Lock test for when it's just for synchronization of ring access.
  1030. *
  1031. * In that case, we don't need to do it when GEM is initialized as nobody else
  1032. * has access to the ring.
  1033. */
  1034. #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
  1035. if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
  1036. == NULL) \
  1037. LOCK_TEST_WITH_RETURN(dev, file_priv); \
  1038. } while (0)
  1039. static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg)
  1040. {
  1041. u32 val;
  1042. val = readl(dev_priv->regs + reg);
  1043. if (dev_priv->debug_flags & I915_DEBUG_READ)
  1044. printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg);
  1045. return val;
  1046. }
  1047. static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
  1048. u32 val)
  1049. {
  1050. writel(val, dev_priv->regs + reg);
  1051. if (dev_priv->debug_flags & I915_DEBUG_WRITE)
  1052. printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg);
  1053. }
  1054. #define I915_READ(reg) i915_read(dev_priv, (reg))
  1055. #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
  1056. #define I915_READ16(reg) readw(dev_priv->regs + (reg))
  1057. #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
  1058. #define I915_READ8(reg) readb(dev_priv->regs + (reg))
  1059. #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
  1060. #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
  1061. #define I915_READ64(reg) readq(dev_priv->regs + (reg))
  1062. #define POSTING_READ(reg) (void)I915_READ(reg)
  1063. #define POSTING_READ16(reg) (void)I915_READ16(reg)
  1064. #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
  1065. I915_DEBUG_WRITE)
  1066. #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
  1067. I915_DEBUG_WRITE))
  1068. #define BEGIN_LP_RING(n) \
  1069. intel_ring_begin(&dev_priv->render_ring, (n))
  1070. #define OUT_RING(x) \
  1071. intel_ring_emit(&dev_priv->render_ring, x)
  1072. #define ADVANCE_LP_RING() \
  1073. intel_ring_advance(&dev_priv->render_ring)
  1074. /**
  1075. * Reads a dword out of the status page, which is written to from the command
  1076. * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
  1077. * MI_STORE_DATA_IMM.
  1078. *
  1079. * The following dwords have a reserved meaning:
  1080. * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
  1081. * 0x04: ring 0 head pointer
  1082. * 0x05: ring 1 head pointer (915-class)
  1083. * 0x06: ring 2 head pointer (915-class)
  1084. * 0x10-0x1b: Context status DWords (GM45)
  1085. * 0x1f: Last written status offset. (GM45)
  1086. *
  1087. * The area from dword 0x20 to 0x3ff is available for driver usage.
  1088. */
  1089. #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
  1090. (dev_priv->render_ring.status_page.page_addr))[reg])
  1091. #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  1092. #define I915_GEM_HWS_INDEX 0x20
  1093. #define I915_BREADCRUMB_INDEX 0x21
  1094. #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
  1095. #define IS_I830(dev) ((dev)->pci_device == 0x3577)
  1096. #define IS_845G(dev) ((dev)->pci_device == 0x2562)
  1097. #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
  1098. #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
  1099. #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
  1100. #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
  1101. #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
  1102. #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
  1103. #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
  1104. #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
  1105. #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
  1106. #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
  1107. #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
  1108. #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
  1109. #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
  1110. #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
  1111. #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
  1112. #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
  1113. #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
  1114. #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
  1115. #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
  1116. #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
  1117. #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
  1118. #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
  1119. #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
  1120. #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
  1121. #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
  1122. #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
  1123. #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
  1124. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  1125. * rows, which changed the alignment requirements and fence programming.
  1126. */
  1127. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  1128. IS_I915GM(dev)))
  1129. #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  1130. #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
  1131. #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
  1132. #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
  1133. #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
  1134. #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
  1135. /* dsparb controlled by hw only */
  1136. #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  1137. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  1138. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  1139. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  1140. #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
  1141. #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
  1142. #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
  1143. #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
  1144. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1145. #define PRIMARY_RINGBUFFER_SIZE (128*1024)
  1146. #endif