tifm_sd.c 29 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Special thanks to Brad Campbell for extensive testing of this driver.
  11. *
  12. */
  13. #include <linux/tifm.h>
  14. #include <linux/mmc/protocol.h>
  15. #include <linux/mmc/host.h>
  16. #include <linux/highmem.h>
  17. #include <linux/scatterlist.h>
  18. #include <asm/io.h>
  19. #define DRIVER_NAME "tifm_sd"
  20. #define DRIVER_VERSION "0.8"
  21. static int no_dma = 0;
  22. static int fixed_timeout = 0;
  23. module_param(no_dma, bool, 0644);
  24. module_param(fixed_timeout, bool, 0644);
  25. /* Constants here are mostly from OMAP5912 datasheet */
  26. #define TIFM_MMCSD_RESET 0x0002
  27. #define TIFM_MMCSD_CLKMASK 0x03ff
  28. #define TIFM_MMCSD_POWER 0x0800
  29. #define TIFM_MMCSD_4BBUS 0x8000
  30. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  31. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  32. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  33. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  34. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  35. #define TIFM_MMCSD_READ 0x8000
  36. #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
  37. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  38. #define TIFM_MMCSD_CD 0x0002 /* card detect */
  39. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  40. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  41. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  42. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  43. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  44. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  45. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  46. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  47. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  48. #define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
  49. #define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
  50. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  51. #define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
  52. #define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
  53. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  54. #define TIFM_MMCSD_RSP_R0 0x0000
  55. #define TIFM_MMCSD_RSP_R1 0x0100
  56. #define TIFM_MMCSD_RSP_R2 0x0200
  57. #define TIFM_MMCSD_RSP_R3 0x0300
  58. #define TIFM_MMCSD_RSP_R4 0x0400
  59. #define TIFM_MMCSD_RSP_R5 0x0500
  60. #define TIFM_MMCSD_RSP_R6 0x0600
  61. #define TIFM_MMCSD_RSP_BUSY 0x0800
  62. #define TIFM_MMCSD_CMD_BC 0x0000
  63. #define TIFM_MMCSD_CMD_BCR 0x1000
  64. #define TIFM_MMCSD_CMD_AC 0x2000
  65. #define TIFM_MMCSD_CMD_ADTC 0x3000
  66. #define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
  67. enum {
  68. CMD_READY = 0x0001,
  69. FIFO_READY = 0x0002,
  70. BRS_READY = 0x0004,
  71. SCMD_ACTIVE = 0x0008,
  72. SCMD_READY = 0x0010,
  73. CARD_BUSY = 0x0020,
  74. DATA_CARRY = 0x0040
  75. };
  76. struct tifm_sd {
  77. struct tifm_dev *dev;
  78. unsigned short eject:1,
  79. open_drain:1,
  80. no_dma:1;
  81. unsigned short cmd_flags;
  82. unsigned int clk_freq;
  83. unsigned int clk_div;
  84. unsigned long timeout_jiffies;
  85. struct tasklet_struct finish_tasklet;
  86. struct timer_list timer;
  87. struct mmc_request *req;
  88. int sg_len;
  89. int sg_pos;
  90. unsigned int block_pos;
  91. struct scatterlist bounce_buf;
  92. unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
  93. };
  94. /* for some reason, host won't respond correctly to readw/writew */
  95. static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
  96. unsigned int off, unsigned int cnt)
  97. {
  98. struct tifm_dev *sock = host->dev;
  99. unsigned char *buf;
  100. unsigned int pos = 0, val;
  101. buf = kmap_atomic(pg, KM_BIO_DST_IRQ) + off;
  102. if (host->cmd_flags & DATA_CARRY) {
  103. buf[pos++] = host->bounce_buf_data[0];
  104. host->cmd_flags &= ~DATA_CARRY;
  105. }
  106. while (pos < cnt) {
  107. val = readl(sock->addr + SOCK_MMCSD_DATA);
  108. buf[pos++] = val & 0xff;
  109. if (pos == cnt) {
  110. host->bounce_buf_data[0] = (val >> 8) & 0xff;
  111. host->cmd_flags |= DATA_CARRY;
  112. break;
  113. }
  114. buf[pos++] = (val >> 8) & 0xff;
  115. }
  116. kunmap_atomic(buf - off, KM_BIO_DST_IRQ);
  117. }
  118. static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
  119. unsigned int off, unsigned int cnt)
  120. {
  121. struct tifm_dev *sock = host->dev;
  122. unsigned char *buf;
  123. unsigned int pos = 0, val;
  124. buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + off;
  125. if (host->cmd_flags & DATA_CARRY) {
  126. val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
  127. writel(val, sock->addr + SOCK_MMCSD_DATA);
  128. host->cmd_flags &= ~DATA_CARRY;
  129. }
  130. while (pos < cnt) {
  131. val = buf[pos++];
  132. if (pos == cnt) {
  133. host->bounce_buf_data[0] = val & 0xff;
  134. host->cmd_flags |= DATA_CARRY;
  135. break;
  136. }
  137. val |= (buf[pos++] << 8) & 0xff00;
  138. writel(val, sock->addr + SOCK_MMCSD_DATA);
  139. }
  140. kunmap_atomic(buf - off, KM_BIO_SRC_IRQ);
  141. }
  142. static void tifm_sd_transfer_data(struct tifm_sd *host)
  143. {
  144. struct mmc_data *r_data = host->req->cmd->data;
  145. struct scatterlist *sg = r_data->sg;
  146. unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
  147. unsigned int p_off, p_cnt;
  148. struct page *pg;
  149. if (host->sg_pos == host->sg_len)
  150. return;
  151. while (t_size) {
  152. cnt = sg[host->sg_pos].length - host->block_pos;
  153. if (!cnt) {
  154. host->block_pos = 0;
  155. host->sg_pos++;
  156. if (host->sg_pos == host->sg_len) {
  157. if ((r_data->flags & MMC_DATA_WRITE)
  158. && DATA_CARRY)
  159. writel(host->bounce_buf_data[0],
  160. host->dev->addr
  161. + SOCK_MMCSD_DATA);
  162. return;
  163. }
  164. cnt = sg[host->sg_pos].length;
  165. }
  166. off = sg[host->sg_pos].offset + host->block_pos;
  167. pg = nth_page(sg[host->sg_pos].page, off >> PAGE_SHIFT);
  168. p_off = offset_in_page(off);
  169. p_cnt = PAGE_SIZE - p_off;
  170. p_cnt = min(p_cnt, cnt);
  171. p_cnt = min(p_cnt, t_size);
  172. if (r_data->flags & MMC_DATA_READ)
  173. tifm_sd_read_fifo(host, pg, p_off, p_cnt);
  174. else if (r_data->flags & MMC_DATA_WRITE)
  175. tifm_sd_write_fifo(host, pg, p_off, p_cnt);
  176. t_size -= p_cnt;
  177. host->block_pos += p_cnt;
  178. }
  179. }
  180. static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
  181. struct page *src, unsigned int src_off,
  182. unsigned int count)
  183. {
  184. unsigned char *src_buf = kmap_atomic(src, KM_BIO_SRC_IRQ) + src_off;
  185. unsigned char *dst_buf = kmap_atomic(dst, KM_BIO_DST_IRQ) + dst_off;
  186. memcpy(dst_buf, src_buf, count);
  187. kunmap_atomic(dst_buf - dst_off, KM_BIO_DST_IRQ);
  188. kunmap_atomic(src_buf - src_off, KM_BIO_SRC_IRQ);
  189. }
  190. static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
  191. {
  192. struct scatterlist *sg = r_data->sg;
  193. unsigned int t_size = r_data->blksz;
  194. unsigned int off, cnt;
  195. unsigned int p_off, p_cnt;
  196. struct page *pg;
  197. dev_dbg(&host->dev->dev, "bouncing block\n");
  198. while (t_size) {
  199. cnt = sg[host->sg_pos].length - host->block_pos;
  200. if (!cnt) {
  201. host->block_pos = 0;
  202. host->sg_pos++;
  203. if (host->sg_pos == host->sg_len)
  204. return;
  205. cnt = sg[host->sg_pos].length;
  206. }
  207. off = sg[host->sg_pos].offset + host->block_pos;
  208. pg = nth_page(sg[host->sg_pos].page, off >> PAGE_SHIFT);
  209. p_off = offset_in_page(off);
  210. p_cnt = PAGE_SIZE - p_off;
  211. p_cnt = min(p_cnt, cnt);
  212. p_cnt = min(p_cnt, t_size);
  213. if (r_data->flags & MMC_DATA_WRITE)
  214. tifm_sd_copy_page(host->bounce_buf.page,
  215. r_data->blksz - t_size,
  216. pg, p_off, p_cnt);
  217. else if (r_data->flags & MMC_DATA_READ)
  218. tifm_sd_copy_page(pg, p_off, host->bounce_buf.page,
  219. r_data->blksz - t_size, p_cnt);
  220. t_size -= p_cnt;
  221. host->block_pos += p_cnt;
  222. }
  223. }
  224. int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
  225. {
  226. struct tifm_dev *sock = host->dev;
  227. unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
  228. unsigned int dma_len, dma_blk_cnt, dma_off;
  229. struct scatterlist *sg = NULL;
  230. unsigned long flags;
  231. if (host->sg_pos == host->sg_len)
  232. return 1;
  233. if (host->cmd_flags & DATA_CARRY) {
  234. host->cmd_flags &= ~DATA_CARRY;
  235. local_irq_save(flags);
  236. tifm_sd_bounce_block(host, r_data);
  237. local_irq_restore(flags);
  238. if (host->sg_pos == host->sg_len)
  239. return 1;
  240. }
  241. dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
  242. if (!dma_len) {
  243. host->block_pos = 0;
  244. host->sg_pos++;
  245. if (host->sg_pos == host->sg_len)
  246. return 1;
  247. dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
  248. }
  249. if (dma_len < t_size) {
  250. dma_blk_cnt = dma_len / r_data->blksz;
  251. dma_off = host->block_pos;
  252. host->block_pos += dma_blk_cnt * r_data->blksz;
  253. } else {
  254. dma_blk_cnt = TIFM_DMA_TSIZE;
  255. dma_off = host->block_pos;
  256. host->block_pos += t_size;
  257. }
  258. if (dma_blk_cnt)
  259. sg = &r_data->sg[host->sg_pos];
  260. else if (dma_len) {
  261. if (r_data->flags & MMC_DATA_WRITE) {
  262. local_irq_save(flags);
  263. tifm_sd_bounce_block(host, r_data);
  264. local_irq_restore(flags);
  265. } else
  266. host->cmd_flags |= DATA_CARRY;
  267. sg = &host->bounce_buf;
  268. dma_off = 0;
  269. dma_blk_cnt = 1;
  270. } else
  271. return 1;
  272. dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
  273. writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
  274. if (r_data->flags & MMC_DATA_WRITE)
  275. writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
  276. sock->addr + SOCK_DMA_CONTROL);
  277. else
  278. writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
  279. sock->addr + SOCK_DMA_CONTROL);
  280. return 0;
  281. }
  282. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  283. {
  284. unsigned int rc = 0;
  285. switch (mmc_resp_type(cmd)) {
  286. case MMC_RSP_NONE:
  287. rc |= TIFM_MMCSD_RSP_R0;
  288. break;
  289. case MMC_RSP_R1B:
  290. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  291. case MMC_RSP_R1:
  292. rc |= TIFM_MMCSD_RSP_R1;
  293. break;
  294. case MMC_RSP_R2:
  295. rc |= TIFM_MMCSD_RSP_R2;
  296. break;
  297. case MMC_RSP_R3:
  298. rc |= TIFM_MMCSD_RSP_R3;
  299. break;
  300. default:
  301. BUG();
  302. }
  303. switch (mmc_cmd_type(cmd)) {
  304. case MMC_CMD_BC:
  305. rc |= TIFM_MMCSD_CMD_BC;
  306. break;
  307. case MMC_CMD_BCR:
  308. rc |= TIFM_MMCSD_CMD_BCR;
  309. break;
  310. case MMC_CMD_AC:
  311. rc |= TIFM_MMCSD_CMD_AC;
  312. break;
  313. case MMC_CMD_ADTC:
  314. rc |= TIFM_MMCSD_CMD_ADTC;
  315. break;
  316. default:
  317. BUG();
  318. }
  319. return rc;
  320. }
  321. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  322. {
  323. struct tifm_dev *sock = host->dev;
  324. unsigned int cmd_mask = tifm_sd_op_flags(cmd);
  325. if (host->open_drain)
  326. cmd_mask |= TIFM_MMCSD_ODTO;
  327. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  328. cmd_mask |= TIFM_MMCSD_READ;
  329. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  330. cmd->opcode, cmd->arg, cmd_mask);
  331. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  332. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  333. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  334. }
  335. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  336. {
  337. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  338. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  339. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  340. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  341. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  342. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  343. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  344. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  345. }
  346. static void tifm_sd_check_status(struct tifm_sd *host)
  347. {
  348. struct tifm_dev *sock = host->dev;
  349. struct mmc_command *cmd = host->req->cmd;
  350. if (cmd->error != MMC_ERR_NONE)
  351. goto finish_request;
  352. if (!(host->cmd_flags & CMD_READY))
  353. return;
  354. if (cmd->data) {
  355. if (cmd->data->error != MMC_ERR_NONE) {
  356. if ((host->cmd_flags & SCMD_ACTIVE)
  357. && !(host->cmd_flags & SCMD_READY))
  358. return;
  359. goto finish_request;
  360. }
  361. if (!(host->cmd_flags & BRS_READY))
  362. return;
  363. if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
  364. return;
  365. if (cmd->data->flags & MMC_DATA_WRITE) {
  366. if (host->req->stop) {
  367. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  368. host->cmd_flags |= SCMD_ACTIVE;
  369. writel(TIFM_MMCSD_EOFB
  370. | readl(sock->addr
  371. + SOCK_MMCSD_INT_ENABLE),
  372. sock->addr
  373. + SOCK_MMCSD_INT_ENABLE);
  374. tifm_sd_exec(host, host->req->stop);
  375. return;
  376. } else {
  377. if (!(host->cmd_flags & SCMD_READY)
  378. || (host->cmd_flags & CARD_BUSY))
  379. return;
  380. writel((~TIFM_MMCSD_EOFB)
  381. & readl(sock->addr
  382. + SOCK_MMCSD_INT_ENABLE),
  383. sock->addr
  384. + SOCK_MMCSD_INT_ENABLE);
  385. }
  386. } else {
  387. if (host->cmd_flags & CARD_BUSY)
  388. return;
  389. writel((~TIFM_MMCSD_EOFB)
  390. & readl(sock->addr
  391. + SOCK_MMCSD_INT_ENABLE),
  392. sock->addr + SOCK_MMCSD_INT_ENABLE);
  393. }
  394. } else {
  395. if (host->req->stop) {
  396. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  397. host->cmd_flags |= SCMD_ACTIVE;
  398. tifm_sd_exec(host, host->req->stop);
  399. return;
  400. } else {
  401. if (!(host->cmd_flags & SCMD_READY))
  402. return;
  403. }
  404. }
  405. }
  406. }
  407. finish_request:
  408. tasklet_schedule(&host->finish_tasklet);
  409. }
  410. /* Called from interrupt handler */
  411. static void tifm_sd_data_event(struct tifm_dev *sock)
  412. {
  413. struct tifm_sd *host;
  414. unsigned int fifo_status = 0;
  415. struct mmc_data *r_data = NULL;
  416. spin_lock(&sock->lock);
  417. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  418. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  419. dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
  420. fifo_status, host->cmd_flags);
  421. if (host->req) {
  422. r_data = host->req->cmd->data;
  423. if (r_data && (fifo_status & TIFM_FIFO_READY)) {
  424. if (tifm_sd_set_dma_data(host, r_data)) {
  425. host->cmd_flags |= FIFO_READY;
  426. tifm_sd_check_status(host);
  427. }
  428. }
  429. }
  430. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  431. spin_unlock(&sock->lock);
  432. }
  433. /* Called from interrupt handler */
  434. static void tifm_sd_card_event(struct tifm_dev *sock)
  435. {
  436. struct tifm_sd *host;
  437. unsigned int host_status = 0;
  438. int cmd_error = MMC_ERR_NONE;
  439. struct mmc_command *cmd = NULL;
  440. unsigned long flags;
  441. spin_lock(&sock->lock);
  442. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  443. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  444. dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
  445. host_status, host->cmd_flags);
  446. if (host->req) {
  447. cmd = host->req->cmd;
  448. if (host_status & TIFM_MMCSD_ERRMASK) {
  449. writel(host_status & TIFM_MMCSD_ERRMASK,
  450. sock->addr + SOCK_MMCSD_STATUS);
  451. if (host_status & TIFM_MMCSD_CTO)
  452. cmd_error = MMC_ERR_TIMEOUT;
  453. else if (host_status & TIFM_MMCSD_CCRC)
  454. cmd_error = MMC_ERR_BADCRC;
  455. if (cmd->data) {
  456. if (host_status & TIFM_MMCSD_DTO)
  457. cmd->data->error = MMC_ERR_TIMEOUT;
  458. else if (host_status & TIFM_MMCSD_DCRC)
  459. cmd->data->error = MMC_ERR_BADCRC;
  460. }
  461. writel(TIFM_FIFO_INT_SETALL,
  462. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  463. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  464. if (host->req->stop) {
  465. if (host->cmd_flags & SCMD_ACTIVE) {
  466. host->req->stop->error = cmd_error;
  467. host->cmd_flags |= SCMD_READY;
  468. } else {
  469. cmd->error = cmd_error;
  470. host->cmd_flags |= SCMD_ACTIVE;
  471. tifm_sd_exec(host, host->req->stop);
  472. goto done;
  473. }
  474. } else
  475. cmd->error = cmd_error;
  476. } else {
  477. if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
  478. if (!(host->cmd_flags & CMD_READY)) {
  479. host->cmd_flags |= CMD_READY;
  480. tifm_sd_fetch_resp(cmd, sock);
  481. } else if (host->cmd_flags & SCMD_ACTIVE) {
  482. host->cmd_flags |= SCMD_READY;
  483. tifm_sd_fetch_resp(host->req->stop,
  484. sock);
  485. }
  486. }
  487. if (host_status & TIFM_MMCSD_BRS)
  488. host->cmd_flags |= BRS_READY;
  489. }
  490. if (host->no_dma && cmd->data) {
  491. if (host_status & TIFM_MMCSD_AE)
  492. writel(host_status & TIFM_MMCSD_AE,
  493. sock->addr + SOCK_MMCSD_STATUS);
  494. if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
  495. | TIFM_MMCSD_BRS)) {
  496. local_irq_save(flags);
  497. tifm_sd_transfer_data(host);
  498. local_irq_restore(flags);
  499. host_status &= ~TIFM_MMCSD_AE;
  500. }
  501. }
  502. if (host_status & TIFM_MMCSD_EOFB)
  503. host->cmd_flags &= ~CARD_BUSY;
  504. else if (host_status & TIFM_MMCSD_CB)
  505. host->cmd_flags |= CARD_BUSY;
  506. tifm_sd_check_status(host);
  507. }
  508. done:
  509. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  510. spin_unlock(&sock->lock);
  511. }
  512. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  513. struct mmc_data *data)
  514. {
  515. struct tifm_dev *sock = host->dev;
  516. unsigned int data_timeout = data->timeout_clks;
  517. if (fixed_timeout)
  518. return;
  519. data_timeout += data->timeout_ns /
  520. ((1000000000UL / host->clk_freq) * host->clk_div);
  521. if (data_timeout < 0xffff) {
  522. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  523. writel((~TIFM_MMCSD_DPE)
  524. & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  525. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  526. } else {
  527. data_timeout = (data_timeout >> 10) + 1;
  528. if (data_timeout > 0xffff)
  529. data_timeout = 0; /* set to unlimited */
  530. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  531. writel(TIFM_MMCSD_DPE
  532. | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  533. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  534. }
  535. }
  536. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  537. {
  538. struct tifm_sd *host = mmc_priv(mmc);
  539. struct tifm_dev *sock = host->dev;
  540. unsigned long flags;
  541. struct mmc_data *r_data = mrq->cmd->data;
  542. spin_lock_irqsave(&sock->lock, flags);
  543. if (host->eject) {
  544. spin_unlock_irqrestore(&sock->lock, flags);
  545. goto err_out;
  546. }
  547. if (host->req) {
  548. printk(KERN_ERR "%s : unfinished request detected\n",
  549. sock->dev.bus_id);
  550. spin_unlock_irqrestore(&sock->lock, flags);
  551. goto err_out;
  552. }
  553. host->cmd_flags = 0;
  554. host->block_pos = 0;
  555. host->sg_pos = 0;
  556. if (r_data) {
  557. tifm_sd_set_data_timeout(host, r_data);
  558. if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
  559. writel(TIFM_MMCSD_EOFB
  560. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  561. sock->addr + SOCK_MMCSD_INT_ENABLE);
  562. if (host->no_dma) {
  563. writel(TIFM_MMCSD_BUFINT
  564. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  565. sock->addr + SOCK_MMCSD_INT_ENABLE);
  566. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
  567. | (TIFM_MMCSD_FIFO_SIZE - 1),
  568. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  569. host->sg_len = r_data->sg_len;
  570. } else {
  571. sg_init_one(&host->bounce_buf, host->bounce_buf_data,
  572. r_data->blksz);
  573. if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
  574. r_data->flags & MMC_DATA_WRITE
  575. ? PCI_DMA_TODEVICE
  576. : PCI_DMA_FROMDEVICE)) {
  577. printk(KERN_ERR "%s : scatterlist map failed\n",
  578. sock->dev.bus_id);
  579. spin_unlock_irqrestore(&sock->lock, flags);
  580. goto err_out;
  581. }
  582. host->sg_len = tifm_map_sg(sock, r_data->sg,
  583. r_data->sg_len,
  584. r_data->flags
  585. & MMC_DATA_WRITE
  586. ? PCI_DMA_TODEVICE
  587. : PCI_DMA_FROMDEVICE);
  588. if (host->sg_len < 1) {
  589. printk(KERN_ERR "%s : scatterlist map failed\n",
  590. sock->dev.bus_id);
  591. tifm_unmap_sg(sock, &host->bounce_buf, 1,
  592. r_data->flags & MMC_DATA_WRITE
  593. ? PCI_DMA_TODEVICE
  594. : PCI_DMA_FROMDEVICE);
  595. spin_unlock_irqrestore(&sock->lock, flags);
  596. goto err_out;
  597. }
  598. writel(TIFM_FIFO_INT_SETALL,
  599. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  600. writel(ilog2(r_data->blksz) - 2,
  601. sock->addr + SOCK_FIFO_PAGE_SIZE);
  602. writel(TIFM_FIFO_ENABLE,
  603. sock->addr + SOCK_FIFO_CONTROL);
  604. writel(TIFM_FIFO_INTMASK,
  605. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  606. if (r_data->flags & MMC_DATA_WRITE)
  607. writel(TIFM_MMCSD_TXDE,
  608. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  609. else
  610. writel(TIFM_MMCSD_RXDE,
  611. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  612. tifm_sd_set_dma_data(host, r_data);
  613. }
  614. writel(r_data->blocks - 1,
  615. sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  616. writel(r_data->blksz - 1,
  617. sock->addr + SOCK_MMCSD_BLOCK_LEN);
  618. }
  619. host->req = mrq;
  620. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  621. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  622. sock->addr + SOCK_CONTROL);
  623. tifm_sd_exec(host, mrq->cmd);
  624. spin_unlock_irqrestore(&sock->lock, flags);
  625. return;
  626. err_out:
  627. mrq->cmd->error = MMC_ERR_TIMEOUT;
  628. mmc_request_done(mmc, mrq);
  629. }
  630. static void tifm_sd_end_cmd(unsigned long data)
  631. {
  632. struct tifm_sd *host = (struct tifm_sd*)data;
  633. struct tifm_dev *sock = host->dev;
  634. struct mmc_host *mmc = tifm_get_drvdata(sock);
  635. struct mmc_request *mrq;
  636. struct mmc_data *r_data = NULL;
  637. unsigned long flags;
  638. spin_lock_irqsave(&sock->lock, flags);
  639. del_timer(&host->timer);
  640. mrq = host->req;
  641. host->req = NULL;
  642. if (!mrq) {
  643. printk(KERN_ERR " %s : no request to complete?\n",
  644. sock->dev.bus_id);
  645. spin_unlock_irqrestore(&sock->lock, flags);
  646. return;
  647. }
  648. r_data = mrq->cmd->data;
  649. if (r_data) {
  650. if (host->no_dma) {
  651. writel((~TIFM_MMCSD_BUFINT)
  652. & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  653. sock->addr + SOCK_MMCSD_INT_ENABLE);
  654. } else {
  655. tifm_unmap_sg(sock, &host->bounce_buf, 1,
  656. (r_data->flags & MMC_DATA_WRITE)
  657. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  658. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  659. (r_data->flags & MMC_DATA_WRITE)
  660. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  661. }
  662. r_data->bytes_xfered = r_data->blocks
  663. - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  664. r_data->bytes_xfered *= r_data->blksz;
  665. r_data->bytes_xfered += r_data->blksz
  666. - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  667. }
  668. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  669. sock->addr + SOCK_CONTROL);
  670. spin_unlock_irqrestore(&sock->lock, flags);
  671. mmc_request_done(mmc, mrq);
  672. }
  673. static void tifm_sd_abort(unsigned long data)
  674. {
  675. struct tifm_sd *host = (struct tifm_sd*)data;
  676. printk(KERN_ERR
  677. "%s : card failed to respond for a long period of time "
  678. "(%x, %x)\n",
  679. host->dev->dev.bus_id, host->req->cmd->opcode, host->cmd_flags);
  680. tifm_eject(host->dev);
  681. }
  682. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  683. {
  684. struct tifm_sd *host = mmc_priv(mmc);
  685. struct tifm_dev *sock = host->dev;
  686. unsigned int clk_div1, clk_div2;
  687. unsigned long flags;
  688. spin_lock_irqsave(&sock->lock, flags);
  689. dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
  690. "chip_select = %x, power_mode = %x, bus_width = %x\n",
  691. ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
  692. ios->power_mode, ios->bus_width);
  693. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  694. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  695. sock->addr + SOCK_MMCSD_CONFIG);
  696. } else {
  697. writel((~TIFM_MMCSD_4BBUS)
  698. & readl(sock->addr + SOCK_MMCSD_CONFIG),
  699. sock->addr + SOCK_MMCSD_CONFIG);
  700. }
  701. if (ios->clock) {
  702. clk_div1 = 20000000 / ios->clock;
  703. if (!clk_div1)
  704. clk_div1 = 1;
  705. clk_div2 = 24000000 / ios->clock;
  706. if (!clk_div2)
  707. clk_div2 = 1;
  708. if ((20000000 / clk_div1) > ios->clock)
  709. clk_div1++;
  710. if ((24000000 / clk_div2) > ios->clock)
  711. clk_div2++;
  712. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  713. host->clk_freq = 20000000;
  714. host->clk_div = clk_div1;
  715. writel((~TIFM_CTRL_FAST_CLK)
  716. & readl(sock->addr + SOCK_CONTROL),
  717. sock->addr + SOCK_CONTROL);
  718. } else {
  719. host->clk_freq = 24000000;
  720. host->clk_div = clk_div2;
  721. writel(TIFM_CTRL_FAST_CLK
  722. | readl(sock->addr + SOCK_CONTROL),
  723. sock->addr + SOCK_CONTROL);
  724. }
  725. } else {
  726. host->clk_div = 0;
  727. }
  728. host->clk_div &= TIFM_MMCSD_CLKMASK;
  729. writel(host->clk_div
  730. | ((~TIFM_MMCSD_CLKMASK)
  731. & readl(sock->addr + SOCK_MMCSD_CONFIG)),
  732. sock->addr + SOCK_MMCSD_CONFIG);
  733. host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
  734. /* chip_select : maybe later */
  735. //vdd
  736. //power is set before probe / after remove
  737. spin_unlock_irqrestore(&sock->lock, flags);
  738. }
  739. static int tifm_sd_ro(struct mmc_host *mmc)
  740. {
  741. int rc = 0;
  742. struct tifm_sd *host = mmc_priv(mmc);
  743. struct tifm_dev *sock = host->dev;
  744. unsigned long flags;
  745. spin_lock_irqsave(&sock->lock, flags);
  746. if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
  747. rc = 1;
  748. spin_unlock_irqrestore(&sock->lock, flags);
  749. return rc;
  750. }
  751. static const struct mmc_host_ops tifm_sd_ops = {
  752. .request = tifm_sd_request,
  753. .set_ios = tifm_sd_ios,
  754. .get_ro = tifm_sd_ro
  755. };
  756. static int tifm_sd_initialize_host(struct tifm_sd *host)
  757. {
  758. int rc;
  759. unsigned int host_status = 0;
  760. struct tifm_dev *sock = host->dev;
  761. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  762. mmiowb();
  763. host->clk_div = 61;
  764. host->clk_freq = 20000000;
  765. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  766. writel(host->clk_div | TIFM_MMCSD_POWER,
  767. sock->addr + SOCK_MMCSD_CONFIG);
  768. /* wait up to 0.51 sec for reset */
  769. for (rc = 32; rc <= 256; rc <<= 1) {
  770. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  771. rc = 0;
  772. break;
  773. }
  774. msleep(rc);
  775. }
  776. if (rc) {
  777. printk(KERN_ERR "%s : controller failed to reset\n",
  778. sock->dev.bus_id);
  779. return -ENODEV;
  780. }
  781. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  782. writel(host->clk_div | TIFM_MMCSD_POWER,
  783. sock->addr + SOCK_MMCSD_CONFIG);
  784. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  785. // command timeout fixed to 64 clocks for now
  786. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
  787. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  788. for (rc = 16; rc <= 64; rc <<= 1) {
  789. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  790. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  791. if (!(host_status & TIFM_MMCSD_ERRMASK)
  792. && (host_status & TIFM_MMCSD_EOC)) {
  793. rc = 0;
  794. break;
  795. }
  796. msleep(rc);
  797. }
  798. if (rc) {
  799. printk(KERN_ERR
  800. "%s : card not ready - probe failed on initialization\n",
  801. sock->dev.bus_id);
  802. return -ENODEV;
  803. }
  804. writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
  805. | TIFM_MMCSD_ERRMASK,
  806. sock->addr + SOCK_MMCSD_INT_ENABLE);
  807. mmiowb();
  808. return 0;
  809. }
  810. static int tifm_sd_probe(struct tifm_dev *sock)
  811. {
  812. struct mmc_host *mmc;
  813. struct tifm_sd *host;
  814. int rc = -EIO;
  815. if (!(TIFM_SOCK_STATE_OCCUPIED
  816. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  817. printk(KERN_WARNING "%s : card gone, unexpectedly\n",
  818. sock->dev.bus_id);
  819. return rc;
  820. }
  821. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  822. if (!mmc)
  823. return -ENOMEM;
  824. host = mmc_priv(mmc);
  825. host->no_dma = no_dma;
  826. tifm_set_drvdata(sock, mmc);
  827. host->dev = sock;
  828. host->timeout_jiffies = msecs_to_jiffies(1000);
  829. tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
  830. (unsigned long)host);
  831. setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
  832. mmc->ops = &tifm_sd_ops;
  833. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  834. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
  835. mmc->f_min = 20000000 / 60;
  836. mmc->f_max = 24000000;
  837. mmc->max_blk_count = 2048;
  838. mmc->max_hw_segs = mmc->max_blk_count;
  839. mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
  840. mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
  841. mmc->max_req_size = mmc->max_seg_size;
  842. mmc->max_phys_segs = mmc->max_hw_segs;
  843. sock->card_event = tifm_sd_card_event;
  844. sock->data_event = tifm_sd_data_event;
  845. rc = tifm_sd_initialize_host(host);
  846. if (!rc)
  847. rc = mmc_add_host(mmc);
  848. if (!rc)
  849. return 0;
  850. mmc_free_host(mmc);
  851. return rc;
  852. }
  853. static void tifm_sd_remove(struct tifm_dev *sock)
  854. {
  855. struct mmc_host *mmc = tifm_get_drvdata(sock);
  856. struct tifm_sd *host = mmc_priv(mmc);
  857. unsigned long flags;
  858. spin_lock_irqsave(&sock->lock, flags);
  859. host->eject = 1;
  860. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  861. mmiowb();
  862. spin_unlock_irqrestore(&sock->lock, flags);
  863. tasklet_kill(&host->finish_tasklet);
  864. spin_lock_irqsave(&sock->lock, flags);
  865. if (host->req) {
  866. writel(TIFM_FIFO_INT_SETALL,
  867. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  868. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  869. host->req->cmd->error = MMC_ERR_TIMEOUT;
  870. if (host->req->stop)
  871. host->req->stop->error = MMC_ERR_TIMEOUT;
  872. tasklet_schedule(&host->finish_tasklet);
  873. }
  874. spin_unlock_irqrestore(&sock->lock, flags);
  875. mmc_remove_host(mmc);
  876. dev_dbg(&sock->dev, "after remove\n");
  877. /* The meaning of the bit majority in this constant is unknown. */
  878. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  879. sock->addr + SOCK_CONTROL);
  880. mmc_free_host(mmc);
  881. }
  882. #ifdef CONFIG_PM
  883. static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
  884. {
  885. struct mmc_host *mmc = tifm_get_drvdata(sock);
  886. int rc;
  887. rc = mmc_suspend_host(mmc, state);
  888. /* The meaning of the bit majority in this constant is unknown. */
  889. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  890. sock->addr + SOCK_CONTROL);
  891. return rc;
  892. }
  893. static int tifm_sd_resume(struct tifm_dev *sock)
  894. {
  895. struct mmc_host *mmc = tifm_get_drvdata(sock);
  896. struct tifm_sd *host = mmc_priv(mmc);
  897. int rc;
  898. rc = tifm_sd_initialize_host(host);
  899. dev_dbg(&sock->dev, "resume initialize %d\n", rc);
  900. if (rc)
  901. host->eject = 1;
  902. else
  903. rc = mmc_resume_host(mmc);
  904. return rc;
  905. }
  906. #else
  907. #define tifm_sd_suspend NULL
  908. #define tifm_sd_resume NULL
  909. #endif /* CONFIG_PM */
  910. static struct tifm_device_id tifm_sd_id_tbl[] = {
  911. { TIFM_TYPE_SD }, { }
  912. };
  913. static struct tifm_driver tifm_sd_driver = {
  914. .driver = {
  915. .name = DRIVER_NAME,
  916. .owner = THIS_MODULE
  917. },
  918. .id_table = tifm_sd_id_tbl,
  919. .probe = tifm_sd_probe,
  920. .remove = tifm_sd_remove,
  921. .suspend = tifm_sd_suspend,
  922. .resume = tifm_sd_resume
  923. };
  924. static int __init tifm_sd_init(void)
  925. {
  926. return tifm_register_driver(&tifm_sd_driver);
  927. }
  928. static void __exit tifm_sd_exit(void)
  929. {
  930. tifm_unregister_driver(&tifm_sd_driver);
  931. }
  932. MODULE_AUTHOR("Alex Dubov");
  933. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  934. MODULE_LICENSE("GPL");
  935. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  936. MODULE_VERSION(DRIVER_VERSION);
  937. module_init(tifm_sd_init);
  938. module_exit(tifm_sd_exit);