iwl-agn.c 112 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. #include "iwl-agn.h"
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /*
  59. * module name, copyright, version, etc.
  60. */
  61. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  62. #ifdef CONFIG_IWLWIFI_DEBUG
  63. #define VD "d"
  64. #else
  65. #define VD
  66. #endif
  67. #define DRV_VERSION IWLWIFI_VERSION VD
  68. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  69. MODULE_VERSION(DRV_VERSION);
  70. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  71. MODULE_LICENSE("GPL");
  72. MODULE_ALIAS("iwl4965");
  73. /**
  74. * iwl_commit_rxon - commit staging_rxon to hardware
  75. *
  76. * The RXON command in staging_rxon is committed to the hardware and
  77. * the active_rxon structure is updated with the new data. This
  78. * function correctly transitions out of the RXON_ASSOC_MSK state if
  79. * a HW tune is required based on the RXON structure changes.
  80. */
  81. int iwl_commit_rxon(struct iwl_priv *priv)
  82. {
  83. /* cast away the const for active_rxon in this function */
  84. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  85. int ret;
  86. bool new_assoc =
  87. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  88. if (!iwl_is_alive(priv))
  89. return -EBUSY;
  90. /* always get timestamp with Rx frame */
  91. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  92. ret = iwl_check_rxon_cmd(priv);
  93. if (ret) {
  94. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  95. return -EINVAL;
  96. }
  97. /*
  98. * receive commit_rxon request
  99. * abort any previous channel switch if still in process
  100. */
  101. if (priv->switch_rxon.switch_in_progress &&
  102. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  103. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  104. le16_to_cpu(priv->switch_rxon.channel));
  105. priv->switch_rxon.switch_in_progress = false;
  106. }
  107. /* If we don't need to send a full RXON, we can use
  108. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  109. * and other flags for the current radio configuration. */
  110. if (!iwl_full_rxon_required(priv)) {
  111. ret = iwl_send_rxon_assoc(priv);
  112. if (ret) {
  113. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  114. return ret;
  115. }
  116. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  117. iwl_print_rx_config_cmd(priv);
  118. return 0;
  119. }
  120. /* If we are currently associated and the new config requires
  121. * an RXON_ASSOC and the new config wants the associated mask enabled,
  122. * we must clear the associated from the active configuration
  123. * before we apply the new config */
  124. if (iwl_is_associated(priv) && new_assoc) {
  125. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  126. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  127. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  128. sizeof(struct iwl_rxon_cmd),
  129. &priv->active_rxon);
  130. /* If the mask clearing failed then we set
  131. * active_rxon back to what it was previously */
  132. if (ret) {
  133. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  134. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  135. return ret;
  136. }
  137. iwl_clear_ucode_stations(priv, false);
  138. iwl_restore_stations(priv);
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode so restoration of
  150. * stations is needed after it (the RXON command) completes
  151. */
  152. if (!new_assoc) {
  153. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  154. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  155. if (ret) {
  156. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  157. return ret;
  158. }
  159. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. iwl_clear_ucode_stations(priv, false);
  162. iwl_restore_stations(priv);
  163. }
  164. priv->start_calib = 0;
  165. if (new_assoc) {
  166. /*
  167. * allow CTS-to-self if possible for new association.
  168. * this is relevant only for 5000 series and up,
  169. * but will not damage 4965
  170. */
  171. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  172. /* Apply the new configuration
  173. * RXON assoc doesn't clear the station table in uCode,
  174. */
  175. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  176. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  177. if (ret) {
  178. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  179. return ret;
  180. }
  181. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  182. }
  183. iwl_print_rx_config_cmd(priv);
  184. iwl_init_sensitivity(priv);
  185. /* If we issue a new RXON command which required a tune then we must
  186. * send a new TXPOWER command or we won't be able to Tx any frames */
  187. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  188. if (ret) {
  189. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  190. return ret;
  191. }
  192. return 0;
  193. }
  194. void iwl_update_chain_flags(struct iwl_priv *priv)
  195. {
  196. if (priv->cfg->ops->hcmd->set_rxon_chain)
  197. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  198. iwlcore_commit_rxon(priv);
  199. }
  200. static void iwl_clear_free_frames(struct iwl_priv *priv)
  201. {
  202. struct list_head *element;
  203. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  204. priv->frames_count);
  205. while (!list_empty(&priv->free_frames)) {
  206. element = priv->free_frames.next;
  207. list_del(element);
  208. kfree(list_entry(element, struct iwl_frame, list));
  209. priv->frames_count--;
  210. }
  211. if (priv->frames_count) {
  212. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  213. priv->frames_count);
  214. priv->frames_count = 0;
  215. }
  216. }
  217. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  218. {
  219. struct iwl_frame *frame;
  220. struct list_head *element;
  221. if (list_empty(&priv->free_frames)) {
  222. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  223. if (!frame) {
  224. IWL_ERR(priv, "Could not allocate frame!\n");
  225. return NULL;
  226. }
  227. priv->frames_count++;
  228. return frame;
  229. }
  230. element = priv->free_frames.next;
  231. list_del(element);
  232. return list_entry(element, struct iwl_frame, list);
  233. }
  234. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  235. {
  236. memset(frame, 0, sizeof(*frame));
  237. list_add(&frame->list, &priv->free_frames);
  238. }
  239. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  240. struct ieee80211_hdr *hdr,
  241. int left)
  242. {
  243. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  244. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  245. (priv->iw_mode != NL80211_IFTYPE_AP)))
  246. return 0;
  247. if (priv->ibss_beacon->len > left)
  248. return 0;
  249. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  250. return priv->ibss_beacon->len;
  251. }
  252. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  253. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  254. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  255. u8 *beacon, u32 frame_size)
  256. {
  257. u16 tim_idx;
  258. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  259. /*
  260. * The index is relative to frame start but we start looking at the
  261. * variable-length part of the beacon.
  262. */
  263. tim_idx = mgmt->u.beacon.variable - beacon;
  264. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  265. while ((tim_idx < (frame_size - 2)) &&
  266. (beacon[tim_idx] != WLAN_EID_TIM))
  267. tim_idx += beacon[tim_idx+1] + 2;
  268. /* If TIM field was found, set variables */
  269. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  270. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  271. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  272. } else
  273. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  274. }
  275. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  276. struct iwl_frame *frame)
  277. {
  278. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  279. u32 frame_size;
  280. u32 rate_flags;
  281. u32 rate;
  282. /*
  283. * We have to set up the TX command, the TX Beacon command, and the
  284. * beacon contents.
  285. */
  286. /* Initialize memory */
  287. tx_beacon_cmd = &frame->u.beacon;
  288. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  289. /* Set up TX beacon contents */
  290. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  291. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  292. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  293. return 0;
  294. /* Set up TX command fields */
  295. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  296. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  297. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  298. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  299. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  300. /* Set up TX beacon command fields */
  301. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  302. frame_size);
  303. /* Set up packet rate and flags */
  304. rate = iwl_rate_get_lowest_plcp(priv);
  305. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  306. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  307. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  308. rate_flags |= RATE_MCS_CCK_MSK;
  309. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  310. rate_flags);
  311. return sizeof(*tx_beacon_cmd) + frame_size;
  312. }
  313. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  314. {
  315. struct iwl_frame *frame;
  316. unsigned int frame_size;
  317. int rc;
  318. frame = iwl_get_free_frame(priv);
  319. if (!frame) {
  320. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  321. "command.\n");
  322. return -ENOMEM;
  323. }
  324. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  325. if (!frame_size) {
  326. IWL_ERR(priv, "Error configuring the beacon command\n");
  327. iwl_free_frame(priv, frame);
  328. return -EINVAL;
  329. }
  330. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  331. &frame->u.cmd[0]);
  332. iwl_free_frame(priv, frame);
  333. return rc;
  334. }
  335. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  336. {
  337. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  338. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  339. if (sizeof(dma_addr_t) > sizeof(u32))
  340. addr |=
  341. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  342. return addr;
  343. }
  344. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  345. {
  346. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  347. return le16_to_cpu(tb->hi_n_len) >> 4;
  348. }
  349. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  350. dma_addr_t addr, u16 len)
  351. {
  352. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  353. u16 hi_n_len = len << 4;
  354. put_unaligned_le32(addr, &tb->lo);
  355. if (sizeof(dma_addr_t) > sizeof(u32))
  356. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  357. tb->hi_n_len = cpu_to_le16(hi_n_len);
  358. tfd->num_tbs = idx + 1;
  359. }
  360. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  361. {
  362. return tfd->num_tbs & 0x1f;
  363. }
  364. /**
  365. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  366. * @priv - driver private data
  367. * @txq - tx queue
  368. *
  369. * Does NOT advance any TFD circular buffer read/write indexes
  370. * Does NOT free the TFD itself (which is within circular buffer)
  371. */
  372. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  373. {
  374. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  375. struct iwl_tfd *tfd;
  376. struct pci_dev *dev = priv->pci_dev;
  377. int index = txq->q.read_ptr;
  378. int i;
  379. int num_tbs;
  380. tfd = &tfd_tmp[index];
  381. /* Sanity check on number of chunks */
  382. num_tbs = iwl_tfd_get_num_tbs(tfd);
  383. if (num_tbs >= IWL_NUM_OF_TBS) {
  384. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  385. /* @todo issue fatal error, it is quite serious situation */
  386. return;
  387. }
  388. /* Unmap tx_cmd */
  389. if (num_tbs)
  390. pci_unmap_single(dev,
  391. pci_unmap_addr(&txq->meta[index], mapping),
  392. pci_unmap_len(&txq->meta[index], len),
  393. PCI_DMA_BIDIRECTIONAL);
  394. /* Unmap chunks, if any. */
  395. for (i = 1; i < num_tbs; i++) {
  396. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  397. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  398. if (txq->txb) {
  399. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  400. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  401. }
  402. }
  403. }
  404. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  405. struct iwl_tx_queue *txq,
  406. dma_addr_t addr, u16 len,
  407. u8 reset, u8 pad)
  408. {
  409. struct iwl_queue *q;
  410. struct iwl_tfd *tfd, *tfd_tmp;
  411. u32 num_tbs;
  412. q = &txq->q;
  413. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  414. tfd = &tfd_tmp[q->write_ptr];
  415. if (reset)
  416. memset(tfd, 0, sizeof(*tfd));
  417. num_tbs = iwl_tfd_get_num_tbs(tfd);
  418. /* Each TFD can point to a maximum 20 Tx buffers */
  419. if (num_tbs >= IWL_NUM_OF_TBS) {
  420. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  421. IWL_NUM_OF_TBS);
  422. return -EINVAL;
  423. }
  424. BUG_ON(addr & ~DMA_BIT_MASK(36));
  425. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  426. IWL_ERR(priv, "Unaligned address = %llx\n",
  427. (unsigned long long)addr);
  428. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  429. return 0;
  430. }
  431. /*
  432. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  433. * given Tx queue, and enable the DMA channel used for that queue.
  434. *
  435. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  436. * channels supported in hardware.
  437. */
  438. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  439. struct iwl_tx_queue *txq)
  440. {
  441. int txq_id = txq->q.id;
  442. /* Circular buffer (TFD queue in DRAM) physical base address */
  443. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  444. txq->q.dma_addr >> 8);
  445. return 0;
  446. }
  447. /******************************************************************************
  448. *
  449. * Generic RX handler implementations
  450. *
  451. ******************************************************************************/
  452. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  453. struct iwl_rx_mem_buffer *rxb)
  454. {
  455. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  456. struct iwl_alive_resp *palive;
  457. struct delayed_work *pwork;
  458. palive = &pkt->u.alive_frame;
  459. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  460. "0x%01X 0x%01X\n",
  461. palive->is_valid, palive->ver_type,
  462. palive->ver_subtype);
  463. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  464. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  465. memcpy(&priv->card_alive_init,
  466. &pkt->u.alive_frame,
  467. sizeof(struct iwl_init_alive_resp));
  468. pwork = &priv->init_alive_start;
  469. } else {
  470. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  471. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  472. sizeof(struct iwl_alive_resp));
  473. pwork = &priv->alive_start;
  474. }
  475. /* We delay the ALIVE response by 5ms to
  476. * give the HW RF Kill time to activate... */
  477. if (palive->is_valid == UCODE_VALID_OK)
  478. queue_delayed_work(priv->workqueue, pwork,
  479. msecs_to_jiffies(5));
  480. else
  481. IWL_WARN(priv, "uCode did not respond OK.\n");
  482. }
  483. static void iwl_bg_beacon_update(struct work_struct *work)
  484. {
  485. struct iwl_priv *priv =
  486. container_of(work, struct iwl_priv, beacon_update);
  487. struct sk_buff *beacon;
  488. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  489. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  490. if (!beacon) {
  491. IWL_ERR(priv, "update beacon failed\n");
  492. return;
  493. }
  494. mutex_lock(&priv->mutex);
  495. /* new beacon skb is allocated every time; dispose previous.*/
  496. if (priv->ibss_beacon)
  497. dev_kfree_skb(priv->ibss_beacon);
  498. priv->ibss_beacon = beacon;
  499. mutex_unlock(&priv->mutex);
  500. iwl_send_beacon_cmd(priv);
  501. }
  502. /**
  503. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  504. *
  505. * This callback is provided in order to send a statistics request.
  506. *
  507. * This timer function is continually reset to execute within
  508. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  509. * was received. We need to ensure we receive the statistics in order
  510. * to update the temperature used for calibrating the TXPOWER.
  511. */
  512. static void iwl_bg_statistics_periodic(unsigned long data)
  513. {
  514. struct iwl_priv *priv = (struct iwl_priv *)data;
  515. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  516. return;
  517. /* dont send host command if rf-kill is on */
  518. if (!iwl_is_ready_rf(priv))
  519. return;
  520. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  521. }
  522. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  523. u32 start_idx, u32 num_events,
  524. u32 mode)
  525. {
  526. u32 i;
  527. u32 ptr; /* SRAM byte address of log data */
  528. u32 ev, time, data; /* event log data */
  529. unsigned long reg_flags;
  530. if (mode == 0)
  531. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  532. else
  533. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  534. /* Make sure device is powered up for SRAM reads */
  535. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  536. if (iwl_grab_nic_access(priv)) {
  537. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  538. return;
  539. }
  540. /* Set starting address; reads will auto-increment */
  541. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  542. rmb();
  543. /*
  544. * "time" is actually "data" for mode 0 (no timestamp).
  545. * place event id # at far right for easier visual parsing.
  546. */
  547. for (i = 0; i < num_events; i++) {
  548. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  549. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  550. if (mode == 0) {
  551. trace_iwlwifi_dev_ucode_cont_event(priv,
  552. 0, time, ev);
  553. } else {
  554. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  555. trace_iwlwifi_dev_ucode_cont_event(priv,
  556. time, data, ev);
  557. }
  558. }
  559. /* Allow device to power down */
  560. iwl_release_nic_access(priv);
  561. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  562. }
  563. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  564. {
  565. u32 capacity; /* event log capacity in # entries */
  566. u32 base; /* SRAM byte address of event log header */
  567. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  568. u32 num_wraps; /* # times uCode wrapped to top of log */
  569. u32 next_entry; /* index of next entry to be written by uCode */
  570. if (priv->ucode_type == UCODE_INIT)
  571. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  572. else
  573. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  574. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  575. capacity = iwl_read_targ_mem(priv, base);
  576. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  577. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  578. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  579. } else
  580. return;
  581. if (num_wraps == priv->event_log.num_wraps) {
  582. iwl_print_cont_event_trace(priv,
  583. base, priv->event_log.next_entry,
  584. next_entry - priv->event_log.next_entry,
  585. mode);
  586. priv->event_log.non_wraps_count++;
  587. } else {
  588. if ((num_wraps - priv->event_log.num_wraps) > 1)
  589. priv->event_log.wraps_more_count++;
  590. else
  591. priv->event_log.wraps_once_count++;
  592. trace_iwlwifi_dev_ucode_wrap_event(priv,
  593. num_wraps - priv->event_log.num_wraps,
  594. next_entry, priv->event_log.next_entry);
  595. if (next_entry < priv->event_log.next_entry) {
  596. iwl_print_cont_event_trace(priv, base,
  597. priv->event_log.next_entry,
  598. capacity - priv->event_log.next_entry,
  599. mode);
  600. iwl_print_cont_event_trace(priv, base, 0,
  601. next_entry, mode);
  602. } else {
  603. iwl_print_cont_event_trace(priv, base,
  604. next_entry, capacity - next_entry,
  605. mode);
  606. iwl_print_cont_event_trace(priv, base, 0,
  607. next_entry, mode);
  608. }
  609. }
  610. priv->event_log.num_wraps = num_wraps;
  611. priv->event_log.next_entry = next_entry;
  612. }
  613. /**
  614. * iwl_bg_ucode_trace - Timer callback to log ucode event
  615. *
  616. * The timer is continually set to execute every
  617. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  618. * this function is to perform continuous uCode event logging operation
  619. * if enabled
  620. */
  621. static void iwl_bg_ucode_trace(unsigned long data)
  622. {
  623. struct iwl_priv *priv = (struct iwl_priv *)data;
  624. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  625. return;
  626. if (priv->event_log.ucode_trace) {
  627. iwl_continuous_event_trace(priv);
  628. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  629. mod_timer(&priv->ucode_trace,
  630. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  631. }
  632. }
  633. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  634. struct iwl_rx_mem_buffer *rxb)
  635. {
  636. #ifdef CONFIG_IWLWIFI_DEBUG
  637. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  638. struct iwl4965_beacon_notif *beacon =
  639. (struct iwl4965_beacon_notif *)pkt->u.raw;
  640. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  641. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  642. "tsf %d %d rate %d\n",
  643. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  644. beacon->beacon_notify_hdr.failure_frame,
  645. le32_to_cpu(beacon->ibss_mgr_status),
  646. le32_to_cpu(beacon->high_tsf),
  647. le32_to_cpu(beacon->low_tsf), rate);
  648. #endif
  649. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  650. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  651. queue_work(priv->workqueue, &priv->beacon_update);
  652. }
  653. /* Handle notification from uCode that card's power state is changing
  654. * due to software, hardware, or critical temperature RFKILL */
  655. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  656. struct iwl_rx_mem_buffer *rxb)
  657. {
  658. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  659. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  660. unsigned long status = priv->status;
  661. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  662. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  663. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  664. (flags & CT_CARD_DISABLED) ?
  665. "Reached" : "Not reached");
  666. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  667. CT_CARD_DISABLED)) {
  668. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  669. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  670. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  671. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  672. if (!(flags & RXON_CARD_DISABLED)) {
  673. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  674. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  675. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  676. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  677. }
  678. if (flags & CT_CARD_DISABLED)
  679. iwl_tt_enter_ct_kill(priv);
  680. }
  681. if (!(flags & CT_CARD_DISABLED))
  682. iwl_tt_exit_ct_kill(priv);
  683. if (flags & HW_CARD_DISABLED)
  684. set_bit(STATUS_RF_KILL_HW, &priv->status);
  685. else
  686. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  687. if (!(flags & RXON_CARD_DISABLED))
  688. iwl_scan_cancel(priv);
  689. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  690. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  691. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  692. test_bit(STATUS_RF_KILL_HW, &priv->status));
  693. else
  694. wake_up_interruptible(&priv->wait_command_queue);
  695. }
  696. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  697. {
  698. if (src == IWL_PWR_SRC_VAUX) {
  699. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  700. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  701. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  702. ~APMG_PS_CTRL_MSK_PWR_SRC);
  703. } else {
  704. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  705. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  706. ~APMG_PS_CTRL_MSK_PWR_SRC);
  707. }
  708. return 0;
  709. }
  710. /**
  711. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  712. *
  713. * Setup the RX handlers for each of the reply types sent from the uCode
  714. * to the host.
  715. *
  716. * This function chains into the hardware specific files for them to setup
  717. * any hardware specific handlers as well.
  718. */
  719. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  720. {
  721. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  722. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  723. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  724. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  725. iwl_rx_spectrum_measure_notif;
  726. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  727. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  728. iwl_rx_pm_debug_statistics_notif;
  729. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  730. /*
  731. * The same handler is used for both the REPLY to a discrete
  732. * statistics request from the host as well as for the periodic
  733. * statistics notifications (after received beacons) from the uCode.
  734. */
  735. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  736. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  737. iwl_setup_rx_scan_handlers(priv);
  738. /* status change handler */
  739. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  740. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  741. iwl_rx_missed_beacon_notif;
  742. /* Rx handlers */
  743. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
  744. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
  745. /* block ack */
  746. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
  747. /* Set up hardware specific Rx handlers */
  748. priv->cfg->ops->lib->rx_handler_setup(priv);
  749. }
  750. /**
  751. * iwl_rx_handle - Main entry function for receiving responses from uCode
  752. *
  753. * Uses the priv->rx_handlers callback function array to invoke
  754. * the appropriate handlers, including command responses,
  755. * frame-received notifications, and other notifications.
  756. */
  757. void iwl_rx_handle(struct iwl_priv *priv)
  758. {
  759. struct iwl_rx_mem_buffer *rxb;
  760. struct iwl_rx_packet *pkt;
  761. struct iwl_rx_queue *rxq = &priv->rxq;
  762. u32 r, i;
  763. int reclaim;
  764. unsigned long flags;
  765. u8 fill_rx = 0;
  766. u32 count = 8;
  767. int total_empty;
  768. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  769. * buffer that the driver may process (last buffer filled by ucode). */
  770. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  771. i = rxq->read;
  772. /* Rx interrupt, but nothing sent from uCode */
  773. if (i == r)
  774. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  775. /* calculate total frames need to be restock after handling RX */
  776. total_empty = r - rxq->write_actual;
  777. if (total_empty < 0)
  778. total_empty += RX_QUEUE_SIZE;
  779. if (total_empty > (RX_QUEUE_SIZE / 2))
  780. fill_rx = 1;
  781. while (i != r) {
  782. rxb = rxq->queue[i];
  783. /* If an RXB doesn't have a Rx queue slot associated with it,
  784. * then a bug has been introduced in the queue refilling
  785. * routines -- catch it here */
  786. BUG_ON(rxb == NULL);
  787. rxq->queue[i] = NULL;
  788. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  789. PAGE_SIZE << priv->hw_params.rx_page_order,
  790. PCI_DMA_FROMDEVICE);
  791. pkt = rxb_addr(rxb);
  792. trace_iwlwifi_dev_rx(priv, pkt,
  793. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  794. /* Reclaim a command buffer only if this packet is a response
  795. * to a (driver-originated) command.
  796. * If the packet (e.g. Rx frame) originated from uCode,
  797. * there is no command buffer to reclaim.
  798. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  799. * but apparently a few don't get set; catch them here. */
  800. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  801. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  802. (pkt->hdr.cmd != REPLY_RX) &&
  803. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  804. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  805. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  806. (pkt->hdr.cmd != REPLY_TX);
  807. /* Based on type of command response or notification,
  808. * handle those that need handling via function in
  809. * rx_handlers table. See iwl_setup_rx_handlers() */
  810. if (priv->rx_handlers[pkt->hdr.cmd]) {
  811. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  812. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  813. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  814. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  815. } else {
  816. /* No handling needed */
  817. IWL_DEBUG_RX(priv,
  818. "r %d i %d No handler needed for %s, 0x%02x\n",
  819. r, i, get_cmd_string(pkt->hdr.cmd),
  820. pkt->hdr.cmd);
  821. }
  822. /*
  823. * XXX: After here, we should always check rxb->page
  824. * against NULL before touching it or its virtual
  825. * memory (pkt). Because some rx_handler might have
  826. * already taken or freed the pages.
  827. */
  828. if (reclaim) {
  829. /* Invoke any callbacks, transfer the buffer to caller,
  830. * and fire off the (possibly) blocking iwl_send_cmd()
  831. * as we reclaim the driver command queue */
  832. if (rxb->page)
  833. iwl_tx_cmd_complete(priv, rxb);
  834. else
  835. IWL_WARN(priv, "Claim null rxb?\n");
  836. }
  837. /* Reuse the page if possible. For notification packets and
  838. * SKBs that fail to Rx correctly, add them back into the
  839. * rx_free list for reuse later. */
  840. spin_lock_irqsave(&rxq->lock, flags);
  841. if (rxb->page != NULL) {
  842. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  843. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  844. PCI_DMA_FROMDEVICE);
  845. list_add_tail(&rxb->list, &rxq->rx_free);
  846. rxq->free_count++;
  847. } else
  848. list_add_tail(&rxb->list, &rxq->rx_used);
  849. spin_unlock_irqrestore(&rxq->lock, flags);
  850. i = (i + 1) & RX_QUEUE_MASK;
  851. /* If there are a lot of unused frames,
  852. * restock the Rx queue so ucode wont assert. */
  853. if (fill_rx) {
  854. count++;
  855. if (count >= 8) {
  856. rxq->read = i;
  857. iwlagn_rx_replenish_now(priv);
  858. count = 0;
  859. }
  860. }
  861. }
  862. /* Backtrack one entry */
  863. rxq->read = i;
  864. if (fill_rx)
  865. iwlagn_rx_replenish_now(priv);
  866. else
  867. iwlagn_rx_queue_restock(priv);
  868. }
  869. /* call this function to flush any scheduled tasklet */
  870. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  871. {
  872. /* wait to make sure we flush pending tasklet*/
  873. synchronize_irq(priv->pci_dev->irq);
  874. tasklet_kill(&priv->irq_tasklet);
  875. }
  876. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  877. {
  878. u32 inta, handled = 0;
  879. u32 inta_fh;
  880. unsigned long flags;
  881. u32 i;
  882. #ifdef CONFIG_IWLWIFI_DEBUG
  883. u32 inta_mask;
  884. #endif
  885. spin_lock_irqsave(&priv->lock, flags);
  886. /* Ack/clear/reset pending uCode interrupts.
  887. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  888. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  889. inta = iwl_read32(priv, CSR_INT);
  890. iwl_write32(priv, CSR_INT, inta);
  891. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  892. * Any new interrupts that happen after this, either while we're
  893. * in this tasklet, or later, will show up in next ISR/tasklet. */
  894. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  895. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  896. #ifdef CONFIG_IWLWIFI_DEBUG
  897. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  898. /* just for debug */
  899. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  900. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  901. inta, inta_mask, inta_fh);
  902. }
  903. #endif
  904. spin_unlock_irqrestore(&priv->lock, flags);
  905. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  906. * atomic, make sure that inta covers all the interrupts that
  907. * we've discovered, even if FH interrupt came in just after
  908. * reading CSR_INT. */
  909. if (inta_fh & CSR49_FH_INT_RX_MASK)
  910. inta |= CSR_INT_BIT_FH_RX;
  911. if (inta_fh & CSR49_FH_INT_TX_MASK)
  912. inta |= CSR_INT_BIT_FH_TX;
  913. /* Now service all interrupt bits discovered above. */
  914. if (inta & CSR_INT_BIT_HW_ERR) {
  915. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  916. /* Tell the device to stop sending interrupts */
  917. iwl_disable_interrupts(priv);
  918. priv->isr_stats.hw++;
  919. iwl_irq_handle_error(priv);
  920. handled |= CSR_INT_BIT_HW_ERR;
  921. return;
  922. }
  923. #ifdef CONFIG_IWLWIFI_DEBUG
  924. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  925. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  926. if (inta & CSR_INT_BIT_SCD) {
  927. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  928. "the frame/frames.\n");
  929. priv->isr_stats.sch++;
  930. }
  931. /* Alive notification via Rx interrupt will do the real work */
  932. if (inta & CSR_INT_BIT_ALIVE) {
  933. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  934. priv->isr_stats.alive++;
  935. }
  936. }
  937. #endif
  938. /* Safely ignore these bits for debug checks below */
  939. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  940. /* HW RF KILL switch toggled */
  941. if (inta & CSR_INT_BIT_RF_KILL) {
  942. int hw_rf_kill = 0;
  943. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  944. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  945. hw_rf_kill = 1;
  946. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  947. hw_rf_kill ? "disable radio" : "enable radio");
  948. priv->isr_stats.rfkill++;
  949. /* driver only loads ucode once setting the interface up.
  950. * the driver allows loading the ucode even if the radio
  951. * is killed. Hence update the killswitch state here. The
  952. * rfkill handler will care about restarting if needed.
  953. */
  954. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  955. if (hw_rf_kill)
  956. set_bit(STATUS_RF_KILL_HW, &priv->status);
  957. else
  958. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  959. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  960. }
  961. handled |= CSR_INT_BIT_RF_KILL;
  962. }
  963. /* Chip got too hot and stopped itself */
  964. if (inta & CSR_INT_BIT_CT_KILL) {
  965. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  966. priv->isr_stats.ctkill++;
  967. handled |= CSR_INT_BIT_CT_KILL;
  968. }
  969. /* Error detected by uCode */
  970. if (inta & CSR_INT_BIT_SW_ERR) {
  971. IWL_ERR(priv, "Microcode SW error detected. "
  972. " Restarting 0x%X.\n", inta);
  973. priv->isr_stats.sw++;
  974. priv->isr_stats.sw_err = inta;
  975. iwl_irq_handle_error(priv);
  976. handled |= CSR_INT_BIT_SW_ERR;
  977. }
  978. /*
  979. * uCode wakes up after power-down sleep.
  980. * Tell device about any new tx or host commands enqueued,
  981. * and about any Rx buffers made available while asleep.
  982. */
  983. if (inta & CSR_INT_BIT_WAKEUP) {
  984. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  985. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  986. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  987. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  988. priv->isr_stats.wakeup++;
  989. handled |= CSR_INT_BIT_WAKEUP;
  990. }
  991. /* All uCode command responses, including Tx command responses,
  992. * Rx "responses" (frame-received notification), and other
  993. * notifications from uCode come through here*/
  994. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  995. iwl_rx_handle(priv);
  996. priv->isr_stats.rx++;
  997. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  998. }
  999. /* This "Tx" DMA channel is used only for loading uCode */
  1000. if (inta & CSR_INT_BIT_FH_TX) {
  1001. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1002. priv->isr_stats.tx++;
  1003. handled |= CSR_INT_BIT_FH_TX;
  1004. /* Wake up uCode load routine, now that load is complete */
  1005. priv->ucode_write_complete = 1;
  1006. wake_up_interruptible(&priv->wait_command_queue);
  1007. }
  1008. if (inta & ~handled) {
  1009. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1010. priv->isr_stats.unhandled++;
  1011. }
  1012. if (inta & ~(priv->inta_mask)) {
  1013. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1014. inta & ~priv->inta_mask);
  1015. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1016. }
  1017. /* Re-enable all interrupts */
  1018. /* only Re-enable if diabled by irq */
  1019. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1020. iwl_enable_interrupts(priv);
  1021. #ifdef CONFIG_IWLWIFI_DEBUG
  1022. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1023. inta = iwl_read32(priv, CSR_INT);
  1024. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1025. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1026. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1027. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1028. }
  1029. #endif
  1030. }
  1031. /* tasklet for iwlagn interrupt */
  1032. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1033. {
  1034. u32 inta = 0;
  1035. u32 handled = 0;
  1036. unsigned long flags;
  1037. u32 i;
  1038. #ifdef CONFIG_IWLWIFI_DEBUG
  1039. u32 inta_mask;
  1040. #endif
  1041. spin_lock_irqsave(&priv->lock, flags);
  1042. /* Ack/clear/reset pending uCode interrupts.
  1043. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1044. */
  1045. iwl_write32(priv, CSR_INT, priv->_agn.inta);
  1046. inta = priv->_agn.inta;
  1047. #ifdef CONFIG_IWLWIFI_DEBUG
  1048. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1049. /* just for debug */
  1050. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1051. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1052. inta, inta_mask);
  1053. }
  1054. #endif
  1055. spin_unlock_irqrestore(&priv->lock, flags);
  1056. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1057. priv->_agn.inta = 0;
  1058. /* Now service all interrupt bits discovered above. */
  1059. if (inta & CSR_INT_BIT_HW_ERR) {
  1060. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1061. /* Tell the device to stop sending interrupts */
  1062. iwl_disable_interrupts(priv);
  1063. priv->isr_stats.hw++;
  1064. iwl_irq_handle_error(priv);
  1065. handled |= CSR_INT_BIT_HW_ERR;
  1066. return;
  1067. }
  1068. #ifdef CONFIG_IWLWIFI_DEBUG
  1069. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1070. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1071. if (inta & CSR_INT_BIT_SCD) {
  1072. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1073. "the frame/frames.\n");
  1074. priv->isr_stats.sch++;
  1075. }
  1076. /* Alive notification via Rx interrupt will do the real work */
  1077. if (inta & CSR_INT_BIT_ALIVE) {
  1078. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1079. priv->isr_stats.alive++;
  1080. }
  1081. }
  1082. #endif
  1083. /* Safely ignore these bits for debug checks below */
  1084. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1085. /* HW RF KILL switch toggled */
  1086. if (inta & CSR_INT_BIT_RF_KILL) {
  1087. int hw_rf_kill = 0;
  1088. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1089. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1090. hw_rf_kill = 1;
  1091. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1092. hw_rf_kill ? "disable radio" : "enable radio");
  1093. priv->isr_stats.rfkill++;
  1094. /* driver only loads ucode once setting the interface up.
  1095. * the driver allows loading the ucode even if the radio
  1096. * is killed. Hence update the killswitch state here. The
  1097. * rfkill handler will care about restarting if needed.
  1098. */
  1099. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1100. if (hw_rf_kill)
  1101. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1102. else
  1103. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1104. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1105. }
  1106. handled |= CSR_INT_BIT_RF_KILL;
  1107. }
  1108. /* Chip got too hot and stopped itself */
  1109. if (inta & CSR_INT_BIT_CT_KILL) {
  1110. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1111. priv->isr_stats.ctkill++;
  1112. handled |= CSR_INT_BIT_CT_KILL;
  1113. }
  1114. /* Error detected by uCode */
  1115. if (inta & CSR_INT_BIT_SW_ERR) {
  1116. IWL_ERR(priv, "Microcode SW error detected. "
  1117. " Restarting 0x%X.\n", inta);
  1118. priv->isr_stats.sw++;
  1119. priv->isr_stats.sw_err = inta;
  1120. iwl_irq_handle_error(priv);
  1121. handled |= CSR_INT_BIT_SW_ERR;
  1122. }
  1123. /* uCode wakes up after power-down sleep */
  1124. if (inta & CSR_INT_BIT_WAKEUP) {
  1125. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1126. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1127. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1128. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1129. priv->isr_stats.wakeup++;
  1130. handled |= CSR_INT_BIT_WAKEUP;
  1131. }
  1132. /* All uCode command responses, including Tx command responses,
  1133. * Rx "responses" (frame-received notification), and other
  1134. * notifications from uCode come through here*/
  1135. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1136. CSR_INT_BIT_RX_PERIODIC)) {
  1137. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1138. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1139. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1140. iwl_write32(priv, CSR_FH_INT_STATUS,
  1141. CSR49_FH_INT_RX_MASK);
  1142. }
  1143. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1144. handled |= CSR_INT_BIT_RX_PERIODIC;
  1145. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1146. }
  1147. /* Sending RX interrupt require many steps to be done in the
  1148. * the device:
  1149. * 1- write interrupt to current index in ICT table.
  1150. * 2- dma RX frame.
  1151. * 3- update RX shared data to indicate last write index.
  1152. * 4- send interrupt.
  1153. * This could lead to RX race, driver could receive RX interrupt
  1154. * but the shared data changes does not reflect this;
  1155. * periodic interrupt will detect any dangling Rx activity.
  1156. */
  1157. /* Disable periodic interrupt; we use it as just a one-shot. */
  1158. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1159. CSR_INT_PERIODIC_DIS);
  1160. iwl_rx_handle(priv);
  1161. /*
  1162. * Enable periodic interrupt in 8 msec only if we received
  1163. * real RX interrupt (instead of just periodic int), to catch
  1164. * any dangling Rx interrupt. If it was just the periodic
  1165. * interrupt, there was no dangling Rx activity, and no need
  1166. * to extend the periodic interrupt; one-shot is enough.
  1167. */
  1168. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1169. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1170. CSR_INT_PERIODIC_ENA);
  1171. priv->isr_stats.rx++;
  1172. }
  1173. /* This "Tx" DMA channel is used only for loading uCode */
  1174. if (inta & CSR_INT_BIT_FH_TX) {
  1175. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1176. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1177. priv->isr_stats.tx++;
  1178. handled |= CSR_INT_BIT_FH_TX;
  1179. /* Wake up uCode load routine, now that load is complete */
  1180. priv->ucode_write_complete = 1;
  1181. wake_up_interruptible(&priv->wait_command_queue);
  1182. }
  1183. if (inta & ~handled) {
  1184. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1185. priv->isr_stats.unhandled++;
  1186. }
  1187. if (inta & ~(priv->inta_mask)) {
  1188. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1189. inta & ~priv->inta_mask);
  1190. }
  1191. /* Re-enable all interrupts */
  1192. /* only Re-enable if diabled by irq */
  1193. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1194. iwl_enable_interrupts(priv);
  1195. }
  1196. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  1197. #define ACK_CNT_RATIO (50)
  1198. #define BA_TIMEOUT_CNT (5)
  1199. #define BA_TIMEOUT_MAX (16)
  1200. /**
  1201. * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
  1202. *
  1203. * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
  1204. * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
  1205. * operation state.
  1206. */
  1207. bool iwl_good_ack_health(struct iwl_priv *priv,
  1208. struct iwl_rx_packet *pkt)
  1209. {
  1210. bool rc = true;
  1211. int actual_ack_cnt_delta, expected_ack_cnt_delta;
  1212. int ba_timeout_delta;
  1213. actual_ack_cnt_delta =
  1214. le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  1215. le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
  1216. expected_ack_cnt_delta =
  1217. le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
  1218. le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
  1219. ba_timeout_delta =
  1220. le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
  1221. le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
  1222. if ((priv->_agn.agg_tids_count > 0) &&
  1223. (expected_ack_cnt_delta > 0) &&
  1224. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
  1225. < ACK_CNT_RATIO) &&
  1226. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  1227. IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
  1228. " expected_ack_cnt = %d\n",
  1229. actual_ack_cnt_delta, expected_ack_cnt_delta);
  1230. #ifdef CONFIG_IWLWIFI_DEBUG
  1231. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  1232. priv->delta_statistics.tx.rx_detected_cnt);
  1233. IWL_DEBUG_RADIO(priv,
  1234. "ack_or_ba_timeout_collision delta = %d\n",
  1235. priv->delta_statistics.tx.
  1236. ack_or_ba_timeout_collision);
  1237. #endif
  1238. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  1239. ba_timeout_delta);
  1240. if (!actual_ack_cnt_delta &&
  1241. (ba_timeout_delta >= BA_TIMEOUT_MAX))
  1242. rc = false;
  1243. }
  1244. return rc;
  1245. }
  1246. /******************************************************************************
  1247. *
  1248. * uCode download functions
  1249. *
  1250. ******************************************************************************/
  1251. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1252. {
  1253. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1254. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1255. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1256. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1257. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1258. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1259. }
  1260. static void iwl_nic_start(struct iwl_priv *priv)
  1261. {
  1262. /* Remove all resets to allow NIC to operate */
  1263. iwl_write32(priv, CSR_RESET, 0);
  1264. }
  1265. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1266. static int iwl_mac_setup_register(struct iwl_priv *priv);
  1267. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1268. {
  1269. const char *name_pre = priv->cfg->fw_name_pre;
  1270. if (first)
  1271. priv->fw_index = priv->cfg->ucode_api_max;
  1272. else
  1273. priv->fw_index--;
  1274. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1275. IWL_ERR(priv, "no suitable firmware found!\n");
  1276. return -ENOENT;
  1277. }
  1278. sprintf(priv->firmware_name, "%s%d%s",
  1279. name_pre, priv->fw_index, ".ucode");
  1280. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1281. priv->firmware_name);
  1282. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1283. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1284. iwl_ucode_callback);
  1285. }
  1286. /**
  1287. * iwl_ucode_callback - callback when firmware was loaded
  1288. *
  1289. * If loaded successfully, copies the firmware into buffers
  1290. * for the card to fetch (via DMA).
  1291. */
  1292. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1293. {
  1294. struct iwl_priv *priv = context;
  1295. struct iwl_ucode_header *ucode;
  1296. const unsigned int api_max = priv->cfg->ucode_api_max;
  1297. const unsigned int api_min = priv->cfg->ucode_api_min;
  1298. u8 *src;
  1299. size_t len;
  1300. u32 api_ver, build;
  1301. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1302. int err;
  1303. u16 eeprom_ver;
  1304. if (!ucode_raw) {
  1305. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1306. priv->firmware_name);
  1307. goto try_again;
  1308. }
  1309. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1310. priv->firmware_name, ucode_raw->size);
  1311. /* Make sure that we got at least the v1 header! */
  1312. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1313. IWL_ERR(priv, "File size way too small!\n");
  1314. goto try_again;
  1315. }
  1316. /* Data from ucode file: header followed by uCode images */
  1317. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1318. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1319. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1320. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1321. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1322. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1323. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1324. init_data_size =
  1325. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1326. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1327. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1328. /* api_ver should match the api version forming part of the
  1329. * firmware filename ... but we don't check for that and only rely
  1330. * on the API version read from firmware header from here on forward */
  1331. if (api_ver < api_min || api_ver > api_max) {
  1332. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1333. "Driver supports v%u, firmware is v%u.\n",
  1334. api_max, api_ver);
  1335. goto try_again;
  1336. }
  1337. if (api_ver != api_max)
  1338. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1339. "got v%u. New firmware can be obtained "
  1340. "from http://www.intellinuxwireless.org.\n",
  1341. api_max, api_ver);
  1342. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1343. IWL_UCODE_MAJOR(priv->ucode_ver),
  1344. IWL_UCODE_MINOR(priv->ucode_ver),
  1345. IWL_UCODE_API(priv->ucode_ver),
  1346. IWL_UCODE_SERIAL(priv->ucode_ver));
  1347. snprintf(priv->hw->wiphy->fw_version,
  1348. sizeof(priv->hw->wiphy->fw_version),
  1349. "%u.%u.%u.%u",
  1350. IWL_UCODE_MAJOR(priv->ucode_ver),
  1351. IWL_UCODE_MINOR(priv->ucode_ver),
  1352. IWL_UCODE_API(priv->ucode_ver),
  1353. IWL_UCODE_SERIAL(priv->ucode_ver));
  1354. if (build)
  1355. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1356. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1357. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1358. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1359. ? "OTP" : "EEPROM", eeprom_ver);
  1360. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1361. priv->ucode_ver);
  1362. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1363. inst_size);
  1364. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1365. data_size);
  1366. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1367. init_size);
  1368. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1369. init_data_size);
  1370. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1371. boot_size);
  1372. /*
  1373. * For any of the failures below (before allocating pci memory)
  1374. * we will try to load a version with a smaller API -- maybe the
  1375. * user just got a corrupted version of the latest API.
  1376. */
  1377. /* Verify size of file vs. image size info in file's header */
  1378. if (ucode_raw->size !=
  1379. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1380. inst_size + data_size + init_size +
  1381. init_data_size + boot_size) {
  1382. IWL_DEBUG_INFO(priv,
  1383. "uCode file size %d does not match expected size\n",
  1384. (int)ucode_raw->size);
  1385. goto try_again;
  1386. }
  1387. /* Verify that uCode images will fit in card's SRAM */
  1388. if (inst_size > priv->hw_params.max_inst_size) {
  1389. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1390. inst_size);
  1391. goto try_again;
  1392. }
  1393. if (data_size > priv->hw_params.max_data_size) {
  1394. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1395. data_size);
  1396. goto try_again;
  1397. }
  1398. if (init_size > priv->hw_params.max_inst_size) {
  1399. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1400. init_size);
  1401. goto try_again;
  1402. }
  1403. if (init_data_size > priv->hw_params.max_data_size) {
  1404. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1405. init_data_size);
  1406. goto try_again;
  1407. }
  1408. if (boot_size > priv->hw_params.max_bsm_size) {
  1409. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1410. boot_size);
  1411. goto try_again;
  1412. }
  1413. /* Allocate ucode buffers for card's bus-master loading ... */
  1414. /* Runtime instructions and 2 copies of data:
  1415. * 1) unmodified from disk
  1416. * 2) backup cache for save/restore during power-downs */
  1417. priv->ucode_code.len = inst_size;
  1418. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1419. priv->ucode_data.len = data_size;
  1420. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1421. priv->ucode_data_backup.len = data_size;
  1422. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1423. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1424. !priv->ucode_data_backup.v_addr)
  1425. goto err_pci_alloc;
  1426. /* Initialization instructions and data */
  1427. if (init_size && init_data_size) {
  1428. priv->ucode_init.len = init_size;
  1429. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1430. priv->ucode_init_data.len = init_data_size;
  1431. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1432. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1433. goto err_pci_alloc;
  1434. }
  1435. /* Bootstrap (instructions only, no data) */
  1436. if (boot_size) {
  1437. priv->ucode_boot.len = boot_size;
  1438. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1439. if (!priv->ucode_boot.v_addr)
  1440. goto err_pci_alloc;
  1441. }
  1442. /* Copy images into buffers for card's bus-master reads ... */
  1443. /* Runtime instructions (first block of data in file) */
  1444. len = inst_size;
  1445. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1446. memcpy(priv->ucode_code.v_addr, src, len);
  1447. src += len;
  1448. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1449. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1450. /* Runtime data (2nd block)
  1451. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1452. len = data_size;
  1453. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1454. memcpy(priv->ucode_data.v_addr, src, len);
  1455. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1456. src += len;
  1457. /* Initialization instructions (3rd block) */
  1458. if (init_size) {
  1459. len = init_size;
  1460. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1461. len);
  1462. memcpy(priv->ucode_init.v_addr, src, len);
  1463. src += len;
  1464. }
  1465. /* Initialization data (4th block) */
  1466. if (init_data_size) {
  1467. len = init_data_size;
  1468. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1469. len);
  1470. memcpy(priv->ucode_init_data.v_addr, src, len);
  1471. src += len;
  1472. }
  1473. /* Bootstrap instructions (5th block) */
  1474. len = boot_size;
  1475. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1476. memcpy(priv->ucode_boot.v_addr, src, len);
  1477. /**************************************************
  1478. * This is still part of probe() in a sense...
  1479. *
  1480. * 9. Setup and register with mac80211 and debugfs
  1481. **************************************************/
  1482. err = iwl_mac_setup_register(priv);
  1483. if (err)
  1484. goto out_unbind;
  1485. err = iwl_dbgfs_register(priv, DRV_NAME);
  1486. if (err)
  1487. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1488. /* We have our copies now, allow OS release its copies */
  1489. release_firmware(ucode_raw);
  1490. return;
  1491. try_again:
  1492. /* try next, if any */
  1493. if (iwl_request_firmware(priv, false))
  1494. goto out_unbind;
  1495. release_firmware(ucode_raw);
  1496. return;
  1497. err_pci_alloc:
  1498. IWL_ERR(priv, "failed to allocate pci memory\n");
  1499. iwl_dealloc_ucode_pci(priv);
  1500. out_unbind:
  1501. device_release_driver(&priv->pci_dev->dev);
  1502. release_firmware(ucode_raw);
  1503. }
  1504. static const char *desc_lookup_text[] = {
  1505. "OK",
  1506. "FAIL",
  1507. "BAD_PARAM",
  1508. "BAD_CHECKSUM",
  1509. "NMI_INTERRUPT_WDG",
  1510. "SYSASSERT",
  1511. "FATAL_ERROR",
  1512. "BAD_COMMAND",
  1513. "HW_ERROR_TUNE_LOCK",
  1514. "HW_ERROR_TEMPERATURE",
  1515. "ILLEGAL_CHAN_FREQ",
  1516. "VCC_NOT_STABLE",
  1517. "FH_ERROR",
  1518. "NMI_INTERRUPT_HOST",
  1519. "NMI_INTERRUPT_ACTION_PT",
  1520. "NMI_INTERRUPT_UNKNOWN",
  1521. "UCODE_VERSION_MISMATCH",
  1522. "HW_ERROR_ABS_LOCK",
  1523. "HW_ERROR_CAL_LOCK_FAIL",
  1524. "NMI_INTERRUPT_INST_ACTION_PT",
  1525. "NMI_INTERRUPT_DATA_ACTION_PT",
  1526. "NMI_TRM_HW_ER",
  1527. "NMI_INTERRUPT_TRM",
  1528. "NMI_INTERRUPT_BREAK_POINT"
  1529. "DEBUG_0",
  1530. "DEBUG_1",
  1531. "DEBUG_2",
  1532. "DEBUG_3",
  1533. "ADVANCED SYSASSERT"
  1534. };
  1535. static const char *desc_lookup(int i)
  1536. {
  1537. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1538. if (i < 0 || i > max)
  1539. i = max;
  1540. return desc_lookup_text[i];
  1541. }
  1542. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1543. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1544. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1545. {
  1546. u32 data2, line;
  1547. u32 desc, time, count, base, data1;
  1548. u32 blink1, blink2, ilink1, ilink2;
  1549. if (priv->ucode_type == UCODE_INIT)
  1550. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1551. else
  1552. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1553. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1554. IWL_ERR(priv,
  1555. "Not valid error log pointer 0x%08X for %s uCode\n",
  1556. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1557. return;
  1558. }
  1559. count = iwl_read_targ_mem(priv, base);
  1560. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1561. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1562. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1563. priv->status, count);
  1564. }
  1565. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1566. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1567. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1568. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1569. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1570. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1571. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1572. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1573. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1574. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1575. blink1, blink2, ilink1, ilink2);
  1576. IWL_ERR(priv, "Desc Time "
  1577. "data1 data2 line\n");
  1578. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1579. desc_lookup(desc), desc, time, data1, data2, line);
  1580. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1581. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1582. ilink1, ilink2);
  1583. }
  1584. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1585. /**
  1586. * iwl_print_event_log - Dump error event log to syslog
  1587. *
  1588. */
  1589. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1590. u32 num_events, u32 mode,
  1591. int pos, char **buf, size_t bufsz)
  1592. {
  1593. u32 i;
  1594. u32 base; /* SRAM byte address of event log header */
  1595. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1596. u32 ptr; /* SRAM byte address of log data */
  1597. u32 ev, time, data; /* event log data */
  1598. unsigned long reg_flags;
  1599. if (num_events == 0)
  1600. return pos;
  1601. if (priv->ucode_type == UCODE_INIT)
  1602. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1603. else
  1604. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1605. if (mode == 0)
  1606. event_size = 2 * sizeof(u32);
  1607. else
  1608. event_size = 3 * sizeof(u32);
  1609. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1610. /* Make sure device is powered up for SRAM reads */
  1611. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1612. iwl_grab_nic_access(priv);
  1613. /* Set starting address; reads will auto-increment */
  1614. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1615. rmb();
  1616. /* "time" is actually "data" for mode 0 (no timestamp).
  1617. * place event id # at far right for easier visual parsing. */
  1618. for (i = 0; i < num_events; i++) {
  1619. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1620. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1621. if (mode == 0) {
  1622. /* data, ev */
  1623. if (bufsz) {
  1624. pos += scnprintf(*buf + pos, bufsz - pos,
  1625. "EVT_LOG:0x%08x:%04u\n",
  1626. time, ev);
  1627. } else {
  1628. trace_iwlwifi_dev_ucode_event(priv, 0,
  1629. time, ev);
  1630. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1631. time, ev);
  1632. }
  1633. } else {
  1634. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1635. if (bufsz) {
  1636. pos += scnprintf(*buf + pos, bufsz - pos,
  1637. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1638. time, data, ev);
  1639. } else {
  1640. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1641. time, data, ev);
  1642. trace_iwlwifi_dev_ucode_event(priv, time,
  1643. data, ev);
  1644. }
  1645. }
  1646. }
  1647. /* Allow device to power down */
  1648. iwl_release_nic_access(priv);
  1649. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1650. return pos;
  1651. }
  1652. /**
  1653. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1654. */
  1655. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1656. u32 num_wraps, u32 next_entry,
  1657. u32 size, u32 mode,
  1658. int pos, char **buf, size_t bufsz)
  1659. {
  1660. /*
  1661. * display the newest DEFAULT_LOG_ENTRIES entries
  1662. * i.e the entries just before the next ont that uCode would fill.
  1663. */
  1664. if (num_wraps) {
  1665. if (next_entry < size) {
  1666. pos = iwl_print_event_log(priv,
  1667. capacity - (size - next_entry),
  1668. size - next_entry, mode,
  1669. pos, buf, bufsz);
  1670. pos = iwl_print_event_log(priv, 0,
  1671. next_entry, mode,
  1672. pos, buf, bufsz);
  1673. } else
  1674. pos = iwl_print_event_log(priv, next_entry - size,
  1675. size, mode, pos, buf, bufsz);
  1676. } else {
  1677. if (next_entry < size) {
  1678. pos = iwl_print_event_log(priv, 0, next_entry,
  1679. mode, pos, buf, bufsz);
  1680. } else {
  1681. pos = iwl_print_event_log(priv, next_entry - size,
  1682. size, mode, pos, buf, bufsz);
  1683. }
  1684. }
  1685. return pos;
  1686. }
  1687. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1688. #define MAX_EVENT_LOG_SIZE (512)
  1689. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1690. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1691. char **buf, bool display)
  1692. {
  1693. u32 base; /* SRAM byte address of event log header */
  1694. u32 capacity; /* event log capacity in # entries */
  1695. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1696. u32 num_wraps; /* # times uCode wrapped to top of log */
  1697. u32 next_entry; /* index of next entry to be written by uCode */
  1698. u32 size; /* # entries that we'll print */
  1699. int pos = 0;
  1700. size_t bufsz = 0;
  1701. if (priv->ucode_type == UCODE_INIT)
  1702. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1703. else
  1704. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1705. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1706. IWL_ERR(priv,
  1707. "Invalid event log pointer 0x%08X for %s uCode\n",
  1708. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1709. return -EINVAL;
  1710. }
  1711. /* event log header */
  1712. capacity = iwl_read_targ_mem(priv, base);
  1713. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1714. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1715. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1716. if (capacity > MAX_EVENT_LOG_SIZE) {
  1717. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1718. capacity, MAX_EVENT_LOG_SIZE);
  1719. capacity = MAX_EVENT_LOG_SIZE;
  1720. }
  1721. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1722. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1723. next_entry, MAX_EVENT_LOG_SIZE);
  1724. next_entry = MAX_EVENT_LOG_SIZE;
  1725. }
  1726. size = num_wraps ? capacity : next_entry;
  1727. /* bail out if nothing in log */
  1728. if (size == 0) {
  1729. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1730. return pos;
  1731. }
  1732. #ifdef CONFIG_IWLWIFI_DEBUG
  1733. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1734. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1735. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1736. #else
  1737. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1738. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1739. #endif
  1740. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1741. size);
  1742. #ifdef CONFIG_IWLWIFI_DEBUG
  1743. if (display) {
  1744. if (full_log)
  1745. bufsz = capacity * 48;
  1746. else
  1747. bufsz = size * 48;
  1748. *buf = kmalloc(bufsz, GFP_KERNEL);
  1749. if (!*buf)
  1750. return -ENOMEM;
  1751. }
  1752. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1753. /*
  1754. * if uCode has wrapped back to top of log,
  1755. * start at the oldest entry,
  1756. * i.e the next one that uCode would fill.
  1757. */
  1758. if (num_wraps)
  1759. pos = iwl_print_event_log(priv, next_entry,
  1760. capacity - next_entry, mode,
  1761. pos, buf, bufsz);
  1762. /* (then/else) start at top of log */
  1763. pos = iwl_print_event_log(priv, 0,
  1764. next_entry, mode, pos, buf, bufsz);
  1765. } else
  1766. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1767. next_entry, size, mode,
  1768. pos, buf, bufsz);
  1769. #else
  1770. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1771. next_entry, size, mode,
  1772. pos, buf, bufsz);
  1773. #endif
  1774. return pos;
  1775. }
  1776. /**
  1777. * iwl_alive_start - called after REPLY_ALIVE notification received
  1778. * from protocol/runtime uCode (initialization uCode's
  1779. * Alive gets handled by iwl_init_alive_start()).
  1780. */
  1781. static void iwl_alive_start(struct iwl_priv *priv)
  1782. {
  1783. int ret = 0;
  1784. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1785. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1786. /* We had an error bringing up the hardware, so take it
  1787. * all the way back down so we can try again */
  1788. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1789. goto restart;
  1790. }
  1791. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1792. * This is a paranoid check, because we would not have gotten the
  1793. * "runtime" alive if code weren't properly loaded. */
  1794. if (iwl_verify_ucode(priv)) {
  1795. /* Runtime instruction load was bad;
  1796. * take it all the way back down so we can try again */
  1797. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1798. goto restart;
  1799. }
  1800. ret = priv->cfg->ops->lib->alive_notify(priv);
  1801. if (ret) {
  1802. IWL_WARN(priv,
  1803. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1804. goto restart;
  1805. }
  1806. /* After the ALIVE response, we can send host commands to the uCode */
  1807. set_bit(STATUS_ALIVE, &priv->status);
  1808. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  1809. /* Enable timer to monitor the driver queues */
  1810. mod_timer(&priv->monitor_recover,
  1811. jiffies +
  1812. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  1813. }
  1814. if (iwl_is_rfkill(priv))
  1815. return;
  1816. ieee80211_wake_queues(priv->hw);
  1817. priv->active_rate = IWL_RATES_MASK;
  1818. /* Configure Tx antenna selection based on H/W config */
  1819. if (priv->cfg->ops->hcmd->set_tx_ant)
  1820. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1821. if (iwl_is_associated(priv)) {
  1822. struct iwl_rxon_cmd *active_rxon =
  1823. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1824. /* apply any changes in staging */
  1825. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1826. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1827. } else {
  1828. /* Initialize our rx_config data */
  1829. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1830. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1831. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1832. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1833. }
  1834. /* Configure Bluetooth device coexistence support */
  1835. iwl_send_bt_config(priv);
  1836. iwl_reset_run_time_calib(priv);
  1837. /* Configure the adapter for unassociated operation */
  1838. iwlcore_commit_rxon(priv);
  1839. /* At this point, the NIC is initialized and operational */
  1840. iwl_rf_kill_ct_config(priv);
  1841. iwl_leds_init(priv);
  1842. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1843. set_bit(STATUS_READY, &priv->status);
  1844. wake_up_interruptible(&priv->wait_command_queue);
  1845. iwl_power_update_mode(priv, true);
  1846. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  1847. return;
  1848. restart:
  1849. queue_work(priv->workqueue, &priv->restart);
  1850. }
  1851. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1852. static void __iwl_down(struct iwl_priv *priv)
  1853. {
  1854. unsigned long flags;
  1855. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1856. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1857. if (!exit_pending)
  1858. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1859. iwl_clear_ucode_stations(priv, true);
  1860. /* Unblock any waiting calls */
  1861. wake_up_interruptible_all(&priv->wait_command_queue);
  1862. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1863. * exiting the module */
  1864. if (!exit_pending)
  1865. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1866. /* stop and reset the on-board processor */
  1867. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1868. /* tell the device to stop sending interrupts */
  1869. spin_lock_irqsave(&priv->lock, flags);
  1870. iwl_disable_interrupts(priv);
  1871. spin_unlock_irqrestore(&priv->lock, flags);
  1872. iwl_synchronize_irq(priv);
  1873. if (priv->mac80211_registered)
  1874. ieee80211_stop_queues(priv->hw);
  1875. /* If we have not previously called iwl_init() then
  1876. * clear all bits but the RF Kill bit and return */
  1877. if (!iwl_is_init(priv)) {
  1878. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1879. STATUS_RF_KILL_HW |
  1880. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1881. STATUS_GEO_CONFIGURED |
  1882. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1883. STATUS_EXIT_PENDING;
  1884. goto exit;
  1885. }
  1886. /* ...otherwise clear out all the status bits but the RF Kill
  1887. * bit and continue taking the NIC down. */
  1888. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1889. STATUS_RF_KILL_HW |
  1890. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1891. STATUS_GEO_CONFIGURED |
  1892. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1893. STATUS_FW_ERROR |
  1894. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1895. STATUS_EXIT_PENDING;
  1896. /* device going down, Stop using ICT table */
  1897. iwl_disable_ict(priv);
  1898. iwlagn_txq_ctx_stop(priv);
  1899. iwlagn_rxq_stop(priv);
  1900. /* Power-down device's busmaster DMA clocks */
  1901. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1902. udelay(5);
  1903. /* Make sure (redundant) we've released our request to stay awake */
  1904. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1905. /* Stop the device, and put it in low power state */
  1906. priv->cfg->ops->lib->apm_ops.stop(priv);
  1907. exit:
  1908. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1909. if (priv->ibss_beacon)
  1910. dev_kfree_skb(priv->ibss_beacon);
  1911. priv->ibss_beacon = NULL;
  1912. /* clear out any free frames */
  1913. iwl_clear_free_frames(priv);
  1914. }
  1915. static void iwl_down(struct iwl_priv *priv)
  1916. {
  1917. mutex_lock(&priv->mutex);
  1918. __iwl_down(priv);
  1919. mutex_unlock(&priv->mutex);
  1920. iwl_cancel_deferred_work(priv);
  1921. }
  1922. #define HW_READY_TIMEOUT (50)
  1923. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1924. {
  1925. int ret = 0;
  1926. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1927. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1928. /* See if we got it */
  1929. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1930. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1931. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1932. HW_READY_TIMEOUT);
  1933. if (ret != -ETIMEDOUT)
  1934. priv->hw_ready = true;
  1935. else
  1936. priv->hw_ready = false;
  1937. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1938. (priv->hw_ready == 1) ? "ready" : "not ready");
  1939. return ret;
  1940. }
  1941. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1942. {
  1943. int ret = 0;
  1944. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  1945. ret = iwl_set_hw_ready(priv);
  1946. if (priv->hw_ready)
  1947. return ret;
  1948. /* If HW is not ready, prepare the conditions to check again */
  1949. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1950. CSR_HW_IF_CONFIG_REG_PREPARE);
  1951. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1952. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1953. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1954. /* HW should be ready by now, check again. */
  1955. if (ret != -ETIMEDOUT)
  1956. iwl_set_hw_ready(priv);
  1957. return ret;
  1958. }
  1959. #define MAX_HW_RESTARTS 5
  1960. static int __iwl_up(struct iwl_priv *priv)
  1961. {
  1962. int i;
  1963. int ret;
  1964. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1965. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1966. return -EIO;
  1967. }
  1968. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1969. IWL_ERR(priv, "ucode not available for device bringup\n");
  1970. return -EIO;
  1971. }
  1972. iwl_prepare_card_hw(priv);
  1973. if (!priv->hw_ready) {
  1974. IWL_WARN(priv, "Exit HW not ready\n");
  1975. return -EIO;
  1976. }
  1977. /* If platform's RF_KILL switch is NOT set to KILL */
  1978. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1979. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1980. else
  1981. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1982. if (iwl_is_rfkill(priv)) {
  1983. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1984. iwl_enable_interrupts(priv);
  1985. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1986. return 0;
  1987. }
  1988. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1989. ret = iwlagn_hw_nic_init(priv);
  1990. if (ret) {
  1991. IWL_ERR(priv, "Unable to init nic\n");
  1992. return ret;
  1993. }
  1994. /* make sure rfkill handshake bits are cleared */
  1995. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1996. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1997. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1998. /* clear (again), then enable host interrupts */
  1999. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2000. iwl_enable_interrupts(priv);
  2001. /* really make sure rfkill handshake bits are cleared */
  2002. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2003. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2004. /* Copy original ucode data image from disk into backup cache.
  2005. * This will be used to initialize the on-board processor's
  2006. * data SRAM for a clean start when the runtime program first loads. */
  2007. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2008. priv->ucode_data.len);
  2009. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2010. /* load bootstrap state machine,
  2011. * load bootstrap program into processor's memory,
  2012. * prepare to load the "initialize" uCode */
  2013. ret = priv->cfg->ops->lib->load_ucode(priv);
  2014. if (ret) {
  2015. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2016. ret);
  2017. continue;
  2018. }
  2019. /* start card; "initialize" will load runtime ucode */
  2020. iwl_nic_start(priv);
  2021. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2022. return 0;
  2023. }
  2024. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2025. __iwl_down(priv);
  2026. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2027. /* tried to restart and config the device for as long as our
  2028. * patience could withstand */
  2029. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2030. return -EIO;
  2031. }
  2032. /*****************************************************************************
  2033. *
  2034. * Workqueue callbacks
  2035. *
  2036. *****************************************************************************/
  2037. static void iwl_bg_init_alive_start(struct work_struct *data)
  2038. {
  2039. struct iwl_priv *priv =
  2040. container_of(data, struct iwl_priv, init_alive_start.work);
  2041. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2042. return;
  2043. mutex_lock(&priv->mutex);
  2044. priv->cfg->ops->lib->init_alive_start(priv);
  2045. mutex_unlock(&priv->mutex);
  2046. }
  2047. static void iwl_bg_alive_start(struct work_struct *data)
  2048. {
  2049. struct iwl_priv *priv =
  2050. container_of(data, struct iwl_priv, alive_start.work);
  2051. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2052. return;
  2053. /* enable dram interrupt */
  2054. iwl_reset_ict(priv);
  2055. mutex_lock(&priv->mutex);
  2056. iwl_alive_start(priv);
  2057. mutex_unlock(&priv->mutex);
  2058. }
  2059. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2060. {
  2061. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2062. run_time_calib_work);
  2063. mutex_lock(&priv->mutex);
  2064. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2065. test_bit(STATUS_SCANNING, &priv->status)) {
  2066. mutex_unlock(&priv->mutex);
  2067. return;
  2068. }
  2069. if (priv->start_calib) {
  2070. iwl_chain_noise_calibration(priv, &priv->statistics);
  2071. iwl_sensitivity_calibration(priv, &priv->statistics);
  2072. }
  2073. mutex_unlock(&priv->mutex);
  2074. return;
  2075. }
  2076. static void iwl_bg_restart(struct work_struct *data)
  2077. {
  2078. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2079. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2080. return;
  2081. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2082. mutex_lock(&priv->mutex);
  2083. priv->vif = NULL;
  2084. priv->is_open = 0;
  2085. mutex_unlock(&priv->mutex);
  2086. iwl_down(priv);
  2087. ieee80211_restart_hw(priv->hw);
  2088. } else {
  2089. iwl_down(priv);
  2090. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2091. return;
  2092. mutex_lock(&priv->mutex);
  2093. __iwl_up(priv);
  2094. mutex_unlock(&priv->mutex);
  2095. }
  2096. }
  2097. static void iwl_bg_rx_replenish(struct work_struct *data)
  2098. {
  2099. struct iwl_priv *priv =
  2100. container_of(data, struct iwl_priv, rx_replenish);
  2101. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2102. return;
  2103. mutex_lock(&priv->mutex);
  2104. iwlagn_rx_replenish(priv);
  2105. mutex_unlock(&priv->mutex);
  2106. }
  2107. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2108. void iwl_post_associate(struct iwl_priv *priv)
  2109. {
  2110. struct ieee80211_conf *conf = NULL;
  2111. int ret = 0;
  2112. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  2113. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2114. return;
  2115. }
  2116. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2117. return;
  2118. if (!priv->vif || !priv->is_open)
  2119. return;
  2120. iwl_scan_cancel_timeout(priv, 200);
  2121. conf = ieee80211_get_hw_conf(priv->hw);
  2122. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2123. iwlcore_commit_rxon(priv);
  2124. iwl_setup_rxon_timing(priv);
  2125. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2126. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2127. if (ret)
  2128. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2129. "Attempting to continue.\n");
  2130. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2131. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2132. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2133. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2134. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2135. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2136. priv->assoc_id, priv->beacon_int);
  2137. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2138. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2139. else
  2140. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2141. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2142. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2143. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2144. else
  2145. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2146. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2147. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2148. }
  2149. iwlcore_commit_rxon(priv);
  2150. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2151. priv->assoc_id, priv->active_rxon.bssid_addr);
  2152. switch (priv->iw_mode) {
  2153. case NL80211_IFTYPE_STATION:
  2154. break;
  2155. case NL80211_IFTYPE_ADHOC:
  2156. /* assume default assoc id */
  2157. priv->assoc_id = 1;
  2158. iwl_add_local_station(priv, priv->bssid, true);
  2159. iwl_send_beacon_cmd(priv);
  2160. break;
  2161. default:
  2162. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2163. __func__, priv->iw_mode);
  2164. break;
  2165. }
  2166. /* the chain noise calibration will enabled PM upon completion
  2167. * If chain noise has already been run, then we need to enable
  2168. * power management here */
  2169. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2170. iwl_power_update_mode(priv, false);
  2171. /* Enable Rx differential gain and sensitivity calibrations */
  2172. iwl_chain_noise_reset(priv);
  2173. priv->start_calib = 1;
  2174. }
  2175. /*****************************************************************************
  2176. *
  2177. * mac80211 entry point functions
  2178. *
  2179. *****************************************************************************/
  2180. #define UCODE_READY_TIMEOUT (4 * HZ)
  2181. /*
  2182. * Not a mac80211 entry point function, but it fits in with all the
  2183. * other mac80211 functions grouped here.
  2184. */
  2185. static int iwl_mac_setup_register(struct iwl_priv *priv)
  2186. {
  2187. int ret;
  2188. struct ieee80211_hw *hw = priv->hw;
  2189. hw->rate_control_algorithm = "iwl-agn-rs";
  2190. /* Tell mac80211 our characteristics */
  2191. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2192. IEEE80211_HW_NOISE_DBM |
  2193. IEEE80211_HW_AMPDU_AGGREGATION |
  2194. IEEE80211_HW_SPECTRUM_MGMT;
  2195. if (!priv->cfg->broken_powersave)
  2196. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2197. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2198. if (priv->cfg->sku & IWL_SKU_N)
  2199. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2200. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2201. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2202. hw->wiphy->interface_modes =
  2203. BIT(NL80211_IFTYPE_STATION) |
  2204. BIT(NL80211_IFTYPE_ADHOC);
  2205. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2206. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2207. /*
  2208. * For now, disable PS by default because it affects
  2209. * RX performance significantly.
  2210. */
  2211. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2212. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX + 1;
  2213. /* we create the 802.11 header and a zero-length SSID element */
  2214. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2215. /* Default value; 4 EDCA QOS priorities */
  2216. hw->queues = 4;
  2217. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2218. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2219. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2220. &priv->bands[IEEE80211_BAND_2GHZ];
  2221. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2222. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2223. &priv->bands[IEEE80211_BAND_5GHZ];
  2224. ret = ieee80211_register_hw(priv->hw);
  2225. if (ret) {
  2226. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2227. return ret;
  2228. }
  2229. priv->mac80211_registered = 1;
  2230. return 0;
  2231. }
  2232. static int iwl_mac_start(struct ieee80211_hw *hw)
  2233. {
  2234. struct iwl_priv *priv = hw->priv;
  2235. int ret;
  2236. IWL_DEBUG_MAC80211(priv, "enter\n");
  2237. /* we should be verifying the device is ready to be opened */
  2238. mutex_lock(&priv->mutex);
  2239. ret = __iwl_up(priv);
  2240. mutex_unlock(&priv->mutex);
  2241. if (ret)
  2242. return ret;
  2243. if (iwl_is_rfkill(priv))
  2244. goto out;
  2245. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2246. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2247. * mac80211 will not be run successfully. */
  2248. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2249. test_bit(STATUS_READY, &priv->status),
  2250. UCODE_READY_TIMEOUT);
  2251. if (!ret) {
  2252. if (!test_bit(STATUS_READY, &priv->status)) {
  2253. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2254. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2255. return -ETIMEDOUT;
  2256. }
  2257. }
  2258. iwl_led_start(priv);
  2259. out:
  2260. priv->is_open = 1;
  2261. IWL_DEBUG_MAC80211(priv, "leave\n");
  2262. return 0;
  2263. }
  2264. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2265. {
  2266. struct iwl_priv *priv = hw->priv;
  2267. IWL_DEBUG_MAC80211(priv, "enter\n");
  2268. if (!priv->is_open)
  2269. return;
  2270. priv->is_open = 0;
  2271. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2272. /* stop mac, cancel any scan request and clear
  2273. * RXON_FILTER_ASSOC_MSK BIT
  2274. */
  2275. mutex_lock(&priv->mutex);
  2276. iwl_scan_cancel_timeout(priv, 100);
  2277. mutex_unlock(&priv->mutex);
  2278. }
  2279. iwl_down(priv);
  2280. flush_workqueue(priv->workqueue);
  2281. /* enable interrupts again in order to receive rfkill changes */
  2282. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2283. iwl_enable_interrupts(priv);
  2284. IWL_DEBUG_MAC80211(priv, "leave\n");
  2285. }
  2286. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2287. {
  2288. struct iwl_priv *priv = hw->priv;
  2289. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2290. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2291. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2292. if (iwlagn_tx_skb(priv, skb))
  2293. dev_kfree_skb_any(skb);
  2294. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2295. return NETDEV_TX_OK;
  2296. }
  2297. void iwl_config_ap(struct iwl_priv *priv)
  2298. {
  2299. int ret = 0;
  2300. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2301. return;
  2302. /* The following should be done only at AP bring up */
  2303. if (!iwl_is_associated(priv)) {
  2304. /* RXON - unassoc (to set timing command) */
  2305. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2306. iwlcore_commit_rxon(priv);
  2307. /* RXON Timing */
  2308. iwl_setup_rxon_timing(priv);
  2309. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2310. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2311. if (ret)
  2312. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2313. "Attempting to continue.\n");
  2314. /* AP has all antennas */
  2315. priv->chain_noise_data.active_chains =
  2316. priv->hw_params.valid_rx_ant;
  2317. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2318. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2319. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2320. /* FIXME: what should be the assoc_id for AP? */
  2321. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2322. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2323. priv->staging_rxon.flags |=
  2324. RXON_FLG_SHORT_PREAMBLE_MSK;
  2325. else
  2326. priv->staging_rxon.flags &=
  2327. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2328. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2329. if (priv->assoc_capability &
  2330. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2331. priv->staging_rxon.flags |=
  2332. RXON_FLG_SHORT_SLOT_MSK;
  2333. else
  2334. priv->staging_rxon.flags &=
  2335. ~RXON_FLG_SHORT_SLOT_MSK;
  2336. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2337. priv->staging_rxon.flags &=
  2338. ~RXON_FLG_SHORT_SLOT_MSK;
  2339. }
  2340. /* restore RXON assoc */
  2341. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2342. iwlcore_commit_rxon(priv);
  2343. iwl_add_bcast_station(priv);
  2344. }
  2345. iwl_send_beacon_cmd(priv);
  2346. /* FIXME - we need to add code here to detect a totally new
  2347. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2348. * clear sta table, add BCAST sta... */
  2349. }
  2350. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2351. struct ieee80211_vif *vif,
  2352. struct ieee80211_key_conf *keyconf,
  2353. struct ieee80211_sta *sta,
  2354. u32 iv32, u16 *phase1key)
  2355. {
  2356. struct iwl_priv *priv = hw->priv;
  2357. IWL_DEBUG_MAC80211(priv, "enter\n");
  2358. iwl_update_tkip_key(priv, keyconf,
  2359. sta ? sta->addr : iwl_bcast_addr,
  2360. iv32, phase1key);
  2361. IWL_DEBUG_MAC80211(priv, "leave\n");
  2362. }
  2363. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2364. struct ieee80211_vif *vif,
  2365. struct ieee80211_sta *sta,
  2366. struct ieee80211_key_conf *key)
  2367. {
  2368. struct iwl_priv *priv = hw->priv;
  2369. const u8 *addr;
  2370. int ret;
  2371. u8 sta_id;
  2372. bool is_default_wep_key = false;
  2373. IWL_DEBUG_MAC80211(priv, "enter\n");
  2374. if (priv->cfg->mod_params->sw_crypto) {
  2375. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2376. return -EOPNOTSUPP;
  2377. }
  2378. addr = sta ? sta->addr : iwl_bcast_addr;
  2379. sta_id = iwl_find_station(priv, addr);
  2380. if (sta_id == IWL_INVALID_STATION) {
  2381. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2382. addr);
  2383. return -EINVAL;
  2384. }
  2385. mutex_lock(&priv->mutex);
  2386. iwl_scan_cancel_timeout(priv, 100);
  2387. /* If we are getting WEP group key and we didn't receive any key mapping
  2388. * so far, we are in legacy wep mode (group key only), otherwise we are
  2389. * in 1X mode.
  2390. * In legacy wep mode, we use another host command to the uCode */
  2391. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2392. priv->iw_mode != NL80211_IFTYPE_AP) {
  2393. if (cmd == SET_KEY)
  2394. is_default_wep_key = !priv->key_mapping_key;
  2395. else
  2396. is_default_wep_key =
  2397. (key->hw_key_idx == HW_KEY_DEFAULT);
  2398. }
  2399. switch (cmd) {
  2400. case SET_KEY:
  2401. if (is_default_wep_key)
  2402. ret = iwl_set_default_wep_key(priv, key);
  2403. else
  2404. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2405. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2406. break;
  2407. case DISABLE_KEY:
  2408. if (is_default_wep_key)
  2409. ret = iwl_remove_default_wep_key(priv, key);
  2410. else
  2411. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2412. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2413. break;
  2414. default:
  2415. ret = -EINVAL;
  2416. }
  2417. mutex_unlock(&priv->mutex);
  2418. IWL_DEBUG_MAC80211(priv, "leave\n");
  2419. return ret;
  2420. }
  2421. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2422. struct ieee80211_vif *vif,
  2423. enum ieee80211_ampdu_mlme_action action,
  2424. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2425. {
  2426. struct iwl_priv *priv = hw->priv;
  2427. int ret;
  2428. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2429. sta->addr, tid);
  2430. if (!(priv->cfg->sku & IWL_SKU_N))
  2431. return -EACCES;
  2432. switch (action) {
  2433. case IEEE80211_AMPDU_RX_START:
  2434. IWL_DEBUG_HT(priv, "start Rx\n");
  2435. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2436. case IEEE80211_AMPDU_RX_STOP:
  2437. IWL_DEBUG_HT(priv, "stop Rx\n");
  2438. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2439. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2440. return 0;
  2441. else
  2442. return ret;
  2443. case IEEE80211_AMPDU_TX_START:
  2444. IWL_DEBUG_HT(priv, "start Tx\n");
  2445. ret = iwlagn_tx_agg_start(priv, sta->addr, tid, ssn);
  2446. if (ret == 0) {
  2447. priv->_agn.agg_tids_count++;
  2448. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2449. priv->_agn.agg_tids_count);
  2450. }
  2451. return ret;
  2452. case IEEE80211_AMPDU_TX_STOP:
  2453. IWL_DEBUG_HT(priv, "stop Tx\n");
  2454. ret = iwlagn_tx_agg_stop(priv, sta->addr, tid);
  2455. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2456. priv->_agn.agg_tids_count--;
  2457. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2458. priv->_agn.agg_tids_count);
  2459. }
  2460. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2461. return 0;
  2462. else
  2463. return ret;
  2464. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2465. /* do nothing */
  2466. return -EOPNOTSUPP;
  2467. default:
  2468. IWL_DEBUG_HT(priv, "unknown\n");
  2469. return -EINVAL;
  2470. break;
  2471. }
  2472. return 0;
  2473. }
  2474. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2475. struct ieee80211_low_level_stats *stats)
  2476. {
  2477. struct iwl_priv *priv = hw->priv;
  2478. priv = hw->priv;
  2479. IWL_DEBUG_MAC80211(priv, "enter\n");
  2480. IWL_DEBUG_MAC80211(priv, "leave\n");
  2481. return 0;
  2482. }
  2483. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2484. struct ieee80211_vif *vif,
  2485. enum sta_notify_cmd cmd,
  2486. struct ieee80211_sta *sta)
  2487. {
  2488. struct iwl_priv *priv = hw->priv;
  2489. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2490. int sta_id;
  2491. switch (cmd) {
  2492. case STA_NOTIFY_SLEEP:
  2493. WARN_ON(!sta_priv->client);
  2494. sta_priv->asleep = true;
  2495. if (atomic_read(&sta_priv->pending_frames) > 0)
  2496. ieee80211_sta_block_awake(hw, sta, true);
  2497. break;
  2498. case STA_NOTIFY_AWAKE:
  2499. WARN_ON(!sta_priv->client);
  2500. if (!sta_priv->asleep)
  2501. break;
  2502. sta_priv->asleep = false;
  2503. sta_id = iwl_find_station(priv, sta->addr);
  2504. if (sta_id != IWL_INVALID_STATION)
  2505. iwl_sta_modify_ps_wake(priv, sta_id);
  2506. break;
  2507. default:
  2508. break;
  2509. }
  2510. }
  2511. /**
  2512. * iwl_restore_wepkeys - Restore WEP keys to device
  2513. */
  2514. static void iwl_restore_wepkeys(struct iwl_priv *priv)
  2515. {
  2516. mutex_lock(&priv->mutex);
  2517. if (priv->iw_mode == NL80211_IFTYPE_STATION &&
  2518. priv->default_wep_key &&
  2519. iwl_send_static_wepkey_cmd(priv, 0))
  2520. IWL_ERR(priv, "Could not send WEP static key\n");
  2521. mutex_unlock(&priv->mutex);
  2522. }
  2523. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2524. struct ieee80211_vif *vif,
  2525. struct ieee80211_sta *sta)
  2526. {
  2527. struct iwl_priv *priv = hw->priv;
  2528. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2529. bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION;
  2530. int ret;
  2531. u8 sta_id;
  2532. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2533. sta->addr);
  2534. atomic_set(&sta_priv->pending_frames, 0);
  2535. if (vif->type == NL80211_IFTYPE_AP)
  2536. sta_priv->client = true;
  2537. ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
  2538. &sta_id);
  2539. if (ret) {
  2540. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2541. sta->addr, ret);
  2542. /* Should we return success if return code is EEXIST ? */
  2543. return ret;
  2544. }
  2545. iwl_restore_wepkeys(priv);
  2546. /* Initialize rate scaling */
  2547. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2548. sta->addr);
  2549. iwl_rs_rate_init(priv, sta, sta_id);
  2550. return ret;
  2551. }
  2552. /*****************************************************************************
  2553. *
  2554. * sysfs attributes
  2555. *
  2556. *****************************************************************************/
  2557. #ifdef CONFIG_IWLWIFI_DEBUG
  2558. /*
  2559. * The following adds a new attribute to the sysfs representation
  2560. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2561. * used for controlling the debug level.
  2562. *
  2563. * See the level definitions in iwl for details.
  2564. *
  2565. * The debug_level being managed using sysfs below is a per device debug
  2566. * level that is used instead of the global debug level if it (the per
  2567. * device debug level) is set.
  2568. */
  2569. static ssize_t show_debug_level(struct device *d,
  2570. struct device_attribute *attr, char *buf)
  2571. {
  2572. struct iwl_priv *priv = dev_get_drvdata(d);
  2573. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2574. }
  2575. static ssize_t store_debug_level(struct device *d,
  2576. struct device_attribute *attr,
  2577. const char *buf, size_t count)
  2578. {
  2579. struct iwl_priv *priv = dev_get_drvdata(d);
  2580. unsigned long val;
  2581. int ret;
  2582. ret = strict_strtoul(buf, 0, &val);
  2583. if (ret)
  2584. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2585. else {
  2586. priv->debug_level = val;
  2587. if (iwl_alloc_traffic_mem(priv))
  2588. IWL_ERR(priv,
  2589. "Not enough memory to generate traffic log\n");
  2590. }
  2591. return strnlen(buf, count);
  2592. }
  2593. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2594. show_debug_level, store_debug_level);
  2595. #endif /* CONFIG_IWLWIFI_DEBUG */
  2596. static ssize_t show_temperature(struct device *d,
  2597. struct device_attribute *attr, char *buf)
  2598. {
  2599. struct iwl_priv *priv = dev_get_drvdata(d);
  2600. if (!iwl_is_alive(priv))
  2601. return -EAGAIN;
  2602. return sprintf(buf, "%d\n", priv->temperature);
  2603. }
  2604. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2605. static ssize_t show_tx_power(struct device *d,
  2606. struct device_attribute *attr, char *buf)
  2607. {
  2608. struct iwl_priv *priv = dev_get_drvdata(d);
  2609. if (!iwl_is_ready_rf(priv))
  2610. return sprintf(buf, "off\n");
  2611. else
  2612. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2613. }
  2614. static ssize_t store_tx_power(struct device *d,
  2615. struct device_attribute *attr,
  2616. const char *buf, size_t count)
  2617. {
  2618. struct iwl_priv *priv = dev_get_drvdata(d);
  2619. unsigned long val;
  2620. int ret;
  2621. ret = strict_strtoul(buf, 10, &val);
  2622. if (ret)
  2623. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2624. else {
  2625. ret = iwl_set_tx_power(priv, val, false);
  2626. if (ret)
  2627. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2628. ret);
  2629. else
  2630. ret = count;
  2631. }
  2632. return ret;
  2633. }
  2634. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2635. static ssize_t show_statistics(struct device *d,
  2636. struct device_attribute *attr, char *buf)
  2637. {
  2638. struct iwl_priv *priv = dev_get_drvdata(d);
  2639. u32 size = sizeof(struct iwl_notif_statistics);
  2640. u32 len = 0, ofs = 0;
  2641. u8 *data = (u8 *)&priv->statistics;
  2642. int rc = 0;
  2643. if (!iwl_is_alive(priv))
  2644. return -EAGAIN;
  2645. mutex_lock(&priv->mutex);
  2646. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2647. mutex_unlock(&priv->mutex);
  2648. if (rc) {
  2649. len = sprintf(buf,
  2650. "Error sending statistics request: 0x%08X\n", rc);
  2651. return len;
  2652. }
  2653. while (size && (PAGE_SIZE - len)) {
  2654. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2655. PAGE_SIZE - len, 1);
  2656. len = strlen(buf);
  2657. if (PAGE_SIZE - len)
  2658. buf[len++] = '\n';
  2659. ofs += 16;
  2660. size -= min(size, 16U);
  2661. }
  2662. return len;
  2663. }
  2664. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2665. static ssize_t show_rts_ht_protection(struct device *d,
  2666. struct device_attribute *attr, char *buf)
  2667. {
  2668. struct iwl_priv *priv = dev_get_drvdata(d);
  2669. return sprintf(buf, "%s\n",
  2670. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2671. }
  2672. static ssize_t store_rts_ht_protection(struct device *d,
  2673. struct device_attribute *attr,
  2674. const char *buf, size_t count)
  2675. {
  2676. struct iwl_priv *priv = dev_get_drvdata(d);
  2677. unsigned long val;
  2678. int ret;
  2679. ret = strict_strtoul(buf, 10, &val);
  2680. if (ret)
  2681. IWL_INFO(priv, "Input is not in decimal form.\n");
  2682. else {
  2683. if (!iwl_is_associated(priv))
  2684. priv->cfg->use_rts_for_ht = val ? true : false;
  2685. else
  2686. IWL_ERR(priv, "Sta associated with AP - "
  2687. "Change protection mechanism is not allowed\n");
  2688. ret = count;
  2689. }
  2690. return ret;
  2691. }
  2692. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2693. show_rts_ht_protection, store_rts_ht_protection);
  2694. /*****************************************************************************
  2695. *
  2696. * driver setup and teardown
  2697. *
  2698. *****************************************************************************/
  2699. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2700. {
  2701. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2702. init_waitqueue_head(&priv->wait_command_queue);
  2703. INIT_WORK(&priv->restart, iwl_bg_restart);
  2704. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2705. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2706. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2707. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2708. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2709. iwl_setup_scan_deferred_work(priv);
  2710. if (priv->cfg->ops->lib->setup_deferred_work)
  2711. priv->cfg->ops->lib->setup_deferred_work(priv);
  2712. init_timer(&priv->statistics_periodic);
  2713. priv->statistics_periodic.data = (unsigned long)priv;
  2714. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2715. init_timer(&priv->ucode_trace);
  2716. priv->ucode_trace.data = (unsigned long)priv;
  2717. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2718. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2719. init_timer(&priv->monitor_recover);
  2720. priv->monitor_recover.data = (unsigned long)priv;
  2721. priv->monitor_recover.function =
  2722. priv->cfg->ops->lib->recover_from_tx_stall;
  2723. }
  2724. if (!priv->cfg->use_isr_legacy)
  2725. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2726. iwl_irq_tasklet, (unsigned long)priv);
  2727. else
  2728. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2729. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2730. }
  2731. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2732. {
  2733. if (priv->cfg->ops->lib->cancel_deferred_work)
  2734. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2735. cancel_delayed_work_sync(&priv->init_alive_start);
  2736. cancel_delayed_work(&priv->scan_check);
  2737. cancel_delayed_work(&priv->alive_start);
  2738. cancel_work_sync(&priv->beacon_update);
  2739. del_timer_sync(&priv->statistics_periodic);
  2740. del_timer_sync(&priv->ucode_trace);
  2741. if (priv->cfg->ops->lib->recover_from_tx_stall)
  2742. del_timer_sync(&priv->monitor_recover);
  2743. }
  2744. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2745. struct ieee80211_rate *rates)
  2746. {
  2747. int i;
  2748. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2749. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2750. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2751. rates[i].hw_value_short = i;
  2752. rates[i].flags = 0;
  2753. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2754. /*
  2755. * If CCK != 1M then set short preamble rate flag.
  2756. */
  2757. rates[i].flags |=
  2758. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2759. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2760. }
  2761. }
  2762. }
  2763. static int iwl_init_drv(struct iwl_priv *priv)
  2764. {
  2765. int ret;
  2766. priv->ibss_beacon = NULL;
  2767. spin_lock_init(&priv->sta_lock);
  2768. spin_lock_init(&priv->hcmd_lock);
  2769. INIT_LIST_HEAD(&priv->free_frames);
  2770. mutex_init(&priv->mutex);
  2771. mutex_init(&priv->sync_cmd_mutex);
  2772. priv->ieee_channels = NULL;
  2773. priv->ieee_rates = NULL;
  2774. priv->band = IEEE80211_BAND_2GHZ;
  2775. priv->iw_mode = NL80211_IFTYPE_STATION;
  2776. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2777. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2778. priv->_agn.agg_tids_count = 0;
  2779. /* initialize force reset */
  2780. priv->force_reset[IWL_RF_RESET].reset_duration =
  2781. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2782. priv->force_reset[IWL_FW_RESET].reset_duration =
  2783. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2784. /* Choose which receivers/antennas to use */
  2785. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2786. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2787. iwl_init_scan_params(priv);
  2788. /* Set the tx_power_user_lmt to the lowest power level
  2789. * this value will get overwritten by channel max power avg
  2790. * from eeprom */
  2791. priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  2792. ret = iwl_init_channel_map(priv);
  2793. if (ret) {
  2794. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2795. goto err;
  2796. }
  2797. ret = iwlcore_init_geos(priv);
  2798. if (ret) {
  2799. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2800. goto err_free_channel_map;
  2801. }
  2802. iwl_init_hw_rates(priv, priv->ieee_rates);
  2803. return 0;
  2804. err_free_channel_map:
  2805. iwl_free_channel_map(priv);
  2806. err:
  2807. return ret;
  2808. }
  2809. static void iwl_uninit_drv(struct iwl_priv *priv)
  2810. {
  2811. iwl_calib_free_results(priv);
  2812. iwlcore_free_geos(priv);
  2813. iwl_free_channel_map(priv);
  2814. kfree(priv->scan);
  2815. }
  2816. static struct attribute *iwl_sysfs_entries[] = {
  2817. &dev_attr_statistics.attr,
  2818. &dev_attr_temperature.attr,
  2819. &dev_attr_tx_power.attr,
  2820. &dev_attr_rts_ht_protection.attr,
  2821. #ifdef CONFIG_IWLWIFI_DEBUG
  2822. &dev_attr_debug_level.attr,
  2823. #endif
  2824. NULL
  2825. };
  2826. static struct attribute_group iwl_attribute_group = {
  2827. .name = NULL, /* put in device directory */
  2828. .attrs = iwl_sysfs_entries,
  2829. };
  2830. static struct ieee80211_ops iwl_hw_ops = {
  2831. .tx = iwl_mac_tx,
  2832. .start = iwl_mac_start,
  2833. .stop = iwl_mac_stop,
  2834. .add_interface = iwl_mac_add_interface,
  2835. .remove_interface = iwl_mac_remove_interface,
  2836. .config = iwl_mac_config,
  2837. .configure_filter = iwl_configure_filter,
  2838. .set_key = iwl_mac_set_key,
  2839. .update_tkip_key = iwl_mac_update_tkip_key,
  2840. .get_stats = iwl_mac_get_stats,
  2841. .conf_tx = iwl_mac_conf_tx,
  2842. .reset_tsf = iwl_mac_reset_tsf,
  2843. .bss_info_changed = iwl_bss_info_changed,
  2844. .ampdu_action = iwl_mac_ampdu_action,
  2845. .hw_scan = iwl_mac_hw_scan,
  2846. .sta_notify = iwl_mac_sta_notify,
  2847. .sta_add = iwlagn_mac_sta_add,
  2848. .sta_remove = iwl_mac_sta_remove,
  2849. };
  2850. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2851. {
  2852. int err = 0;
  2853. struct iwl_priv *priv;
  2854. struct ieee80211_hw *hw;
  2855. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2856. unsigned long flags;
  2857. u16 pci_cmd;
  2858. /************************
  2859. * 1. Allocating HW data
  2860. ************************/
  2861. /* Disabling hardware scan means that mac80211 will perform scans
  2862. * "the hard way", rather than using device's scan. */
  2863. if (cfg->mod_params->disable_hw_scan) {
  2864. if (iwl_debug_level & IWL_DL_INFO)
  2865. dev_printk(KERN_DEBUG, &(pdev->dev),
  2866. "Disabling hw_scan\n");
  2867. iwl_hw_ops.hw_scan = NULL;
  2868. }
  2869. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2870. if (!hw) {
  2871. err = -ENOMEM;
  2872. goto out;
  2873. }
  2874. priv = hw->priv;
  2875. /* At this point both hw and priv are allocated. */
  2876. SET_IEEE80211_DEV(hw, &pdev->dev);
  2877. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2878. priv->cfg = cfg;
  2879. priv->pci_dev = pdev;
  2880. priv->inta_mask = CSR_INI_SET_MASK;
  2881. #ifdef CONFIG_IWLWIFI_DEBUG
  2882. atomic_set(&priv->restrict_refcnt, 0);
  2883. #endif
  2884. if (iwl_alloc_traffic_mem(priv))
  2885. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2886. /**************************
  2887. * 2. Initializing PCI bus
  2888. **************************/
  2889. if (pci_enable_device(pdev)) {
  2890. err = -ENODEV;
  2891. goto out_ieee80211_free_hw;
  2892. }
  2893. pci_set_master(pdev);
  2894. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2895. if (!err)
  2896. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2897. if (err) {
  2898. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2899. if (!err)
  2900. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2901. /* both attempts failed: */
  2902. if (err) {
  2903. IWL_WARN(priv, "No suitable DMA available.\n");
  2904. goto out_pci_disable_device;
  2905. }
  2906. }
  2907. err = pci_request_regions(pdev, DRV_NAME);
  2908. if (err)
  2909. goto out_pci_disable_device;
  2910. pci_set_drvdata(pdev, priv);
  2911. /***********************
  2912. * 3. Read REV register
  2913. ***********************/
  2914. priv->hw_base = pci_iomap(pdev, 0, 0);
  2915. if (!priv->hw_base) {
  2916. err = -ENODEV;
  2917. goto out_pci_release_regions;
  2918. }
  2919. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2920. (unsigned long long) pci_resource_len(pdev, 0));
  2921. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2922. /* these spin locks will be used in apm_ops.init and EEPROM access
  2923. * we should init now
  2924. */
  2925. spin_lock_init(&priv->reg_lock);
  2926. spin_lock_init(&priv->lock);
  2927. /*
  2928. * stop and reset the on-board processor just in case it is in a
  2929. * strange state ... like being left stranded by a primary kernel
  2930. * and this is now the kdump kernel trying to start up
  2931. */
  2932. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2933. iwl_hw_detect(priv);
  2934. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  2935. priv->cfg->name, priv->hw_rev);
  2936. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2937. * PCI Tx retries from interfering with C3 CPU state */
  2938. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2939. iwl_prepare_card_hw(priv);
  2940. if (!priv->hw_ready) {
  2941. IWL_WARN(priv, "Failed, HW not ready\n");
  2942. goto out_iounmap;
  2943. }
  2944. /*****************
  2945. * 4. Read EEPROM
  2946. *****************/
  2947. /* Read the EEPROM */
  2948. err = iwl_eeprom_init(priv);
  2949. if (err) {
  2950. IWL_ERR(priv, "Unable to init EEPROM\n");
  2951. goto out_iounmap;
  2952. }
  2953. err = iwl_eeprom_check_version(priv);
  2954. if (err)
  2955. goto out_free_eeprom;
  2956. /* extract MAC Address */
  2957. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2958. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2959. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2960. /************************
  2961. * 5. Setup HW constants
  2962. ************************/
  2963. if (iwl_set_hw_params(priv)) {
  2964. IWL_ERR(priv, "failed to set hw parameters\n");
  2965. goto out_free_eeprom;
  2966. }
  2967. /*******************
  2968. * 6. Setup priv
  2969. *******************/
  2970. err = iwl_init_drv(priv);
  2971. if (err)
  2972. goto out_free_eeprom;
  2973. /* At this point both hw and priv are initialized. */
  2974. /********************
  2975. * 7. Setup services
  2976. ********************/
  2977. spin_lock_irqsave(&priv->lock, flags);
  2978. iwl_disable_interrupts(priv);
  2979. spin_unlock_irqrestore(&priv->lock, flags);
  2980. pci_enable_msi(priv->pci_dev);
  2981. iwl_alloc_isr_ict(priv);
  2982. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2983. IRQF_SHARED, DRV_NAME, priv);
  2984. if (err) {
  2985. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2986. goto out_disable_msi;
  2987. }
  2988. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2989. if (err) {
  2990. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2991. goto out_free_irq;
  2992. }
  2993. iwl_setup_deferred_work(priv);
  2994. iwl_setup_rx_handlers(priv);
  2995. /*********************************************
  2996. * 8. Enable interrupts and read RFKILL state
  2997. *********************************************/
  2998. /* enable interrupts if needed: hw bug w/a */
  2999. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3000. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3001. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3002. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3003. }
  3004. iwl_enable_interrupts(priv);
  3005. /* If platform's RF_KILL switch is NOT set to KILL */
  3006. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3007. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3008. else
  3009. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3010. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3011. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3012. iwl_power_initialize(priv);
  3013. iwl_tt_initialize(priv);
  3014. err = iwl_request_firmware(priv, true);
  3015. if (err)
  3016. goto out_remove_sysfs;
  3017. return 0;
  3018. out_remove_sysfs:
  3019. destroy_workqueue(priv->workqueue);
  3020. priv->workqueue = NULL;
  3021. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3022. out_free_irq:
  3023. free_irq(priv->pci_dev->irq, priv);
  3024. iwl_free_isr_ict(priv);
  3025. out_disable_msi:
  3026. pci_disable_msi(priv->pci_dev);
  3027. iwl_uninit_drv(priv);
  3028. out_free_eeprom:
  3029. iwl_eeprom_free(priv);
  3030. out_iounmap:
  3031. pci_iounmap(pdev, priv->hw_base);
  3032. out_pci_release_regions:
  3033. pci_set_drvdata(pdev, NULL);
  3034. pci_release_regions(pdev);
  3035. out_pci_disable_device:
  3036. pci_disable_device(pdev);
  3037. out_ieee80211_free_hw:
  3038. iwl_free_traffic_mem(priv);
  3039. ieee80211_free_hw(priv->hw);
  3040. out:
  3041. return err;
  3042. }
  3043. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3044. {
  3045. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3046. unsigned long flags;
  3047. if (!priv)
  3048. return;
  3049. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3050. iwl_dbgfs_unregister(priv);
  3051. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3052. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3053. * to be called and iwl_down since we are removing the device
  3054. * we need to set STATUS_EXIT_PENDING bit.
  3055. */
  3056. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3057. if (priv->mac80211_registered) {
  3058. ieee80211_unregister_hw(priv->hw);
  3059. priv->mac80211_registered = 0;
  3060. } else {
  3061. iwl_down(priv);
  3062. }
  3063. /*
  3064. * Make sure device is reset to low power before unloading driver.
  3065. * This may be redundant with iwl_down(), but there are paths to
  3066. * run iwl_down() without calling apm_ops.stop(), and there are
  3067. * paths to avoid running iwl_down() at all before leaving driver.
  3068. * This (inexpensive) call *makes sure* device is reset.
  3069. */
  3070. priv->cfg->ops->lib->apm_ops.stop(priv);
  3071. iwl_tt_exit(priv);
  3072. /* make sure we flush any pending irq or
  3073. * tasklet for the driver
  3074. */
  3075. spin_lock_irqsave(&priv->lock, flags);
  3076. iwl_disable_interrupts(priv);
  3077. spin_unlock_irqrestore(&priv->lock, flags);
  3078. iwl_synchronize_irq(priv);
  3079. iwl_dealloc_ucode_pci(priv);
  3080. if (priv->rxq.bd)
  3081. iwlagn_rx_queue_free(priv, &priv->rxq);
  3082. iwlagn_hw_txq_ctx_free(priv);
  3083. iwl_eeprom_free(priv);
  3084. /*netif_stop_queue(dev); */
  3085. flush_workqueue(priv->workqueue);
  3086. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3087. * priv->workqueue... so we can't take down the workqueue
  3088. * until now... */
  3089. destroy_workqueue(priv->workqueue);
  3090. priv->workqueue = NULL;
  3091. iwl_free_traffic_mem(priv);
  3092. free_irq(priv->pci_dev->irq, priv);
  3093. pci_disable_msi(priv->pci_dev);
  3094. pci_iounmap(pdev, priv->hw_base);
  3095. pci_release_regions(pdev);
  3096. pci_disable_device(pdev);
  3097. pci_set_drvdata(pdev, NULL);
  3098. iwl_uninit_drv(priv);
  3099. iwl_free_isr_ict(priv);
  3100. if (priv->ibss_beacon)
  3101. dev_kfree_skb(priv->ibss_beacon);
  3102. ieee80211_free_hw(priv->hw);
  3103. }
  3104. /*****************************************************************************
  3105. *
  3106. * driver and module entry point
  3107. *
  3108. *****************************************************************************/
  3109. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3110. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3111. #ifdef CONFIG_IWL4965
  3112. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3113. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3114. #endif /* CONFIG_IWL4965 */
  3115. #ifdef CONFIG_IWL5000
  3116. /* 5100 Series WiFi */
  3117. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3118. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3119. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3120. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3121. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3122. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3123. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3124. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3125. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3126. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3127. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3128. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3129. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3130. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3131. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3132. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3133. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3134. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3135. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3136. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3137. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3138. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3139. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3140. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3141. /* 5300 Series WiFi */
  3142. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3143. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3144. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3145. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3146. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3147. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3148. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3149. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3150. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3151. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3152. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3153. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3154. /* 5350 Series WiFi/WiMax */
  3155. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3156. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3157. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3158. /* 5150 Series Wifi/WiMax */
  3159. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3160. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3161. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3162. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3163. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3164. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3165. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3166. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3167. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3168. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3169. /* 6x00 Series */
  3170. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3171. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3172. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3173. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3174. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3175. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3176. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3177. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3178. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3179. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3180. {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000i_g2_2agn_cfg)},
  3181. /* 6x50 WiFi/WiMax Series */
  3182. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3183. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3184. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3185. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3186. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3187. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3188. /* 1000 Series WiFi */
  3189. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3190. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3191. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3192. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3193. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3194. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3195. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3196. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3197. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3198. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3199. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3200. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3201. #endif /* CONFIG_IWL5000 */
  3202. {0}
  3203. };
  3204. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3205. static struct pci_driver iwl_driver = {
  3206. .name = DRV_NAME,
  3207. .id_table = iwl_hw_card_ids,
  3208. .probe = iwl_pci_probe,
  3209. .remove = __devexit_p(iwl_pci_remove),
  3210. #ifdef CONFIG_PM
  3211. .suspend = iwl_pci_suspend,
  3212. .resume = iwl_pci_resume,
  3213. #endif
  3214. };
  3215. static int __init iwl_init(void)
  3216. {
  3217. int ret;
  3218. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3219. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3220. ret = iwlagn_rate_control_register();
  3221. if (ret) {
  3222. printk(KERN_ERR DRV_NAME
  3223. "Unable to register rate control algorithm: %d\n", ret);
  3224. return ret;
  3225. }
  3226. ret = pci_register_driver(&iwl_driver);
  3227. if (ret) {
  3228. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3229. goto error_register;
  3230. }
  3231. return ret;
  3232. error_register:
  3233. iwlagn_rate_control_unregister();
  3234. return ret;
  3235. }
  3236. static void __exit iwl_exit(void)
  3237. {
  3238. pci_unregister_driver(&iwl_driver);
  3239. iwlagn_rate_control_unregister();
  3240. }
  3241. module_exit(iwl_exit);
  3242. module_init(iwl_init);
  3243. #ifdef CONFIG_IWLWIFI_DEBUG
  3244. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3245. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3246. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3247. MODULE_PARM_DESC(debug, "debug output mask");
  3248. #endif
  3249. module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
  3250. MODULE_PARM_DESC(swcrypto50,
  3251. "using crypto in software (default 0 [hardware]) (deprecated)");
  3252. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3253. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3254. module_param_named(queues_num50,
  3255. iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3256. MODULE_PARM_DESC(queues_num50,
  3257. "number of hw queues in 50xx series (deprecated)");
  3258. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3259. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3260. module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3261. MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
  3262. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3263. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3264. module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
  3265. int, S_IRUGO);
  3266. MODULE_PARM_DESC(amsdu_size_8K50,
  3267. "enable 8K amsdu size in 50XX series (deprecated)");
  3268. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3269. int, S_IRUGO);
  3270. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3271. module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3272. MODULE_PARM_DESC(fw_restart50,
  3273. "restart firmware in case of error (deprecated)");
  3274. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3275. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3276. module_param_named(
  3277. disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
  3278. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");