mpc8349emitx.dts 8.4 KB

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  1. /*
  2. * MPC8349E-mITX Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITX";
  14. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>;
  43. };
  44. soc8349@e0000000 {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. device_type = "soc";
  48. compatible = "simple-bus";
  49. ranges = <0x0 0xe0000000 0x00100000>;
  50. reg = <0xe0000000 0x00000200>;
  51. bus-frequency = <0>; // from bootloader
  52. wdt@200 {
  53. device_type = "watchdog";
  54. compatible = "mpc83xx_wdt";
  55. reg = <0x200 0x100>;
  56. };
  57. gpio1: gpio-controller@c00 {
  58. #gpio-cells = <2>;
  59. compatible = "fsl,mpc8349-gpio";
  60. reg = <0xc00 0x100>;
  61. interrupts = <74 0x8>;
  62. interrupt-parent = <&ipic>;
  63. gpio-controller;
  64. };
  65. gpio2: gpio-controller@d00 {
  66. #gpio-cells = <2>;
  67. compatible = "fsl,mpc8349-gpio";
  68. reg = <0xd00 0x100>;
  69. interrupts = <75 0x8>;
  70. interrupt-parent = <&ipic>;
  71. gpio-controller;
  72. };
  73. i2c@3000 {
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. cell-index = <0>;
  77. compatible = "fsl-i2c";
  78. reg = <0x3000 0x100>;
  79. interrupts = <14 0x8>;
  80. interrupt-parent = <&ipic>;
  81. dfsrr;
  82. };
  83. i2c@3100 {
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. cell-index = <1>;
  87. compatible = "fsl-i2c";
  88. reg = <0x3100 0x100>;
  89. interrupts = <15 0x8>;
  90. interrupt-parent = <&ipic>;
  91. dfsrr;
  92. rtc@68 {
  93. compatible = "dallas,ds1339";
  94. reg = <0x68>;
  95. interrupts = <18 0x8>;
  96. interrupt-parent = <&ipic>;
  97. };
  98. mcu_pio: mcu@a {
  99. #gpio-cells = <2>;
  100. compatible = "fsl,mc9s08qg8-mpc8349emitx",
  101. "fsl,mcu-mpc8349emitx";
  102. reg = <0x0a>;
  103. gpio-controller;
  104. };
  105. };
  106. spi@7000 {
  107. cell-index = <0>;
  108. compatible = "fsl,spi";
  109. reg = <0x7000 0x1000>;
  110. interrupts = <16 0x8>;
  111. interrupt-parent = <&ipic>;
  112. mode = "cpu";
  113. };
  114. dma@82a8 {
  115. #address-cells = <1>;
  116. #size-cells = <1>;
  117. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  118. reg = <0x82a8 4>;
  119. ranges = <0 0x8100 0x1a8>;
  120. interrupt-parent = <&ipic>;
  121. interrupts = <71 8>;
  122. cell-index = <0>;
  123. dma-channel@0 {
  124. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  125. reg = <0 0x80>;
  126. cell-index = <0>;
  127. interrupt-parent = <&ipic>;
  128. interrupts = <71 8>;
  129. };
  130. dma-channel@80 {
  131. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  132. reg = <0x80 0x80>;
  133. cell-index = <1>;
  134. interrupt-parent = <&ipic>;
  135. interrupts = <71 8>;
  136. };
  137. dma-channel@100 {
  138. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  139. reg = <0x100 0x80>;
  140. cell-index = <2>;
  141. interrupt-parent = <&ipic>;
  142. interrupts = <71 8>;
  143. };
  144. dma-channel@180 {
  145. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  146. reg = <0x180 0x28>;
  147. cell-index = <3>;
  148. interrupt-parent = <&ipic>;
  149. interrupts = <71 8>;
  150. };
  151. };
  152. usb@22000 {
  153. compatible = "fsl-usb2-mph";
  154. reg = <0x22000 0x1000>;
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. interrupt-parent = <&ipic>;
  158. interrupts = <39 0x8>;
  159. phy_type = "ulpi";
  160. port0;
  161. };
  162. usb@23000 {
  163. compatible = "fsl-usb2-dr";
  164. reg = <0x23000 0x1000>;
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. interrupt-parent = <&ipic>;
  168. interrupts = <38 0x8>;
  169. dr_mode = "peripheral";
  170. phy_type = "ulpi";
  171. };
  172. enet0: ethernet@24000 {
  173. #address-cells = <1>;
  174. #size-cells = <1>;
  175. cell-index = <0>;
  176. device_type = "network";
  177. model = "TSEC";
  178. compatible = "gianfar";
  179. reg = <0x24000 0x1000>;
  180. ranges = <0x0 0x24000 0x1000>;
  181. local-mac-address = [ 00 00 00 00 00 00 ];
  182. interrupts = <32 0x8 33 0x8 34 0x8>;
  183. interrupt-parent = <&ipic>;
  184. tbi-handle = <&tbi0>;
  185. phy-handle = <&phy1c>;
  186. linux,network-index = <0>;
  187. mdio@520 {
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. compatible = "fsl,gianfar-mdio";
  191. reg = <0x520 0x20>;
  192. /* Vitesse 8201 */
  193. phy1c: ethernet-phy@1c {
  194. interrupt-parent = <&ipic>;
  195. interrupts = <18 0x8>;
  196. reg = <0x1c>;
  197. device_type = "ethernet-phy";
  198. };
  199. tbi0: tbi-phy@11 {
  200. reg = <0x11>;
  201. device_type = "tbi-phy";
  202. };
  203. };
  204. };
  205. enet1: ethernet@25000 {
  206. #address-cells = <1>;
  207. #size-cells = <1>;
  208. cell-index = <1>;
  209. device_type = "network";
  210. model = "TSEC";
  211. compatible = "gianfar";
  212. reg = <0x25000 0x1000>;
  213. ranges = <0x0 0x25000 0x1000>;
  214. local-mac-address = [ 00 00 00 00 00 00 ];
  215. interrupts = <35 0x8 36 0x8 37 0x8>;
  216. interrupt-parent = <&ipic>;
  217. /* Vitesse 7385 isn't on the MDIO bus */
  218. fixed-link = <1 1 1000 0 0>;
  219. linux,network-index = <1>;
  220. tbi-handle = <&tbi1>;
  221. mdio@520 {
  222. #address-cells = <1>;
  223. #size-cells = <0>;
  224. compatible = "fsl,gianfar-tbi";
  225. reg = <0x520 0x20>;
  226. tbi1: tbi-phy@11 {
  227. reg = <0x11>;
  228. device_type = "tbi-phy";
  229. };
  230. };
  231. };
  232. serial0: serial@4500 {
  233. cell-index = <0>;
  234. device_type = "serial";
  235. compatible = "ns16550";
  236. reg = <0x4500 0x100>;
  237. clock-frequency = <0>; // from bootloader
  238. interrupts = <9 0x8>;
  239. interrupt-parent = <&ipic>;
  240. };
  241. serial1: serial@4600 {
  242. cell-index = <1>;
  243. device_type = "serial";
  244. compatible = "ns16550";
  245. reg = <0x4600 0x100>;
  246. clock-frequency = <0>; // from bootloader
  247. interrupts = <10 0x8>;
  248. interrupt-parent = <&ipic>;
  249. };
  250. crypto@30000 {
  251. compatible = "fsl,sec2.0";
  252. reg = <0x30000 0x10000>;
  253. interrupts = <11 0x8>;
  254. interrupt-parent = <&ipic>;
  255. fsl,num-channels = <4>;
  256. fsl,channel-fifo-len = <24>;
  257. fsl,exec-units-mask = <0x7e>;
  258. fsl,descriptor-types-mask = <0x01010ebf>;
  259. };
  260. ipic: pic@700 {
  261. interrupt-controller;
  262. #address-cells = <0>;
  263. #interrupt-cells = <2>;
  264. reg = <0x700 0x100>;
  265. device_type = "ipic";
  266. };
  267. };
  268. pci0: pci@e0008500 {
  269. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  270. interrupt-map = <
  271. /* IDSEL 0x10 - SATA */
  272. 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
  273. >;
  274. interrupt-parent = <&ipic>;
  275. interrupts = <66 0x8>;
  276. bus-range = <0x0 0x0>;
  277. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  278. 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  279. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
  280. clock-frequency = <66666666>;
  281. #interrupt-cells = <1>;
  282. #size-cells = <2>;
  283. #address-cells = <3>;
  284. reg = <0xe0008500 0x100 /* internal registers */
  285. 0xe0008300 0x8>; /* config space access registers */
  286. compatible = "fsl,mpc8349-pci";
  287. device_type = "pci";
  288. };
  289. pci1: pci@e0008600 {
  290. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  291. interrupt-map = <
  292. /* IDSEL 0x0E - MiniPCI Slot */
  293. 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
  294. /* IDSEL 0x0F - PCI Slot */
  295. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  296. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  297. >;
  298. interrupt-parent = <&ipic>;
  299. interrupts = <67 0x8>;
  300. bus-range = <0x0 0x0>;
  301. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  302. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  303. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  304. clock-frequency = <66666666>;
  305. #interrupt-cells = <1>;
  306. #size-cells = <2>;
  307. #address-cells = <3>;
  308. reg = <0xe0008600 0x100 /* internal registers */
  309. 0xe0008380 0x8>; /* config space access registers */
  310. compatible = "fsl,mpc8349-pci";
  311. device_type = "pci";
  312. };
  313. localbus@e0005000 {
  314. #address-cells = <2>;
  315. #size-cells = <1>;
  316. compatible = "fsl,mpc8349e-localbus",
  317. "fsl,pq2pro-localbus";
  318. reg = <0xe0005000 0xd8>;
  319. ranges = <0x3 0x0 0xf0000000 0x210>;
  320. pata@3,0 {
  321. compatible = "fsl,mpc8349emitx-pata", "ata-generic";
  322. reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
  323. reg-shift = <1>;
  324. pio-mode = <6>;
  325. interrupts = <23 0x8>;
  326. interrupt-parent = <&ipic>;
  327. };
  328. };
  329. };