events.c 35 KB

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  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is recieved, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. /* IRQ <-> VIRQ mapping. */
  55. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  56. /* IRQ <-> IPI mapping */
  57. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  58. /* Interrupt types. */
  59. enum xen_irq_type {
  60. IRQT_UNBOUND = 0,
  61. IRQT_PIRQ,
  62. IRQT_VIRQ,
  63. IRQT_IPI,
  64. IRQT_EVTCHN
  65. };
  66. /*
  67. * Packed IRQ information:
  68. * type - enum xen_irq_type
  69. * event channel - irq->event channel mapping
  70. * cpu - cpu this event channel is bound to
  71. * index - type-specific information:
  72. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  73. * guest, or GSI (real passthrough IRQ) of the device.
  74. * VIRQ - virq number
  75. * IPI - IPI vector
  76. * EVTCHN -
  77. */
  78. struct irq_info
  79. {
  80. enum xen_irq_type type; /* type */
  81. unsigned short evtchn; /* event channel */
  82. unsigned short cpu; /* cpu bound */
  83. union {
  84. unsigned short virq;
  85. enum ipi_vector ipi;
  86. struct {
  87. unsigned short pirq;
  88. unsigned short gsi;
  89. unsigned char vector;
  90. unsigned char flags;
  91. } pirq;
  92. } u;
  93. };
  94. #define PIRQ_NEEDS_EOI (1 << 0)
  95. #define PIRQ_SHAREABLE (1 << 1)
  96. static struct irq_info *irq_info;
  97. static int *pirq_to_irq;
  98. static int *evtchn_to_irq;
  99. static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
  100. cpu_evtchn_mask);
  101. /* Xen will never allocate port zero for any purpose. */
  102. #define VALID_EVTCHN(chn) ((chn) != 0)
  103. static struct irq_chip xen_dynamic_chip;
  104. static struct irq_chip xen_percpu_chip;
  105. static struct irq_chip xen_pirq_chip;
  106. /* Get info for IRQ */
  107. static struct irq_info *info_for_irq(unsigned irq)
  108. {
  109. return &irq_info[irq];
  110. }
  111. /* Constructors for packed IRQ information. */
  112. static void xen_irq_info_common_init(struct irq_info *info,
  113. enum xen_irq_type type,
  114. unsigned short evtchn,
  115. unsigned short cpu)
  116. {
  117. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  118. info->type = type;
  119. info->evtchn = evtchn;
  120. info->cpu = cpu;
  121. }
  122. static void xen_irq_info_evtchn_init(unsigned irq,
  123. unsigned short evtchn)
  124. {
  125. struct irq_info *info = info_for_irq(irq);
  126. xen_irq_info_common_init(info, IRQT_EVTCHN, evtchn, 0);
  127. }
  128. static void xen_irq_info_ipi_init(unsigned irq,
  129. unsigned short evtchn,
  130. enum ipi_vector ipi)
  131. {
  132. struct irq_info *info = info_for_irq(irq);
  133. xen_irq_info_common_init(info, IRQT_IPI, evtchn, 0);
  134. info->u.ipi = ipi;
  135. }
  136. static void xen_irq_info_virq_init(unsigned irq,
  137. unsigned short evtchn,
  138. unsigned short virq)
  139. {
  140. struct irq_info *info = info_for_irq(irq);
  141. xen_irq_info_common_init(info, IRQT_VIRQ, evtchn, 0);
  142. info->u.virq = virq;
  143. }
  144. static void xen_irq_info_pirq_init(unsigned irq,
  145. unsigned short evtchn,
  146. unsigned short pirq,
  147. unsigned short gsi,
  148. unsigned short vector,
  149. unsigned char flags)
  150. {
  151. struct irq_info *info = info_for_irq(irq);
  152. xen_irq_info_common_init(info, IRQT_PIRQ, evtchn, 0);
  153. info->u.pirq.pirq = pirq;
  154. info->u.pirq.gsi = gsi;
  155. info->u.pirq.vector = vector;
  156. info->u.pirq.flags = flags;
  157. }
  158. /*
  159. * Accessors for packed IRQ information.
  160. */
  161. static unsigned int evtchn_from_irq(unsigned irq)
  162. {
  163. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  164. return 0;
  165. return info_for_irq(irq)->evtchn;
  166. }
  167. unsigned irq_from_evtchn(unsigned int evtchn)
  168. {
  169. return evtchn_to_irq[evtchn];
  170. }
  171. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  172. static enum ipi_vector ipi_from_irq(unsigned irq)
  173. {
  174. struct irq_info *info = info_for_irq(irq);
  175. BUG_ON(info == NULL);
  176. BUG_ON(info->type != IRQT_IPI);
  177. return info->u.ipi;
  178. }
  179. static unsigned virq_from_irq(unsigned irq)
  180. {
  181. struct irq_info *info = info_for_irq(irq);
  182. BUG_ON(info == NULL);
  183. BUG_ON(info->type != IRQT_VIRQ);
  184. return info->u.virq;
  185. }
  186. static unsigned pirq_from_irq(unsigned irq)
  187. {
  188. struct irq_info *info = info_for_irq(irq);
  189. BUG_ON(info == NULL);
  190. BUG_ON(info->type != IRQT_PIRQ);
  191. return info->u.pirq.pirq;
  192. }
  193. static unsigned gsi_from_irq(unsigned irq)
  194. {
  195. struct irq_info *info = info_for_irq(irq);
  196. BUG_ON(info == NULL);
  197. BUG_ON(info->type != IRQT_PIRQ);
  198. return info->u.pirq.gsi;
  199. }
  200. static enum xen_irq_type type_from_irq(unsigned irq)
  201. {
  202. return info_for_irq(irq)->type;
  203. }
  204. static unsigned cpu_from_irq(unsigned irq)
  205. {
  206. return info_for_irq(irq)->cpu;
  207. }
  208. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  209. {
  210. int irq = evtchn_to_irq[evtchn];
  211. unsigned ret = 0;
  212. if (irq != -1)
  213. ret = cpu_from_irq(irq);
  214. return ret;
  215. }
  216. static bool pirq_needs_eoi(unsigned irq)
  217. {
  218. struct irq_info *info = info_for_irq(irq);
  219. BUG_ON(info->type != IRQT_PIRQ);
  220. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  221. }
  222. static inline unsigned long active_evtchns(unsigned int cpu,
  223. struct shared_info *sh,
  224. unsigned int idx)
  225. {
  226. return (sh->evtchn_pending[idx] &
  227. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  228. ~sh->evtchn_mask[idx]);
  229. }
  230. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  231. {
  232. int irq = evtchn_to_irq[chn];
  233. BUG_ON(irq == -1);
  234. #ifdef CONFIG_SMP
  235. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  236. #endif
  237. clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
  238. set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
  239. irq_info[irq].cpu = cpu;
  240. }
  241. static void init_evtchn_cpu_bindings(void)
  242. {
  243. int i;
  244. #ifdef CONFIG_SMP
  245. struct irq_desc *desc;
  246. /* By default all event channels notify CPU#0. */
  247. for_each_irq_desc(i, desc) {
  248. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  249. }
  250. #endif
  251. for_each_possible_cpu(i)
  252. memset(per_cpu(cpu_evtchn_mask, i),
  253. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  254. }
  255. static inline void clear_evtchn(int port)
  256. {
  257. struct shared_info *s = HYPERVISOR_shared_info;
  258. sync_clear_bit(port, &s->evtchn_pending[0]);
  259. }
  260. static inline void set_evtchn(int port)
  261. {
  262. struct shared_info *s = HYPERVISOR_shared_info;
  263. sync_set_bit(port, &s->evtchn_pending[0]);
  264. }
  265. static inline int test_evtchn(int port)
  266. {
  267. struct shared_info *s = HYPERVISOR_shared_info;
  268. return sync_test_bit(port, &s->evtchn_pending[0]);
  269. }
  270. /**
  271. * notify_remote_via_irq - send event to remote end of event channel via irq
  272. * @irq: irq of event channel to send event to
  273. *
  274. * Unlike notify_remote_via_evtchn(), this is safe to use across
  275. * save/restore. Notifications on a broken connection are silently
  276. * dropped.
  277. */
  278. void notify_remote_via_irq(int irq)
  279. {
  280. int evtchn = evtchn_from_irq(irq);
  281. if (VALID_EVTCHN(evtchn))
  282. notify_remote_via_evtchn(evtchn);
  283. }
  284. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  285. static void mask_evtchn(int port)
  286. {
  287. struct shared_info *s = HYPERVISOR_shared_info;
  288. sync_set_bit(port, &s->evtchn_mask[0]);
  289. }
  290. static void unmask_evtchn(int port)
  291. {
  292. struct shared_info *s = HYPERVISOR_shared_info;
  293. unsigned int cpu = get_cpu();
  294. BUG_ON(!irqs_disabled());
  295. /* Slow path (hypercall) if this is a non-local port. */
  296. if (unlikely(cpu != cpu_from_evtchn(port))) {
  297. struct evtchn_unmask unmask = { .port = port };
  298. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  299. } else {
  300. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  301. sync_clear_bit(port, &s->evtchn_mask[0]);
  302. /*
  303. * The following is basically the equivalent of
  304. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  305. * the interrupt edge' if the channel is masked.
  306. */
  307. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  308. !sync_test_and_set_bit(port / BITS_PER_LONG,
  309. &vcpu_info->evtchn_pending_sel))
  310. vcpu_info->evtchn_upcall_pending = 1;
  311. }
  312. put_cpu();
  313. }
  314. static int xen_allocate_irq_dynamic(void)
  315. {
  316. int first = 0;
  317. int irq;
  318. #ifdef CONFIG_X86_IO_APIC
  319. /*
  320. * For an HVM guest or domain 0 which see "real" (emulated or
  321. * actual repectively) GSIs we allocate dynamic IRQs
  322. * e.g. those corresponding to event channels or MSIs
  323. * etc. from the range above those "real" GSIs to avoid
  324. * collisions.
  325. */
  326. if (xen_initial_domain() || xen_hvm_domain())
  327. first = get_nr_irqs_gsi();
  328. #endif
  329. retry:
  330. irq = irq_alloc_desc_from(first, -1);
  331. if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
  332. printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
  333. first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
  334. goto retry;
  335. }
  336. if (irq < 0)
  337. panic("No available IRQ to bind to: increase nr_irqs!\n");
  338. return irq;
  339. }
  340. static int xen_allocate_irq_gsi(unsigned gsi)
  341. {
  342. int irq;
  343. /*
  344. * A PV guest has no concept of a GSI (since it has no ACPI
  345. * nor access to/knowledge of the physical APICs). Therefore
  346. * all IRQs are dynamically allocated from the entire IRQ
  347. * space.
  348. */
  349. if (xen_pv_domain() && !xen_initial_domain())
  350. return xen_allocate_irq_dynamic();
  351. /* Legacy IRQ descriptors are already allocated by the arch. */
  352. if (gsi < NR_IRQS_LEGACY)
  353. return gsi;
  354. irq = irq_alloc_desc_at(gsi, -1);
  355. if (irq < 0)
  356. panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
  357. return irq;
  358. }
  359. static void xen_free_irq(unsigned irq)
  360. {
  361. irq_info[irq].type = IRQT_UNBOUND;
  362. /* Legacy IRQ descriptors are managed by the arch. */
  363. if (irq < NR_IRQS_LEGACY)
  364. return;
  365. irq_free_desc(irq);
  366. }
  367. static void pirq_unmask_notify(int irq)
  368. {
  369. struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
  370. if (unlikely(pirq_needs_eoi(irq))) {
  371. int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  372. WARN_ON(rc);
  373. }
  374. }
  375. static void pirq_query_unmask(int irq)
  376. {
  377. struct physdev_irq_status_query irq_status;
  378. struct irq_info *info = info_for_irq(irq);
  379. BUG_ON(info->type != IRQT_PIRQ);
  380. irq_status.irq = pirq_from_irq(irq);
  381. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  382. irq_status.flags = 0;
  383. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  384. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  385. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  386. }
  387. static bool probing_irq(int irq)
  388. {
  389. struct irq_desc *desc = irq_to_desc(irq);
  390. return desc && desc->action == NULL;
  391. }
  392. static unsigned int __startup_pirq(unsigned int irq)
  393. {
  394. struct evtchn_bind_pirq bind_pirq;
  395. struct irq_info *info = info_for_irq(irq);
  396. int evtchn = evtchn_from_irq(irq);
  397. int rc;
  398. BUG_ON(info->type != IRQT_PIRQ);
  399. if (VALID_EVTCHN(evtchn))
  400. goto out;
  401. bind_pirq.pirq = pirq_from_irq(irq);
  402. /* NB. We are happy to share unless we are probing. */
  403. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  404. BIND_PIRQ__WILL_SHARE : 0;
  405. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  406. if (rc != 0) {
  407. if (!probing_irq(irq))
  408. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  409. irq);
  410. return 0;
  411. }
  412. evtchn = bind_pirq.port;
  413. pirq_query_unmask(irq);
  414. evtchn_to_irq[evtchn] = irq;
  415. bind_evtchn_to_cpu(evtchn, 0);
  416. info->evtchn = evtchn;
  417. out:
  418. unmask_evtchn(evtchn);
  419. pirq_unmask_notify(irq);
  420. return 0;
  421. }
  422. static unsigned int startup_pirq(struct irq_data *data)
  423. {
  424. return __startup_pirq(data->irq);
  425. }
  426. static void shutdown_pirq(struct irq_data *data)
  427. {
  428. struct evtchn_close close;
  429. unsigned int irq = data->irq;
  430. struct irq_info *info = info_for_irq(irq);
  431. int evtchn = evtchn_from_irq(irq);
  432. BUG_ON(info->type != IRQT_PIRQ);
  433. if (!VALID_EVTCHN(evtchn))
  434. return;
  435. mask_evtchn(evtchn);
  436. close.port = evtchn;
  437. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  438. BUG();
  439. bind_evtchn_to_cpu(evtchn, 0);
  440. evtchn_to_irq[evtchn] = -1;
  441. info->evtchn = 0;
  442. }
  443. static void enable_pirq(struct irq_data *data)
  444. {
  445. startup_pirq(data);
  446. }
  447. static void disable_pirq(struct irq_data *data)
  448. {
  449. }
  450. static void ack_pirq(struct irq_data *data)
  451. {
  452. int evtchn = evtchn_from_irq(data->irq);
  453. move_native_irq(data->irq);
  454. if (VALID_EVTCHN(evtchn)) {
  455. mask_evtchn(evtchn);
  456. clear_evtchn(evtchn);
  457. }
  458. }
  459. static int find_irq_by_gsi(unsigned gsi)
  460. {
  461. int irq;
  462. for (irq = 0; irq < nr_irqs; irq++) {
  463. struct irq_info *info = info_for_irq(irq);
  464. if (info == NULL || info->type != IRQT_PIRQ)
  465. continue;
  466. if (gsi_from_irq(irq) == gsi)
  467. return irq;
  468. }
  469. return -1;
  470. }
  471. int xen_allocate_pirq_gsi(unsigned gsi)
  472. {
  473. return gsi;
  474. }
  475. /*
  476. * Do not make any assumptions regarding the relationship between the
  477. * IRQ number returned here and the Xen pirq argument.
  478. *
  479. * Note: We don't assign an event channel until the irq actually started
  480. * up. Return an existing irq if we've already got one for the gsi.
  481. */
  482. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  483. unsigned pirq, int shareable, char *name)
  484. {
  485. int irq = -1;
  486. struct physdev_irq irq_op;
  487. spin_lock(&irq_mapping_update_lock);
  488. if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
  489. printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
  490. pirq > nr_irqs ? "pirq" :"",
  491. gsi > nr_irqs ? "gsi" : "");
  492. goto out;
  493. }
  494. irq = find_irq_by_gsi(gsi);
  495. if (irq != -1) {
  496. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  497. irq, gsi);
  498. goto out; /* XXX need refcount? */
  499. }
  500. irq = xen_allocate_irq_gsi(gsi);
  501. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  502. handle_level_irq, name);
  503. irq_op.irq = irq;
  504. irq_op.vector = 0;
  505. /* Only the privileged domain can do this. For non-priv, the pcifront
  506. * driver provides a PCI bus that does the call to do exactly
  507. * this in the priv domain. */
  508. if (xen_initial_domain() &&
  509. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  510. xen_free_irq(irq);
  511. irq = -ENOSPC;
  512. goto out;
  513. }
  514. xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector,
  515. shareable ? PIRQ_SHAREABLE : 0);
  516. pirq_to_irq[pirq] = irq;
  517. out:
  518. spin_unlock(&irq_mapping_update_lock);
  519. return irq;
  520. }
  521. #ifdef CONFIG_PCI_MSI
  522. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  523. {
  524. int rc;
  525. struct physdev_get_free_pirq op_get_free_pirq;
  526. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  527. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  528. WARN_ONCE(rc == -ENOSYS,
  529. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  530. return rc ? -1 : op_get_free_pirq.pirq;
  531. }
  532. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  533. int pirq, int vector, const char *name)
  534. {
  535. int irq, ret;
  536. spin_lock(&irq_mapping_update_lock);
  537. irq = xen_allocate_irq_dynamic();
  538. if (irq == -1)
  539. goto out;
  540. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  541. handle_level_irq, name);
  542. xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, 0);
  543. pirq_to_irq[pirq] = irq;
  544. ret = set_irq_msi(irq, msidesc);
  545. if (ret < 0)
  546. goto error_irq;
  547. out:
  548. spin_unlock(&irq_mapping_update_lock);
  549. return irq;
  550. error_irq:
  551. spin_unlock(&irq_mapping_update_lock);
  552. xen_free_irq(irq);
  553. return -1;
  554. }
  555. #endif
  556. int xen_destroy_irq(int irq)
  557. {
  558. struct irq_desc *desc;
  559. struct physdev_unmap_pirq unmap_irq;
  560. struct irq_info *info = info_for_irq(irq);
  561. int rc = -ENOENT;
  562. spin_lock(&irq_mapping_update_lock);
  563. desc = irq_to_desc(irq);
  564. if (!desc)
  565. goto out;
  566. if (xen_initial_domain()) {
  567. unmap_irq.pirq = info->u.pirq.pirq;
  568. unmap_irq.domid = DOMID_SELF;
  569. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  570. if (rc) {
  571. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  572. goto out;
  573. }
  574. }
  575. pirq_to_irq[info->u.pirq.pirq] = -1;
  576. xen_free_irq(irq);
  577. out:
  578. spin_unlock(&irq_mapping_update_lock);
  579. return rc;
  580. }
  581. int xen_irq_from_pirq(unsigned pirq)
  582. {
  583. return pirq_to_irq[pirq];
  584. }
  585. int bind_evtchn_to_irq(unsigned int evtchn)
  586. {
  587. int irq;
  588. spin_lock(&irq_mapping_update_lock);
  589. irq = evtchn_to_irq[evtchn];
  590. if (irq == -1) {
  591. irq = xen_allocate_irq_dynamic();
  592. set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
  593. handle_fasteoi_irq, "event");
  594. evtchn_to_irq[evtchn] = irq;
  595. xen_irq_info_evtchn_init(irq, evtchn);
  596. }
  597. spin_unlock(&irq_mapping_update_lock);
  598. return irq;
  599. }
  600. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  601. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  602. {
  603. struct evtchn_bind_ipi bind_ipi;
  604. int evtchn, irq;
  605. spin_lock(&irq_mapping_update_lock);
  606. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  607. if (irq == -1) {
  608. irq = xen_allocate_irq_dynamic();
  609. if (irq < 0)
  610. goto out;
  611. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  612. handle_percpu_irq, "ipi");
  613. bind_ipi.vcpu = cpu;
  614. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  615. &bind_ipi) != 0)
  616. BUG();
  617. evtchn = bind_ipi.port;
  618. evtchn_to_irq[evtchn] = irq;
  619. xen_irq_info_ipi_init(irq, evtchn, ipi);
  620. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  621. bind_evtchn_to_cpu(evtchn, cpu);
  622. }
  623. out:
  624. spin_unlock(&irq_mapping_update_lock);
  625. return irq;
  626. }
  627. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  628. {
  629. struct evtchn_bind_virq bind_virq;
  630. int evtchn, irq;
  631. spin_lock(&irq_mapping_update_lock);
  632. irq = per_cpu(virq_to_irq, cpu)[virq];
  633. if (irq == -1) {
  634. irq = xen_allocate_irq_dynamic();
  635. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  636. handle_percpu_irq, "virq");
  637. bind_virq.virq = virq;
  638. bind_virq.vcpu = cpu;
  639. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  640. &bind_virq) != 0)
  641. BUG();
  642. evtchn = bind_virq.port;
  643. evtchn_to_irq[evtchn] = irq;
  644. xen_irq_info_virq_init(irq, evtchn, virq);
  645. per_cpu(virq_to_irq, cpu)[virq] = irq;
  646. bind_evtchn_to_cpu(evtchn, cpu);
  647. }
  648. spin_unlock(&irq_mapping_update_lock);
  649. return irq;
  650. }
  651. static void unbind_from_irq(unsigned int irq)
  652. {
  653. struct evtchn_close close;
  654. int evtchn = evtchn_from_irq(irq);
  655. spin_lock(&irq_mapping_update_lock);
  656. if (VALID_EVTCHN(evtchn)) {
  657. close.port = evtchn;
  658. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  659. BUG();
  660. switch (type_from_irq(irq)) {
  661. case IRQT_VIRQ:
  662. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  663. [virq_from_irq(irq)] = -1;
  664. break;
  665. case IRQT_IPI:
  666. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  667. [ipi_from_irq(irq)] = -1;
  668. break;
  669. default:
  670. break;
  671. }
  672. /* Closed ports are implicitly re-bound to VCPU0. */
  673. bind_evtchn_to_cpu(evtchn, 0);
  674. evtchn_to_irq[evtchn] = -1;
  675. }
  676. BUG_ON(irq_info[irq].type == IRQT_UNBOUND);
  677. xen_free_irq(irq);
  678. spin_unlock(&irq_mapping_update_lock);
  679. }
  680. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  681. irq_handler_t handler,
  682. unsigned long irqflags,
  683. const char *devname, void *dev_id)
  684. {
  685. unsigned int irq;
  686. int retval;
  687. irq = bind_evtchn_to_irq(evtchn);
  688. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  689. if (retval != 0) {
  690. unbind_from_irq(irq);
  691. return retval;
  692. }
  693. return irq;
  694. }
  695. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  696. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  697. irq_handler_t handler,
  698. unsigned long irqflags, const char *devname, void *dev_id)
  699. {
  700. unsigned int irq;
  701. int retval;
  702. irq = bind_virq_to_irq(virq, cpu);
  703. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  704. if (retval != 0) {
  705. unbind_from_irq(irq);
  706. return retval;
  707. }
  708. return irq;
  709. }
  710. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  711. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  712. unsigned int cpu,
  713. irq_handler_t handler,
  714. unsigned long irqflags,
  715. const char *devname,
  716. void *dev_id)
  717. {
  718. int irq, retval;
  719. irq = bind_ipi_to_irq(ipi, cpu);
  720. if (irq < 0)
  721. return irq;
  722. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
  723. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  724. if (retval != 0) {
  725. unbind_from_irq(irq);
  726. return retval;
  727. }
  728. return irq;
  729. }
  730. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  731. {
  732. free_irq(irq, dev_id);
  733. unbind_from_irq(irq);
  734. }
  735. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  736. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  737. {
  738. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  739. BUG_ON(irq < 0);
  740. notify_remote_via_irq(irq);
  741. }
  742. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  743. {
  744. struct shared_info *sh = HYPERVISOR_shared_info;
  745. int cpu = smp_processor_id();
  746. unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  747. int i;
  748. unsigned long flags;
  749. static DEFINE_SPINLOCK(debug_lock);
  750. struct vcpu_info *v;
  751. spin_lock_irqsave(&debug_lock, flags);
  752. printk("\nvcpu %d\n ", cpu);
  753. for_each_online_cpu(i) {
  754. int pending;
  755. v = per_cpu(xen_vcpu, i);
  756. pending = (get_irq_regs() && i == cpu)
  757. ? xen_irqs_disabled(get_irq_regs())
  758. : v->evtchn_upcall_mask;
  759. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  760. pending, v->evtchn_upcall_pending,
  761. (int)(sizeof(v->evtchn_pending_sel)*2),
  762. v->evtchn_pending_sel);
  763. }
  764. v = per_cpu(xen_vcpu, cpu);
  765. printk("\npending:\n ");
  766. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  767. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  768. sh->evtchn_pending[i],
  769. i % 8 == 0 ? "\n " : " ");
  770. printk("\nglobal mask:\n ");
  771. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  772. printk("%0*lx%s",
  773. (int)(sizeof(sh->evtchn_mask[0])*2),
  774. sh->evtchn_mask[i],
  775. i % 8 == 0 ? "\n " : " ");
  776. printk("\nglobally unmasked:\n ");
  777. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  778. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  779. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  780. i % 8 == 0 ? "\n " : " ");
  781. printk("\nlocal cpu%d mask:\n ", cpu);
  782. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  783. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  784. cpu_evtchn[i],
  785. i % 8 == 0 ? "\n " : " ");
  786. printk("\nlocally unmasked:\n ");
  787. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  788. unsigned long pending = sh->evtchn_pending[i]
  789. & ~sh->evtchn_mask[i]
  790. & cpu_evtchn[i];
  791. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  792. pending, i % 8 == 0 ? "\n " : " ");
  793. }
  794. printk("\npending list:\n");
  795. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  796. if (sync_test_bit(i, sh->evtchn_pending)) {
  797. int word_idx = i / BITS_PER_LONG;
  798. printk(" %d: event %d -> irq %d%s%s%s\n",
  799. cpu_from_evtchn(i), i,
  800. evtchn_to_irq[i],
  801. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  802. ? "" : " l2-clear",
  803. !sync_test_bit(i, sh->evtchn_mask)
  804. ? "" : " globally-masked",
  805. sync_test_bit(i, cpu_evtchn)
  806. ? "" : " locally-masked");
  807. }
  808. }
  809. spin_unlock_irqrestore(&debug_lock, flags);
  810. return IRQ_HANDLED;
  811. }
  812. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  813. /*
  814. * Search the CPUs pending events bitmasks. For each one found, map
  815. * the event number to an irq, and feed it into do_IRQ() for
  816. * handling.
  817. *
  818. * Xen uses a two-level bitmap to speed searching. The first level is
  819. * a bitset of words which contain pending event bits. The second
  820. * level is a bitset of pending events themselves.
  821. */
  822. static void __xen_evtchn_do_upcall(void)
  823. {
  824. int cpu = get_cpu();
  825. struct shared_info *s = HYPERVISOR_shared_info;
  826. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  827. unsigned count;
  828. do {
  829. unsigned long pending_words;
  830. vcpu_info->evtchn_upcall_pending = 0;
  831. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  832. goto out;
  833. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  834. /* Clear master flag /before/ clearing selector flag. */
  835. wmb();
  836. #endif
  837. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  838. while (pending_words != 0) {
  839. unsigned long pending_bits;
  840. int word_idx = __ffs(pending_words);
  841. pending_words &= ~(1UL << word_idx);
  842. while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
  843. int bit_idx = __ffs(pending_bits);
  844. int port = (word_idx * BITS_PER_LONG) + bit_idx;
  845. int irq = evtchn_to_irq[port];
  846. struct irq_desc *desc;
  847. mask_evtchn(port);
  848. clear_evtchn(port);
  849. if (irq != -1) {
  850. desc = irq_to_desc(irq);
  851. if (desc)
  852. generic_handle_irq_desc(irq, desc);
  853. }
  854. }
  855. }
  856. BUG_ON(!irqs_disabled());
  857. count = __this_cpu_read(xed_nesting_count);
  858. __this_cpu_write(xed_nesting_count, 0);
  859. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  860. out:
  861. put_cpu();
  862. }
  863. void xen_evtchn_do_upcall(struct pt_regs *regs)
  864. {
  865. struct pt_regs *old_regs = set_irq_regs(regs);
  866. exit_idle();
  867. irq_enter();
  868. __xen_evtchn_do_upcall();
  869. irq_exit();
  870. set_irq_regs(old_regs);
  871. }
  872. void xen_hvm_evtchn_do_upcall(void)
  873. {
  874. __xen_evtchn_do_upcall();
  875. }
  876. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  877. /* Rebind a new event channel to an existing irq. */
  878. void rebind_evtchn_irq(int evtchn, int irq)
  879. {
  880. struct irq_info *info = info_for_irq(irq);
  881. /* Make sure the irq is masked, since the new event channel
  882. will also be masked. */
  883. disable_irq(irq);
  884. spin_lock(&irq_mapping_update_lock);
  885. /* After resume the irq<->evtchn mappings are all cleared out */
  886. BUG_ON(evtchn_to_irq[evtchn] != -1);
  887. /* Expect irq to have been bound before,
  888. so there should be a proper type */
  889. BUG_ON(info->type == IRQT_UNBOUND);
  890. evtchn_to_irq[evtchn] = irq;
  891. xen_irq_info_evtchn_init(irq, evtchn);
  892. spin_unlock(&irq_mapping_update_lock);
  893. /* new event channels are always bound to cpu 0 */
  894. irq_set_affinity(irq, cpumask_of(0));
  895. /* Unmask the event channel. */
  896. enable_irq(irq);
  897. }
  898. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  899. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  900. {
  901. struct evtchn_bind_vcpu bind_vcpu;
  902. int evtchn = evtchn_from_irq(irq);
  903. if (!VALID_EVTCHN(evtchn))
  904. return -1;
  905. /*
  906. * Events delivered via platform PCI interrupts are always
  907. * routed to vcpu 0 and hence cannot be rebound.
  908. */
  909. if (xen_hvm_domain() && !xen_have_vector_callback)
  910. return -1;
  911. /* Send future instances of this interrupt to other vcpu. */
  912. bind_vcpu.port = evtchn;
  913. bind_vcpu.vcpu = tcpu;
  914. /*
  915. * If this fails, it usually just indicates that we're dealing with a
  916. * virq or IPI channel, which don't actually need to be rebound. Ignore
  917. * it, but don't do the xenlinux-level rebind in that case.
  918. */
  919. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  920. bind_evtchn_to_cpu(evtchn, tcpu);
  921. return 0;
  922. }
  923. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  924. bool force)
  925. {
  926. unsigned tcpu = cpumask_first(dest);
  927. return rebind_irq_to_cpu(data->irq, tcpu);
  928. }
  929. int resend_irq_on_evtchn(unsigned int irq)
  930. {
  931. int masked, evtchn = evtchn_from_irq(irq);
  932. struct shared_info *s = HYPERVISOR_shared_info;
  933. if (!VALID_EVTCHN(evtchn))
  934. return 1;
  935. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  936. sync_set_bit(evtchn, s->evtchn_pending);
  937. if (!masked)
  938. unmask_evtchn(evtchn);
  939. return 1;
  940. }
  941. static void enable_dynirq(struct irq_data *data)
  942. {
  943. int evtchn = evtchn_from_irq(data->irq);
  944. if (VALID_EVTCHN(evtchn))
  945. unmask_evtchn(evtchn);
  946. }
  947. static void disable_dynirq(struct irq_data *data)
  948. {
  949. int evtchn = evtchn_from_irq(data->irq);
  950. if (VALID_EVTCHN(evtchn))
  951. mask_evtchn(evtchn);
  952. }
  953. static void ack_dynirq(struct irq_data *data)
  954. {
  955. int evtchn = evtchn_from_irq(data->irq);
  956. move_masked_irq(data->irq);
  957. if (VALID_EVTCHN(evtchn))
  958. unmask_evtchn(evtchn);
  959. }
  960. static int retrigger_dynirq(struct irq_data *data)
  961. {
  962. int evtchn = evtchn_from_irq(data->irq);
  963. struct shared_info *sh = HYPERVISOR_shared_info;
  964. int ret = 0;
  965. if (VALID_EVTCHN(evtchn)) {
  966. int masked;
  967. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  968. sync_set_bit(evtchn, sh->evtchn_pending);
  969. if (!masked)
  970. unmask_evtchn(evtchn);
  971. ret = 1;
  972. }
  973. return ret;
  974. }
  975. static void restore_pirqs(void)
  976. {
  977. int pirq, rc, irq, gsi;
  978. struct physdev_map_pirq map_irq;
  979. for (pirq = 0; pirq < nr_irqs; pirq++) {
  980. irq = pirq_to_irq[pirq];
  981. if (irq == -1)
  982. continue;
  983. /* save/restore of PT devices doesn't work, so at this point the
  984. * only devices present are GSI based emulated devices */
  985. gsi = gsi_from_irq(irq);
  986. if (!gsi)
  987. continue;
  988. map_irq.domid = DOMID_SELF;
  989. map_irq.type = MAP_PIRQ_TYPE_GSI;
  990. map_irq.index = gsi;
  991. map_irq.pirq = pirq;
  992. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  993. if (rc) {
  994. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  995. gsi, irq, pirq, rc);
  996. xen_free_irq(irq);
  997. pirq_to_irq[pirq] = -1;
  998. continue;
  999. }
  1000. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1001. __startup_pirq(irq);
  1002. }
  1003. }
  1004. static void restore_cpu_virqs(unsigned int cpu)
  1005. {
  1006. struct evtchn_bind_virq bind_virq;
  1007. int virq, irq, evtchn;
  1008. for (virq = 0; virq < NR_VIRQS; virq++) {
  1009. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1010. continue;
  1011. BUG_ON(virq_from_irq(irq) != virq);
  1012. /* Get a new binding from Xen. */
  1013. bind_virq.virq = virq;
  1014. bind_virq.vcpu = cpu;
  1015. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1016. &bind_virq) != 0)
  1017. BUG();
  1018. evtchn = bind_virq.port;
  1019. /* Record the new mapping. */
  1020. evtchn_to_irq[evtchn] = irq;
  1021. xen_irq_info_virq_init(irq, evtchn, virq);
  1022. bind_evtchn_to_cpu(evtchn, cpu);
  1023. }
  1024. }
  1025. static void restore_cpu_ipis(unsigned int cpu)
  1026. {
  1027. struct evtchn_bind_ipi bind_ipi;
  1028. int ipi, irq, evtchn;
  1029. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1030. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1031. continue;
  1032. BUG_ON(ipi_from_irq(irq) != ipi);
  1033. /* Get a new binding from Xen. */
  1034. bind_ipi.vcpu = cpu;
  1035. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1036. &bind_ipi) != 0)
  1037. BUG();
  1038. evtchn = bind_ipi.port;
  1039. /* Record the new mapping. */
  1040. evtchn_to_irq[evtchn] = irq;
  1041. xen_irq_info_ipi_init(irq, evtchn, ipi);
  1042. bind_evtchn_to_cpu(evtchn, cpu);
  1043. }
  1044. }
  1045. /* Clear an irq's pending state, in preparation for polling on it */
  1046. void xen_clear_irq_pending(int irq)
  1047. {
  1048. int evtchn = evtchn_from_irq(irq);
  1049. if (VALID_EVTCHN(evtchn))
  1050. clear_evtchn(evtchn);
  1051. }
  1052. EXPORT_SYMBOL(xen_clear_irq_pending);
  1053. void xen_set_irq_pending(int irq)
  1054. {
  1055. int evtchn = evtchn_from_irq(irq);
  1056. if (VALID_EVTCHN(evtchn))
  1057. set_evtchn(evtchn);
  1058. }
  1059. bool xen_test_irq_pending(int irq)
  1060. {
  1061. int evtchn = evtchn_from_irq(irq);
  1062. bool ret = false;
  1063. if (VALID_EVTCHN(evtchn))
  1064. ret = test_evtchn(evtchn);
  1065. return ret;
  1066. }
  1067. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1068. * the irq will be disabled so it won't deliver an interrupt. */
  1069. void xen_poll_irq_timeout(int irq, u64 timeout)
  1070. {
  1071. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1072. if (VALID_EVTCHN(evtchn)) {
  1073. struct sched_poll poll;
  1074. poll.nr_ports = 1;
  1075. poll.timeout = timeout;
  1076. set_xen_guest_handle(poll.ports, &evtchn);
  1077. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1078. BUG();
  1079. }
  1080. }
  1081. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1082. /* Poll waiting for an irq to become pending. In the usual case, the
  1083. * irq will be disabled so it won't deliver an interrupt. */
  1084. void xen_poll_irq(int irq)
  1085. {
  1086. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1087. }
  1088. void xen_irq_resume(void)
  1089. {
  1090. unsigned int cpu, irq, evtchn;
  1091. init_evtchn_cpu_bindings();
  1092. /* New event-channel space is not 'live' yet. */
  1093. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1094. mask_evtchn(evtchn);
  1095. /* No IRQ <-> event-channel mappings. */
  1096. for (irq = 0; irq < nr_irqs; irq++)
  1097. irq_info[irq].evtchn = 0; /* zap event-channel binding */
  1098. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1099. evtchn_to_irq[evtchn] = -1;
  1100. for_each_possible_cpu(cpu) {
  1101. restore_cpu_virqs(cpu);
  1102. restore_cpu_ipis(cpu);
  1103. }
  1104. restore_pirqs();
  1105. }
  1106. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1107. .name = "xen-dyn",
  1108. .irq_disable = disable_dynirq,
  1109. .irq_mask = disable_dynirq,
  1110. .irq_unmask = enable_dynirq,
  1111. .irq_eoi = ack_dynirq,
  1112. .irq_set_affinity = set_affinity_irq,
  1113. .irq_retrigger = retrigger_dynirq,
  1114. };
  1115. static struct irq_chip xen_pirq_chip __read_mostly = {
  1116. .name = "xen-pirq",
  1117. .irq_startup = startup_pirq,
  1118. .irq_shutdown = shutdown_pirq,
  1119. .irq_enable = enable_pirq,
  1120. .irq_unmask = enable_pirq,
  1121. .irq_disable = disable_pirq,
  1122. .irq_mask = disable_pirq,
  1123. .irq_ack = ack_pirq,
  1124. .irq_set_affinity = set_affinity_irq,
  1125. .irq_retrigger = retrigger_dynirq,
  1126. };
  1127. static struct irq_chip xen_percpu_chip __read_mostly = {
  1128. .name = "xen-percpu",
  1129. .irq_disable = disable_dynirq,
  1130. .irq_mask = disable_dynirq,
  1131. .irq_unmask = enable_dynirq,
  1132. .irq_ack = ack_dynirq,
  1133. };
  1134. int xen_set_callback_via(uint64_t via)
  1135. {
  1136. struct xen_hvm_param a;
  1137. a.domid = DOMID_SELF;
  1138. a.index = HVM_PARAM_CALLBACK_IRQ;
  1139. a.value = via;
  1140. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1141. }
  1142. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1143. #ifdef CONFIG_XEN_PVHVM
  1144. /* Vector callbacks are better than PCI interrupts to receive event
  1145. * channel notifications because we can receive vector callbacks on any
  1146. * vcpu and we don't need PCI support or APIC interactions. */
  1147. void xen_callback_vector(void)
  1148. {
  1149. int rc;
  1150. uint64_t callback_via;
  1151. if (xen_have_vector_callback) {
  1152. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1153. rc = xen_set_callback_via(callback_via);
  1154. if (rc) {
  1155. printk(KERN_ERR "Request for Xen HVM callback vector"
  1156. " failed.\n");
  1157. xen_have_vector_callback = 0;
  1158. return;
  1159. }
  1160. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1161. "enabled\n");
  1162. /* in the restore case the vector has already been allocated */
  1163. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1164. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1165. }
  1166. }
  1167. #else
  1168. void xen_callback_vector(void) {}
  1169. #endif
  1170. void __init xen_init_IRQ(void)
  1171. {
  1172. int i;
  1173. irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
  1174. /* We are using nr_irqs as the maximum number of pirq available but
  1175. * that number is actually chosen by Xen and we don't know exactly
  1176. * what it is. Be careful choosing high pirq numbers. */
  1177. pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
  1178. for (i = 0; i < nr_irqs; i++)
  1179. pirq_to_irq[i] = -1;
  1180. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1181. GFP_KERNEL);
  1182. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1183. evtchn_to_irq[i] = -1;
  1184. init_evtchn_cpu_bindings();
  1185. /* No event channels are 'live' right now. */
  1186. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1187. mask_evtchn(i);
  1188. if (xen_hvm_domain()) {
  1189. xen_callback_vector();
  1190. native_init_IRQ();
  1191. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1192. * __acpi_register_gsi can point at the right function */
  1193. pci_xen_hvm_init();
  1194. } else {
  1195. irq_ctx_init(smp_processor_id());
  1196. if (xen_initial_domain())
  1197. xen_setup_pirqs();
  1198. }
  1199. }