ipr.c 6.0 KB

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  1. /*
  2. * arch/sh/kernel/cpu/irq/ipr.c
  3. *
  4. * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
  5. * Copyright (C) 2000 Kazumoto Kojima
  6. * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
  7. *
  8. * Interrupt handling for IPR-based IRQ.
  9. *
  10. * Supported system:
  11. * On-chip supporting modules (TMU, RTC, etc.).
  12. * On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
  13. * Hitachi SolutionEngine external I/O:
  14. * MS7709SE01, MS7709ASE01, and MS7750SE01
  15. *
  16. */
  17. #include <linux/init.h>
  18. #include <linux/irq.h>
  19. #include <linux/module.h>
  20. #include <asm/system.h>
  21. #include <asm/io.h>
  22. #include <asm/machvec.h>
  23. struct ipr_data {
  24. unsigned int addr; /* Address of Interrupt Priority Register */
  25. int shift; /* Shifts of the 16-bit data */
  26. int priority; /* The priority */
  27. };
  28. static struct ipr_data ipr_data[NR_IRQS];
  29. static void enable_ipr_irq(unsigned int irq);
  30. static void disable_ipr_irq(unsigned int irq);
  31. /* shutdown is same as "disable" */
  32. #define shutdown_ipr_irq disable_ipr_irq
  33. static void mask_and_ack_ipr(unsigned int);
  34. static void end_ipr_irq(unsigned int irq);
  35. static unsigned int startup_ipr_irq(unsigned int irq)
  36. {
  37. enable_ipr_irq(irq);
  38. return 0; /* never anything pending */
  39. }
  40. static struct hw_interrupt_type ipr_irq_type = {
  41. .typename = "IPR-IRQ",
  42. .startup = startup_ipr_irq,
  43. .shutdown = shutdown_ipr_irq,
  44. .enable = enable_ipr_irq,
  45. .disable = disable_ipr_irq,
  46. .ack = mask_and_ack_ipr,
  47. .end = end_ipr_irq
  48. };
  49. static void disable_ipr_irq(unsigned int irq)
  50. {
  51. unsigned long val, flags;
  52. unsigned int addr = ipr_data[irq].addr;
  53. unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
  54. /* Set the priority in IPR to 0 */
  55. local_irq_save(flags);
  56. val = ctrl_inw(addr);
  57. val &= mask;
  58. ctrl_outw(val, addr);
  59. local_irq_restore(flags);
  60. }
  61. static void enable_ipr_irq(unsigned int irq)
  62. {
  63. unsigned long val, flags;
  64. unsigned int addr = ipr_data[irq].addr;
  65. int priority = ipr_data[irq].priority;
  66. unsigned short value = (priority << ipr_data[irq].shift);
  67. /* Set priority in IPR back to original value */
  68. local_irq_save(flags);
  69. val = ctrl_inw(addr);
  70. val |= value;
  71. ctrl_outw(val, addr);
  72. local_irq_restore(flags);
  73. }
  74. static void mask_and_ack_ipr(unsigned int irq)
  75. {
  76. disable_ipr_irq(irq);
  77. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
  78. defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  79. defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
  80. /* This is needed when we use edge triggered setting */
  81. /* XXX: Is it really needed? */
  82. if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
  83. /* Clear external interrupt request */
  84. int a = ctrl_inb(INTC_IRR0);
  85. a &= ~(1 << (irq - IRQ0_IRQ));
  86. ctrl_outb(a, INTC_IRR0);
  87. }
  88. #endif
  89. }
  90. static void end_ipr_irq(unsigned int irq)
  91. {
  92. if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  93. enable_ipr_irq(irq);
  94. }
  95. void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
  96. {
  97. disable_irq_nosync(irq);
  98. ipr_data[irq].addr = addr;
  99. ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
  100. ipr_data[irq].priority = priority;
  101. irq_desc[irq].chip = &ipr_irq_type;
  102. disable_ipr_irq(irq);
  103. }
  104. void __init init_IRQ(void)
  105. {
  106. #ifndef CONFIG_CPU_SUBTYPE_SH7780
  107. make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
  108. make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
  109. #ifdef RTC_IRQ
  110. make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
  111. #endif
  112. #ifdef SCI_ERI_IRQ
  113. make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
  114. make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
  115. make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
  116. #endif
  117. #ifdef SCIF1_ERI_IRQ
  118. make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
  119. make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
  120. make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
  121. make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
  122. #endif
  123. #if defined(CONFIG_CPU_SUBTYPE_SH7300)
  124. make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
  125. make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
  126. make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
  127. make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
  128. #endif
  129. #ifdef SCIF_ERI_IRQ
  130. make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
  131. make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
  132. make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
  133. make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
  134. #endif
  135. #ifdef IRDA_ERI_IRQ
  136. make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
  137. make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
  138. make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
  139. make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
  140. #endif
  141. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
  142. defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  143. defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
  144. /*
  145. * Initialize the Interrupt Controller (INTC)
  146. * registers to their power on values
  147. */
  148. /*
  149. * Enable external irq (INTC IRQ mode).
  150. * You should set corresponding bits of PFC to "00"
  151. * to enable these interrupts.
  152. */
  153. make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
  154. make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
  155. make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
  156. make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
  157. make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
  158. make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
  159. #endif
  160. #endif
  161. #ifdef CONFIG_CPU_HAS_PINT_IRQ
  162. init_IRQ_pint();
  163. #endif
  164. #ifdef CONFIG_CPU_HAS_INTC2_IRQ
  165. init_IRQ_intc2();
  166. #endif
  167. /* Perform the machine specific initialisation */
  168. if (sh_mv.mv_init_irq != NULL)
  169. sh_mv.mv_init_irq();
  170. }
  171. #if !defined(CONFIG_CPU_HAS_PINT_IRQ)
  172. int ipr_irq_demux(int irq)
  173. {
  174. return irq;
  175. }
  176. #endif
  177. EXPORT_SYMBOL(make_ipr_irq);