board-3430sdp.c 22 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/board-3430sdp.c
  3. *
  4. * Copyright (C) 2007 Texas Instruments
  5. *
  6. * Modified from mach-omap2/board-generic.c
  7. *
  8. * Initial code: Syed Mohammed Khasim
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/delay.h>
  18. #include <linux/input.h>
  19. #include <linux/input/matrix_keypad.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/spi/ads7846.h>
  22. #include <linux/i2c/twl.h>
  23. #include <linux/regulator/machine.h>
  24. #include <linux/io.h>
  25. #include <linux/gpio.h>
  26. #include <linux/mmc/host.h>
  27. #include <mach/hardware.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/mach/arch.h>
  30. #include <asm/mach/map.h>
  31. #include <plat/mcspi.h>
  32. #include <plat/board.h>
  33. #include <plat/usb.h>
  34. #include <plat/common.h>
  35. #include <plat/dma.h>
  36. #include <plat/gpmc.h>
  37. #include <plat/display.h>
  38. #include <plat/panel-generic-dpi.h>
  39. #include <plat/gpmc-smc91x.h>
  40. #include "board-flash.h"
  41. #include "mux.h"
  42. #include "sdram-qimonda-hyb18m512160af-6.h"
  43. #include "hsmmc.h"
  44. #include "pm.h"
  45. #include "control.h"
  46. #define CONFIG_DISABLE_HFCLK 1
  47. #define SDP3430_TS_GPIO_IRQ_SDPV1 3
  48. #define SDP3430_TS_GPIO_IRQ_SDPV2 2
  49. #define ENABLE_VAUX3_DEDICATED 0x03
  50. #define ENABLE_VAUX3_DEV_GRP 0x20
  51. #define TWL4030_MSECURE_GPIO 22
  52. static uint32_t board_keymap[] = {
  53. KEY(0, 0, KEY_LEFT),
  54. KEY(0, 1, KEY_RIGHT),
  55. KEY(0, 2, KEY_A),
  56. KEY(0, 3, KEY_B),
  57. KEY(0, 4, KEY_C),
  58. KEY(1, 0, KEY_DOWN),
  59. KEY(1, 1, KEY_UP),
  60. KEY(1, 2, KEY_E),
  61. KEY(1, 3, KEY_F),
  62. KEY(1, 4, KEY_G),
  63. KEY(2, 0, KEY_ENTER),
  64. KEY(2, 1, KEY_I),
  65. KEY(2, 2, KEY_J),
  66. KEY(2, 3, KEY_K),
  67. KEY(2, 4, KEY_3),
  68. KEY(3, 0, KEY_M),
  69. KEY(3, 1, KEY_N),
  70. KEY(3, 2, KEY_O),
  71. KEY(3, 3, KEY_P),
  72. KEY(3, 4, KEY_Q),
  73. KEY(4, 0, KEY_R),
  74. KEY(4, 1, KEY_4),
  75. KEY(4, 2, KEY_T),
  76. KEY(4, 3, KEY_U),
  77. KEY(4, 4, KEY_D),
  78. KEY(5, 0, KEY_V),
  79. KEY(5, 1, KEY_W),
  80. KEY(5, 2, KEY_L),
  81. KEY(5, 3, KEY_S),
  82. KEY(5, 4, KEY_H),
  83. 0
  84. };
  85. static struct matrix_keymap_data board_map_data = {
  86. .keymap = board_keymap,
  87. .keymap_size = ARRAY_SIZE(board_keymap),
  88. };
  89. static struct twl4030_keypad_data sdp3430_kp_data = {
  90. .keymap_data = &board_map_data,
  91. .rows = 5,
  92. .cols = 6,
  93. .rep = 1,
  94. };
  95. static int ts_gpio; /* Needed for ads7846_get_pendown_state */
  96. /**
  97. * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq
  98. *
  99. * @return - void. If request gpio fails then Flag KERN_ERR.
  100. */
  101. static void ads7846_dev_init(void)
  102. {
  103. if (gpio_request(ts_gpio, "ADS7846 pendown") < 0) {
  104. printk(KERN_ERR "can't get ads746 pen down GPIO\n");
  105. return;
  106. }
  107. gpio_direction_input(ts_gpio);
  108. gpio_set_debounce(ts_gpio, 310);
  109. }
  110. static int ads7846_get_pendown_state(void)
  111. {
  112. return !gpio_get_value(ts_gpio);
  113. }
  114. static struct ads7846_platform_data tsc2046_config __initdata = {
  115. .get_pendown_state = ads7846_get_pendown_state,
  116. .keep_vref_on = 1,
  117. .wakeup = true,
  118. };
  119. static struct omap2_mcspi_device_config tsc2046_mcspi_config = {
  120. .turbo_mode = 0,
  121. .single_channel = 1, /* 0: slave, 1: master */
  122. };
  123. static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
  124. [0] = {
  125. /*
  126. * TSC2046 operates at a max freqency of 2MHz, so
  127. * operate slightly below at 1.5MHz
  128. */
  129. .modalias = "ads7846",
  130. .bus_num = 1,
  131. .chip_select = 0,
  132. .max_speed_hz = 1500000,
  133. .controller_data = &tsc2046_mcspi_config,
  134. .irq = 0,
  135. .platform_data = &tsc2046_config,
  136. },
  137. };
  138. #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
  139. #define SDP3430_LCD_PANEL_ENABLE_GPIO 5
  140. static unsigned backlight_gpio;
  141. static unsigned enable_gpio;
  142. static int lcd_enabled;
  143. static int dvi_enabled;
  144. static void __init sdp3430_display_init(void)
  145. {
  146. int r;
  147. enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO;
  148. backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
  149. r = gpio_request(enable_gpio, "LCD reset");
  150. if (r) {
  151. printk(KERN_ERR "failed to get LCD reset GPIO\n");
  152. goto err0;
  153. }
  154. r = gpio_request(backlight_gpio, "LCD Backlight");
  155. if (r) {
  156. printk(KERN_ERR "failed to get LCD backlight GPIO\n");
  157. goto err1;
  158. }
  159. gpio_direction_output(enable_gpio, 0);
  160. gpio_direction_output(backlight_gpio, 0);
  161. return;
  162. err1:
  163. gpio_free(enable_gpio);
  164. err0:
  165. return;
  166. }
  167. static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
  168. {
  169. if (dvi_enabled) {
  170. printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
  171. return -EINVAL;
  172. }
  173. gpio_direction_output(enable_gpio, 1);
  174. gpio_direction_output(backlight_gpio, 1);
  175. lcd_enabled = 1;
  176. return 0;
  177. }
  178. static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
  179. {
  180. lcd_enabled = 0;
  181. gpio_direction_output(enable_gpio, 0);
  182. gpio_direction_output(backlight_gpio, 0);
  183. }
  184. static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
  185. {
  186. if (lcd_enabled) {
  187. printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
  188. return -EINVAL;
  189. }
  190. dvi_enabled = 1;
  191. return 0;
  192. }
  193. static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
  194. {
  195. dvi_enabled = 0;
  196. }
  197. static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
  198. {
  199. return 0;
  200. }
  201. static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
  202. {
  203. }
  204. static struct omap_dss_device sdp3430_lcd_device = {
  205. .name = "lcd",
  206. .driver_name = "sharp_ls_panel",
  207. .type = OMAP_DISPLAY_TYPE_DPI,
  208. .phy.dpi.data_lines = 16,
  209. .platform_enable = sdp3430_panel_enable_lcd,
  210. .platform_disable = sdp3430_panel_disable_lcd,
  211. };
  212. static struct panel_generic_dpi_data dvi_panel = {
  213. .name = "generic",
  214. .platform_enable = sdp3430_panel_enable_dvi,
  215. .platform_disable = sdp3430_panel_disable_dvi,
  216. };
  217. static struct omap_dss_device sdp3430_dvi_device = {
  218. .name = "dvi",
  219. .type = OMAP_DISPLAY_TYPE_DPI,
  220. .driver_name = "generic_dpi_panel",
  221. .data = &dvi_panel,
  222. .phy.dpi.data_lines = 24,
  223. };
  224. static struct omap_dss_device sdp3430_tv_device = {
  225. .name = "tv",
  226. .driver_name = "venc",
  227. .type = OMAP_DISPLAY_TYPE_VENC,
  228. .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
  229. .platform_enable = sdp3430_panel_enable_tv,
  230. .platform_disable = sdp3430_panel_disable_tv,
  231. };
  232. static struct omap_dss_device *sdp3430_dss_devices[] = {
  233. &sdp3430_lcd_device,
  234. &sdp3430_dvi_device,
  235. &sdp3430_tv_device,
  236. };
  237. static struct omap_dss_board_info sdp3430_dss_data = {
  238. .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
  239. .devices = sdp3430_dss_devices,
  240. .default_device = &sdp3430_lcd_device,
  241. };
  242. static struct omap_board_config_kernel sdp3430_config[] __initdata = {
  243. };
  244. static void __init omap_3430sdp_init_early(void)
  245. {
  246. omap2_init_common_infrastructure();
  247. omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
  248. }
  249. static int sdp3430_batt_table[] = {
  250. /* 0 C*/
  251. 30800, 29500, 28300, 27100,
  252. 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
  253. 17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
  254. 11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
  255. 8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
  256. 5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
  257. 4040, 3910, 3790, 3670, 3550
  258. };
  259. static struct twl4030_bci_platform_data sdp3430_bci_data = {
  260. .battery_tmp_tbl = sdp3430_batt_table,
  261. .tblsize = ARRAY_SIZE(sdp3430_batt_table),
  262. };
  263. static struct omap2_hsmmc_info mmc[] = {
  264. {
  265. .mmc = 1,
  266. /* 8 bits (default) requires S6.3 == ON,
  267. * so the SIM card isn't used; else 4 bits.
  268. */
  269. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  270. .gpio_wp = 4,
  271. },
  272. {
  273. .mmc = 2,
  274. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  275. .gpio_wp = 7,
  276. },
  277. {} /* Terminator */
  278. };
  279. static int sdp3430_twl_gpio_setup(struct device *dev,
  280. unsigned gpio, unsigned ngpio)
  281. {
  282. /* gpio + 0 is "mmc0_cd" (input/IRQ),
  283. * gpio + 1 is "mmc1_cd" (input/IRQ)
  284. */
  285. mmc[0].gpio_cd = gpio + 0;
  286. mmc[1].gpio_cd = gpio + 1;
  287. omap2_hsmmc_init(mmc);
  288. /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
  289. gpio_request(gpio + 7, "sub_lcd_en_bkl");
  290. gpio_direction_output(gpio + 7, 0);
  291. /* gpio + 15 is "sub_lcd_nRST" (output) */
  292. gpio_request(gpio + 15, "sub_lcd_nRST");
  293. gpio_direction_output(gpio + 15, 0);
  294. return 0;
  295. }
  296. static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
  297. .gpio_base = OMAP_MAX_GPIO_LINES,
  298. .irq_base = TWL4030_GPIO_IRQ_BASE,
  299. .irq_end = TWL4030_GPIO_IRQ_END,
  300. .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
  301. | BIT(16) | BIT(17),
  302. .setup = sdp3430_twl_gpio_setup,
  303. };
  304. static struct twl4030_usb_data sdp3430_usb_data = {
  305. .usb_mode = T2_USB_MODE_ULPI,
  306. };
  307. static struct twl4030_madc_platform_data sdp3430_madc_data = {
  308. .irq_line = 1,
  309. };
  310. /* regulator consumer mappings */
  311. /* ads7846 on SPI */
  312. static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
  313. REGULATOR_SUPPLY("vcc", "spi1.0"),
  314. };
  315. static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
  316. REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
  317. };
  318. /* VPLL2 for digital video outputs */
  319. static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
  320. REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
  321. REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
  322. };
  323. static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
  324. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
  325. };
  326. static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
  327. REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
  328. };
  329. static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
  330. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
  331. };
  332. /*
  333. * Apply all the fixed voltages since most versions of U-Boot
  334. * don't bother with that initialization.
  335. */
  336. /* VAUX1 for mainboard (irda and sub-lcd) */
  337. static struct regulator_init_data sdp3430_vaux1 = {
  338. .constraints = {
  339. .min_uV = 2800000,
  340. .max_uV = 2800000,
  341. .apply_uV = true,
  342. .valid_modes_mask = REGULATOR_MODE_NORMAL
  343. | REGULATOR_MODE_STANDBY,
  344. .valid_ops_mask = REGULATOR_CHANGE_MODE
  345. | REGULATOR_CHANGE_STATUS,
  346. },
  347. };
  348. /* VAUX2 for camera module */
  349. static struct regulator_init_data sdp3430_vaux2 = {
  350. .constraints = {
  351. .min_uV = 2800000,
  352. .max_uV = 2800000,
  353. .apply_uV = true,
  354. .valid_modes_mask = REGULATOR_MODE_NORMAL
  355. | REGULATOR_MODE_STANDBY,
  356. .valid_ops_mask = REGULATOR_CHANGE_MODE
  357. | REGULATOR_CHANGE_STATUS,
  358. },
  359. };
  360. /* VAUX3 for LCD board */
  361. static struct regulator_init_data sdp3430_vaux3 = {
  362. .constraints = {
  363. .min_uV = 2800000,
  364. .max_uV = 2800000,
  365. .apply_uV = true,
  366. .valid_modes_mask = REGULATOR_MODE_NORMAL
  367. | REGULATOR_MODE_STANDBY,
  368. .valid_ops_mask = REGULATOR_CHANGE_MODE
  369. | REGULATOR_CHANGE_STATUS,
  370. },
  371. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
  372. .consumer_supplies = sdp3430_vaux3_supplies,
  373. };
  374. /* VAUX4 for OMAP VDD_CSI2 (camera) */
  375. static struct regulator_init_data sdp3430_vaux4 = {
  376. .constraints = {
  377. .min_uV = 1800000,
  378. .max_uV = 1800000,
  379. .apply_uV = true,
  380. .valid_modes_mask = REGULATOR_MODE_NORMAL
  381. | REGULATOR_MODE_STANDBY,
  382. .valid_ops_mask = REGULATOR_CHANGE_MODE
  383. | REGULATOR_CHANGE_STATUS,
  384. },
  385. };
  386. /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
  387. static struct regulator_init_data sdp3430_vmmc1 = {
  388. .constraints = {
  389. .min_uV = 1850000,
  390. .max_uV = 3150000,
  391. .valid_modes_mask = REGULATOR_MODE_NORMAL
  392. | REGULATOR_MODE_STANDBY,
  393. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  394. | REGULATOR_CHANGE_MODE
  395. | REGULATOR_CHANGE_STATUS,
  396. },
  397. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
  398. .consumer_supplies = sdp3430_vmmc1_supplies,
  399. };
  400. /* VMMC2 for MMC2 card */
  401. static struct regulator_init_data sdp3430_vmmc2 = {
  402. .constraints = {
  403. .min_uV = 1850000,
  404. .max_uV = 1850000,
  405. .apply_uV = true,
  406. .valid_modes_mask = REGULATOR_MODE_NORMAL
  407. | REGULATOR_MODE_STANDBY,
  408. .valid_ops_mask = REGULATOR_CHANGE_MODE
  409. | REGULATOR_CHANGE_STATUS,
  410. },
  411. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
  412. .consumer_supplies = sdp3430_vmmc2_supplies,
  413. };
  414. /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
  415. static struct regulator_init_data sdp3430_vsim = {
  416. .constraints = {
  417. .min_uV = 1800000,
  418. .max_uV = 3000000,
  419. .valid_modes_mask = REGULATOR_MODE_NORMAL
  420. | REGULATOR_MODE_STANDBY,
  421. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  422. | REGULATOR_CHANGE_MODE
  423. | REGULATOR_CHANGE_STATUS,
  424. },
  425. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
  426. .consumer_supplies = sdp3430_vsim_supplies,
  427. };
  428. /* VDAC for DSS driving S-Video */
  429. static struct regulator_init_data sdp3430_vdac = {
  430. .constraints = {
  431. .min_uV = 1800000,
  432. .max_uV = 1800000,
  433. .apply_uV = true,
  434. .valid_modes_mask = REGULATOR_MODE_NORMAL
  435. | REGULATOR_MODE_STANDBY,
  436. .valid_ops_mask = REGULATOR_CHANGE_MODE
  437. | REGULATOR_CHANGE_STATUS,
  438. },
  439. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
  440. .consumer_supplies = sdp3430_vdda_dac_supplies,
  441. };
  442. static struct regulator_init_data sdp3430_vpll2 = {
  443. .constraints = {
  444. .name = "VDVI",
  445. .min_uV = 1800000,
  446. .max_uV = 1800000,
  447. .apply_uV = true,
  448. .valid_modes_mask = REGULATOR_MODE_NORMAL
  449. | REGULATOR_MODE_STANDBY,
  450. .valid_ops_mask = REGULATOR_CHANGE_MODE
  451. | REGULATOR_CHANGE_STATUS,
  452. },
  453. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
  454. .consumer_supplies = sdp3430_vpll2_supplies,
  455. };
  456. static struct twl4030_codec_audio_data sdp3430_audio;
  457. static struct twl4030_codec_data sdp3430_codec = {
  458. .audio_mclk = 26000000,
  459. .audio = &sdp3430_audio,
  460. };
  461. static struct twl4030_platform_data sdp3430_twldata = {
  462. .irq_base = TWL4030_IRQ_BASE,
  463. .irq_end = TWL4030_IRQ_END,
  464. /* platform_data for children goes here */
  465. .bci = &sdp3430_bci_data,
  466. .gpio = &sdp3430_gpio_data,
  467. .madc = &sdp3430_madc_data,
  468. .keypad = &sdp3430_kp_data,
  469. .usb = &sdp3430_usb_data,
  470. .codec = &sdp3430_codec,
  471. .vaux1 = &sdp3430_vaux1,
  472. .vaux2 = &sdp3430_vaux2,
  473. .vaux3 = &sdp3430_vaux3,
  474. .vaux4 = &sdp3430_vaux4,
  475. .vmmc1 = &sdp3430_vmmc1,
  476. .vmmc2 = &sdp3430_vmmc2,
  477. .vsim = &sdp3430_vsim,
  478. .vdac = &sdp3430_vdac,
  479. .vpll2 = &sdp3430_vpll2,
  480. };
  481. static struct i2c_board_info __initdata sdp3430_i2c_boardinfo[] = {
  482. {
  483. I2C_BOARD_INFO("twl4030", 0x48),
  484. .flags = I2C_CLIENT_WAKE,
  485. .irq = INT_34XX_SYS_NIRQ,
  486. .platform_data = &sdp3430_twldata,
  487. },
  488. };
  489. static int __init omap3430_i2c_init(void)
  490. {
  491. /* i2c1 for PMIC only */
  492. omap_register_i2c_bus(1, 2600, sdp3430_i2c_boardinfo,
  493. ARRAY_SIZE(sdp3430_i2c_boardinfo));
  494. /* i2c2 on camera connector (for sensor control) and optional isp1301 */
  495. omap_register_i2c_bus(2, 400, NULL, 0);
  496. /* i2c3 on display connector (for DVI, tfp410) */
  497. omap_register_i2c_bus(3, 400, NULL, 0);
  498. return 0;
  499. }
  500. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  501. static struct omap_smc91x_platform_data board_smc91x_data = {
  502. .cs = 3,
  503. .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
  504. IORESOURCE_IRQ_LOWLEVEL,
  505. };
  506. static void __init board_smc91x_init(void)
  507. {
  508. if (omap_rev() > OMAP3430_REV_ES1_0)
  509. board_smc91x_data.gpio_irq = 6;
  510. else
  511. board_smc91x_data.gpio_irq = 29;
  512. gpmc_smc91x_init(&board_smc91x_data);
  513. }
  514. #else
  515. static inline void board_smc91x_init(void)
  516. {
  517. }
  518. #endif
  519. static void enable_board_wakeup_source(void)
  520. {
  521. /* T2 interrupt line (keypad) */
  522. omap_mux_init_signal("sys_nirq",
  523. OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
  524. }
  525. static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
  526. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  527. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  528. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  529. .phy_reset = true,
  530. .reset_gpio_port[0] = 57,
  531. .reset_gpio_port[1] = 61,
  532. .reset_gpio_port[2] = -EINVAL
  533. };
  534. #ifdef CONFIG_OMAP_MUX
  535. static struct omap_board_mux board_mux[] __initdata = {
  536. { .reg_offset = OMAP_MUX_TERMINATOR },
  537. };
  538. static struct omap_device_pad serial1_pads[] __initdata = {
  539. /*
  540. * Note that off output enable is an active low
  541. * signal. So setting this means pin is a
  542. * input enabled in off mode
  543. */
  544. OMAP_MUX_STATIC("uart1_cts.uart1_cts",
  545. OMAP_PIN_INPUT |
  546. OMAP_PIN_OFF_INPUT_PULLDOWN |
  547. OMAP_OFFOUT_EN |
  548. OMAP_MUX_MODE0),
  549. OMAP_MUX_STATIC("uart1_rts.uart1_rts",
  550. OMAP_PIN_OUTPUT |
  551. OMAP_OFF_EN |
  552. OMAP_MUX_MODE0),
  553. OMAP_MUX_STATIC("uart1_rx.uart1_rx",
  554. OMAP_PIN_INPUT |
  555. OMAP_PIN_OFF_INPUT_PULLDOWN |
  556. OMAP_OFFOUT_EN |
  557. OMAP_MUX_MODE0),
  558. OMAP_MUX_STATIC("uart1_tx.uart1_tx",
  559. OMAP_PIN_OUTPUT |
  560. OMAP_OFF_EN |
  561. OMAP_MUX_MODE0),
  562. };
  563. static struct omap_device_pad serial2_pads[] __initdata = {
  564. OMAP_MUX_STATIC("uart2_cts.uart2_cts",
  565. OMAP_PIN_INPUT_PULLUP |
  566. OMAP_PIN_OFF_INPUT_PULLDOWN |
  567. OMAP_OFFOUT_EN |
  568. OMAP_MUX_MODE0),
  569. OMAP_MUX_STATIC("uart2_rts.uart2_rts",
  570. OMAP_PIN_OUTPUT |
  571. OMAP_OFF_EN |
  572. OMAP_MUX_MODE0),
  573. OMAP_MUX_STATIC("uart2_rx.uart2_rx",
  574. OMAP_PIN_INPUT |
  575. OMAP_PIN_OFF_INPUT_PULLDOWN |
  576. OMAP_OFFOUT_EN |
  577. OMAP_MUX_MODE0),
  578. OMAP_MUX_STATIC("uart2_tx.uart2_tx",
  579. OMAP_PIN_OUTPUT |
  580. OMAP_OFF_EN |
  581. OMAP_MUX_MODE0),
  582. };
  583. static struct omap_device_pad serial3_pads[] __initdata = {
  584. OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
  585. OMAP_PIN_INPUT_PULLDOWN |
  586. OMAP_PIN_OFF_INPUT_PULLDOWN |
  587. OMAP_OFFOUT_EN |
  588. OMAP_MUX_MODE0),
  589. OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
  590. OMAP_PIN_OUTPUT |
  591. OMAP_OFF_EN |
  592. OMAP_MUX_MODE0),
  593. OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
  594. OMAP_PIN_INPUT |
  595. OMAP_PIN_OFF_INPUT_PULLDOWN |
  596. OMAP_OFFOUT_EN |
  597. OMAP_MUX_MODE0),
  598. OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
  599. OMAP_PIN_OUTPUT |
  600. OMAP_OFF_EN |
  601. OMAP_MUX_MODE0),
  602. };
  603. static struct omap_board_data serial1_data = {
  604. .id = 0,
  605. .pads = serial1_pads,
  606. .pads_cnt = ARRAY_SIZE(serial1_pads),
  607. };
  608. static struct omap_board_data serial2_data = {
  609. .id = 1,
  610. .pads = serial2_pads,
  611. .pads_cnt = ARRAY_SIZE(serial2_pads),
  612. };
  613. static struct omap_board_data serial3_data = {
  614. .id = 2,
  615. .pads = serial3_pads,
  616. .pads_cnt = ARRAY_SIZE(serial3_pads),
  617. };
  618. static inline void board_serial_init(void)
  619. {
  620. omap_serial_init_port(&serial1_data);
  621. omap_serial_init_port(&serial2_data);
  622. omap_serial_init_port(&serial3_data);
  623. }
  624. #else
  625. #define board_mux NULL
  626. static inline void board_serial_init(void)
  627. {
  628. omap_serial_init();
  629. }
  630. #endif
  631. /*
  632. * SDP3430 V2 Board CS organization
  633. * Different from SDP3430 V1. Now 4 switches used to specify CS
  634. *
  635. * See also the Switch S8 settings in the comments.
  636. */
  637. static char chip_sel_3430[][GPMC_CS_NUM] = {
  638. {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
  639. {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
  640. {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
  641. };
  642. static struct mtd_partition sdp_nor_partitions[] = {
  643. /* bootloader (U-Boot, etc) in first sector */
  644. {
  645. .name = "Bootloader-NOR",
  646. .offset = 0,
  647. .size = SZ_256K,
  648. .mask_flags = MTD_WRITEABLE, /* force read-only */
  649. },
  650. /* bootloader params in the next sector */
  651. {
  652. .name = "Params-NOR",
  653. .offset = MTDPART_OFS_APPEND,
  654. .size = SZ_256K,
  655. .mask_flags = 0,
  656. },
  657. /* kernel */
  658. {
  659. .name = "Kernel-NOR",
  660. .offset = MTDPART_OFS_APPEND,
  661. .size = SZ_2M,
  662. .mask_flags = 0
  663. },
  664. /* file system */
  665. {
  666. .name = "Filesystem-NOR",
  667. .offset = MTDPART_OFS_APPEND,
  668. .size = MTDPART_SIZ_FULL,
  669. .mask_flags = 0
  670. }
  671. };
  672. static struct mtd_partition sdp_onenand_partitions[] = {
  673. {
  674. .name = "X-Loader-OneNAND",
  675. .offset = 0,
  676. .size = 4 * (64 * 2048),
  677. .mask_flags = MTD_WRITEABLE /* force read-only */
  678. },
  679. {
  680. .name = "U-Boot-OneNAND",
  681. .offset = MTDPART_OFS_APPEND,
  682. .size = 2 * (64 * 2048),
  683. .mask_flags = MTD_WRITEABLE /* force read-only */
  684. },
  685. {
  686. .name = "U-Boot Environment-OneNAND",
  687. .offset = MTDPART_OFS_APPEND,
  688. .size = 1 * (64 * 2048),
  689. },
  690. {
  691. .name = "Kernel-OneNAND",
  692. .offset = MTDPART_OFS_APPEND,
  693. .size = 16 * (64 * 2048),
  694. },
  695. {
  696. .name = "File System-OneNAND",
  697. .offset = MTDPART_OFS_APPEND,
  698. .size = MTDPART_SIZ_FULL,
  699. },
  700. };
  701. static struct mtd_partition sdp_nand_partitions[] = {
  702. /* All the partition sizes are listed in terms of NAND block size */
  703. {
  704. .name = "X-Loader-NAND",
  705. .offset = 0,
  706. .size = 4 * (64 * 2048),
  707. .mask_flags = MTD_WRITEABLE, /* force read-only */
  708. },
  709. {
  710. .name = "U-Boot-NAND",
  711. .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
  712. .size = 10 * (64 * 2048),
  713. .mask_flags = MTD_WRITEABLE, /* force read-only */
  714. },
  715. {
  716. .name = "Boot Env-NAND",
  717. .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
  718. .size = 6 * (64 * 2048),
  719. },
  720. {
  721. .name = "Kernel-NAND",
  722. .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
  723. .size = 40 * (64 * 2048),
  724. },
  725. {
  726. .name = "File System - NAND",
  727. .size = MTDPART_SIZ_FULL,
  728. .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
  729. },
  730. };
  731. static struct flash_partitions sdp_flash_partitions[] = {
  732. {
  733. .parts = sdp_nor_partitions,
  734. .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
  735. },
  736. {
  737. .parts = sdp_onenand_partitions,
  738. .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
  739. },
  740. {
  741. .parts = sdp_nand_partitions,
  742. .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
  743. },
  744. };
  745. static struct omap_musb_board_data musb_board_data = {
  746. .interface_type = MUSB_INTERFACE_ULPI,
  747. .mode = MUSB_OTG,
  748. .power = 100,
  749. };
  750. static void __init omap_3430sdp_init(void)
  751. {
  752. omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
  753. omap_board_config = sdp3430_config;
  754. omap_board_config_size = ARRAY_SIZE(sdp3430_config);
  755. omap3430_i2c_init();
  756. omap_display_init(&sdp3430_dss_data);
  757. if (omap_rev() > OMAP3430_REV_ES1_0)
  758. ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
  759. else
  760. ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV1;
  761. sdp3430_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
  762. spi_register_board_info(sdp3430_spi_board_info,
  763. ARRAY_SIZE(sdp3430_spi_board_info));
  764. ads7846_dev_init();
  765. board_serial_init();
  766. usb_musb_init(&musb_board_data);
  767. board_smc91x_init();
  768. board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
  769. sdp3430_display_init();
  770. enable_board_wakeup_source();
  771. usbhs_init(&usbhs_bdata);
  772. }
  773. MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
  774. /* Maintainer: Syed Khasim - Texas Instruments Inc */
  775. .boot_params = 0x80000100,
  776. .reserve = omap_reserve,
  777. .map_io = omap3_map_io,
  778. .init_early = omap_3430sdp_init_early,
  779. .init_irq = omap_init_irq,
  780. .init_machine = omap_3430sdp_init,
  781. .timer = &omap_timer,
  782. MACHINE_END