debug.h 5.9 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef DEBUG_H
  17. #define DEBUG_H
  18. #include "hw.h"
  19. #include "rc.h"
  20. struct ath_txq;
  21. struct ath_buf;
  22. #ifdef CONFIG_ATH9K_DEBUGFS
  23. #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  24. #else
  25. #define TX_STAT_INC(q, c) do { } while (0)
  26. #endif
  27. #ifdef CONFIG_ATH9K_DEBUGFS
  28. /**
  29. * struct ath_interrupt_stats - Contains statistics about interrupts
  30. * @total: Total no. of interrupts generated so far
  31. * @rxok: RX with no errors
  32. * @rxlp: RX with low priority RX
  33. * @rxhp: RX with high priority, uapsd only
  34. * @rxeol: RX with no more RXDESC available
  35. * @rxorn: RX FIFO overrun
  36. * @txok: TX completed at the requested rate
  37. * @txurn: TX FIFO underrun
  38. * @mib: MIB regs reaching its threshold
  39. * @rxphyerr: RX with phy errors
  40. * @rx_keycache_miss: RX with key cache misses
  41. * @swba: Software Beacon Alert
  42. * @bmiss: Beacon Miss
  43. * @bnr: Beacon Not Ready
  44. * @cst: Carrier Sense TImeout
  45. * @gtt: Global TX Timeout
  46. * @tim: RX beacon TIM occurrence
  47. * @cabend: RX End of CAB traffic
  48. * @dtimsync: DTIM sync lossage
  49. * @dtim: RX Beacon with DTIM
  50. * @bb_watchdog: Baseband watchdog
  51. * @tsfoor: TSF out of range, indicates that the corrected TSF received
  52. * from a beacon differs from the PCU's internal TSF by more than a
  53. * (programmable) threshold
  54. */
  55. struct ath_interrupt_stats {
  56. u32 total;
  57. u32 rxok;
  58. u32 rxlp;
  59. u32 rxhp;
  60. u32 rxeol;
  61. u32 rxorn;
  62. u32 txok;
  63. u32 txeol;
  64. u32 txurn;
  65. u32 mib;
  66. u32 rxphyerr;
  67. u32 rx_keycache_miss;
  68. u32 swba;
  69. u32 bmiss;
  70. u32 bnr;
  71. u32 cst;
  72. u32 gtt;
  73. u32 tim;
  74. u32 cabend;
  75. u32 dtimsync;
  76. u32 dtim;
  77. u32 bb_watchdog;
  78. u32 tsfoor;
  79. };
  80. /**
  81. * struct ath_tx_stats - Statistics about TX
  82. * @tx_pkts_all: No. of total frames transmitted, including ones that
  83. may have had errors.
  84. * @tx_bytes_all: No. of total bytes transmitted, including ones that
  85. may have had errors.
  86. * @queued: Total MPDUs (non-aggr) queued
  87. * @completed: Total MPDUs (non-aggr) completed
  88. * @a_aggr: Total no. of aggregates queued
  89. * @a_queued_hw: Total AMPDUs queued to hardware
  90. * @a_queued_sw: Total AMPDUs queued to software queues
  91. * @a_completed: Total AMPDUs completed
  92. * @a_retries: No. of AMPDUs retried (SW)
  93. * @a_xretries: No. of AMPDUs dropped due to xretries
  94. * @fifo_underrun: FIFO underrun occurrences
  95. Valid only for:
  96. - non-aggregate condition.
  97. - first packet of aggregate.
  98. * @xtxop: No. of frames filtered because of TXOP limit
  99. * @timer_exp: Transmit timer expiry
  100. * @desc_cfg_err: Descriptor configuration errors
  101. * @data_urn: TX data underrun errors
  102. * @delim_urn: TX delimiter underrun errors
  103. * @puttxbuf: Number of times hardware was given txbuf to write.
  104. * @txstart: Number of times hardware was told to start tx.
  105. * @txprocdesc: Number of times tx descriptor was processed
  106. */
  107. struct ath_tx_stats {
  108. u32 tx_pkts_all;
  109. u32 tx_bytes_all;
  110. u32 queued;
  111. u32 completed;
  112. u32 a_aggr;
  113. u32 a_queued_hw;
  114. u32 a_queued_sw;
  115. u32 a_completed;
  116. u32 a_retries;
  117. u32 a_xretries;
  118. u32 fifo_underrun;
  119. u32 xtxop;
  120. u32 timer_exp;
  121. u32 desc_cfg_err;
  122. u32 data_underrun;
  123. u32 delim_underrun;
  124. u32 puttxbuf;
  125. u32 txstart;
  126. u32 txprocdesc;
  127. };
  128. /**
  129. * struct ath_rx_stats - RX Statistics
  130. * @rx_pkts_all: No. of total frames received, including ones that
  131. may have had errors.
  132. * @rx_bytes_all: No. of total bytes received, including ones that
  133. may have had errors.
  134. * @crc_err: No. of frames with incorrect CRC value
  135. * @decrypt_crc_err: No. of frames whose CRC check failed after
  136. decryption process completed
  137. * @phy_err: No. of frames whose reception failed because the PHY
  138. encountered an error
  139. * @mic_err: No. of frames with incorrect TKIP MIC verification failure
  140. * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
  141. * @post_delim_crc_err: Post-Frame delimiter CRC error detections
  142. * @decrypt_busy_err: Decryption interruptions counter
  143. * @phy_err_stats: Individual PHY error statistics
  144. */
  145. struct ath_rx_stats {
  146. u32 rx_pkts_all;
  147. u32 rx_bytes_all;
  148. u32 crc_err;
  149. u32 decrypt_crc_err;
  150. u32 phy_err;
  151. u32 mic_err;
  152. u32 pre_delim_crc_err;
  153. u32 post_delim_crc_err;
  154. u32 decrypt_busy_err;
  155. u32 phy_err_stats[ATH9K_PHYERR_MAX];
  156. int8_t rs_rssi_ctl0;
  157. int8_t rs_rssi_ctl1;
  158. int8_t rs_rssi_ctl2;
  159. int8_t rs_rssi_ext0;
  160. int8_t rs_rssi_ext1;
  161. int8_t rs_rssi_ext2;
  162. u8 rs_antenna;
  163. };
  164. struct ath_stats {
  165. struct ath_interrupt_stats istats;
  166. struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
  167. struct ath_rx_stats rxstats;
  168. };
  169. struct ath9k_debug {
  170. struct dentry *debugfs_phy;
  171. u32 regidx;
  172. struct ath_stats stats;
  173. };
  174. int ath9k_init_debug(struct ath_hw *ah);
  175. void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
  176. void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
  177. struct ath_tx_status *ts, struct ath_txq *txq);
  178. void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
  179. #else
  180. static inline int ath9k_init_debug(struct ath_hw *ah)
  181. {
  182. return 0;
  183. }
  184. static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
  185. enum ath9k_int status)
  186. {
  187. }
  188. static inline void ath_debug_stat_tx(struct ath_softc *sc,
  189. struct ath_buf *bf,
  190. struct ath_tx_status *ts,
  191. struct ath_txq *txq)
  192. {
  193. }
  194. static inline void ath_debug_stat_rx(struct ath_softc *sc,
  195. struct ath_rx_status *rs)
  196. {
  197. }
  198. #endif /* CONFIG_ATH9K_DEBUGFS */
  199. #endif /* DEBUG_H */