hpsa.c 129 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12. * NON INFRINGEMENT. See the GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. *
  18. * Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/types.h>
  24. #include <linux/pci.h>
  25. #include <linux/kernel.h>
  26. #include <linux/slab.h>
  27. #include <linux/delay.h>
  28. #include <linux/fs.h>
  29. #include <linux/timer.h>
  30. #include <linux/seq_file.h>
  31. #include <linux/init.h>
  32. #include <linux/spinlock.h>
  33. #include <linux/compat.h>
  34. #include <linux/blktrace_api.h>
  35. #include <linux/uaccess.h>
  36. #include <linux/io.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/completion.h>
  39. #include <linux/moduleparam.h>
  40. #include <scsi/scsi.h>
  41. #include <scsi/scsi_cmnd.h>
  42. #include <scsi/scsi_device.h>
  43. #include <scsi/scsi_host.h>
  44. #include <scsi/scsi_tcq.h>
  45. #include <linux/cciss_ioctl.h>
  46. #include <linux/string.h>
  47. #include <linux/bitmap.h>
  48. #include <linux/atomic.h>
  49. #include <linux/kthread.h>
  50. #include <linux/jiffies.h>
  51. #include "hpsa_cmd.h"
  52. #include "hpsa.h"
  53. /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
  54. #define HPSA_DRIVER_VERSION "2.0.2-1"
  55. #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
  56. /* How long to wait (in milliseconds) for board to go into simple mode */
  57. #define MAX_CONFIG_WAIT 30000
  58. #define MAX_IOCTL_CONFIG_WAIT 1000
  59. /*define how many times we will try a command because of bus resets */
  60. #define MAX_CMD_RETRIES 3
  61. /* Embedded module documentation macros - see modules.h */
  62. MODULE_AUTHOR("Hewlett-Packard Company");
  63. MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
  64. HPSA_DRIVER_VERSION);
  65. MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
  66. MODULE_VERSION(HPSA_DRIVER_VERSION);
  67. MODULE_LICENSE("GPL");
  68. static int hpsa_allow_any;
  69. module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
  70. MODULE_PARM_DESC(hpsa_allow_any,
  71. "Allow hpsa driver to access unknown HP Smart Array hardware");
  72. static int hpsa_simple_mode;
  73. module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
  74. MODULE_PARM_DESC(hpsa_simple_mode,
  75. "Use 'simple mode' rather than 'performant mode'");
  76. /* define the PCI info for the cards we can control */
  77. static const struct pci_device_id hpsa_pci_device_id[] = {
  78. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
  79. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
  80. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
  81. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
  82. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
  83. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324a},
  84. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324b},
  85. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
  86. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
  87. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
  88. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
  90. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
  91. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
  92. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
  93. {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  94. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  95. {0,}
  96. };
  97. MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
  98. /* board_id = Subsystem Device ID & Vendor ID
  99. * product = Marketing Name for the board
  100. * access = Address of the struct of function pointers
  101. */
  102. static struct board_type products[] = {
  103. {0x3241103C, "Smart Array P212", &SA5_access},
  104. {0x3243103C, "Smart Array P410", &SA5_access},
  105. {0x3245103C, "Smart Array P410i", &SA5_access},
  106. {0x3247103C, "Smart Array P411", &SA5_access},
  107. {0x3249103C, "Smart Array P812", &SA5_access},
  108. {0x324a103C, "Smart Array P712m", &SA5_access},
  109. {0x324b103C, "Smart Array P711m", &SA5_access},
  110. {0x3350103C, "Smart Array", &SA5_access},
  111. {0x3351103C, "Smart Array", &SA5_access},
  112. {0x3352103C, "Smart Array", &SA5_access},
  113. {0x3353103C, "Smart Array", &SA5_access},
  114. {0x3354103C, "Smart Array", &SA5_access},
  115. {0x3355103C, "Smart Array", &SA5_access},
  116. {0x3356103C, "Smart Array", &SA5_access},
  117. {0xFFFF103C, "Unknown Smart Array", &SA5_access},
  118. };
  119. static int number_of_controllers;
  120. static struct list_head hpsa_ctlr_list = LIST_HEAD_INIT(hpsa_ctlr_list);
  121. static spinlock_t lockup_detector_lock;
  122. static struct task_struct *hpsa_lockup_detector;
  123. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
  124. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
  125. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
  126. static void start_io(struct ctlr_info *h);
  127. #ifdef CONFIG_COMPAT
  128. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
  129. #endif
  130. static void cmd_free(struct ctlr_info *h, struct CommandList *c);
  131. static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
  132. static struct CommandList *cmd_alloc(struct ctlr_info *h);
  133. static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
  134. static void fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  135. void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
  136. int cmd_type);
  137. static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  138. static void hpsa_scan_start(struct Scsi_Host *);
  139. static int hpsa_scan_finished(struct Scsi_Host *sh,
  140. unsigned long elapsed_time);
  141. static int hpsa_change_queue_depth(struct scsi_device *sdev,
  142. int qdepth, int reason);
  143. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
  144. static int hpsa_slave_alloc(struct scsi_device *sdev);
  145. static void hpsa_slave_destroy(struct scsi_device *sdev);
  146. static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
  147. static int check_for_unit_attention(struct ctlr_info *h,
  148. struct CommandList *c);
  149. static void check_ioctl_unit_attention(struct ctlr_info *h,
  150. struct CommandList *c);
  151. /* performant mode helper functions */
  152. static void calc_bucket_map(int *bucket, int num_buckets,
  153. int nsgs, int *bucket_map);
  154. static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
  155. static inline u32 next_command(struct ctlr_info *h);
  156. static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
  157. void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  158. u64 *cfg_offset);
  159. static int __devinit hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  160. unsigned long *memory_bar);
  161. static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
  162. static int __devinit hpsa_wait_for_board_state(struct pci_dev *pdev,
  163. void __iomem *vaddr, int wait_for_ready);
  164. #define BOARD_NOT_READY 0
  165. #define BOARD_READY 1
  166. static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
  167. {
  168. unsigned long *priv = shost_priv(sdev->host);
  169. return (struct ctlr_info *) *priv;
  170. }
  171. static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
  172. {
  173. unsigned long *priv = shost_priv(sh);
  174. return (struct ctlr_info *) *priv;
  175. }
  176. static int check_for_unit_attention(struct ctlr_info *h,
  177. struct CommandList *c)
  178. {
  179. if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
  180. return 0;
  181. switch (c->err_info->SenseInfo[12]) {
  182. case STATE_CHANGED:
  183. dev_warn(&h->pdev->dev, "hpsa%d: a state change "
  184. "detected, command retried\n", h->ctlr);
  185. break;
  186. case LUN_FAILED:
  187. dev_warn(&h->pdev->dev, "hpsa%d: LUN failure "
  188. "detected, action required\n", h->ctlr);
  189. break;
  190. case REPORT_LUNS_CHANGED:
  191. dev_warn(&h->pdev->dev, "hpsa%d: report LUN data "
  192. "changed, action required\n", h->ctlr);
  193. /*
  194. * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012.
  195. */
  196. break;
  197. case POWER_OR_RESET:
  198. dev_warn(&h->pdev->dev, "hpsa%d: a power on "
  199. "or device reset detected\n", h->ctlr);
  200. break;
  201. case UNIT_ATTENTION_CLEARED:
  202. dev_warn(&h->pdev->dev, "hpsa%d: unit attention "
  203. "cleared by another initiator\n", h->ctlr);
  204. break;
  205. default:
  206. dev_warn(&h->pdev->dev, "hpsa%d: unknown "
  207. "unit attention detected\n", h->ctlr);
  208. break;
  209. }
  210. return 1;
  211. }
  212. static ssize_t host_store_rescan(struct device *dev,
  213. struct device_attribute *attr,
  214. const char *buf, size_t count)
  215. {
  216. struct ctlr_info *h;
  217. struct Scsi_Host *shost = class_to_shost(dev);
  218. h = shost_to_hba(shost);
  219. hpsa_scan_start(h->scsi_host);
  220. return count;
  221. }
  222. static ssize_t host_show_firmware_revision(struct device *dev,
  223. struct device_attribute *attr, char *buf)
  224. {
  225. struct ctlr_info *h;
  226. struct Scsi_Host *shost = class_to_shost(dev);
  227. unsigned char *fwrev;
  228. h = shost_to_hba(shost);
  229. if (!h->hba_inquiry_data)
  230. return 0;
  231. fwrev = &h->hba_inquiry_data[32];
  232. return snprintf(buf, 20, "%c%c%c%c\n",
  233. fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
  234. }
  235. static ssize_t host_show_commands_outstanding(struct device *dev,
  236. struct device_attribute *attr, char *buf)
  237. {
  238. struct Scsi_Host *shost = class_to_shost(dev);
  239. struct ctlr_info *h = shost_to_hba(shost);
  240. return snprintf(buf, 20, "%d\n", h->commands_outstanding);
  241. }
  242. static ssize_t host_show_transport_mode(struct device *dev,
  243. struct device_attribute *attr, char *buf)
  244. {
  245. struct ctlr_info *h;
  246. struct Scsi_Host *shost = class_to_shost(dev);
  247. h = shost_to_hba(shost);
  248. return snprintf(buf, 20, "%s\n",
  249. h->transMethod & CFGTBL_Trans_Performant ?
  250. "performant" : "simple");
  251. }
  252. /* List of controllers which cannot be hard reset on kexec with reset_devices */
  253. static u32 unresettable_controller[] = {
  254. 0x324a103C, /* Smart Array P712m */
  255. 0x324b103C, /* SmartArray P711m */
  256. 0x3223103C, /* Smart Array P800 */
  257. 0x3234103C, /* Smart Array P400 */
  258. 0x3235103C, /* Smart Array P400i */
  259. 0x3211103C, /* Smart Array E200i */
  260. 0x3212103C, /* Smart Array E200 */
  261. 0x3213103C, /* Smart Array E200i */
  262. 0x3214103C, /* Smart Array E200i */
  263. 0x3215103C, /* Smart Array E200i */
  264. 0x3237103C, /* Smart Array E500 */
  265. 0x323D103C, /* Smart Array P700m */
  266. 0x409C0E11, /* Smart Array 6400 */
  267. 0x409D0E11, /* Smart Array 6400 EM */
  268. };
  269. /* List of controllers which cannot even be soft reset */
  270. static u32 soft_unresettable_controller[] = {
  271. /* Exclude 640x boards. These are two pci devices in one slot
  272. * which share a battery backed cache module. One controls the
  273. * cache, the other accesses the cache through the one that controls
  274. * it. If we reset the one controlling the cache, the other will
  275. * likely not be happy. Just forbid resetting this conjoined mess.
  276. * The 640x isn't really supported by hpsa anyway.
  277. */
  278. 0x409C0E11, /* Smart Array 6400 */
  279. 0x409D0E11, /* Smart Array 6400 EM */
  280. };
  281. static int ctlr_is_hard_resettable(u32 board_id)
  282. {
  283. int i;
  284. for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
  285. if (unresettable_controller[i] == board_id)
  286. return 0;
  287. return 1;
  288. }
  289. static int ctlr_is_soft_resettable(u32 board_id)
  290. {
  291. int i;
  292. for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
  293. if (soft_unresettable_controller[i] == board_id)
  294. return 0;
  295. return 1;
  296. }
  297. static int ctlr_is_resettable(u32 board_id)
  298. {
  299. return ctlr_is_hard_resettable(board_id) ||
  300. ctlr_is_soft_resettable(board_id);
  301. }
  302. static ssize_t host_show_resettable(struct device *dev,
  303. struct device_attribute *attr, char *buf)
  304. {
  305. struct ctlr_info *h;
  306. struct Scsi_Host *shost = class_to_shost(dev);
  307. h = shost_to_hba(shost);
  308. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
  309. }
  310. static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
  311. {
  312. return (scsi3addr[3] & 0xC0) == 0x40;
  313. }
  314. static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
  315. "UNKNOWN"
  316. };
  317. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
  318. static ssize_t raid_level_show(struct device *dev,
  319. struct device_attribute *attr, char *buf)
  320. {
  321. ssize_t l = 0;
  322. unsigned char rlevel;
  323. struct ctlr_info *h;
  324. struct scsi_device *sdev;
  325. struct hpsa_scsi_dev_t *hdev;
  326. unsigned long flags;
  327. sdev = to_scsi_device(dev);
  328. h = sdev_to_hba(sdev);
  329. spin_lock_irqsave(&h->lock, flags);
  330. hdev = sdev->hostdata;
  331. if (!hdev) {
  332. spin_unlock_irqrestore(&h->lock, flags);
  333. return -ENODEV;
  334. }
  335. /* Is this even a logical drive? */
  336. if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
  337. spin_unlock_irqrestore(&h->lock, flags);
  338. l = snprintf(buf, PAGE_SIZE, "N/A\n");
  339. return l;
  340. }
  341. rlevel = hdev->raid_level;
  342. spin_unlock_irqrestore(&h->lock, flags);
  343. if (rlevel > RAID_UNKNOWN)
  344. rlevel = RAID_UNKNOWN;
  345. l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
  346. return l;
  347. }
  348. static ssize_t lunid_show(struct device *dev,
  349. struct device_attribute *attr, char *buf)
  350. {
  351. struct ctlr_info *h;
  352. struct scsi_device *sdev;
  353. struct hpsa_scsi_dev_t *hdev;
  354. unsigned long flags;
  355. unsigned char lunid[8];
  356. sdev = to_scsi_device(dev);
  357. h = sdev_to_hba(sdev);
  358. spin_lock_irqsave(&h->lock, flags);
  359. hdev = sdev->hostdata;
  360. if (!hdev) {
  361. spin_unlock_irqrestore(&h->lock, flags);
  362. return -ENODEV;
  363. }
  364. memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
  365. spin_unlock_irqrestore(&h->lock, flags);
  366. return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  367. lunid[0], lunid[1], lunid[2], lunid[3],
  368. lunid[4], lunid[5], lunid[6], lunid[7]);
  369. }
  370. static ssize_t unique_id_show(struct device *dev,
  371. struct device_attribute *attr, char *buf)
  372. {
  373. struct ctlr_info *h;
  374. struct scsi_device *sdev;
  375. struct hpsa_scsi_dev_t *hdev;
  376. unsigned long flags;
  377. unsigned char sn[16];
  378. sdev = to_scsi_device(dev);
  379. h = sdev_to_hba(sdev);
  380. spin_lock_irqsave(&h->lock, flags);
  381. hdev = sdev->hostdata;
  382. if (!hdev) {
  383. spin_unlock_irqrestore(&h->lock, flags);
  384. return -ENODEV;
  385. }
  386. memcpy(sn, hdev->device_id, sizeof(sn));
  387. spin_unlock_irqrestore(&h->lock, flags);
  388. return snprintf(buf, 16 * 2 + 2,
  389. "%02X%02X%02X%02X%02X%02X%02X%02X"
  390. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  391. sn[0], sn[1], sn[2], sn[3],
  392. sn[4], sn[5], sn[6], sn[7],
  393. sn[8], sn[9], sn[10], sn[11],
  394. sn[12], sn[13], sn[14], sn[15]);
  395. }
  396. static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
  397. static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
  398. static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
  399. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  400. static DEVICE_ATTR(firmware_revision, S_IRUGO,
  401. host_show_firmware_revision, NULL);
  402. static DEVICE_ATTR(commands_outstanding, S_IRUGO,
  403. host_show_commands_outstanding, NULL);
  404. static DEVICE_ATTR(transport_mode, S_IRUGO,
  405. host_show_transport_mode, NULL);
  406. static DEVICE_ATTR(resettable, S_IRUGO,
  407. host_show_resettable, NULL);
  408. static struct device_attribute *hpsa_sdev_attrs[] = {
  409. &dev_attr_raid_level,
  410. &dev_attr_lunid,
  411. &dev_attr_unique_id,
  412. NULL,
  413. };
  414. static struct device_attribute *hpsa_shost_attrs[] = {
  415. &dev_attr_rescan,
  416. &dev_attr_firmware_revision,
  417. &dev_attr_commands_outstanding,
  418. &dev_attr_transport_mode,
  419. &dev_attr_resettable,
  420. NULL,
  421. };
  422. static struct scsi_host_template hpsa_driver_template = {
  423. .module = THIS_MODULE,
  424. .name = "hpsa",
  425. .proc_name = "hpsa",
  426. .queuecommand = hpsa_scsi_queue_command,
  427. .scan_start = hpsa_scan_start,
  428. .scan_finished = hpsa_scan_finished,
  429. .change_queue_depth = hpsa_change_queue_depth,
  430. .this_id = -1,
  431. .use_clustering = ENABLE_CLUSTERING,
  432. .eh_device_reset_handler = hpsa_eh_device_reset_handler,
  433. .ioctl = hpsa_ioctl,
  434. .slave_alloc = hpsa_slave_alloc,
  435. .slave_destroy = hpsa_slave_destroy,
  436. #ifdef CONFIG_COMPAT
  437. .compat_ioctl = hpsa_compat_ioctl,
  438. #endif
  439. .sdev_attrs = hpsa_sdev_attrs,
  440. .shost_attrs = hpsa_shost_attrs,
  441. .max_sectors = 8192,
  442. };
  443. /* Enqueuing and dequeuing functions for cmdlists. */
  444. static inline void addQ(struct list_head *list, struct CommandList *c)
  445. {
  446. list_add_tail(&c->list, list);
  447. }
  448. static inline u32 next_command(struct ctlr_info *h)
  449. {
  450. u32 a;
  451. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  452. return h->access.command_completed(h);
  453. if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
  454. a = *(h->reply_pool_head); /* Next cmd in ring buffer */
  455. (h->reply_pool_head)++;
  456. h->commands_outstanding--;
  457. } else {
  458. a = FIFO_EMPTY;
  459. }
  460. /* Check for wraparound */
  461. if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
  462. h->reply_pool_head = h->reply_pool;
  463. h->reply_pool_wraparound ^= 1;
  464. }
  465. return a;
  466. }
  467. /* set_performant_mode: Modify the tag for cciss performant
  468. * set bit 0 for pull model, bits 3-1 for block fetch
  469. * register number
  470. */
  471. static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
  472. {
  473. if (likely(h->transMethod & CFGTBL_Trans_Performant))
  474. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  475. }
  476. static void enqueue_cmd_and_start_io(struct ctlr_info *h,
  477. struct CommandList *c)
  478. {
  479. unsigned long flags;
  480. set_performant_mode(h, c);
  481. spin_lock_irqsave(&h->lock, flags);
  482. addQ(&h->reqQ, c);
  483. h->Qdepth++;
  484. start_io(h);
  485. spin_unlock_irqrestore(&h->lock, flags);
  486. }
  487. static inline void removeQ(struct CommandList *c)
  488. {
  489. if (WARN_ON(list_empty(&c->list)))
  490. return;
  491. list_del_init(&c->list);
  492. }
  493. static inline int is_hba_lunid(unsigned char scsi3addr[])
  494. {
  495. return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
  496. }
  497. static inline int is_scsi_rev_5(struct ctlr_info *h)
  498. {
  499. if (!h->hba_inquiry_data)
  500. return 0;
  501. if ((h->hba_inquiry_data[2] & 0x07) == 5)
  502. return 1;
  503. return 0;
  504. }
  505. static int hpsa_find_target_lun(struct ctlr_info *h,
  506. unsigned char scsi3addr[], int bus, int *target, int *lun)
  507. {
  508. /* finds an unused bus, target, lun for a new physical device
  509. * assumes h->devlock is held
  510. */
  511. int i, found = 0;
  512. DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
  513. memset(&lun_taken[0], 0, HPSA_MAX_DEVICES >> 3);
  514. for (i = 0; i < h->ndevices; i++) {
  515. if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
  516. set_bit(h->dev[i]->target, lun_taken);
  517. }
  518. for (i = 0; i < HPSA_MAX_DEVICES; i++) {
  519. if (!test_bit(i, lun_taken)) {
  520. /* *bus = 1; */
  521. *target = i;
  522. *lun = 0;
  523. found = 1;
  524. break;
  525. }
  526. }
  527. return !found;
  528. }
  529. /* Add an entry into h->dev[] array. */
  530. static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
  531. struct hpsa_scsi_dev_t *device,
  532. struct hpsa_scsi_dev_t *added[], int *nadded)
  533. {
  534. /* assumes h->devlock is held */
  535. int n = h->ndevices;
  536. int i;
  537. unsigned char addr1[8], addr2[8];
  538. struct hpsa_scsi_dev_t *sd;
  539. if (n >= HPSA_MAX_DEVICES) {
  540. dev_err(&h->pdev->dev, "too many devices, some will be "
  541. "inaccessible.\n");
  542. return -1;
  543. }
  544. /* physical devices do not have lun or target assigned until now. */
  545. if (device->lun != -1)
  546. /* Logical device, lun is already assigned. */
  547. goto lun_assigned;
  548. /* If this device a non-zero lun of a multi-lun device
  549. * byte 4 of the 8-byte LUN addr will contain the logical
  550. * unit no, zero otherise.
  551. */
  552. if (device->scsi3addr[4] == 0) {
  553. /* This is not a non-zero lun of a multi-lun device */
  554. if (hpsa_find_target_lun(h, device->scsi3addr,
  555. device->bus, &device->target, &device->lun) != 0)
  556. return -1;
  557. goto lun_assigned;
  558. }
  559. /* This is a non-zero lun of a multi-lun device.
  560. * Search through our list and find the device which
  561. * has the same 8 byte LUN address, excepting byte 4.
  562. * Assign the same bus and target for this new LUN.
  563. * Use the logical unit number from the firmware.
  564. */
  565. memcpy(addr1, device->scsi3addr, 8);
  566. addr1[4] = 0;
  567. for (i = 0; i < n; i++) {
  568. sd = h->dev[i];
  569. memcpy(addr2, sd->scsi3addr, 8);
  570. addr2[4] = 0;
  571. /* differ only in byte 4? */
  572. if (memcmp(addr1, addr2, 8) == 0) {
  573. device->bus = sd->bus;
  574. device->target = sd->target;
  575. device->lun = device->scsi3addr[4];
  576. break;
  577. }
  578. }
  579. if (device->lun == -1) {
  580. dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
  581. " suspect firmware bug or unsupported hardware "
  582. "configuration.\n");
  583. return -1;
  584. }
  585. lun_assigned:
  586. h->dev[n] = device;
  587. h->ndevices++;
  588. added[*nadded] = device;
  589. (*nadded)++;
  590. /* initially, (before registering with scsi layer) we don't
  591. * know our hostno and we don't want to print anything first
  592. * time anyway (the scsi layer's inquiries will show that info)
  593. */
  594. /* if (hostno != -1) */
  595. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
  596. scsi_device_type(device->devtype), hostno,
  597. device->bus, device->target, device->lun);
  598. return 0;
  599. }
  600. /* Replace an entry from h->dev[] array. */
  601. static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
  602. int entry, struct hpsa_scsi_dev_t *new_entry,
  603. struct hpsa_scsi_dev_t *added[], int *nadded,
  604. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  605. {
  606. /* assumes h->devlock is held */
  607. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  608. removed[*nremoved] = h->dev[entry];
  609. (*nremoved)++;
  610. /*
  611. * New physical devices won't have target/lun assigned yet
  612. * so we need to preserve the values in the slot we are replacing.
  613. */
  614. if (new_entry->target == -1) {
  615. new_entry->target = h->dev[entry]->target;
  616. new_entry->lun = h->dev[entry]->lun;
  617. }
  618. h->dev[entry] = new_entry;
  619. added[*nadded] = new_entry;
  620. (*nadded)++;
  621. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
  622. scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
  623. new_entry->target, new_entry->lun);
  624. }
  625. /* Remove an entry from h->dev[] array. */
  626. static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
  627. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  628. {
  629. /* assumes h->devlock is held */
  630. int i;
  631. struct hpsa_scsi_dev_t *sd;
  632. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  633. sd = h->dev[entry];
  634. removed[*nremoved] = h->dev[entry];
  635. (*nremoved)++;
  636. for (i = entry; i < h->ndevices-1; i++)
  637. h->dev[i] = h->dev[i+1];
  638. h->ndevices--;
  639. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
  640. scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
  641. sd->lun);
  642. }
  643. #define SCSI3ADDR_EQ(a, b) ( \
  644. (a)[7] == (b)[7] && \
  645. (a)[6] == (b)[6] && \
  646. (a)[5] == (b)[5] && \
  647. (a)[4] == (b)[4] && \
  648. (a)[3] == (b)[3] && \
  649. (a)[2] == (b)[2] && \
  650. (a)[1] == (b)[1] && \
  651. (a)[0] == (b)[0])
  652. static void fixup_botched_add(struct ctlr_info *h,
  653. struct hpsa_scsi_dev_t *added)
  654. {
  655. /* called when scsi_add_device fails in order to re-adjust
  656. * h->dev[] to match the mid layer's view.
  657. */
  658. unsigned long flags;
  659. int i, j;
  660. spin_lock_irqsave(&h->lock, flags);
  661. for (i = 0; i < h->ndevices; i++) {
  662. if (h->dev[i] == added) {
  663. for (j = i; j < h->ndevices-1; j++)
  664. h->dev[j] = h->dev[j+1];
  665. h->ndevices--;
  666. break;
  667. }
  668. }
  669. spin_unlock_irqrestore(&h->lock, flags);
  670. kfree(added);
  671. }
  672. static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
  673. struct hpsa_scsi_dev_t *dev2)
  674. {
  675. /* we compare everything except lun and target as these
  676. * are not yet assigned. Compare parts likely
  677. * to differ first
  678. */
  679. if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
  680. sizeof(dev1->scsi3addr)) != 0)
  681. return 0;
  682. if (memcmp(dev1->device_id, dev2->device_id,
  683. sizeof(dev1->device_id)) != 0)
  684. return 0;
  685. if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
  686. return 0;
  687. if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
  688. return 0;
  689. if (dev1->devtype != dev2->devtype)
  690. return 0;
  691. if (dev1->bus != dev2->bus)
  692. return 0;
  693. return 1;
  694. }
  695. /* Find needle in haystack. If exact match found, return DEVICE_SAME,
  696. * and return needle location in *index. If scsi3addr matches, but not
  697. * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
  698. * location in *index. If needle not found, return DEVICE_NOT_FOUND.
  699. */
  700. static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
  701. struct hpsa_scsi_dev_t *haystack[], int haystack_size,
  702. int *index)
  703. {
  704. int i;
  705. #define DEVICE_NOT_FOUND 0
  706. #define DEVICE_CHANGED 1
  707. #define DEVICE_SAME 2
  708. for (i = 0; i < haystack_size; i++) {
  709. if (haystack[i] == NULL) /* previously removed. */
  710. continue;
  711. if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
  712. *index = i;
  713. if (device_is_the_same(needle, haystack[i]))
  714. return DEVICE_SAME;
  715. else
  716. return DEVICE_CHANGED;
  717. }
  718. }
  719. *index = -1;
  720. return DEVICE_NOT_FOUND;
  721. }
  722. static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
  723. struct hpsa_scsi_dev_t *sd[], int nsds)
  724. {
  725. /* sd contains scsi3 addresses and devtypes, and inquiry
  726. * data. This function takes what's in sd to be the current
  727. * reality and updates h->dev[] to reflect that reality.
  728. */
  729. int i, entry, device_change, changes = 0;
  730. struct hpsa_scsi_dev_t *csd;
  731. unsigned long flags;
  732. struct hpsa_scsi_dev_t **added, **removed;
  733. int nadded, nremoved;
  734. struct Scsi_Host *sh = NULL;
  735. added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
  736. removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
  737. if (!added || !removed) {
  738. dev_warn(&h->pdev->dev, "out of memory in "
  739. "adjust_hpsa_scsi_table\n");
  740. goto free_and_out;
  741. }
  742. spin_lock_irqsave(&h->devlock, flags);
  743. /* find any devices in h->dev[] that are not in
  744. * sd[] and remove them from h->dev[], and for any
  745. * devices which have changed, remove the old device
  746. * info and add the new device info.
  747. */
  748. i = 0;
  749. nremoved = 0;
  750. nadded = 0;
  751. while (i < h->ndevices) {
  752. csd = h->dev[i];
  753. device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
  754. if (device_change == DEVICE_NOT_FOUND) {
  755. changes++;
  756. hpsa_scsi_remove_entry(h, hostno, i,
  757. removed, &nremoved);
  758. continue; /* remove ^^^, hence i not incremented */
  759. } else if (device_change == DEVICE_CHANGED) {
  760. changes++;
  761. hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
  762. added, &nadded, removed, &nremoved);
  763. /* Set it to NULL to prevent it from being freed
  764. * at the bottom of hpsa_update_scsi_devices()
  765. */
  766. sd[entry] = NULL;
  767. }
  768. i++;
  769. }
  770. /* Now, make sure every device listed in sd[] is also
  771. * listed in h->dev[], adding them if they aren't found
  772. */
  773. for (i = 0; i < nsds; i++) {
  774. if (!sd[i]) /* if already added above. */
  775. continue;
  776. device_change = hpsa_scsi_find_entry(sd[i], h->dev,
  777. h->ndevices, &entry);
  778. if (device_change == DEVICE_NOT_FOUND) {
  779. changes++;
  780. if (hpsa_scsi_add_entry(h, hostno, sd[i],
  781. added, &nadded) != 0)
  782. break;
  783. sd[i] = NULL; /* prevent from being freed later. */
  784. } else if (device_change == DEVICE_CHANGED) {
  785. /* should never happen... */
  786. changes++;
  787. dev_warn(&h->pdev->dev,
  788. "device unexpectedly changed.\n");
  789. /* but if it does happen, we just ignore that device */
  790. }
  791. }
  792. spin_unlock_irqrestore(&h->devlock, flags);
  793. /* Don't notify scsi mid layer of any changes the first time through
  794. * (or if there are no changes) scsi_scan_host will do it later the
  795. * first time through.
  796. */
  797. if (hostno == -1 || !changes)
  798. goto free_and_out;
  799. sh = h->scsi_host;
  800. /* Notify scsi mid layer of any removed devices */
  801. for (i = 0; i < nremoved; i++) {
  802. struct scsi_device *sdev =
  803. scsi_device_lookup(sh, removed[i]->bus,
  804. removed[i]->target, removed[i]->lun);
  805. if (sdev != NULL) {
  806. scsi_remove_device(sdev);
  807. scsi_device_put(sdev);
  808. } else {
  809. /* We don't expect to get here.
  810. * future cmds to this device will get selection
  811. * timeout as if the device was gone.
  812. */
  813. dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
  814. " for removal.", hostno, removed[i]->bus,
  815. removed[i]->target, removed[i]->lun);
  816. }
  817. kfree(removed[i]);
  818. removed[i] = NULL;
  819. }
  820. /* Notify scsi mid layer of any added devices */
  821. for (i = 0; i < nadded; i++) {
  822. if (scsi_add_device(sh, added[i]->bus,
  823. added[i]->target, added[i]->lun) == 0)
  824. continue;
  825. dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
  826. "device not added.\n", hostno, added[i]->bus,
  827. added[i]->target, added[i]->lun);
  828. /* now we have to remove it from h->dev,
  829. * since it didn't get added to scsi mid layer
  830. */
  831. fixup_botched_add(h, added[i]);
  832. }
  833. free_and_out:
  834. kfree(added);
  835. kfree(removed);
  836. }
  837. /*
  838. * Lookup bus/target/lun and retrun corresponding struct hpsa_scsi_dev_t *
  839. * Assume's h->devlock is held.
  840. */
  841. static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
  842. int bus, int target, int lun)
  843. {
  844. int i;
  845. struct hpsa_scsi_dev_t *sd;
  846. for (i = 0; i < h->ndevices; i++) {
  847. sd = h->dev[i];
  848. if (sd->bus == bus && sd->target == target && sd->lun == lun)
  849. return sd;
  850. }
  851. return NULL;
  852. }
  853. /* link sdev->hostdata to our per-device structure. */
  854. static int hpsa_slave_alloc(struct scsi_device *sdev)
  855. {
  856. struct hpsa_scsi_dev_t *sd;
  857. unsigned long flags;
  858. struct ctlr_info *h;
  859. h = sdev_to_hba(sdev);
  860. spin_lock_irqsave(&h->devlock, flags);
  861. sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
  862. sdev_id(sdev), sdev->lun);
  863. if (sd != NULL)
  864. sdev->hostdata = sd;
  865. spin_unlock_irqrestore(&h->devlock, flags);
  866. return 0;
  867. }
  868. static void hpsa_slave_destroy(struct scsi_device *sdev)
  869. {
  870. /* nothing to do. */
  871. }
  872. static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
  873. {
  874. int i;
  875. if (!h->cmd_sg_list)
  876. return;
  877. for (i = 0; i < h->nr_cmds; i++) {
  878. kfree(h->cmd_sg_list[i]);
  879. h->cmd_sg_list[i] = NULL;
  880. }
  881. kfree(h->cmd_sg_list);
  882. h->cmd_sg_list = NULL;
  883. }
  884. static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
  885. {
  886. int i;
  887. if (h->chainsize <= 0)
  888. return 0;
  889. h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
  890. GFP_KERNEL);
  891. if (!h->cmd_sg_list)
  892. return -ENOMEM;
  893. for (i = 0; i < h->nr_cmds; i++) {
  894. h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
  895. h->chainsize, GFP_KERNEL);
  896. if (!h->cmd_sg_list[i])
  897. goto clean;
  898. }
  899. return 0;
  900. clean:
  901. hpsa_free_sg_chain_blocks(h);
  902. return -ENOMEM;
  903. }
  904. static void hpsa_map_sg_chain_block(struct ctlr_info *h,
  905. struct CommandList *c)
  906. {
  907. struct SGDescriptor *chain_sg, *chain_block;
  908. u64 temp64;
  909. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  910. chain_block = h->cmd_sg_list[c->cmdindex];
  911. chain_sg->Ext = HPSA_SG_CHAIN;
  912. chain_sg->Len = sizeof(*chain_sg) *
  913. (c->Header.SGTotal - h->max_cmd_sg_entries);
  914. temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
  915. PCI_DMA_TODEVICE);
  916. chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
  917. chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
  918. }
  919. static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
  920. struct CommandList *c)
  921. {
  922. struct SGDescriptor *chain_sg;
  923. union u64bit temp64;
  924. if (c->Header.SGTotal <= h->max_cmd_sg_entries)
  925. return;
  926. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  927. temp64.val32.lower = chain_sg->Addr.lower;
  928. temp64.val32.upper = chain_sg->Addr.upper;
  929. pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
  930. }
  931. static void complete_scsi_command(struct CommandList *cp)
  932. {
  933. struct scsi_cmnd *cmd;
  934. struct ctlr_info *h;
  935. struct ErrorInfo *ei;
  936. unsigned char sense_key;
  937. unsigned char asc; /* additional sense code */
  938. unsigned char ascq; /* additional sense code qualifier */
  939. unsigned long sense_data_size;
  940. ei = cp->err_info;
  941. cmd = (struct scsi_cmnd *) cp->scsi_cmd;
  942. h = cp->h;
  943. scsi_dma_unmap(cmd); /* undo the DMA mappings */
  944. if (cp->Header.SGTotal > h->max_cmd_sg_entries)
  945. hpsa_unmap_sg_chain_block(h, cp);
  946. cmd->result = (DID_OK << 16); /* host byte */
  947. cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
  948. cmd->result |= ei->ScsiStatus;
  949. /* copy the sense data whether we need to or not. */
  950. if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
  951. sense_data_size = SCSI_SENSE_BUFFERSIZE;
  952. else
  953. sense_data_size = sizeof(ei->SenseInfo);
  954. if (ei->SenseLen < sense_data_size)
  955. sense_data_size = ei->SenseLen;
  956. memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
  957. scsi_set_resid(cmd, ei->ResidualCnt);
  958. if (ei->CommandStatus == 0) {
  959. cmd->scsi_done(cmd);
  960. cmd_free(h, cp);
  961. return;
  962. }
  963. /* an error has occurred */
  964. switch (ei->CommandStatus) {
  965. case CMD_TARGET_STATUS:
  966. if (ei->ScsiStatus) {
  967. /* Get sense key */
  968. sense_key = 0xf & ei->SenseInfo[2];
  969. /* Get additional sense code */
  970. asc = ei->SenseInfo[12];
  971. /* Get addition sense code qualifier */
  972. ascq = ei->SenseInfo[13];
  973. }
  974. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
  975. if (check_for_unit_attention(h, cp)) {
  976. cmd->result = DID_SOFT_ERROR << 16;
  977. break;
  978. }
  979. if (sense_key == ILLEGAL_REQUEST) {
  980. /*
  981. * SCSI REPORT_LUNS is commonly unsupported on
  982. * Smart Array. Suppress noisy complaint.
  983. */
  984. if (cp->Request.CDB[0] == REPORT_LUNS)
  985. break;
  986. /* If ASC/ASCQ indicate Logical Unit
  987. * Not Supported condition,
  988. */
  989. if ((asc == 0x25) && (ascq == 0x0)) {
  990. dev_warn(&h->pdev->dev, "cp %p "
  991. "has check condition\n", cp);
  992. break;
  993. }
  994. }
  995. if (sense_key == NOT_READY) {
  996. /* If Sense is Not Ready, Logical Unit
  997. * Not ready, Manual Intervention
  998. * required
  999. */
  1000. if ((asc == 0x04) && (ascq == 0x03)) {
  1001. dev_warn(&h->pdev->dev, "cp %p "
  1002. "has check condition: unit "
  1003. "not ready, manual "
  1004. "intervention required\n", cp);
  1005. break;
  1006. }
  1007. }
  1008. if (sense_key == ABORTED_COMMAND) {
  1009. /* Aborted command is retryable */
  1010. dev_warn(&h->pdev->dev, "cp %p "
  1011. "has check condition: aborted command: "
  1012. "ASC: 0x%x, ASCQ: 0x%x\n",
  1013. cp, asc, ascq);
  1014. cmd->result = DID_SOFT_ERROR << 16;
  1015. break;
  1016. }
  1017. /* Must be some other type of check condition */
  1018. dev_warn(&h->pdev->dev, "cp %p has check condition: "
  1019. "unknown type: "
  1020. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  1021. "Returning result: 0x%x, "
  1022. "cmd=[%02x %02x %02x %02x %02x "
  1023. "%02x %02x %02x %02x %02x %02x "
  1024. "%02x %02x %02x %02x %02x]\n",
  1025. cp, sense_key, asc, ascq,
  1026. cmd->result,
  1027. cmd->cmnd[0], cmd->cmnd[1],
  1028. cmd->cmnd[2], cmd->cmnd[3],
  1029. cmd->cmnd[4], cmd->cmnd[5],
  1030. cmd->cmnd[6], cmd->cmnd[7],
  1031. cmd->cmnd[8], cmd->cmnd[9],
  1032. cmd->cmnd[10], cmd->cmnd[11],
  1033. cmd->cmnd[12], cmd->cmnd[13],
  1034. cmd->cmnd[14], cmd->cmnd[15]);
  1035. break;
  1036. }
  1037. /* Problem was not a check condition
  1038. * Pass it up to the upper layers...
  1039. */
  1040. if (ei->ScsiStatus) {
  1041. dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
  1042. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  1043. "Returning result: 0x%x\n",
  1044. cp, ei->ScsiStatus,
  1045. sense_key, asc, ascq,
  1046. cmd->result);
  1047. } else { /* scsi status is zero??? How??? */
  1048. dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
  1049. "Returning no connection.\n", cp),
  1050. /* Ordinarily, this case should never happen,
  1051. * but there is a bug in some released firmware
  1052. * revisions that allows it to happen if, for
  1053. * example, a 4100 backplane loses power and
  1054. * the tape drive is in it. We assume that
  1055. * it's a fatal error of some kind because we
  1056. * can't show that it wasn't. We will make it
  1057. * look like selection timeout since that is
  1058. * the most common reason for this to occur,
  1059. * and it's severe enough.
  1060. */
  1061. cmd->result = DID_NO_CONNECT << 16;
  1062. }
  1063. break;
  1064. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  1065. break;
  1066. case CMD_DATA_OVERRUN:
  1067. dev_warn(&h->pdev->dev, "cp %p has"
  1068. " completed with data overrun "
  1069. "reported\n", cp);
  1070. break;
  1071. case CMD_INVALID: {
  1072. /* print_bytes(cp, sizeof(*cp), 1, 0);
  1073. print_cmd(cp); */
  1074. /* We get CMD_INVALID if you address a non-existent device
  1075. * instead of a selection timeout (no response). You will
  1076. * see this if you yank out a drive, then try to access it.
  1077. * This is kind of a shame because it means that any other
  1078. * CMD_INVALID (e.g. driver bug) will get interpreted as a
  1079. * missing target. */
  1080. cmd->result = DID_NO_CONNECT << 16;
  1081. }
  1082. break;
  1083. case CMD_PROTOCOL_ERR:
  1084. dev_warn(&h->pdev->dev, "cp %p has "
  1085. "protocol error \n", cp);
  1086. break;
  1087. case CMD_HARDWARE_ERR:
  1088. cmd->result = DID_ERROR << 16;
  1089. dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
  1090. break;
  1091. case CMD_CONNECTION_LOST:
  1092. cmd->result = DID_ERROR << 16;
  1093. dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
  1094. break;
  1095. case CMD_ABORTED:
  1096. cmd->result = DID_ABORT << 16;
  1097. dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
  1098. cp, ei->ScsiStatus);
  1099. break;
  1100. case CMD_ABORT_FAILED:
  1101. cmd->result = DID_ERROR << 16;
  1102. dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
  1103. break;
  1104. case CMD_UNSOLICITED_ABORT:
  1105. cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
  1106. dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
  1107. "abort\n", cp);
  1108. break;
  1109. case CMD_TIMEOUT:
  1110. cmd->result = DID_TIME_OUT << 16;
  1111. dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
  1112. break;
  1113. case CMD_UNABORTABLE:
  1114. cmd->result = DID_ERROR << 16;
  1115. dev_warn(&h->pdev->dev, "Command unabortable\n");
  1116. break;
  1117. default:
  1118. cmd->result = DID_ERROR << 16;
  1119. dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
  1120. cp, ei->CommandStatus);
  1121. }
  1122. cmd->scsi_done(cmd);
  1123. cmd_free(h, cp);
  1124. }
  1125. static int hpsa_scsi_detect(struct ctlr_info *h)
  1126. {
  1127. struct Scsi_Host *sh;
  1128. int error;
  1129. sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
  1130. if (sh == NULL)
  1131. goto fail;
  1132. sh->io_port = 0;
  1133. sh->n_io_port = 0;
  1134. sh->this_id = -1;
  1135. sh->max_channel = 3;
  1136. sh->max_cmd_len = MAX_COMMAND_SIZE;
  1137. sh->max_lun = HPSA_MAX_LUN;
  1138. sh->max_id = HPSA_MAX_LUN;
  1139. sh->can_queue = h->nr_cmds;
  1140. sh->cmd_per_lun = h->nr_cmds;
  1141. sh->sg_tablesize = h->maxsgentries;
  1142. h->scsi_host = sh;
  1143. sh->hostdata[0] = (unsigned long) h;
  1144. sh->irq = h->intr[h->intr_mode];
  1145. sh->unique_id = sh->irq;
  1146. error = scsi_add_host(sh, &h->pdev->dev);
  1147. if (error)
  1148. goto fail_host_put;
  1149. scsi_scan_host(sh);
  1150. return 0;
  1151. fail_host_put:
  1152. dev_err(&h->pdev->dev, "hpsa_scsi_detect: scsi_add_host"
  1153. " failed for controller %d\n", h->ctlr);
  1154. scsi_host_put(sh);
  1155. return error;
  1156. fail:
  1157. dev_err(&h->pdev->dev, "hpsa_scsi_detect: scsi_host_alloc"
  1158. " failed for controller %d\n", h->ctlr);
  1159. return -ENOMEM;
  1160. }
  1161. static void hpsa_pci_unmap(struct pci_dev *pdev,
  1162. struct CommandList *c, int sg_used, int data_direction)
  1163. {
  1164. int i;
  1165. union u64bit addr64;
  1166. for (i = 0; i < sg_used; i++) {
  1167. addr64.val32.lower = c->SG[i].Addr.lower;
  1168. addr64.val32.upper = c->SG[i].Addr.upper;
  1169. pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
  1170. data_direction);
  1171. }
  1172. }
  1173. static void hpsa_map_one(struct pci_dev *pdev,
  1174. struct CommandList *cp,
  1175. unsigned char *buf,
  1176. size_t buflen,
  1177. int data_direction)
  1178. {
  1179. u64 addr64;
  1180. if (buflen == 0 || data_direction == PCI_DMA_NONE) {
  1181. cp->Header.SGList = 0;
  1182. cp->Header.SGTotal = 0;
  1183. return;
  1184. }
  1185. addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
  1186. cp->SG[0].Addr.lower =
  1187. (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
  1188. cp->SG[0].Addr.upper =
  1189. (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
  1190. cp->SG[0].Len = buflen;
  1191. cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
  1192. cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
  1193. }
  1194. static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
  1195. struct CommandList *c)
  1196. {
  1197. DECLARE_COMPLETION_ONSTACK(wait);
  1198. c->waiting = &wait;
  1199. enqueue_cmd_and_start_io(h, c);
  1200. wait_for_completion(&wait);
  1201. }
  1202. static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
  1203. struct CommandList *c)
  1204. {
  1205. unsigned long flags;
  1206. /* If controller lockup detected, fake a hardware error. */
  1207. spin_lock_irqsave(&h->lock, flags);
  1208. if (unlikely(h->lockup_detected)) {
  1209. spin_unlock_irqrestore(&h->lock, flags);
  1210. c->err_info->CommandStatus = CMD_HARDWARE_ERR;
  1211. } else {
  1212. spin_unlock_irqrestore(&h->lock, flags);
  1213. hpsa_scsi_do_simple_cmd_core(h, c);
  1214. }
  1215. }
  1216. static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
  1217. struct CommandList *c, int data_direction)
  1218. {
  1219. int retry_count = 0;
  1220. do {
  1221. memset(c->err_info, 0, sizeof(*c->err_info));
  1222. hpsa_scsi_do_simple_cmd_core(h, c);
  1223. retry_count++;
  1224. } while (check_for_unit_attention(h, c) && retry_count <= 3);
  1225. hpsa_pci_unmap(h->pdev, c, 1, data_direction);
  1226. }
  1227. static void hpsa_scsi_interpret_error(struct CommandList *cp)
  1228. {
  1229. struct ErrorInfo *ei;
  1230. struct device *d = &cp->h->pdev->dev;
  1231. ei = cp->err_info;
  1232. switch (ei->CommandStatus) {
  1233. case CMD_TARGET_STATUS:
  1234. dev_warn(d, "cmd %p has completed with errors\n", cp);
  1235. dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
  1236. ei->ScsiStatus);
  1237. if (ei->ScsiStatus == 0)
  1238. dev_warn(d, "SCSI status is abnormally zero. "
  1239. "(probably indicates selection timeout "
  1240. "reported incorrectly due to a known "
  1241. "firmware bug, circa July, 2001.)\n");
  1242. break;
  1243. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  1244. dev_info(d, "UNDERRUN\n");
  1245. break;
  1246. case CMD_DATA_OVERRUN:
  1247. dev_warn(d, "cp %p has completed with data overrun\n", cp);
  1248. break;
  1249. case CMD_INVALID: {
  1250. /* controller unfortunately reports SCSI passthru's
  1251. * to non-existent targets as invalid commands.
  1252. */
  1253. dev_warn(d, "cp %p is reported invalid (probably means "
  1254. "target device no longer present)\n", cp);
  1255. /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
  1256. print_cmd(cp); */
  1257. }
  1258. break;
  1259. case CMD_PROTOCOL_ERR:
  1260. dev_warn(d, "cp %p has protocol error \n", cp);
  1261. break;
  1262. case CMD_HARDWARE_ERR:
  1263. /* cmd->result = DID_ERROR << 16; */
  1264. dev_warn(d, "cp %p had hardware error\n", cp);
  1265. break;
  1266. case CMD_CONNECTION_LOST:
  1267. dev_warn(d, "cp %p had connection lost\n", cp);
  1268. break;
  1269. case CMD_ABORTED:
  1270. dev_warn(d, "cp %p was aborted\n", cp);
  1271. break;
  1272. case CMD_ABORT_FAILED:
  1273. dev_warn(d, "cp %p reports abort failed\n", cp);
  1274. break;
  1275. case CMD_UNSOLICITED_ABORT:
  1276. dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
  1277. break;
  1278. case CMD_TIMEOUT:
  1279. dev_warn(d, "cp %p timed out\n", cp);
  1280. break;
  1281. case CMD_UNABORTABLE:
  1282. dev_warn(d, "Command unabortable\n");
  1283. break;
  1284. default:
  1285. dev_warn(d, "cp %p returned unknown status %x\n", cp,
  1286. ei->CommandStatus);
  1287. }
  1288. }
  1289. static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
  1290. unsigned char page, unsigned char *buf,
  1291. unsigned char bufsize)
  1292. {
  1293. int rc = IO_OK;
  1294. struct CommandList *c;
  1295. struct ErrorInfo *ei;
  1296. c = cmd_special_alloc(h);
  1297. if (c == NULL) { /* trouble... */
  1298. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1299. return -ENOMEM;
  1300. }
  1301. fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, page, scsi3addr, TYPE_CMD);
  1302. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
  1303. ei = c->err_info;
  1304. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  1305. hpsa_scsi_interpret_error(c);
  1306. rc = -1;
  1307. }
  1308. cmd_special_free(h, c);
  1309. return rc;
  1310. }
  1311. static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr)
  1312. {
  1313. int rc = IO_OK;
  1314. struct CommandList *c;
  1315. struct ErrorInfo *ei;
  1316. c = cmd_special_alloc(h);
  1317. if (c == NULL) { /* trouble... */
  1318. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1319. return -ENOMEM;
  1320. }
  1321. fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, scsi3addr, TYPE_MSG);
  1322. hpsa_scsi_do_simple_cmd_core(h, c);
  1323. /* no unmap needed here because no data xfer. */
  1324. ei = c->err_info;
  1325. if (ei->CommandStatus != 0) {
  1326. hpsa_scsi_interpret_error(c);
  1327. rc = -1;
  1328. }
  1329. cmd_special_free(h, c);
  1330. return rc;
  1331. }
  1332. static void hpsa_get_raid_level(struct ctlr_info *h,
  1333. unsigned char *scsi3addr, unsigned char *raid_level)
  1334. {
  1335. int rc;
  1336. unsigned char *buf;
  1337. *raid_level = RAID_UNKNOWN;
  1338. buf = kzalloc(64, GFP_KERNEL);
  1339. if (!buf)
  1340. return;
  1341. rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
  1342. if (rc == 0)
  1343. *raid_level = buf[8];
  1344. if (*raid_level > RAID_UNKNOWN)
  1345. *raid_level = RAID_UNKNOWN;
  1346. kfree(buf);
  1347. return;
  1348. }
  1349. /* Get the device id from inquiry page 0x83 */
  1350. static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
  1351. unsigned char *device_id, int buflen)
  1352. {
  1353. int rc;
  1354. unsigned char *buf;
  1355. if (buflen > 16)
  1356. buflen = 16;
  1357. buf = kzalloc(64, GFP_KERNEL);
  1358. if (!buf)
  1359. return -1;
  1360. rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
  1361. if (rc == 0)
  1362. memcpy(device_id, &buf[8], buflen);
  1363. kfree(buf);
  1364. return rc != 0;
  1365. }
  1366. static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
  1367. struct ReportLUNdata *buf, int bufsize,
  1368. int extended_response)
  1369. {
  1370. int rc = IO_OK;
  1371. struct CommandList *c;
  1372. unsigned char scsi3addr[8];
  1373. struct ErrorInfo *ei;
  1374. c = cmd_special_alloc(h);
  1375. if (c == NULL) { /* trouble... */
  1376. dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1377. return -1;
  1378. }
  1379. /* address the controller */
  1380. memset(scsi3addr, 0, sizeof(scsi3addr));
  1381. fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
  1382. buf, bufsize, 0, scsi3addr, TYPE_CMD);
  1383. if (extended_response)
  1384. c->Request.CDB[1] = extended_response;
  1385. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
  1386. ei = c->err_info;
  1387. if (ei->CommandStatus != 0 &&
  1388. ei->CommandStatus != CMD_DATA_UNDERRUN) {
  1389. hpsa_scsi_interpret_error(c);
  1390. rc = -1;
  1391. }
  1392. cmd_special_free(h, c);
  1393. return rc;
  1394. }
  1395. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  1396. struct ReportLUNdata *buf,
  1397. int bufsize, int extended_response)
  1398. {
  1399. return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
  1400. }
  1401. static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
  1402. struct ReportLUNdata *buf, int bufsize)
  1403. {
  1404. return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
  1405. }
  1406. static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
  1407. int bus, int target, int lun)
  1408. {
  1409. device->bus = bus;
  1410. device->target = target;
  1411. device->lun = lun;
  1412. }
  1413. static int hpsa_update_device_info(struct ctlr_info *h,
  1414. unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
  1415. unsigned char *is_OBDR_device)
  1416. {
  1417. #define OBDR_SIG_OFFSET 43
  1418. #define OBDR_TAPE_SIG "$DR-10"
  1419. #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
  1420. #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
  1421. unsigned char *inq_buff;
  1422. unsigned char *obdr_sig;
  1423. inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
  1424. if (!inq_buff)
  1425. goto bail_out;
  1426. /* Do an inquiry to the device to see what it is. */
  1427. if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
  1428. (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
  1429. /* Inquiry failed (msg printed already) */
  1430. dev_err(&h->pdev->dev,
  1431. "hpsa_update_device_info: inquiry failed\n");
  1432. goto bail_out;
  1433. }
  1434. this_device->devtype = (inq_buff[0] & 0x1f);
  1435. memcpy(this_device->scsi3addr, scsi3addr, 8);
  1436. memcpy(this_device->vendor, &inq_buff[8],
  1437. sizeof(this_device->vendor));
  1438. memcpy(this_device->model, &inq_buff[16],
  1439. sizeof(this_device->model));
  1440. memset(this_device->device_id, 0,
  1441. sizeof(this_device->device_id));
  1442. hpsa_get_device_id(h, scsi3addr, this_device->device_id,
  1443. sizeof(this_device->device_id));
  1444. if (this_device->devtype == TYPE_DISK &&
  1445. is_logical_dev_addr_mode(scsi3addr))
  1446. hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
  1447. else
  1448. this_device->raid_level = RAID_UNKNOWN;
  1449. if (is_OBDR_device) {
  1450. /* See if this is a One-Button-Disaster-Recovery device
  1451. * by looking for "$DR-10" at offset 43 in inquiry data.
  1452. */
  1453. obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
  1454. *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
  1455. strncmp(obdr_sig, OBDR_TAPE_SIG,
  1456. OBDR_SIG_LEN) == 0);
  1457. }
  1458. kfree(inq_buff);
  1459. return 0;
  1460. bail_out:
  1461. kfree(inq_buff);
  1462. return 1;
  1463. }
  1464. static unsigned char *msa2xxx_model[] = {
  1465. "MSA2012",
  1466. "MSA2024",
  1467. "MSA2312",
  1468. "MSA2324",
  1469. "P2000 G3 SAS",
  1470. NULL,
  1471. };
  1472. static int is_msa2xxx(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
  1473. {
  1474. int i;
  1475. for (i = 0; msa2xxx_model[i]; i++)
  1476. if (strncmp(device->model, msa2xxx_model[i],
  1477. strlen(msa2xxx_model[i])) == 0)
  1478. return 1;
  1479. return 0;
  1480. }
  1481. /* Helper function to assign bus, target, lun mapping of devices.
  1482. * Puts non-msa2xxx logical volumes on bus 0, msa2xxx logical
  1483. * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
  1484. * Logical drive target and lun are assigned at this time, but
  1485. * physical device lun and target assignment are deferred (assigned
  1486. * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
  1487. */
  1488. static void figure_bus_target_lun(struct ctlr_info *h,
  1489. u8 *lunaddrbytes, int *bus, int *target, int *lun,
  1490. struct hpsa_scsi_dev_t *device)
  1491. {
  1492. u32 lunid;
  1493. if (is_logical_dev_addr_mode(lunaddrbytes)) {
  1494. /* logical device */
  1495. if (unlikely(is_scsi_rev_5(h))) {
  1496. /* p1210m, logical drives lun assignments
  1497. * match SCSI REPORT LUNS data.
  1498. */
  1499. lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
  1500. *bus = 0;
  1501. *target = 0;
  1502. *lun = (lunid & 0x3fff) + 1;
  1503. } else {
  1504. /* not p1210m... */
  1505. lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
  1506. if (is_msa2xxx(h, device)) {
  1507. /* msa2xxx way, put logicals on bus 1
  1508. * and match target/lun numbers box
  1509. * reports.
  1510. */
  1511. *bus = 1;
  1512. *target = (lunid >> 16) & 0x3fff;
  1513. *lun = lunid & 0x00ff;
  1514. } else {
  1515. /* Traditional smart array way. */
  1516. *bus = 0;
  1517. *lun = 0;
  1518. *target = lunid & 0x3fff;
  1519. }
  1520. }
  1521. } else {
  1522. /* physical device */
  1523. if (is_hba_lunid(lunaddrbytes))
  1524. if (unlikely(is_scsi_rev_5(h))) {
  1525. *bus = 0; /* put p1210m ctlr at 0,0,0 */
  1526. *target = 0;
  1527. *lun = 0;
  1528. return;
  1529. } else
  1530. *bus = 3; /* traditional smartarray */
  1531. else
  1532. *bus = 2; /* physical disk */
  1533. *target = -1;
  1534. *lun = -1; /* we will fill these in later. */
  1535. }
  1536. }
  1537. /*
  1538. * If there is no lun 0 on a target, linux won't find any devices.
  1539. * For the MSA2xxx boxes, we have to manually detect the enclosure
  1540. * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
  1541. * it for some reason. *tmpdevice is the target we're adding,
  1542. * this_device is a pointer into the current element of currentsd[]
  1543. * that we're building up in update_scsi_devices(), below.
  1544. * lunzerobits is a bitmap that tracks which targets already have a
  1545. * lun 0 assigned.
  1546. * Returns 1 if an enclosure was added, 0 if not.
  1547. */
  1548. static int add_msa2xxx_enclosure_device(struct ctlr_info *h,
  1549. struct hpsa_scsi_dev_t *tmpdevice,
  1550. struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
  1551. int bus, int target, int lun, unsigned long lunzerobits[],
  1552. int *nmsa2xxx_enclosures)
  1553. {
  1554. unsigned char scsi3addr[8];
  1555. if (test_bit(target, lunzerobits))
  1556. return 0; /* There is already a lun 0 on this target. */
  1557. if (!is_logical_dev_addr_mode(lunaddrbytes))
  1558. return 0; /* It's the logical targets that may lack lun 0. */
  1559. if (!is_msa2xxx(h, tmpdevice))
  1560. return 0; /* It's only the MSA2xxx that have this problem. */
  1561. if (lun == 0) /* if lun is 0, then obviously we have a lun 0. */
  1562. return 0;
  1563. memset(scsi3addr, 0, 8);
  1564. scsi3addr[3] = target;
  1565. if (is_hba_lunid(scsi3addr))
  1566. return 0; /* Don't add the RAID controller here. */
  1567. if (is_scsi_rev_5(h))
  1568. return 0; /* p1210m doesn't need to do this. */
  1569. if (*nmsa2xxx_enclosures >= MAX_MSA2XXX_ENCLOSURES) {
  1570. dev_warn(&h->pdev->dev, "Maximum number of MSA2XXX "
  1571. "enclosures exceeded. Check your hardware "
  1572. "configuration.");
  1573. return 0;
  1574. }
  1575. if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
  1576. return 0;
  1577. (*nmsa2xxx_enclosures)++;
  1578. hpsa_set_bus_target_lun(this_device, bus, target, 0);
  1579. set_bit(target, lunzerobits);
  1580. return 1;
  1581. }
  1582. /*
  1583. * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
  1584. * logdev. The number of luns in physdev and logdev are returned in
  1585. * *nphysicals and *nlogicals, respectively.
  1586. * Returns 0 on success, -1 otherwise.
  1587. */
  1588. static int hpsa_gather_lun_info(struct ctlr_info *h,
  1589. int reportlunsize,
  1590. struct ReportLUNdata *physdev, u32 *nphysicals,
  1591. struct ReportLUNdata *logdev, u32 *nlogicals)
  1592. {
  1593. if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize, 0)) {
  1594. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  1595. return -1;
  1596. }
  1597. *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 8;
  1598. if (*nphysicals > HPSA_MAX_PHYS_LUN) {
  1599. dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
  1600. " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  1601. *nphysicals - HPSA_MAX_PHYS_LUN);
  1602. *nphysicals = HPSA_MAX_PHYS_LUN;
  1603. }
  1604. if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
  1605. dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
  1606. return -1;
  1607. }
  1608. *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
  1609. /* Reject Logicals in excess of our max capability. */
  1610. if (*nlogicals > HPSA_MAX_LUN) {
  1611. dev_warn(&h->pdev->dev,
  1612. "maximum logical LUNs (%d) exceeded. "
  1613. "%d LUNs ignored.\n", HPSA_MAX_LUN,
  1614. *nlogicals - HPSA_MAX_LUN);
  1615. *nlogicals = HPSA_MAX_LUN;
  1616. }
  1617. if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
  1618. dev_warn(&h->pdev->dev,
  1619. "maximum logical + physical LUNs (%d) exceeded. "
  1620. "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  1621. *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
  1622. *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
  1623. }
  1624. return 0;
  1625. }
  1626. u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
  1627. int nphysicals, int nlogicals, struct ReportLUNdata *physdev_list,
  1628. struct ReportLUNdata *logdev_list)
  1629. {
  1630. /* Helper function, figure out where the LUN ID info is coming from
  1631. * given index i, lists of physical and logical devices, where in
  1632. * the list the raid controller is supposed to appear (first or last)
  1633. */
  1634. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  1635. int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
  1636. if (i == raid_ctlr_position)
  1637. return RAID_CTLR_LUNID;
  1638. if (i < logicals_start)
  1639. return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
  1640. if (i < last_device)
  1641. return &logdev_list->LUN[i - nphysicals -
  1642. (raid_ctlr_position == 0)][0];
  1643. BUG();
  1644. return NULL;
  1645. }
  1646. static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
  1647. {
  1648. /* the idea here is we could get notified
  1649. * that some devices have changed, so we do a report
  1650. * physical luns and report logical luns cmd, and adjust
  1651. * our list of devices accordingly.
  1652. *
  1653. * The scsi3addr's of devices won't change so long as the
  1654. * adapter is not reset. That means we can rescan and
  1655. * tell which devices we already know about, vs. new
  1656. * devices, vs. disappearing devices.
  1657. */
  1658. struct ReportLUNdata *physdev_list = NULL;
  1659. struct ReportLUNdata *logdev_list = NULL;
  1660. u32 nphysicals = 0;
  1661. u32 nlogicals = 0;
  1662. u32 ndev_allocated = 0;
  1663. struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
  1664. int ncurrent = 0;
  1665. int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 8;
  1666. int i, nmsa2xxx_enclosures, ndevs_to_allocate;
  1667. int bus, target, lun;
  1668. int raid_ctlr_position;
  1669. DECLARE_BITMAP(lunzerobits, HPSA_MAX_TARGETS_PER_CTLR);
  1670. currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
  1671. physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
  1672. logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
  1673. tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
  1674. if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
  1675. dev_err(&h->pdev->dev, "out of memory\n");
  1676. goto out;
  1677. }
  1678. memset(lunzerobits, 0, sizeof(lunzerobits));
  1679. if (hpsa_gather_lun_info(h, reportlunsize, physdev_list, &nphysicals,
  1680. logdev_list, &nlogicals))
  1681. goto out;
  1682. /* We might see up to 32 MSA2xxx enclosures, actually 8 of them
  1683. * but each of them 4 times through different paths. The plus 1
  1684. * is for the RAID controller.
  1685. */
  1686. ndevs_to_allocate = nphysicals + nlogicals + MAX_MSA2XXX_ENCLOSURES + 1;
  1687. /* Allocate the per device structures */
  1688. for (i = 0; i < ndevs_to_allocate; i++) {
  1689. if (i >= HPSA_MAX_DEVICES) {
  1690. dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
  1691. " %d devices ignored.\n", HPSA_MAX_DEVICES,
  1692. ndevs_to_allocate - HPSA_MAX_DEVICES);
  1693. break;
  1694. }
  1695. currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
  1696. if (!currentsd[i]) {
  1697. dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
  1698. __FILE__, __LINE__);
  1699. goto out;
  1700. }
  1701. ndev_allocated++;
  1702. }
  1703. if (unlikely(is_scsi_rev_5(h)))
  1704. raid_ctlr_position = 0;
  1705. else
  1706. raid_ctlr_position = nphysicals + nlogicals;
  1707. /* adjust our table of devices */
  1708. nmsa2xxx_enclosures = 0;
  1709. for (i = 0; i < nphysicals + nlogicals + 1; i++) {
  1710. u8 *lunaddrbytes, is_OBDR = 0;
  1711. /* Figure out where the LUN ID info is coming from */
  1712. lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
  1713. i, nphysicals, nlogicals, physdev_list, logdev_list);
  1714. /* skip masked physical devices. */
  1715. if (lunaddrbytes[3] & 0xC0 &&
  1716. i < nphysicals + (raid_ctlr_position == 0))
  1717. continue;
  1718. /* Get device type, vendor, model, device id */
  1719. if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
  1720. &is_OBDR))
  1721. continue; /* skip it if we can't talk to it. */
  1722. figure_bus_target_lun(h, lunaddrbytes, &bus, &target, &lun,
  1723. tmpdevice);
  1724. this_device = currentsd[ncurrent];
  1725. /*
  1726. * For the msa2xxx boxes, we have to insert a LUN 0 which
  1727. * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
  1728. * is nonetheless an enclosure device there. We have to
  1729. * present that otherwise linux won't find anything if
  1730. * there is no lun 0.
  1731. */
  1732. if (add_msa2xxx_enclosure_device(h, tmpdevice, this_device,
  1733. lunaddrbytes, bus, target, lun, lunzerobits,
  1734. &nmsa2xxx_enclosures)) {
  1735. ncurrent++;
  1736. this_device = currentsd[ncurrent];
  1737. }
  1738. *this_device = *tmpdevice;
  1739. hpsa_set_bus_target_lun(this_device, bus, target, lun);
  1740. switch (this_device->devtype) {
  1741. case TYPE_ROM:
  1742. /* We don't *really* support actual CD-ROM devices,
  1743. * just "One Button Disaster Recovery" tape drive
  1744. * which temporarily pretends to be a CD-ROM drive.
  1745. * So we check that the device is really an OBDR tape
  1746. * device by checking for "$DR-10" in bytes 43-48 of
  1747. * the inquiry data.
  1748. */
  1749. if (is_OBDR)
  1750. ncurrent++;
  1751. break;
  1752. case TYPE_DISK:
  1753. if (i < nphysicals)
  1754. break;
  1755. ncurrent++;
  1756. break;
  1757. case TYPE_TAPE:
  1758. case TYPE_MEDIUM_CHANGER:
  1759. ncurrent++;
  1760. break;
  1761. case TYPE_RAID:
  1762. /* Only present the Smartarray HBA as a RAID controller.
  1763. * If it's a RAID controller other than the HBA itself
  1764. * (an external RAID controller, MSA500 or similar)
  1765. * don't present it.
  1766. */
  1767. if (!is_hba_lunid(lunaddrbytes))
  1768. break;
  1769. ncurrent++;
  1770. break;
  1771. default:
  1772. break;
  1773. }
  1774. if (ncurrent >= HPSA_MAX_DEVICES)
  1775. break;
  1776. }
  1777. adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
  1778. out:
  1779. kfree(tmpdevice);
  1780. for (i = 0; i < ndev_allocated; i++)
  1781. kfree(currentsd[i]);
  1782. kfree(currentsd);
  1783. kfree(physdev_list);
  1784. kfree(logdev_list);
  1785. }
  1786. /* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
  1787. * dma mapping and fills in the scatter gather entries of the
  1788. * hpsa command, cp.
  1789. */
  1790. static int hpsa_scatter_gather(struct ctlr_info *h,
  1791. struct CommandList *cp,
  1792. struct scsi_cmnd *cmd)
  1793. {
  1794. unsigned int len;
  1795. struct scatterlist *sg;
  1796. u64 addr64;
  1797. int use_sg, i, sg_index, chained;
  1798. struct SGDescriptor *curr_sg;
  1799. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  1800. use_sg = scsi_dma_map(cmd);
  1801. if (use_sg < 0)
  1802. return use_sg;
  1803. if (!use_sg)
  1804. goto sglist_finished;
  1805. curr_sg = cp->SG;
  1806. chained = 0;
  1807. sg_index = 0;
  1808. scsi_for_each_sg(cmd, sg, use_sg, i) {
  1809. if (i == h->max_cmd_sg_entries - 1 &&
  1810. use_sg > h->max_cmd_sg_entries) {
  1811. chained = 1;
  1812. curr_sg = h->cmd_sg_list[cp->cmdindex];
  1813. sg_index = 0;
  1814. }
  1815. addr64 = (u64) sg_dma_address(sg);
  1816. len = sg_dma_len(sg);
  1817. curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
  1818. curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
  1819. curr_sg->Len = len;
  1820. curr_sg->Ext = 0; /* we are not chaining */
  1821. curr_sg++;
  1822. }
  1823. if (use_sg + chained > h->maxSG)
  1824. h->maxSG = use_sg + chained;
  1825. if (chained) {
  1826. cp->Header.SGList = h->max_cmd_sg_entries;
  1827. cp->Header.SGTotal = (u16) (use_sg + 1);
  1828. hpsa_map_sg_chain_block(h, cp);
  1829. return 0;
  1830. }
  1831. sglist_finished:
  1832. cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
  1833. cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
  1834. return 0;
  1835. }
  1836. static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
  1837. void (*done)(struct scsi_cmnd *))
  1838. {
  1839. struct ctlr_info *h;
  1840. struct hpsa_scsi_dev_t *dev;
  1841. unsigned char scsi3addr[8];
  1842. struct CommandList *c;
  1843. unsigned long flags;
  1844. /* Get the ptr to our adapter structure out of cmd->host. */
  1845. h = sdev_to_hba(cmd->device);
  1846. dev = cmd->device->hostdata;
  1847. if (!dev) {
  1848. cmd->result = DID_NO_CONNECT << 16;
  1849. done(cmd);
  1850. return 0;
  1851. }
  1852. memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
  1853. spin_lock_irqsave(&h->lock, flags);
  1854. if (unlikely(h->lockup_detected)) {
  1855. spin_unlock_irqrestore(&h->lock, flags);
  1856. cmd->result = DID_ERROR << 16;
  1857. done(cmd);
  1858. return 0;
  1859. }
  1860. /* Need a lock as this is being allocated from the pool */
  1861. c = cmd_alloc(h);
  1862. spin_unlock_irqrestore(&h->lock, flags);
  1863. if (c == NULL) { /* trouble... */
  1864. dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
  1865. return SCSI_MLQUEUE_HOST_BUSY;
  1866. }
  1867. /* Fill in the command list header */
  1868. cmd->scsi_done = done; /* save this for use by completion code */
  1869. /* save c in case we have to abort it */
  1870. cmd->host_scribble = (unsigned char *) c;
  1871. c->cmd_type = CMD_SCSI;
  1872. c->scsi_cmd = cmd;
  1873. c->Header.ReplyQueue = 0; /* unused in simple mode */
  1874. memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
  1875. c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
  1876. c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
  1877. /* Fill in the request block... */
  1878. c->Request.Timeout = 0;
  1879. memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
  1880. BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
  1881. c->Request.CDBLen = cmd->cmd_len;
  1882. memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
  1883. c->Request.Type.Type = TYPE_CMD;
  1884. c->Request.Type.Attribute = ATTR_SIMPLE;
  1885. switch (cmd->sc_data_direction) {
  1886. case DMA_TO_DEVICE:
  1887. c->Request.Type.Direction = XFER_WRITE;
  1888. break;
  1889. case DMA_FROM_DEVICE:
  1890. c->Request.Type.Direction = XFER_READ;
  1891. break;
  1892. case DMA_NONE:
  1893. c->Request.Type.Direction = XFER_NONE;
  1894. break;
  1895. case DMA_BIDIRECTIONAL:
  1896. /* This can happen if a buggy application does a scsi passthru
  1897. * and sets both inlen and outlen to non-zero. ( see
  1898. * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
  1899. */
  1900. c->Request.Type.Direction = XFER_RSVD;
  1901. /* This is technically wrong, and hpsa controllers should
  1902. * reject it with CMD_INVALID, which is the most correct
  1903. * response, but non-fibre backends appear to let it
  1904. * slide by, and give the same results as if this field
  1905. * were set correctly. Either way is acceptable for
  1906. * our purposes here.
  1907. */
  1908. break;
  1909. default:
  1910. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  1911. cmd->sc_data_direction);
  1912. BUG();
  1913. break;
  1914. }
  1915. if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
  1916. cmd_free(h, c);
  1917. return SCSI_MLQUEUE_HOST_BUSY;
  1918. }
  1919. enqueue_cmd_and_start_io(h, c);
  1920. /* the cmd'll come back via intr handler in complete_scsi_command() */
  1921. return 0;
  1922. }
  1923. static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
  1924. static void hpsa_scan_start(struct Scsi_Host *sh)
  1925. {
  1926. struct ctlr_info *h = shost_to_hba(sh);
  1927. unsigned long flags;
  1928. /* wait until any scan already in progress is finished. */
  1929. while (1) {
  1930. spin_lock_irqsave(&h->scan_lock, flags);
  1931. if (h->scan_finished)
  1932. break;
  1933. spin_unlock_irqrestore(&h->scan_lock, flags);
  1934. wait_event(h->scan_wait_queue, h->scan_finished);
  1935. /* Note: We don't need to worry about a race between this
  1936. * thread and driver unload because the midlayer will
  1937. * have incremented the reference count, so unload won't
  1938. * happen if we're in here.
  1939. */
  1940. }
  1941. h->scan_finished = 0; /* mark scan as in progress */
  1942. spin_unlock_irqrestore(&h->scan_lock, flags);
  1943. hpsa_update_scsi_devices(h, h->scsi_host->host_no);
  1944. spin_lock_irqsave(&h->scan_lock, flags);
  1945. h->scan_finished = 1; /* mark scan as finished. */
  1946. wake_up_all(&h->scan_wait_queue);
  1947. spin_unlock_irqrestore(&h->scan_lock, flags);
  1948. }
  1949. static int hpsa_scan_finished(struct Scsi_Host *sh,
  1950. unsigned long elapsed_time)
  1951. {
  1952. struct ctlr_info *h = shost_to_hba(sh);
  1953. unsigned long flags;
  1954. int finished;
  1955. spin_lock_irqsave(&h->scan_lock, flags);
  1956. finished = h->scan_finished;
  1957. spin_unlock_irqrestore(&h->scan_lock, flags);
  1958. return finished;
  1959. }
  1960. static int hpsa_change_queue_depth(struct scsi_device *sdev,
  1961. int qdepth, int reason)
  1962. {
  1963. struct ctlr_info *h = sdev_to_hba(sdev);
  1964. if (reason != SCSI_QDEPTH_DEFAULT)
  1965. return -ENOTSUPP;
  1966. if (qdepth < 1)
  1967. qdepth = 1;
  1968. else
  1969. if (qdepth > h->nr_cmds)
  1970. qdepth = h->nr_cmds;
  1971. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1972. return sdev->queue_depth;
  1973. }
  1974. static void hpsa_unregister_scsi(struct ctlr_info *h)
  1975. {
  1976. /* we are being forcibly unloaded, and may not refuse. */
  1977. scsi_remove_host(h->scsi_host);
  1978. scsi_host_put(h->scsi_host);
  1979. h->scsi_host = NULL;
  1980. }
  1981. static int hpsa_register_scsi(struct ctlr_info *h)
  1982. {
  1983. int rc;
  1984. rc = hpsa_scsi_detect(h);
  1985. if (rc != 0)
  1986. dev_err(&h->pdev->dev, "hpsa_register_scsi: failed"
  1987. " hpsa_scsi_detect(), rc is %d\n", rc);
  1988. return rc;
  1989. }
  1990. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  1991. unsigned char lunaddr[])
  1992. {
  1993. int rc = 0;
  1994. int count = 0;
  1995. int waittime = 1; /* seconds */
  1996. struct CommandList *c;
  1997. c = cmd_special_alloc(h);
  1998. if (!c) {
  1999. dev_warn(&h->pdev->dev, "out of memory in "
  2000. "wait_for_device_to_become_ready.\n");
  2001. return IO_ERROR;
  2002. }
  2003. /* Send test unit ready until device ready, or give up. */
  2004. while (count < HPSA_TUR_RETRY_LIMIT) {
  2005. /* Wait for a bit. do this first, because if we send
  2006. * the TUR right away, the reset will just abort it.
  2007. */
  2008. msleep(1000 * waittime);
  2009. count++;
  2010. /* Increase wait time with each try, up to a point. */
  2011. if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
  2012. waittime = waittime * 2;
  2013. /* Send the Test Unit Ready */
  2014. fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, lunaddr, TYPE_CMD);
  2015. hpsa_scsi_do_simple_cmd_core(h, c);
  2016. /* no unmap needed here because no data xfer. */
  2017. if (c->err_info->CommandStatus == CMD_SUCCESS)
  2018. break;
  2019. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  2020. c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
  2021. (c->err_info->SenseInfo[2] == NO_SENSE ||
  2022. c->err_info->SenseInfo[2] == UNIT_ATTENTION))
  2023. break;
  2024. dev_warn(&h->pdev->dev, "waiting %d secs "
  2025. "for device to become ready.\n", waittime);
  2026. rc = 1; /* device not ready. */
  2027. }
  2028. if (rc)
  2029. dev_warn(&h->pdev->dev, "giving up on device.\n");
  2030. else
  2031. dev_warn(&h->pdev->dev, "device is ready.\n");
  2032. cmd_special_free(h, c);
  2033. return rc;
  2034. }
  2035. /* Need at least one of these error handlers to keep ../scsi/hosts.c from
  2036. * complaining. Doing a host- or bus-reset can't do anything good here.
  2037. */
  2038. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
  2039. {
  2040. int rc;
  2041. struct ctlr_info *h;
  2042. struct hpsa_scsi_dev_t *dev;
  2043. /* find the controller to which the command to be aborted was sent */
  2044. h = sdev_to_hba(scsicmd->device);
  2045. if (h == NULL) /* paranoia */
  2046. return FAILED;
  2047. dev = scsicmd->device->hostdata;
  2048. if (!dev) {
  2049. dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
  2050. "device lookup failed.\n");
  2051. return FAILED;
  2052. }
  2053. dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
  2054. h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
  2055. /* send a reset to the SCSI LUN which the command was sent to */
  2056. rc = hpsa_send_reset(h, dev->scsi3addr);
  2057. if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
  2058. return SUCCESS;
  2059. dev_warn(&h->pdev->dev, "resetting device failed.\n");
  2060. return FAILED;
  2061. }
  2062. /*
  2063. * For operations that cannot sleep, a command block is allocated at init,
  2064. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  2065. * which ones are free or in use. Lock must be held when calling this.
  2066. * cmd_free() is the complement.
  2067. */
  2068. static struct CommandList *cmd_alloc(struct ctlr_info *h)
  2069. {
  2070. struct CommandList *c;
  2071. int i;
  2072. union u64bit temp64;
  2073. dma_addr_t cmd_dma_handle, err_dma_handle;
  2074. do {
  2075. i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
  2076. if (i == h->nr_cmds)
  2077. return NULL;
  2078. } while (test_and_set_bit
  2079. (i & (BITS_PER_LONG - 1),
  2080. h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
  2081. c = h->cmd_pool + i;
  2082. memset(c, 0, sizeof(*c));
  2083. cmd_dma_handle = h->cmd_pool_dhandle
  2084. + i * sizeof(*c);
  2085. c->err_info = h->errinfo_pool + i;
  2086. memset(c->err_info, 0, sizeof(*c->err_info));
  2087. err_dma_handle = h->errinfo_pool_dhandle
  2088. + i * sizeof(*c->err_info);
  2089. h->nr_allocs++;
  2090. c->cmdindex = i;
  2091. INIT_LIST_HEAD(&c->list);
  2092. c->busaddr = (u32) cmd_dma_handle;
  2093. temp64.val = (u64) err_dma_handle;
  2094. c->ErrDesc.Addr.lower = temp64.val32.lower;
  2095. c->ErrDesc.Addr.upper = temp64.val32.upper;
  2096. c->ErrDesc.Len = sizeof(*c->err_info);
  2097. c->h = h;
  2098. return c;
  2099. }
  2100. /* For operations that can wait for kmalloc to possibly sleep,
  2101. * this routine can be called. Lock need not be held to call
  2102. * cmd_special_alloc. cmd_special_free() is the complement.
  2103. */
  2104. static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
  2105. {
  2106. struct CommandList *c;
  2107. union u64bit temp64;
  2108. dma_addr_t cmd_dma_handle, err_dma_handle;
  2109. c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
  2110. if (c == NULL)
  2111. return NULL;
  2112. memset(c, 0, sizeof(*c));
  2113. c->cmdindex = -1;
  2114. c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
  2115. &err_dma_handle);
  2116. if (c->err_info == NULL) {
  2117. pci_free_consistent(h->pdev,
  2118. sizeof(*c), c, cmd_dma_handle);
  2119. return NULL;
  2120. }
  2121. memset(c->err_info, 0, sizeof(*c->err_info));
  2122. INIT_LIST_HEAD(&c->list);
  2123. c->busaddr = (u32) cmd_dma_handle;
  2124. temp64.val = (u64) err_dma_handle;
  2125. c->ErrDesc.Addr.lower = temp64.val32.lower;
  2126. c->ErrDesc.Addr.upper = temp64.val32.upper;
  2127. c->ErrDesc.Len = sizeof(*c->err_info);
  2128. c->h = h;
  2129. return c;
  2130. }
  2131. static void cmd_free(struct ctlr_info *h, struct CommandList *c)
  2132. {
  2133. int i;
  2134. i = c - h->cmd_pool;
  2135. clear_bit(i & (BITS_PER_LONG - 1),
  2136. h->cmd_pool_bits + (i / BITS_PER_LONG));
  2137. h->nr_frees++;
  2138. }
  2139. static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
  2140. {
  2141. union u64bit temp64;
  2142. temp64.val32.lower = c->ErrDesc.Addr.lower;
  2143. temp64.val32.upper = c->ErrDesc.Addr.upper;
  2144. pci_free_consistent(h->pdev, sizeof(*c->err_info),
  2145. c->err_info, (dma_addr_t) temp64.val);
  2146. pci_free_consistent(h->pdev, sizeof(*c),
  2147. c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
  2148. }
  2149. #ifdef CONFIG_COMPAT
  2150. static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
  2151. {
  2152. IOCTL32_Command_struct __user *arg32 =
  2153. (IOCTL32_Command_struct __user *) arg;
  2154. IOCTL_Command_struct arg64;
  2155. IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
  2156. int err;
  2157. u32 cp;
  2158. memset(&arg64, 0, sizeof(arg64));
  2159. err = 0;
  2160. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  2161. sizeof(arg64.LUN_info));
  2162. err |= copy_from_user(&arg64.Request, &arg32->Request,
  2163. sizeof(arg64.Request));
  2164. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  2165. sizeof(arg64.error_info));
  2166. err |= get_user(arg64.buf_size, &arg32->buf_size);
  2167. err |= get_user(cp, &arg32->buf);
  2168. arg64.buf = compat_ptr(cp);
  2169. err |= copy_to_user(p, &arg64, sizeof(arg64));
  2170. if (err)
  2171. return -EFAULT;
  2172. err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
  2173. if (err)
  2174. return err;
  2175. err |= copy_in_user(&arg32->error_info, &p->error_info,
  2176. sizeof(arg32->error_info));
  2177. if (err)
  2178. return -EFAULT;
  2179. return err;
  2180. }
  2181. static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
  2182. int cmd, void *arg)
  2183. {
  2184. BIG_IOCTL32_Command_struct __user *arg32 =
  2185. (BIG_IOCTL32_Command_struct __user *) arg;
  2186. BIG_IOCTL_Command_struct arg64;
  2187. BIG_IOCTL_Command_struct __user *p =
  2188. compat_alloc_user_space(sizeof(arg64));
  2189. int err;
  2190. u32 cp;
  2191. memset(&arg64, 0, sizeof(arg64));
  2192. err = 0;
  2193. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  2194. sizeof(arg64.LUN_info));
  2195. err |= copy_from_user(&arg64.Request, &arg32->Request,
  2196. sizeof(arg64.Request));
  2197. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  2198. sizeof(arg64.error_info));
  2199. err |= get_user(arg64.buf_size, &arg32->buf_size);
  2200. err |= get_user(arg64.malloc_size, &arg32->malloc_size);
  2201. err |= get_user(cp, &arg32->buf);
  2202. arg64.buf = compat_ptr(cp);
  2203. err |= copy_to_user(p, &arg64, sizeof(arg64));
  2204. if (err)
  2205. return -EFAULT;
  2206. err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
  2207. if (err)
  2208. return err;
  2209. err |= copy_in_user(&arg32->error_info, &p->error_info,
  2210. sizeof(arg32->error_info));
  2211. if (err)
  2212. return -EFAULT;
  2213. return err;
  2214. }
  2215. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
  2216. {
  2217. switch (cmd) {
  2218. case CCISS_GETPCIINFO:
  2219. case CCISS_GETINTINFO:
  2220. case CCISS_SETINTINFO:
  2221. case CCISS_GETNODENAME:
  2222. case CCISS_SETNODENAME:
  2223. case CCISS_GETHEARTBEAT:
  2224. case CCISS_GETBUSTYPES:
  2225. case CCISS_GETFIRMVER:
  2226. case CCISS_GETDRIVVER:
  2227. case CCISS_REVALIDVOLS:
  2228. case CCISS_DEREGDISK:
  2229. case CCISS_REGNEWDISK:
  2230. case CCISS_REGNEWD:
  2231. case CCISS_RESCANDISK:
  2232. case CCISS_GETLUNINFO:
  2233. return hpsa_ioctl(dev, cmd, arg);
  2234. case CCISS_PASSTHRU32:
  2235. return hpsa_ioctl32_passthru(dev, cmd, arg);
  2236. case CCISS_BIG_PASSTHRU32:
  2237. return hpsa_ioctl32_big_passthru(dev, cmd, arg);
  2238. default:
  2239. return -ENOIOCTLCMD;
  2240. }
  2241. }
  2242. #endif
  2243. static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
  2244. {
  2245. struct hpsa_pci_info pciinfo;
  2246. if (!argp)
  2247. return -EINVAL;
  2248. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  2249. pciinfo.bus = h->pdev->bus->number;
  2250. pciinfo.dev_fn = h->pdev->devfn;
  2251. pciinfo.board_id = h->board_id;
  2252. if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
  2253. return -EFAULT;
  2254. return 0;
  2255. }
  2256. static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
  2257. {
  2258. DriverVer_type DriverVer;
  2259. unsigned char vmaj, vmin, vsubmin;
  2260. int rc;
  2261. rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
  2262. &vmaj, &vmin, &vsubmin);
  2263. if (rc != 3) {
  2264. dev_info(&h->pdev->dev, "driver version string '%s' "
  2265. "unrecognized.", HPSA_DRIVER_VERSION);
  2266. vmaj = 0;
  2267. vmin = 0;
  2268. vsubmin = 0;
  2269. }
  2270. DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
  2271. if (!argp)
  2272. return -EINVAL;
  2273. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  2274. return -EFAULT;
  2275. return 0;
  2276. }
  2277. static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  2278. {
  2279. IOCTL_Command_struct iocommand;
  2280. struct CommandList *c;
  2281. char *buff = NULL;
  2282. union u64bit temp64;
  2283. if (!argp)
  2284. return -EINVAL;
  2285. if (!capable(CAP_SYS_RAWIO))
  2286. return -EPERM;
  2287. if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
  2288. return -EFAULT;
  2289. if ((iocommand.buf_size < 1) &&
  2290. (iocommand.Request.Type.Direction != XFER_NONE)) {
  2291. return -EINVAL;
  2292. }
  2293. if (iocommand.buf_size > 0) {
  2294. buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
  2295. if (buff == NULL)
  2296. return -EFAULT;
  2297. if (iocommand.Request.Type.Direction == XFER_WRITE) {
  2298. /* Copy the data into the buffer we created */
  2299. if (copy_from_user(buff, iocommand.buf,
  2300. iocommand.buf_size)) {
  2301. kfree(buff);
  2302. return -EFAULT;
  2303. }
  2304. } else {
  2305. memset(buff, 0, iocommand.buf_size);
  2306. }
  2307. }
  2308. c = cmd_special_alloc(h);
  2309. if (c == NULL) {
  2310. kfree(buff);
  2311. return -ENOMEM;
  2312. }
  2313. /* Fill in the command type */
  2314. c->cmd_type = CMD_IOCTL_PEND;
  2315. /* Fill in Command Header */
  2316. c->Header.ReplyQueue = 0; /* unused in simple mode */
  2317. if (iocommand.buf_size > 0) { /* buffer to fill */
  2318. c->Header.SGList = 1;
  2319. c->Header.SGTotal = 1;
  2320. } else { /* no buffers to fill */
  2321. c->Header.SGList = 0;
  2322. c->Header.SGTotal = 0;
  2323. }
  2324. memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
  2325. /* use the kernel address the cmd block for tag */
  2326. c->Header.Tag.lower = c->busaddr;
  2327. /* Fill in Request block */
  2328. memcpy(&c->Request, &iocommand.Request,
  2329. sizeof(c->Request));
  2330. /* Fill in the scatter gather information */
  2331. if (iocommand.buf_size > 0) {
  2332. temp64.val = pci_map_single(h->pdev, buff,
  2333. iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
  2334. c->SG[0].Addr.lower = temp64.val32.lower;
  2335. c->SG[0].Addr.upper = temp64.val32.upper;
  2336. c->SG[0].Len = iocommand.buf_size;
  2337. c->SG[0].Ext = 0; /* we are not chaining*/
  2338. }
  2339. hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
  2340. if (iocommand.buf_size > 0)
  2341. hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
  2342. check_ioctl_unit_attention(h, c);
  2343. /* Copy the error information out */
  2344. memcpy(&iocommand.error_info, c->err_info,
  2345. sizeof(iocommand.error_info));
  2346. if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
  2347. kfree(buff);
  2348. cmd_special_free(h, c);
  2349. return -EFAULT;
  2350. }
  2351. if (iocommand.Request.Type.Direction == XFER_READ &&
  2352. iocommand.buf_size > 0) {
  2353. /* Copy the data out of the buffer we created */
  2354. if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
  2355. kfree(buff);
  2356. cmd_special_free(h, c);
  2357. return -EFAULT;
  2358. }
  2359. }
  2360. kfree(buff);
  2361. cmd_special_free(h, c);
  2362. return 0;
  2363. }
  2364. static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  2365. {
  2366. BIG_IOCTL_Command_struct *ioc;
  2367. struct CommandList *c;
  2368. unsigned char **buff = NULL;
  2369. int *buff_size = NULL;
  2370. union u64bit temp64;
  2371. BYTE sg_used = 0;
  2372. int status = 0;
  2373. int i;
  2374. u32 left;
  2375. u32 sz;
  2376. BYTE __user *data_ptr;
  2377. if (!argp)
  2378. return -EINVAL;
  2379. if (!capable(CAP_SYS_RAWIO))
  2380. return -EPERM;
  2381. ioc = (BIG_IOCTL_Command_struct *)
  2382. kmalloc(sizeof(*ioc), GFP_KERNEL);
  2383. if (!ioc) {
  2384. status = -ENOMEM;
  2385. goto cleanup1;
  2386. }
  2387. if (copy_from_user(ioc, argp, sizeof(*ioc))) {
  2388. status = -EFAULT;
  2389. goto cleanup1;
  2390. }
  2391. if ((ioc->buf_size < 1) &&
  2392. (ioc->Request.Type.Direction != XFER_NONE)) {
  2393. status = -EINVAL;
  2394. goto cleanup1;
  2395. }
  2396. /* Check kmalloc limits using all SGs */
  2397. if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
  2398. status = -EINVAL;
  2399. goto cleanup1;
  2400. }
  2401. if (ioc->buf_size > ioc->malloc_size * MAXSGENTRIES) {
  2402. status = -EINVAL;
  2403. goto cleanup1;
  2404. }
  2405. buff = kzalloc(MAXSGENTRIES * sizeof(char *), GFP_KERNEL);
  2406. if (!buff) {
  2407. status = -ENOMEM;
  2408. goto cleanup1;
  2409. }
  2410. buff_size = kmalloc(MAXSGENTRIES * sizeof(int), GFP_KERNEL);
  2411. if (!buff_size) {
  2412. status = -ENOMEM;
  2413. goto cleanup1;
  2414. }
  2415. left = ioc->buf_size;
  2416. data_ptr = ioc->buf;
  2417. while (left) {
  2418. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  2419. buff_size[sg_used] = sz;
  2420. buff[sg_used] = kmalloc(sz, GFP_KERNEL);
  2421. if (buff[sg_used] == NULL) {
  2422. status = -ENOMEM;
  2423. goto cleanup1;
  2424. }
  2425. if (ioc->Request.Type.Direction == XFER_WRITE) {
  2426. if (copy_from_user(buff[sg_used], data_ptr, sz)) {
  2427. status = -ENOMEM;
  2428. goto cleanup1;
  2429. }
  2430. } else
  2431. memset(buff[sg_used], 0, sz);
  2432. left -= sz;
  2433. data_ptr += sz;
  2434. sg_used++;
  2435. }
  2436. c = cmd_special_alloc(h);
  2437. if (c == NULL) {
  2438. status = -ENOMEM;
  2439. goto cleanup1;
  2440. }
  2441. c->cmd_type = CMD_IOCTL_PEND;
  2442. c->Header.ReplyQueue = 0;
  2443. c->Header.SGList = c->Header.SGTotal = sg_used;
  2444. memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
  2445. c->Header.Tag.lower = c->busaddr;
  2446. memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
  2447. if (ioc->buf_size > 0) {
  2448. int i;
  2449. for (i = 0; i < sg_used; i++) {
  2450. temp64.val = pci_map_single(h->pdev, buff[i],
  2451. buff_size[i], PCI_DMA_BIDIRECTIONAL);
  2452. c->SG[i].Addr.lower = temp64.val32.lower;
  2453. c->SG[i].Addr.upper = temp64.val32.upper;
  2454. c->SG[i].Len = buff_size[i];
  2455. /* we are not chaining */
  2456. c->SG[i].Ext = 0;
  2457. }
  2458. }
  2459. hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
  2460. if (sg_used)
  2461. hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
  2462. check_ioctl_unit_attention(h, c);
  2463. /* Copy the error information out */
  2464. memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
  2465. if (copy_to_user(argp, ioc, sizeof(*ioc))) {
  2466. cmd_special_free(h, c);
  2467. status = -EFAULT;
  2468. goto cleanup1;
  2469. }
  2470. if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
  2471. /* Copy the data out of the buffer we created */
  2472. BYTE __user *ptr = ioc->buf;
  2473. for (i = 0; i < sg_used; i++) {
  2474. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  2475. cmd_special_free(h, c);
  2476. status = -EFAULT;
  2477. goto cleanup1;
  2478. }
  2479. ptr += buff_size[i];
  2480. }
  2481. }
  2482. cmd_special_free(h, c);
  2483. status = 0;
  2484. cleanup1:
  2485. if (buff) {
  2486. for (i = 0; i < sg_used; i++)
  2487. kfree(buff[i]);
  2488. kfree(buff);
  2489. }
  2490. kfree(buff_size);
  2491. kfree(ioc);
  2492. return status;
  2493. }
  2494. static void check_ioctl_unit_attention(struct ctlr_info *h,
  2495. struct CommandList *c)
  2496. {
  2497. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  2498. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  2499. (void) check_for_unit_attention(h, c);
  2500. }
  2501. /*
  2502. * ioctl
  2503. */
  2504. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
  2505. {
  2506. struct ctlr_info *h;
  2507. void __user *argp = (void __user *)arg;
  2508. h = sdev_to_hba(dev);
  2509. switch (cmd) {
  2510. case CCISS_DEREGDISK:
  2511. case CCISS_REGNEWDISK:
  2512. case CCISS_REGNEWD:
  2513. hpsa_scan_start(h->scsi_host);
  2514. return 0;
  2515. case CCISS_GETPCIINFO:
  2516. return hpsa_getpciinfo_ioctl(h, argp);
  2517. case CCISS_GETDRIVVER:
  2518. return hpsa_getdrivver_ioctl(h, argp);
  2519. case CCISS_PASSTHRU:
  2520. return hpsa_passthru_ioctl(h, argp);
  2521. case CCISS_BIG_PASSTHRU:
  2522. return hpsa_big_passthru_ioctl(h, argp);
  2523. default:
  2524. return -ENOTTY;
  2525. }
  2526. }
  2527. static int __devinit hpsa_send_host_reset(struct ctlr_info *h,
  2528. unsigned char *scsi3addr, u8 reset_type)
  2529. {
  2530. struct CommandList *c;
  2531. c = cmd_alloc(h);
  2532. if (!c)
  2533. return -ENOMEM;
  2534. fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
  2535. RAID_CTLR_LUNID, TYPE_MSG);
  2536. c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
  2537. c->waiting = NULL;
  2538. enqueue_cmd_and_start_io(h, c);
  2539. /* Don't wait for completion, the reset won't complete. Don't free
  2540. * the command either. This is the last command we will send before
  2541. * re-initializing everything, so it doesn't matter and won't leak.
  2542. */
  2543. return 0;
  2544. }
  2545. static void fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  2546. void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
  2547. int cmd_type)
  2548. {
  2549. int pci_dir = XFER_NONE;
  2550. c->cmd_type = CMD_IOCTL_PEND;
  2551. c->Header.ReplyQueue = 0;
  2552. if (buff != NULL && size > 0) {
  2553. c->Header.SGList = 1;
  2554. c->Header.SGTotal = 1;
  2555. } else {
  2556. c->Header.SGList = 0;
  2557. c->Header.SGTotal = 0;
  2558. }
  2559. c->Header.Tag.lower = c->busaddr;
  2560. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  2561. c->Request.Type.Type = cmd_type;
  2562. if (cmd_type == TYPE_CMD) {
  2563. switch (cmd) {
  2564. case HPSA_INQUIRY:
  2565. /* are we trying to read a vital product page */
  2566. if (page_code != 0) {
  2567. c->Request.CDB[1] = 0x01;
  2568. c->Request.CDB[2] = page_code;
  2569. }
  2570. c->Request.CDBLen = 6;
  2571. c->Request.Type.Attribute = ATTR_SIMPLE;
  2572. c->Request.Type.Direction = XFER_READ;
  2573. c->Request.Timeout = 0;
  2574. c->Request.CDB[0] = HPSA_INQUIRY;
  2575. c->Request.CDB[4] = size & 0xFF;
  2576. break;
  2577. case HPSA_REPORT_LOG:
  2578. case HPSA_REPORT_PHYS:
  2579. /* Talking to controller so It's a physical command
  2580. mode = 00 target = 0. Nothing to write.
  2581. */
  2582. c->Request.CDBLen = 12;
  2583. c->Request.Type.Attribute = ATTR_SIMPLE;
  2584. c->Request.Type.Direction = XFER_READ;
  2585. c->Request.Timeout = 0;
  2586. c->Request.CDB[0] = cmd;
  2587. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  2588. c->Request.CDB[7] = (size >> 16) & 0xFF;
  2589. c->Request.CDB[8] = (size >> 8) & 0xFF;
  2590. c->Request.CDB[9] = size & 0xFF;
  2591. break;
  2592. case HPSA_CACHE_FLUSH:
  2593. c->Request.CDBLen = 12;
  2594. c->Request.Type.Attribute = ATTR_SIMPLE;
  2595. c->Request.Type.Direction = XFER_WRITE;
  2596. c->Request.Timeout = 0;
  2597. c->Request.CDB[0] = BMIC_WRITE;
  2598. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  2599. c->Request.CDB[7] = (size >> 8) & 0xFF;
  2600. c->Request.CDB[8] = size & 0xFF;
  2601. break;
  2602. case TEST_UNIT_READY:
  2603. c->Request.CDBLen = 6;
  2604. c->Request.Type.Attribute = ATTR_SIMPLE;
  2605. c->Request.Type.Direction = XFER_NONE;
  2606. c->Request.Timeout = 0;
  2607. break;
  2608. default:
  2609. dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
  2610. BUG();
  2611. return;
  2612. }
  2613. } else if (cmd_type == TYPE_MSG) {
  2614. switch (cmd) {
  2615. case HPSA_DEVICE_RESET_MSG:
  2616. c->Request.CDBLen = 16;
  2617. c->Request.Type.Type = 1; /* It is a MSG not a CMD */
  2618. c->Request.Type.Attribute = ATTR_SIMPLE;
  2619. c->Request.Type.Direction = XFER_NONE;
  2620. c->Request.Timeout = 0; /* Don't time out */
  2621. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  2622. c->Request.CDB[0] = cmd;
  2623. c->Request.CDB[1] = 0x03; /* Reset target above */
  2624. /* If bytes 4-7 are zero, it means reset the */
  2625. /* LunID device */
  2626. c->Request.CDB[4] = 0x00;
  2627. c->Request.CDB[5] = 0x00;
  2628. c->Request.CDB[6] = 0x00;
  2629. c->Request.CDB[7] = 0x00;
  2630. break;
  2631. default:
  2632. dev_warn(&h->pdev->dev, "unknown message type %d\n",
  2633. cmd);
  2634. BUG();
  2635. }
  2636. } else {
  2637. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  2638. BUG();
  2639. }
  2640. switch (c->Request.Type.Direction) {
  2641. case XFER_READ:
  2642. pci_dir = PCI_DMA_FROMDEVICE;
  2643. break;
  2644. case XFER_WRITE:
  2645. pci_dir = PCI_DMA_TODEVICE;
  2646. break;
  2647. case XFER_NONE:
  2648. pci_dir = PCI_DMA_NONE;
  2649. break;
  2650. default:
  2651. pci_dir = PCI_DMA_BIDIRECTIONAL;
  2652. }
  2653. hpsa_map_one(h->pdev, c, buff, size, pci_dir);
  2654. return;
  2655. }
  2656. /*
  2657. * Map (physical) PCI mem into (virtual) kernel space
  2658. */
  2659. static void __iomem *remap_pci_mem(ulong base, ulong size)
  2660. {
  2661. ulong page_base = ((ulong) base) & PAGE_MASK;
  2662. ulong page_offs = ((ulong) base) - page_base;
  2663. void __iomem *page_remapped = ioremap(page_base, page_offs + size);
  2664. return page_remapped ? (page_remapped + page_offs) : NULL;
  2665. }
  2666. /* Takes cmds off the submission queue and sends them to the hardware,
  2667. * then puts them on the queue of cmds waiting for completion.
  2668. */
  2669. static void start_io(struct ctlr_info *h)
  2670. {
  2671. struct CommandList *c;
  2672. while (!list_empty(&h->reqQ)) {
  2673. c = list_entry(h->reqQ.next, struct CommandList, list);
  2674. /* can't do anything if fifo is full */
  2675. if ((h->access.fifo_full(h))) {
  2676. dev_warn(&h->pdev->dev, "fifo full\n");
  2677. break;
  2678. }
  2679. /* Get the first entry from the Request Q */
  2680. removeQ(c);
  2681. h->Qdepth--;
  2682. /* Tell the controller execute command */
  2683. h->access.submit_command(h, c);
  2684. /* Put job onto the completed Q */
  2685. addQ(&h->cmpQ, c);
  2686. }
  2687. }
  2688. static inline unsigned long get_next_completion(struct ctlr_info *h)
  2689. {
  2690. return h->access.command_completed(h);
  2691. }
  2692. static inline bool interrupt_pending(struct ctlr_info *h)
  2693. {
  2694. return h->access.intr_pending(h);
  2695. }
  2696. static inline long interrupt_not_for_us(struct ctlr_info *h)
  2697. {
  2698. return (h->access.intr_pending(h) == 0) ||
  2699. (h->interrupts_enabled == 0);
  2700. }
  2701. static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
  2702. u32 raw_tag)
  2703. {
  2704. if (unlikely(tag_index >= h->nr_cmds)) {
  2705. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  2706. return 1;
  2707. }
  2708. return 0;
  2709. }
  2710. static inline void finish_cmd(struct CommandList *c, u32 raw_tag)
  2711. {
  2712. removeQ(c);
  2713. if (likely(c->cmd_type == CMD_SCSI))
  2714. complete_scsi_command(c);
  2715. else if (c->cmd_type == CMD_IOCTL_PEND)
  2716. complete(c->waiting);
  2717. }
  2718. static inline u32 hpsa_tag_contains_index(u32 tag)
  2719. {
  2720. return tag & DIRECT_LOOKUP_BIT;
  2721. }
  2722. static inline u32 hpsa_tag_to_index(u32 tag)
  2723. {
  2724. return tag >> DIRECT_LOOKUP_SHIFT;
  2725. }
  2726. static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
  2727. {
  2728. #define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
  2729. #define HPSA_SIMPLE_ERROR_BITS 0x03
  2730. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  2731. return tag & ~HPSA_SIMPLE_ERROR_BITS;
  2732. return tag & ~HPSA_PERF_ERROR_BITS;
  2733. }
  2734. /* process completion of an indexed ("direct lookup") command */
  2735. static inline u32 process_indexed_cmd(struct ctlr_info *h,
  2736. u32 raw_tag)
  2737. {
  2738. u32 tag_index;
  2739. struct CommandList *c;
  2740. tag_index = hpsa_tag_to_index(raw_tag);
  2741. if (bad_tag(h, tag_index, raw_tag))
  2742. return next_command(h);
  2743. c = h->cmd_pool + tag_index;
  2744. finish_cmd(c, raw_tag);
  2745. return next_command(h);
  2746. }
  2747. /* process completion of a non-indexed command */
  2748. static inline u32 process_nonindexed_cmd(struct ctlr_info *h,
  2749. u32 raw_tag)
  2750. {
  2751. u32 tag;
  2752. struct CommandList *c = NULL;
  2753. tag = hpsa_tag_discard_error_bits(h, raw_tag);
  2754. list_for_each_entry(c, &h->cmpQ, list) {
  2755. if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
  2756. finish_cmd(c, raw_tag);
  2757. return next_command(h);
  2758. }
  2759. }
  2760. bad_tag(h, h->nr_cmds + 1, raw_tag);
  2761. return next_command(h);
  2762. }
  2763. /* Some controllers, like p400, will give us one interrupt
  2764. * after a soft reset, even if we turned interrupts off.
  2765. * Only need to check for this in the hpsa_xxx_discard_completions
  2766. * functions.
  2767. */
  2768. static int ignore_bogus_interrupt(struct ctlr_info *h)
  2769. {
  2770. if (likely(!reset_devices))
  2771. return 0;
  2772. if (likely(h->interrupts_enabled))
  2773. return 0;
  2774. dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
  2775. "(known firmware bug.) Ignoring.\n");
  2776. return 1;
  2777. }
  2778. static irqreturn_t hpsa_intx_discard_completions(int irq, void *dev_id)
  2779. {
  2780. struct ctlr_info *h = dev_id;
  2781. unsigned long flags;
  2782. u32 raw_tag;
  2783. if (ignore_bogus_interrupt(h))
  2784. return IRQ_NONE;
  2785. if (interrupt_not_for_us(h))
  2786. return IRQ_NONE;
  2787. spin_lock_irqsave(&h->lock, flags);
  2788. h->last_intr_timestamp = get_jiffies_64();
  2789. while (interrupt_pending(h)) {
  2790. raw_tag = get_next_completion(h);
  2791. while (raw_tag != FIFO_EMPTY)
  2792. raw_tag = next_command(h);
  2793. }
  2794. spin_unlock_irqrestore(&h->lock, flags);
  2795. return IRQ_HANDLED;
  2796. }
  2797. static irqreturn_t hpsa_msix_discard_completions(int irq, void *dev_id)
  2798. {
  2799. struct ctlr_info *h = dev_id;
  2800. unsigned long flags;
  2801. u32 raw_tag;
  2802. if (ignore_bogus_interrupt(h))
  2803. return IRQ_NONE;
  2804. spin_lock_irqsave(&h->lock, flags);
  2805. h->last_intr_timestamp = get_jiffies_64();
  2806. raw_tag = get_next_completion(h);
  2807. while (raw_tag != FIFO_EMPTY)
  2808. raw_tag = next_command(h);
  2809. spin_unlock_irqrestore(&h->lock, flags);
  2810. return IRQ_HANDLED;
  2811. }
  2812. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id)
  2813. {
  2814. struct ctlr_info *h = dev_id;
  2815. unsigned long flags;
  2816. u32 raw_tag;
  2817. if (interrupt_not_for_us(h))
  2818. return IRQ_NONE;
  2819. spin_lock_irqsave(&h->lock, flags);
  2820. h->last_intr_timestamp = get_jiffies_64();
  2821. while (interrupt_pending(h)) {
  2822. raw_tag = get_next_completion(h);
  2823. while (raw_tag != FIFO_EMPTY) {
  2824. if (hpsa_tag_contains_index(raw_tag))
  2825. raw_tag = process_indexed_cmd(h, raw_tag);
  2826. else
  2827. raw_tag = process_nonindexed_cmd(h, raw_tag);
  2828. }
  2829. }
  2830. spin_unlock_irqrestore(&h->lock, flags);
  2831. return IRQ_HANDLED;
  2832. }
  2833. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id)
  2834. {
  2835. struct ctlr_info *h = dev_id;
  2836. unsigned long flags;
  2837. u32 raw_tag;
  2838. spin_lock_irqsave(&h->lock, flags);
  2839. h->last_intr_timestamp = get_jiffies_64();
  2840. raw_tag = get_next_completion(h);
  2841. while (raw_tag != FIFO_EMPTY) {
  2842. if (hpsa_tag_contains_index(raw_tag))
  2843. raw_tag = process_indexed_cmd(h, raw_tag);
  2844. else
  2845. raw_tag = process_nonindexed_cmd(h, raw_tag);
  2846. }
  2847. spin_unlock_irqrestore(&h->lock, flags);
  2848. return IRQ_HANDLED;
  2849. }
  2850. /* Send a message CDB to the firmware. Careful, this only works
  2851. * in simple mode, not performant mode due to the tag lookup.
  2852. * We only ever use this immediately after a controller reset.
  2853. */
  2854. static __devinit int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
  2855. unsigned char type)
  2856. {
  2857. struct Command {
  2858. struct CommandListHeader CommandHeader;
  2859. struct RequestBlock Request;
  2860. struct ErrDescriptor ErrorDescriptor;
  2861. };
  2862. struct Command *cmd;
  2863. static const size_t cmd_sz = sizeof(*cmd) +
  2864. sizeof(cmd->ErrorDescriptor);
  2865. dma_addr_t paddr64;
  2866. uint32_t paddr32, tag;
  2867. void __iomem *vaddr;
  2868. int i, err;
  2869. vaddr = pci_ioremap_bar(pdev, 0);
  2870. if (vaddr == NULL)
  2871. return -ENOMEM;
  2872. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  2873. * CCISS commands, so they must be allocated from the lower 4GiB of
  2874. * memory.
  2875. */
  2876. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2877. if (err) {
  2878. iounmap(vaddr);
  2879. return -ENOMEM;
  2880. }
  2881. cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
  2882. if (cmd == NULL) {
  2883. iounmap(vaddr);
  2884. return -ENOMEM;
  2885. }
  2886. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  2887. * although there's no guarantee, we assume that the address is at
  2888. * least 4-byte aligned (most likely, it's page-aligned).
  2889. */
  2890. paddr32 = paddr64;
  2891. cmd->CommandHeader.ReplyQueue = 0;
  2892. cmd->CommandHeader.SGList = 0;
  2893. cmd->CommandHeader.SGTotal = 0;
  2894. cmd->CommandHeader.Tag.lower = paddr32;
  2895. cmd->CommandHeader.Tag.upper = 0;
  2896. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  2897. cmd->Request.CDBLen = 16;
  2898. cmd->Request.Type.Type = TYPE_MSG;
  2899. cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
  2900. cmd->Request.Type.Direction = XFER_NONE;
  2901. cmd->Request.Timeout = 0; /* Don't time out */
  2902. cmd->Request.CDB[0] = opcode;
  2903. cmd->Request.CDB[1] = type;
  2904. memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
  2905. cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
  2906. cmd->ErrorDescriptor.Addr.upper = 0;
  2907. cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
  2908. writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
  2909. for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
  2910. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  2911. if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
  2912. break;
  2913. msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
  2914. }
  2915. iounmap(vaddr);
  2916. /* we leak the DMA buffer here ... no choice since the controller could
  2917. * still complete the command.
  2918. */
  2919. if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
  2920. dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
  2921. opcode, type);
  2922. return -ETIMEDOUT;
  2923. }
  2924. pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
  2925. if (tag & HPSA_ERROR_BIT) {
  2926. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  2927. opcode, type);
  2928. return -EIO;
  2929. }
  2930. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  2931. opcode, type);
  2932. return 0;
  2933. }
  2934. #define hpsa_noop(p) hpsa_message(p, 3, 0)
  2935. static int hpsa_controller_hard_reset(struct pci_dev *pdev,
  2936. void * __iomem vaddr, u32 use_doorbell)
  2937. {
  2938. u16 pmcsr;
  2939. int pos;
  2940. if (use_doorbell) {
  2941. /* For everything after the P600, the PCI power state method
  2942. * of resetting the controller doesn't work, so we have this
  2943. * other way using the doorbell register.
  2944. */
  2945. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  2946. writel(use_doorbell, vaddr + SA5_DOORBELL);
  2947. } else { /* Try to do it the PCI power state way */
  2948. /* Quoting from the Open CISS Specification: "The Power
  2949. * Management Control/Status Register (CSR) controls the power
  2950. * state of the device. The normal operating state is D0,
  2951. * CSR=00h. The software off state is D3, CSR=03h. To reset
  2952. * the controller, place the interface device in D3 then to D0,
  2953. * this causes a secondary PCI reset which will reset the
  2954. * controller." */
  2955. pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
  2956. if (pos == 0) {
  2957. dev_err(&pdev->dev,
  2958. "hpsa_reset_controller: "
  2959. "PCI PM not supported\n");
  2960. return -ENODEV;
  2961. }
  2962. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  2963. /* enter the D3hot power management state */
  2964. pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
  2965. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  2966. pmcsr |= PCI_D3hot;
  2967. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  2968. msleep(500);
  2969. /* enter the D0 power management state */
  2970. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  2971. pmcsr |= PCI_D0;
  2972. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  2973. }
  2974. return 0;
  2975. }
  2976. static __devinit void init_driver_version(char *driver_version, int len)
  2977. {
  2978. memset(driver_version, 0, len);
  2979. strncpy(driver_version, "hpsa " HPSA_DRIVER_VERSION, len - 1);
  2980. }
  2981. static __devinit int write_driver_ver_to_cfgtable(
  2982. struct CfgTable __iomem *cfgtable)
  2983. {
  2984. char *driver_version;
  2985. int i, size = sizeof(cfgtable->driver_version);
  2986. driver_version = kmalloc(size, GFP_KERNEL);
  2987. if (!driver_version)
  2988. return -ENOMEM;
  2989. init_driver_version(driver_version, size);
  2990. for (i = 0; i < size; i++)
  2991. writeb(driver_version[i], &cfgtable->driver_version[i]);
  2992. kfree(driver_version);
  2993. return 0;
  2994. }
  2995. static __devinit void read_driver_ver_from_cfgtable(
  2996. struct CfgTable __iomem *cfgtable, unsigned char *driver_ver)
  2997. {
  2998. int i;
  2999. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  3000. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  3001. }
  3002. static __devinit int controller_reset_failed(
  3003. struct CfgTable __iomem *cfgtable)
  3004. {
  3005. char *driver_ver, *old_driver_ver;
  3006. int rc, size = sizeof(cfgtable->driver_version);
  3007. old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
  3008. if (!old_driver_ver)
  3009. return -ENOMEM;
  3010. driver_ver = old_driver_ver + size;
  3011. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  3012. * should have been changed, otherwise we know the reset failed.
  3013. */
  3014. init_driver_version(old_driver_ver, size);
  3015. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  3016. rc = !memcmp(driver_ver, old_driver_ver, size);
  3017. kfree(old_driver_ver);
  3018. return rc;
  3019. }
  3020. /* This does a hard reset of the controller using PCI power management
  3021. * states or the using the doorbell register.
  3022. */
  3023. static __devinit int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
  3024. {
  3025. u64 cfg_offset;
  3026. u32 cfg_base_addr;
  3027. u64 cfg_base_addr_index;
  3028. void __iomem *vaddr;
  3029. unsigned long paddr;
  3030. u32 misc_fw_support;
  3031. int rc;
  3032. struct CfgTable __iomem *cfgtable;
  3033. u32 use_doorbell;
  3034. u32 board_id;
  3035. u16 command_register;
  3036. /* For controllers as old as the P600, this is very nearly
  3037. * the same thing as
  3038. *
  3039. * pci_save_state(pci_dev);
  3040. * pci_set_power_state(pci_dev, PCI_D3hot);
  3041. * pci_set_power_state(pci_dev, PCI_D0);
  3042. * pci_restore_state(pci_dev);
  3043. *
  3044. * For controllers newer than the P600, the pci power state
  3045. * method of resetting doesn't work so we have another way
  3046. * using the doorbell register.
  3047. */
  3048. rc = hpsa_lookup_board_id(pdev, &board_id);
  3049. if (rc < 0 || !ctlr_is_resettable(board_id)) {
  3050. dev_warn(&pdev->dev, "Not resetting device.\n");
  3051. return -ENODEV;
  3052. }
  3053. /* if controller is soft- but not hard resettable... */
  3054. if (!ctlr_is_hard_resettable(board_id))
  3055. return -ENOTSUPP; /* try soft reset later. */
  3056. /* Save the PCI command register */
  3057. pci_read_config_word(pdev, 4, &command_register);
  3058. /* Turn the board off. This is so that later pci_restore_state()
  3059. * won't turn the board on before the rest of config space is ready.
  3060. */
  3061. pci_disable_device(pdev);
  3062. pci_save_state(pdev);
  3063. /* find the first memory BAR, so we can find the cfg table */
  3064. rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
  3065. if (rc)
  3066. return rc;
  3067. vaddr = remap_pci_mem(paddr, 0x250);
  3068. if (!vaddr)
  3069. return -ENOMEM;
  3070. /* find cfgtable in order to check if reset via doorbell is supported */
  3071. rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  3072. &cfg_base_addr_index, &cfg_offset);
  3073. if (rc)
  3074. goto unmap_vaddr;
  3075. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  3076. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  3077. if (!cfgtable) {
  3078. rc = -ENOMEM;
  3079. goto unmap_vaddr;
  3080. }
  3081. rc = write_driver_ver_to_cfgtable(cfgtable);
  3082. if (rc)
  3083. goto unmap_vaddr;
  3084. /* If reset via doorbell register is supported, use that.
  3085. * There are two such methods. Favor the newest method.
  3086. */
  3087. misc_fw_support = readl(&cfgtable->misc_fw_support);
  3088. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
  3089. if (use_doorbell) {
  3090. use_doorbell = DOORBELL_CTLR_RESET2;
  3091. } else {
  3092. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  3093. if (use_doorbell) {
  3094. dev_warn(&pdev->dev, "Soft reset not supported. "
  3095. "Firmware update is required.\n");
  3096. rc = -ENOTSUPP; /* try soft reset */
  3097. goto unmap_cfgtable;
  3098. }
  3099. }
  3100. rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
  3101. if (rc)
  3102. goto unmap_cfgtable;
  3103. pci_restore_state(pdev);
  3104. rc = pci_enable_device(pdev);
  3105. if (rc) {
  3106. dev_warn(&pdev->dev, "failed to enable device.\n");
  3107. goto unmap_cfgtable;
  3108. }
  3109. pci_write_config_word(pdev, 4, command_register);
  3110. /* Some devices (notably the HP Smart Array 5i Controller)
  3111. need a little pause here */
  3112. msleep(HPSA_POST_RESET_PAUSE_MSECS);
  3113. /* Wait for board to become not ready, then ready. */
  3114. dev_info(&pdev->dev, "Waiting for board to reset.\n");
  3115. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
  3116. if (rc) {
  3117. dev_warn(&pdev->dev,
  3118. "failed waiting for board to reset."
  3119. " Will try soft reset.\n");
  3120. rc = -ENOTSUPP; /* Not expected, but try soft reset later */
  3121. goto unmap_cfgtable;
  3122. }
  3123. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
  3124. if (rc) {
  3125. dev_warn(&pdev->dev,
  3126. "failed waiting for board to become ready "
  3127. "after hard reset\n");
  3128. goto unmap_cfgtable;
  3129. }
  3130. rc = controller_reset_failed(vaddr);
  3131. if (rc < 0)
  3132. goto unmap_cfgtable;
  3133. if (rc) {
  3134. dev_warn(&pdev->dev, "Unable to successfully reset "
  3135. "controller. Will try soft reset.\n");
  3136. rc = -ENOTSUPP;
  3137. } else {
  3138. dev_info(&pdev->dev, "board ready after hard reset.\n");
  3139. }
  3140. unmap_cfgtable:
  3141. iounmap(cfgtable);
  3142. unmap_vaddr:
  3143. iounmap(vaddr);
  3144. return rc;
  3145. }
  3146. /*
  3147. * We cannot read the structure directly, for portability we must use
  3148. * the io functions.
  3149. * This is for debug only.
  3150. */
  3151. static void print_cfg_table(struct device *dev, struct CfgTable *tb)
  3152. {
  3153. #ifdef HPSA_DEBUG
  3154. int i;
  3155. char temp_name[17];
  3156. dev_info(dev, "Controller Configuration information\n");
  3157. dev_info(dev, "------------------------------------\n");
  3158. for (i = 0; i < 4; i++)
  3159. temp_name[i] = readb(&(tb->Signature[i]));
  3160. temp_name[4] = '\0';
  3161. dev_info(dev, " Signature = %s\n", temp_name);
  3162. dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
  3163. dev_info(dev, " Transport methods supported = 0x%x\n",
  3164. readl(&(tb->TransportSupport)));
  3165. dev_info(dev, " Transport methods active = 0x%x\n",
  3166. readl(&(tb->TransportActive)));
  3167. dev_info(dev, " Requested transport Method = 0x%x\n",
  3168. readl(&(tb->HostWrite.TransportRequest)));
  3169. dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
  3170. readl(&(tb->HostWrite.CoalIntDelay)));
  3171. dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
  3172. readl(&(tb->HostWrite.CoalIntCount)));
  3173. dev_info(dev, " Max outstanding commands = 0x%d\n",
  3174. readl(&(tb->CmdsOutMax)));
  3175. dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
  3176. for (i = 0; i < 16; i++)
  3177. temp_name[i] = readb(&(tb->ServerName[i]));
  3178. temp_name[16] = '\0';
  3179. dev_info(dev, " Server Name = %s\n", temp_name);
  3180. dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
  3181. readl(&(tb->HeartBeat)));
  3182. #endif /* HPSA_DEBUG */
  3183. }
  3184. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  3185. {
  3186. int i, offset, mem_type, bar_type;
  3187. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  3188. return 0;
  3189. offset = 0;
  3190. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  3191. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  3192. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  3193. offset += 4;
  3194. else {
  3195. mem_type = pci_resource_flags(pdev, i) &
  3196. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  3197. switch (mem_type) {
  3198. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  3199. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  3200. offset += 4; /* 32 bit */
  3201. break;
  3202. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  3203. offset += 8;
  3204. break;
  3205. default: /* reserved in PCI 2.2 */
  3206. dev_warn(&pdev->dev,
  3207. "base address is invalid\n");
  3208. return -1;
  3209. break;
  3210. }
  3211. }
  3212. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  3213. return i + 1;
  3214. }
  3215. return -1;
  3216. }
  3217. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  3218. * controllers that are capable. If not, we use IO-APIC mode.
  3219. */
  3220. static void __devinit hpsa_interrupt_mode(struct ctlr_info *h)
  3221. {
  3222. #ifdef CONFIG_PCI_MSI
  3223. int err;
  3224. struct msix_entry hpsa_msix_entries[4] = { {0, 0}, {0, 1},
  3225. {0, 2}, {0, 3}
  3226. };
  3227. /* Some boards advertise MSI but don't really support it */
  3228. if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
  3229. (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
  3230. goto default_int_mode;
  3231. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
  3232. dev_info(&h->pdev->dev, "MSIX\n");
  3233. err = pci_enable_msix(h->pdev, hpsa_msix_entries, 4);
  3234. if (!err) {
  3235. h->intr[0] = hpsa_msix_entries[0].vector;
  3236. h->intr[1] = hpsa_msix_entries[1].vector;
  3237. h->intr[2] = hpsa_msix_entries[2].vector;
  3238. h->intr[3] = hpsa_msix_entries[3].vector;
  3239. h->msix_vector = 1;
  3240. return;
  3241. }
  3242. if (err > 0) {
  3243. dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
  3244. "available\n", err);
  3245. goto default_int_mode;
  3246. } else {
  3247. dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
  3248. err);
  3249. goto default_int_mode;
  3250. }
  3251. }
  3252. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
  3253. dev_info(&h->pdev->dev, "MSI\n");
  3254. if (!pci_enable_msi(h->pdev))
  3255. h->msi_vector = 1;
  3256. else
  3257. dev_warn(&h->pdev->dev, "MSI init failed\n");
  3258. }
  3259. default_int_mode:
  3260. #endif /* CONFIG_PCI_MSI */
  3261. /* if we get here we're going to use the default interrupt mode */
  3262. h->intr[h->intr_mode] = h->pdev->irq;
  3263. }
  3264. static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
  3265. {
  3266. int i;
  3267. u32 subsystem_vendor_id, subsystem_device_id;
  3268. subsystem_vendor_id = pdev->subsystem_vendor;
  3269. subsystem_device_id = pdev->subsystem_device;
  3270. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  3271. subsystem_vendor_id;
  3272. for (i = 0; i < ARRAY_SIZE(products); i++)
  3273. if (*board_id == products[i].board_id)
  3274. return i;
  3275. if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
  3276. subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
  3277. !hpsa_allow_any) {
  3278. dev_warn(&pdev->dev, "unrecognized board ID: "
  3279. "0x%08x, ignoring.\n", *board_id);
  3280. return -ENODEV;
  3281. }
  3282. return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
  3283. }
  3284. static inline bool hpsa_board_disabled(struct pci_dev *pdev)
  3285. {
  3286. u16 command;
  3287. (void) pci_read_config_word(pdev, PCI_COMMAND, &command);
  3288. return ((command & PCI_COMMAND_MEMORY) == 0);
  3289. }
  3290. static int __devinit hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  3291. unsigned long *memory_bar)
  3292. {
  3293. int i;
  3294. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  3295. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  3296. /* addressing mode bits already removed */
  3297. *memory_bar = pci_resource_start(pdev, i);
  3298. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  3299. *memory_bar);
  3300. return 0;
  3301. }
  3302. dev_warn(&pdev->dev, "no memory BAR found\n");
  3303. return -ENODEV;
  3304. }
  3305. static int __devinit hpsa_wait_for_board_state(struct pci_dev *pdev,
  3306. void __iomem *vaddr, int wait_for_ready)
  3307. {
  3308. int i, iterations;
  3309. u32 scratchpad;
  3310. if (wait_for_ready)
  3311. iterations = HPSA_BOARD_READY_ITERATIONS;
  3312. else
  3313. iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
  3314. for (i = 0; i < iterations; i++) {
  3315. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  3316. if (wait_for_ready) {
  3317. if (scratchpad == HPSA_FIRMWARE_READY)
  3318. return 0;
  3319. } else {
  3320. if (scratchpad != HPSA_FIRMWARE_READY)
  3321. return 0;
  3322. }
  3323. msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
  3324. }
  3325. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  3326. return -ENODEV;
  3327. }
  3328. static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
  3329. void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  3330. u64 *cfg_offset)
  3331. {
  3332. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  3333. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  3334. *cfg_base_addr &= (u32) 0x0000ffff;
  3335. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  3336. if (*cfg_base_addr_index == -1) {
  3337. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
  3338. return -ENODEV;
  3339. }
  3340. return 0;
  3341. }
  3342. static int __devinit hpsa_find_cfgtables(struct ctlr_info *h)
  3343. {
  3344. u64 cfg_offset;
  3345. u32 cfg_base_addr;
  3346. u64 cfg_base_addr_index;
  3347. u32 trans_offset;
  3348. int rc;
  3349. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  3350. &cfg_base_addr_index, &cfg_offset);
  3351. if (rc)
  3352. return rc;
  3353. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  3354. cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
  3355. if (!h->cfgtable)
  3356. return -ENOMEM;
  3357. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  3358. if (rc)
  3359. return rc;
  3360. /* Find performant mode table. */
  3361. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  3362. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  3363. cfg_base_addr_index)+cfg_offset+trans_offset,
  3364. sizeof(*h->transtable));
  3365. if (!h->transtable)
  3366. return -ENOMEM;
  3367. return 0;
  3368. }
  3369. static void __devinit hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
  3370. {
  3371. h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
  3372. /* Limit commands in memory limited kdump scenario. */
  3373. if (reset_devices && h->max_commands > 32)
  3374. h->max_commands = 32;
  3375. if (h->max_commands < 16) {
  3376. dev_warn(&h->pdev->dev, "Controller reports "
  3377. "max supported commands of %d, an obvious lie. "
  3378. "Using 16. Ensure that firmware is up to date.\n",
  3379. h->max_commands);
  3380. h->max_commands = 16;
  3381. }
  3382. }
  3383. /* Interrogate the hardware for some limits:
  3384. * max commands, max SG elements without chaining, and with chaining,
  3385. * SG chain block size, etc.
  3386. */
  3387. static void __devinit hpsa_find_board_params(struct ctlr_info *h)
  3388. {
  3389. hpsa_get_max_perf_mode_cmds(h);
  3390. h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
  3391. h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
  3392. /*
  3393. * Limit in-command s/g elements to 32 save dma'able memory.
  3394. * Howvever spec says if 0, use 31
  3395. */
  3396. h->max_cmd_sg_entries = 31;
  3397. if (h->maxsgentries > 512) {
  3398. h->max_cmd_sg_entries = 32;
  3399. h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
  3400. h->maxsgentries--; /* save one for chain pointer */
  3401. } else {
  3402. h->maxsgentries = 31; /* default to traditional values */
  3403. h->chainsize = 0;
  3404. }
  3405. }
  3406. static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
  3407. {
  3408. if ((readb(&h->cfgtable->Signature[0]) != 'C') ||
  3409. (readb(&h->cfgtable->Signature[1]) != 'I') ||
  3410. (readb(&h->cfgtable->Signature[2]) != 'S') ||
  3411. (readb(&h->cfgtable->Signature[3]) != 'S')) {
  3412. dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
  3413. return false;
  3414. }
  3415. return true;
  3416. }
  3417. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  3418. static inline void hpsa_enable_scsi_prefetch(struct ctlr_info *h)
  3419. {
  3420. #ifdef CONFIG_X86
  3421. u32 prefetch;
  3422. prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
  3423. prefetch |= 0x100;
  3424. writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
  3425. #endif
  3426. }
  3427. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  3428. * in a prefetch beyond physical memory.
  3429. */
  3430. static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
  3431. {
  3432. u32 dma_prefetch;
  3433. if (h->board_id != 0x3225103C)
  3434. return;
  3435. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  3436. dma_prefetch |= 0x8000;
  3437. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  3438. }
  3439. static void __devinit hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
  3440. {
  3441. int i;
  3442. u32 doorbell_value;
  3443. unsigned long flags;
  3444. /* under certain very rare conditions, this can take awhile.
  3445. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  3446. * as we enter this code.)
  3447. */
  3448. for (i = 0; i < MAX_CONFIG_WAIT; i++) {
  3449. spin_lock_irqsave(&h->lock, flags);
  3450. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  3451. spin_unlock_irqrestore(&h->lock, flags);
  3452. if (!(doorbell_value & CFGTBL_ChangeReq))
  3453. break;
  3454. /* delay and try again */
  3455. usleep_range(10000, 20000);
  3456. }
  3457. }
  3458. static int __devinit hpsa_enter_simple_mode(struct ctlr_info *h)
  3459. {
  3460. u32 trans_support;
  3461. trans_support = readl(&(h->cfgtable->TransportSupport));
  3462. if (!(trans_support & SIMPLE_MODE))
  3463. return -ENOTSUPP;
  3464. h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
  3465. /* Update the field, and then ring the doorbell */
  3466. writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
  3467. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  3468. hpsa_wait_for_mode_change_ack(h);
  3469. print_cfg_table(&h->pdev->dev, h->cfgtable);
  3470. if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
  3471. dev_warn(&h->pdev->dev,
  3472. "unable to get board into simple mode\n");
  3473. return -ENODEV;
  3474. }
  3475. h->transMethod = CFGTBL_Trans_Simple;
  3476. return 0;
  3477. }
  3478. static int __devinit hpsa_pci_init(struct ctlr_info *h)
  3479. {
  3480. int prod_index, err;
  3481. prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
  3482. if (prod_index < 0)
  3483. return -ENODEV;
  3484. h->product_name = products[prod_index].product_name;
  3485. h->access = *(products[prod_index].access);
  3486. if (hpsa_board_disabled(h->pdev)) {
  3487. dev_warn(&h->pdev->dev, "controller appears to be disabled\n");
  3488. return -ENODEV;
  3489. }
  3490. err = pci_enable_device(h->pdev);
  3491. if (err) {
  3492. dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
  3493. return err;
  3494. }
  3495. err = pci_request_regions(h->pdev, "hpsa");
  3496. if (err) {
  3497. dev_err(&h->pdev->dev,
  3498. "cannot obtain PCI resources, aborting\n");
  3499. return err;
  3500. }
  3501. hpsa_interrupt_mode(h);
  3502. err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
  3503. if (err)
  3504. goto err_out_free_res;
  3505. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  3506. if (!h->vaddr) {
  3507. err = -ENOMEM;
  3508. goto err_out_free_res;
  3509. }
  3510. err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  3511. if (err)
  3512. goto err_out_free_res;
  3513. err = hpsa_find_cfgtables(h);
  3514. if (err)
  3515. goto err_out_free_res;
  3516. hpsa_find_board_params(h);
  3517. if (!hpsa_CISS_signature_present(h)) {
  3518. err = -ENODEV;
  3519. goto err_out_free_res;
  3520. }
  3521. hpsa_enable_scsi_prefetch(h);
  3522. hpsa_p600_dma_prefetch_quirk(h);
  3523. err = hpsa_enter_simple_mode(h);
  3524. if (err)
  3525. goto err_out_free_res;
  3526. return 0;
  3527. err_out_free_res:
  3528. if (h->transtable)
  3529. iounmap(h->transtable);
  3530. if (h->cfgtable)
  3531. iounmap(h->cfgtable);
  3532. if (h->vaddr)
  3533. iounmap(h->vaddr);
  3534. /*
  3535. * Deliberately omit pci_disable_device(): it does something nasty to
  3536. * Smart Array controllers that pci_enable_device does not undo
  3537. */
  3538. pci_release_regions(h->pdev);
  3539. return err;
  3540. }
  3541. static void __devinit hpsa_hba_inquiry(struct ctlr_info *h)
  3542. {
  3543. int rc;
  3544. #define HBA_INQUIRY_BYTE_COUNT 64
  3545. h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
  3546. if (!h->hba_inquiry_data)
  3547. return;
  3548. rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
  3549. h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
  3550. if (rc != 0) {
  3551. kfree(h->hba_inquiry_data);
  3552. h->hba_inquiry_data = NULL;
  3553. }
  3554. }
  3555. static __devinit int hpsa_init_reset_devices(struct pci_dev *pdev)
  3556. {
  3557. int rc, i;
  3558. if (!reset_devices)
  3559. return 0;
  3560. /* Reset the controller with a PCI power-cycle or via doorbell */
  3561. rc = hpsa_kdump_hard_reset_controller(pdev);
  3562. /* -ENOTSUPP here means we cannot reset the controller
  3563. * but it's already (and still) up and running in
  3564. * "performant mode". Or, it might be 640x, which can't reset
  3565. * due to concerns about shared bbwc between 6402/6404 pair.
  3566. */
  3567. if (rc == -ENOTSUPP)
  3568. return rc; /* just try to do the kdump anyhow. */
  3569. if (rc)
  3570. return -ENODEV;
  3571. /* Now try to get the controller to respond to a no-op */
  3572. dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
  3573. for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
  3574. if (hpsa_noop(pdev) == 0)
  3575. break;
  3576. else
  3577. dev_warn(&pdev->dev, "no-op failed%s\n",
  3578. (i < 11 ? "; re-trying" : ""));
  3579. }
  3580. return 0;
  3581. }
  3582. static __devinit int hpsa_allocate_cmd_pool(struct ctlr_info *h)
  3583. {
  3584. h->cmd_pool_bits = kzalloc(
  3585. DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
  3586. sizeof(unsigned long), GFP_KERNEL);
  3587. h->cmd_pool = pci_alloc_consistent(h->pdev,
  3588. h->nr_cmds * sizeof(*h->cmd_pool),
  3589. &(h->cmd_pool_dhandle));
  3590. h->errinfo_pool = pci_alloc_consistent(h->pdev,
  3591. h->nr_cmds * sizeof(*h->errinfo_pool),
  3592. &(h->errinfo_pool_dhandle));
  3593. if ((h->cmd_pool_bits == NULL)
  3594. || (h->cmd_pool == NULL)
  3595. || (h->errinfo_pool == NULL)) {
  3596. dev_err(&h->pdev->dev, "out of memory in %s", __func__);
  3597. return -ENOMEM;
  3598. }
  3599. return 0;
  3600. }
  3601. static void hpsa_free_cmd_pool(struct ctlr_info *h)
  3602. {
  3603. kfree(h->cmd_pool_bits);
  3604. if (h->cmd_pool)
  3605. pci_free_consistent(h->pdev,
  3606. h->nr_cmds * sizeof(struct CommandList),
  3607. h->cmd_pool, h->cmd_pool_dhandle);
  3608. if (h->errinfo_pool)
  3609. pci_free_consistent(h->pdev,
  3610. h->nr_cmds * sizeof(struct ErrorInfo),
  3611. h->errinfo_pool,
  3612. h->errinfo_pool_dhandle);
  3613. }
  3614. static int hpsa_request_irq(struct ctlr_info *h,
  3615. irqreturn_t (*msixhandler)(int, void *),
  3616. irqreturn_t (*intxhandler)(int, void *))
  3617. {
  3618. int rc;
  3619. if (h->msix_vector || h->msi_vector)
  3620. rc = request_irq(h->intr[h->intr_mode], msixhandler,
  3621. IRQF_DISABLED, h->devname, h);
  3622. else
  3623. rc = request_irq(h->intr[h->intr_mode], intxhandler,
  3624. IRQF_DISABLED, h->devname, h);
  3625. if (rc) {
  3626. dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
  3627. h->intr[h->intr_mode], h->devname);
  3628. return -ENODEV;
  3629. }
  3630. return 0;
  3631. }
  3632. static int __devinit hpsa_kdump_soft_reset(struct ctlr_info *h)
  3633. {
  3634. if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
  3635. HPSA_RESET_TYPE_CONTROLLER)) {
  3636. dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
  3637. return -EIO;
  3638. }
  3639. dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
  3640. if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
  3641. dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
  3642. return -1;
  3643. }
  3644. dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
  3645. if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
  3646. dev_warn(&h->pdev->dev, "Board failed to become ready "
  3647. "after soft reset.\n");
  3648. return -1;
  3649. }
  3650. return 0;
  3651. }
  3652. static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
  3653. {
  3654. free_irq(h->intr[h->intr_mode], h);
  3655. #ifdef CONFIG_PCI_MSI
  3656. if (h->msix_vector)
  3657. pci_disable_msix(h->pdev);
  3658. else if (h->msi_vector)
  3659. pci_disable_msi(h->pdev);
  3660. #endif /* CONFIG_PCI_MSI */
  3661. hpsa_free_sg_chain_blocks(h);
  3662. hpsa_free_cmd_pool(h);
  3663. kfree(h->blockFetchTable);
  3664. pci_free_consistent(h->pdev, h->reply_pool_size,
  3665. h->reply_pool, h->reply_pool_dhandle);
  3666. if (h->vaddr)
  3667. iounmap(h->vaddr);
  3668. if (h->transtable)
  3669. iounmap(h->transtable);
  3670. if (h->cfgtable)
  3671. iounmap(h->cfgtable);
  3672. pci_release_regions(h->pdev);
  3673. kfree(h);
  3674. }
  3675. static void remove_ctlr_from_lockup_detector_list(struct ctlr_info *h)
  3676. {
  3677. assert_spin_locked(&lockup_detector_lock);
  3678. if (!hpsa_lockup_detector)
  3679. return;
  3680. if (h->lockup_detected)
  3681. return; /* already stopped the lockup detector */
  3682. list_del(&h->lockup_list);
  3683. }
  3684. /* Called when controller lockup detected. */
  3685. static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
  3686. {
  3687. struct CommandList *c = NULL;
  3688. assert_spin_locked(&h->lock);
  3689. /* Mark all outstanding commands as failed and complete them. */
  3690. while (!list_empty(list)) {
  3691. c = list_entry(list->next, struct CommandList, list);
  3692. c->err_info->CommandStatus = CMD_HARDWARE_ERR;
  3693. finish_cmd(c, c->Header.Tag.lower);
  3694. }
  3695. }
  3696. static void controller_lockup_detected(struct ctlr_info *h)
  3697. {
  3698. unsigned long flags;
  3699. assert_spin_locked(&lockup_detector_lock);
  3700. remove_ctlr_from_lockup_detector_list(h);
  3701. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3702. spin_lock_irqsave(&h->lock, flags);
  3703. h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  3704. spin_unlock_irqrestore(&h->lock, flags);
  3705. dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
  3706. h->lockup_detected);
  3707. pci_disable_device(h->pdev);
  3708. spin_lock_irqsave(&h->lock, flags);
  3709. fail_all_cmds_on_list(h, &h->cmpQ);
  3710. fail_all_cmds_on_list(h, &h->reqQ);
  3711. spin_unlock_irqrestore(&h->lock, flags);
  3712. }
  3713. #define HEARTBEAT_SAMPLE_INTERVAL (10 * HZ)
  3714. #define HEARTBEAT_CHECK_MINIMUM_INTERVAL (HEARTBEAT_SAMPLE_INTERVAL / 2)
  3715. static void detect_controller_lockup(struct ctlr_info *h)
  3716. {
  3717. u64 now;
  3718. u32 heartbeat;
  3719. unsigned long flags;
  3720. assert_spin_locked(&lockup_detector_lock);
  3721. now = get_jiffies_64();
  3722. /* If we've received an interrupt recently, we're ok. */
  3723. if (time_after64(h->last_intr_timestamp +
  3724. (HEARTBEAT_CHECK_MINIMUM_INTERVAL), now))
  3725. return;
  3726. /*
  3727. * If we've already checked the heartbeat recently, we're ok.
  3728. * This could happen if someone sends us a signal. We
  3729. * otherwise don't care about signals in this thread.
  3730. */
  3731. if (time_after64(h->last_heartbeat_timestamp +
  3732. (HEARTBEAT_CHECK_MINIMUM_INTERVAL), now))
  3733. return;
  3734. /* If heartbeat has not changed since we last looked, we're not ok. */
  3735. spin_lock_irqsave(&h->lock, flags);
  3736. heartbeat = readl(&h->cfgtable->HeartBeat);
  3737. spin_unlock_irqrestore(&h->lock, flags);
  3738. if (h->last_heartbeat == heartbeat) {
  3739. controller_lockup_detected(h);
  3740. return;
  3741. }
  3742. /* We're ok. */
  3743. h->last_heartbeat = heartbeat;
  3744. h->last_heartbeat_timestamp = now;
  3745. }
  3746. static int detect_controller_lockup_thread(void *notused)
  3747. {
  3748. struct ctlr_info *h;
  3749. unsigned long flags;
  3750. while (1) {
  3751. struct list_head *this, *tmp;
  3752. schedule_timeout_interruptible(HEARTBEAT_SAMPLE_INTERVAL);
  3753. if (kthread_should_stop())
  3754. break;
  3755. spin_lock_irqsave(&lockup_detector_lock, flags);
  3756. list_for_each_safe(this, tmp, &hpsa_ctlr_list) {
  3757. h = list_entry(this, struct ctlr_info, lockup_list);
  3758. detect_controller_lockup(h);
  3759. }
  3760. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  3761. }
  3762. return 0;
  3763. }
  3764. static void add_ctlr_to_lockup_detector_list(struct ctlr_info *h)
  3765. {
  3766. unsigned long flags;
  3767. spin_lock_irqsave(&lockup_detector_lock, flags);
  3768. list_add_tail(&h->lockup_list, &hpsa_ctlr_list);
  3769. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  3770. }
  3771. static void start_controller_lockup_detector(struct ctlr_info *h)
  3772. {
  3773. /* Start the lockup detector thread if not already started */
  3774. if (!hpsa_lockup_detector) {
  3775. spin_lock_init(&lockup_detector_lock);
  3776. hpsa_lockup_detector =
  3777. kthread_run(detect_controller_lockup_thread,
  3778. NULL, "hpsa");
  3779. }
  3780. if (!hpsa_lockup_detector) {
  3781. dev_warn(&h->pdev->dev,
  3782. "Could not start lockup detector thread\n");
  3783. return;
  3784. }
  3785. add_ctlr_to_lockup_detector_list(h);
  3786. }
  3787. static void stop_controller_lockup_detector(struct ctlr_info *h)
  3788. {
  3789. unsigned long flags;
  3790. spin_lock_irqsave(&lockup_detector_lock, flags);
  3791. remove_ctlr_from_lockup_detector_list(h);
  3792. /* If the list of ctlr's to monitor is empty, stop the thread */
  3793. if (list_empty(&hpsa_ctlr_list)) {
  3794. kthread_stop(hpsa_lockup_detector);
  3795. hpsa_lockup_detector = NULL;
  3796. }
  3797. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  3798. }
  3799. static int __devinit hpsa_init_one(struct pci_dev *pdev,
  3800. const struct pci_device_id *ent)
  3801. {
  3802. int dac, rc;
  3803. struct ctlr_info *h;
  3804. int try_soft_reset = 0;
  3805. unsigned long flags;
  3806. if (number_of_controllers == 0)
  3807. printk(KERN_INFO DRIVER_NAME "\n");
  3808. rc = hpsa_init_reset_devices(pdev);
  3809. if (rc) {
  3810. if (rc != -ENOTSUPP)
  3811. return rc;
  3812. /* If the reset fails in a particular way (it has no way to do
  3813. * a proper hard reset, so returns -ENOTSUPP) we can try to do
  3814. * a soft reset once we get the controller configured up to the
  3815. * point that it can accept a command.
  3816. */
  3817. try_soft_reset = 1;
  3818. rc = 0;
  3819. }
  3820. reinit_after_soft_reset:
  3821. /* Command structures must be aligned on a 32-byte boundary because
  3822. * the 5 lower bits of the address are used by the hardware. and by
  3823. * the driver. See comments in hpsa.h for more info.
  3824. */
  3825. #define COMMANDLIST_ALIGNMENT 32
  3826. BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
  3827. h = kzalloc(sizeof(*h), GFP_KERNEL);
  3828. if (!h)
  3829. return -ENOMEM;
  3830. h->pdev = pdev;
  3831. h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
  3832. INIT_LIST_HEAD(&h->cmpQ);
  3833. INIT_LIST_HEAD(&h->reqQ);
  3834. spin_lock_init(&h->lock);
  3835. spin_lock_init(&h->scan_lock);
  3836. rc = hpsa_pci_init(h);
  3837. if (rc != 0)
  3838. goto clean1;
  3839. sprintf(h->devname, "hpsa%d", number_of_controllers);
  3840. h->ctlr = number_of_controllers;
  3841. number_of_controllers++;
  3842. /* configure PCI DMA stuff */
  3843. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  3844. if (rc == 0) {
  3845. dac = 1;
  3846. } else {
  3847. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3848. if (rc == 0) {
  3849. dac = 0;
  3850. } else {
  3851. dev_err(&pdev->dev, "no suitable DMA available\n");
  3852. goto clean1;
  3853. }
  3854. }
  3855. /* make sure the board interrupts are off */
  3856. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3857. if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
  3858. goto clean2;
  3859. dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
  3860. h->devname, pdev->device,
  3861. h->intr[h->intr_mode], dac ? "" : " not");
  3862. if (hpsa_allocate_cmd_pool(h))
  3863. goto clean4;
  3864. if (hpsa_allocate_sg_chain_blocks(h))
  3865. goto clean4;
  3866. init_waitqueue_head(&h->scan_wait_queue);
  3867. h->scan_finished = 1; /* no scan currently in progress */
  3868. pci_set_drvdata(pdev, h);
  3869. h->ndevices = 0;
  3870. h->scsi_host = NULL;
  3871. spin_lock_init(&h->devlock);
  3872. hpsa_put_ctlr_into_performant_mode(h);
  3873. /* At this point, the controller is ready to take commands.
  3874. * Now, if reset_devices and the hard reset didn't work, try
  3875. * the soft reset and see if that works.
  3876. */
  3877. if (try_soft_reset) {
  3878. /* This is kind of gross. We may or may not get a completion
  3879. * from the soft reset command, and if we do, then the value
  3880. * from the fifo may or may not be valid. So, we wait 10 secs
  3881. * after the reset throwing away any completions we get during
  3882. * that time. Unregister the interrupt handler and register
  3883. * fake ones to scoop up any residual completions.
  3884. */
  3885. spin_lock_irqsave(&h->lock, flags);
  3886. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3887. spin_unlock_irqrestore(&h->lock, flags);
  3888. free_irq(h->intr[h->intr_mode], h);
  3889. rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
  3890. hpsa_intx_discard_completions);
  3891. if (rc) {
  3892. dev_warn(&h->pdev->dev, "Failed to request_irq after "
  3893. "soft reset.\n");
  3894. goto clean4;
  3895. }
  3896. rc = hpsa_kdump_soft_reset(h);
  3897. if (rc)
  3898. /* Neither hard nor soft reset worked, we're hosed. */
  3899. goto clean4;
  3900. dev_info(&h->pdev->dev, "Board READY.\n");
  3901. dev_info(&h->pdev->dev,
  3902. "Waiting for stale completions to drain.\n");
  3903. h->access.set_intr_mask(h, HPSA_INTR_ON);
  3904. msleep(10000);
  3905. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3906. rc = controller_reset_failed(h->cfgtable);
  3907. if (rc)
  3908. dev_info(&h->pdev->dev,
  3909. "Soft reset appears to have failed.\n");
  3910. /* since the controller's reset, we have to go back and re-init
  3911. * everything. Easiest to just forget what we've done and do it
  3912. * all over again.
  3913. */
  3914. hpsa_undo_allocations_after_kdump_soft_reset(h);
  3915. try_soft_reset = 0;
  3916. if (rc)
  3917. /* don't go to clean4, we already unallocated */
  3918. return -ENODEV;
  3919. goto reinit_after_soft_reset;
  3920. }
  3921. /* Turn the interrupts on so we can service requests */
  3922. h->access.set_intr_mask(h, HPSA_INTR_ON);
  3923. hpsa_hba_inquiry(h);
  3924. hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
  3925. start_controller_lockup_detector(h);
  3926. return 1;
  3927. clean4:
  3928. hpsa_free_sg_chain_blocks(h);
  3929. hpsa_free_cmd_pool(h);
  3930. free_irq(h->intr[h->intr_mode], h);
  3931. clean2:
  3932. clean1:
  3933. kfree(h);
  3934. return rc;
  3935. }
  3936. static void hpsa_flush_cache(struct ctlr_info *h)
  3937. {
  3938. char *flush_buf;
  3939. struct CommandList *c;
  3940. flush_buf = kzalloc(4, GFP_KERNEL);
  3941. if (!flush_buf)
  3942. return;
  3943. c = cmd_special_alloc(h);
  3944. if (!c) {
  3945. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  3946. goto out_of_memory;
  3947. }
  3948. fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
  3949. RAID_CTLR_LUNID, TYPE_CMD);
  3950. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
  3951. if (c->err_info->CommandStatus != 0)
  3952. dev_warn(&h->pdev->dev,
  3953. "error flushing cache on controller\n");
  3954. cmd_special_free(h, c);
  3955. out_of_memory:
  3956. kfree(flush_buf);
  3957. }
  3958. static void hpsa_shutdown(struct pci_dev *pdev)
  3959. {
  3960. struct ctlr_info *h;
  3961. h = pci_get_drvdata(pdev);
  3962. /* Turn board interrupts off and send the flush cache command
  3963. * sendcmd will turn off interrupt, and send the flush...
  3964. * To write all data in the battery backed cache to disks
  3965. */
  3966. hpsa_flush_cache(h);
  3967. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3968. free_irq(h->intr[h->intr_mode], h);
  3969. #ifdef CONFIG_PCI_MSI
  3970. if (h->msix_vector)
  3971. pci_disable_msix(h->pdev);
  3972. else if (h->msi_vector)
  3973. pci_disable_msi(h->pdev);
  3974. #endif /* CONFIG_PCI_MSI */
  3975. }
  3976. static void __devexit hpsa_remove_one(struct pci_dev *pdev)
  3977. {
  3978. struct ctlr_info *h;
  3979. if (pci_get_drvdata(pdev) == NULL) {
  3980. dev_err(&pdev->dev, "unable to remove device\n");
  3981. return;
  3982. }
  3983. h = pci_get_drvdata(pdev);
  3984. stop_controller_lockup_detector(h);
  3985. hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
  3986. hpsa_shutdown(pdev);
  3987. iounmap(h->vaddr);
  3988. iounmap(h->transtable);
  3989. iounmap(h->cfgtable);
  3990. hpsa_free_sg_chain_blocks(h);
  3991. pci_free_consistent(h->pdev,
  3992. h->nr_cmds * sizeof(struct CommandList),
  3993. h->cmd_pool, h->cmd_pool_dhandle);
  3994. pci_free_consistent(h->pdev,
  3995. h->nr_cmds * sizeof(struct ErrorInfo),
  3996. h->errinfo_pool, h->errinfo_pool_dhandle);
  3997. pci_free_consistent(h->pdev, h->reply_pool_size,
  3998. h->reply_pool, h->reply_pool_dhandle);
  3999. kfree(h->cmd_pool_bits);
  4000. kfree(h->blockFetchTable);
  4001. kfree(h->hba_inquiry_data);
  4002. /*
  4003. * Deliberately omit pci_disable_device(): it does something nasty to
  4004. * Smart Array controllers that pci_enable_device does not undo
  4005. */
  4006. pci_release_regions(pdev);
  4007. pci_set_drvdata(pdev, NULL);
  4008. kfree(h);
  4009. }
  4010. static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
  4011. __attribute__((unused)) pm_message_t state)
  4012. {
  4013. return -ENOSYS;
  4014. }
  4015. static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
  4016. {
  4017. return -ENOSYS;
  4018. }
  4019. static struct pci_driver hpsa_pci_driver = {
  4020. .name = "hpsa",
  4021. .probe = hpsa_init_one,
  4022. .remove = __devexit_p(hpsa_remove_one),
  4023. .id_table = hpsa_pci_device_id, /* id_table */
  4024. .shutdown = hpsa_shutdown,
  4025. .suspend = hpsa_suspend,
  4026. .resume = hpsa_resume,
  4027. };
  4028. /* Fill in bucket_map[], given nsgs (the max number of
  4029. * scatter gather elements supported) and bucket[],
  4030. * which is an array of 8 integers. The bucket[] array
  4031. * contains 8 different DMA transfer sizes (in 16
  4032. * byte increments) which the controller uses to fetch
  4033. * commands. This function fills in bucket_map[], which
  4034. * maps a given number of scatter gather elements to one of
  4035. * the 8 DMA transfer sizes. The point of it is to allow the
  4036. * controller to only do as much DMA as needed to fetch the
  4037. * command, with the DMA transfer size encoded in the lower
  4038. * bits of the command address.
  4039. */
  4040. static void calc_bucket_map(int bucket[], int num_buckets,
  4041. int nsgs, int *bucket_map)
  4042. {
  4043. int i, j, b, size;
  4044. /* even a command with 0 SGs requires 4 blocks */
  4045. #define MINIMUM_TRANSFER_BLOCKS 4
  4046. #define NUM_BUCKETS 8
  4047. /* Note, bucket_map must have nsgs+1 entries. */
  4048. for (i = 0; i <= nsgs; i++) {
  4049. /* Compute size of a command with i SG entries */
  4050. size = i + MINIMUM_TRANSFER_BLOCKS;
  4051. b = num_buckets; /* Assume the biggest bucket */
  4052. /* Find the bucket that is just big enough */
  4053. for (j = 0; j < 8; j++) {
  4054. if (bucket[j] >= size) {
  4055. b = j;
  4056. break;
  4057. }
  4058. }
  4059. /* for a command with i SG entries, use bucket b. */
  4060. bucket_map[i] = b;
  4061. }
  4062. }
  4063. static __devinit void hpsa_enter_performant_mode(struct ctlr_info *h,
  4064. u32 use_short_tags)
  4065. {
  4066. int i;
  4067. unsigned long register_value;
  4068. /* This is a bit complicated. There are 8 registers on
  4069. * the controller which we write to to tell it 8 different
  4070. * sizes of commands which there may be. It's a way of
  4071. * reducing the DMA done to fetch each command. Encoded into
  4072. * each command's tag are 3 bits which communicate to the controller
  4073. * which of the eight sizes that command fits within. The size of
  4074. * each command depends on how many scatter gather entries there are.
  4075. * Each SG entry requires 16 bytes. The eight registers are programmed
  4076. * with the number of 16-byte blocks a command of that size requires.
  4077. * The smallest command possible requires 5 such 16 byte blocks.
  4078. * the largest command possible requires MAXSGENTRIES + 4 16-byte
  4079. * blocks. Note, this only extends to the SG entries contained
  4080. * within the command block, and does not extend to chained blocks
  4081. * of SG elements. bft[] contains the eight values we write to
  4082. * the registers. They are not evenly distributed, but have more
  4083. * sizes for small commands, and fewer sizes for larger commands.
  4084. */
  4085. int bft[8] = {5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
  4086. BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
  4087. /* 5 = 1 s/g entry or 4k
  4088. * 6 = 2 s/g entry or 8k
  4089. * 8 = 4 s/g entry or 16k
  4090. * 10 = 6 s/g entry or 24k
  4091. */
  4092. h->reply_pool_wraparound = 1; /* spec: init to 1 */
  4093. /* Controller spec: zero out this buffer. */
  4094. memset(h->reply_pool, 0, h->reply_pool_size);
  4095. h->reply_pool_head = h->reply_pool;
  4096. bft[7] = h->max_sg_entries + 4;
  4097. calc_bucket_map(bft, ARRAY_SIZE(bft), 32, h->blockFetchTable);
  4098. for (i = 0; i < 8; i++)
  4099. writel(bft[i], &h->transtable->BlockFetch[i]);
  4100. /* size of controller ring buffer */
  4101. writel(h->max_commands, &h->transtable->RepQSize);
  4102. writel(1, &h->transtable->RepQCount);
  4103. writel(0, &h->transtable->RepQCtrAddrLow32);
  4104. writel(0, &h->transtable->RepQCtrAddrHigh32);
  4105. writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
  4106. writel(0, &h->transtable->RepQAddr0High32);
  4107. writel(CFGTBL_Trans_Performant | use_short_tags,
  4108. &(h->cfgtable->HostWrite.TransportRequest));
  4109. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  4110. hpsa_wait_for_mode_change_ack(h);
  4111. register_value = readl(&(h->cfgtable->TransportActive));
  4112. if (!(register_value & CFGTBL_Trans_Performant)) {
  4113. dev_warn(&h->pdev->dev, "unable to get board into"
  4114. " performant mode\n");
  4115. return;
  4116. }
  4117. /* Change the access methods to the performant access methods */
  4118. h->access = SA5_performant_access;
  4119. h->transMethod = CFGTBL_Trans_Performant;
  4120. }
  4121. static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
  4122. {
  4123. u32 trans_support;
  4124. if (hpsa_simple_mode)
  4125. return;
  4126. trans_support = readl(&(h->cfgtable->TransportSupport));
  4127. if (!(trans_support & PERFORMANT_MODE))
  4128. return;
  4129. hpsa_get_max_perf_mode_cmds(h);
  4130. h->max_sg_entries = 32;
  4131. /* Performant mode ring buffer and supporting data structures */
  4132. h->reply_pool_size = h->max_commands * sizeof(u64);
  4133. h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
  4134. &(h->reply_pool_dhandle));
  4135. /* Need a block fetch table for performant mode */
  4136. h->blockFetchTable = kmalloc(((h->max_sg_entries+1) *
  4137. sizeof(u32)), GFP_KERNEL);
  4138. if ((h->reply_pool == NULL)
  4139. || (h->blockFetchTable == NULL))
  4140. goto clean_up;
  4141. hpsa_enter_performant_mode(h,
  4142. trans_support & CFGTBL_Trans_use_short_tags);
  4143. return;
  4144. clean_up:
  4145. if (h->reply_pool)
  4146. pci_free_consistent(h->pdev, h->reply_pool_size,
  4147. h->reply_pool, h->reply_pool_dhandle);
  4148. kfree(h->blockFetchTable);
  4149. }
  4150. /*
  4151. * This is it. Register the PCI driver information for the cards we control
  4152. * the OS will call our registered routines when it finds one of our cards.
  4153. */
  4154. static int __init hpsa_init(void)
  4155. {
  4156. return pci_register_driver(&hpsa_pci_driver);
  4157. }
  4158. static void __exit hpsa_cleanup(void)
  4159. {
  4160. pci_unregister_driver(&hpsa_pci_driver);
  4161. }
  4162. module_init(hpsa_init);
  4163. module_exit(hpsa_cleanup);