hpsa.c 146 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210
  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12. * NON INFRINGEMENT. See the GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. *
  18. * Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/types.h>
  24. #include <linux/pci.h>
  25. #include <linux/pci-aspm.h>
  26. #include <linux/kernel.h>
  27. #include <linux/slab.h>
  28. #include <linux/delay.h>
  29. #include <linux/fs.h>
  30. #include <linux/timer.h>
  31. #include <linux/seq_file.h>
  32. #include <linux/init.h>
  33. #include <linux/spinlock.h>
  34. #include <linux/compat.h>
  35. #include <linux/blktrace_api.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/completion.h>
  40. #include <linux/moduleparam.h>
  41. #include <scsi/scsi.h>
  42. #include <scsi/scsi_cmnd.h>
  43. #include <scsi/scsi_device.h>
  44. #include <scsi/scsi_host.h>
  45. #include <scsi/scsi_tcq.h>
  46. #include <linux/cciss_ioctl.h>
  47. #include <linux/string.h>
  48. #include <linux/bitmap.h>
  49. #include <linux/atomic.h>
  50. #include <linux/kthread.h>
  51. #include <linux/jiffies.h>
  52. #include "hpsa_cmd.h"
  53. #include "hpsa.h"
  54. /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
  55. #define HPSA_DRIVER_VERSION "3.4.0-1"
  56. #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
  57. #define HPSA "hpsa"
  58. /* How long to wait (in milliseconds) for board to go into simple mode */
  59. #define MAX_CONFIG_WAIT 30000
  60. #define MAX_IOCTL_CONFIG_WAIT 1000
  61. /*define how many times we will try a command because of bus resets */
  62. #define MAX_CMD_RETRIES 3
  63. /* Embedded module documentation macros - see modules.h */
  64. MODULE_AUTHOR("Hewlett-Packard Company");
  65. MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
  66. HPSA_DRIVER_VERSION);
  67. MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
  68. MODULE_VERSION(HPSA_DRIVER_VERSION);
  69. MODULE_LICENSE("GPL");
  70. static int hpsa_allow_any;
  71. module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
  72. MODULE_PARM_DESC(hpsa_allow_any,
  73. "Allow hpsa driver to access unknown HP Smart Array hardware");
  74. static int hpsa_simple_mode;
  75. module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(hpsa_simple_mode,
  77. "Use 'simple mode' rather than 'performant mode'");
  78. /* define the PCI info for the cards we can control */
  79. static const struct pci_device_id hpsa_pci_device_id[] = {
  80. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
  81. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
  82. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
  83. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
  84. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
  85. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
  86. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
  87. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
  88. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
  90. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
  91. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
  92. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x334D},
  93. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
  94. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
  95. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
  96. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
  97. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
  98. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
  99. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
  100. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
  101. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
  102. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
  103. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
  104. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
  105. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
  106. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
  107. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
  108. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
  109. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
  110. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
  111. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
  112. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
  113. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
  114. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
  115. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
  116. {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  117. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  118. {0,}
  119. };
  120. MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
  121. /* board_id = Subsystem Device ID & Vendor ID
  122. * product = Marketing Name for the board
  123. * access = Address of the struct of function pointers
  124. */
  125. static struct board_type products[] = {
  126. {0x3241103C, "Smart Array P212", &SA5_access},
  127. {0x3243103C, "Smart Array P410", &SA5_access},
  128. {0x3245103C, "Smart Array P410i", &SA5_access},
  129. {0x3247103C, "Smart Array P411", &SA5_access},
  130. {0x3249103C, "Smart Array P812", &SA5_access},
  131. {0x324A103C, "Smart Array P712m", &SA5_access},
  132. {0x324B103C, "Smart Array P711m", &SA5_access},
  133. {0x3350103C, "Smart Array P222", &SA5_access},
  134. {0x3351103C, "Smart Array P420", &SA5_access},
  135. {0x3352103C, "Smart Array P421", &SA5_access},
  136. {0x3353103C, "Smart Array P822", &SA5_access},
  137. {0x334D103C, "Smart Array P822se", &SA5_access},
  138. {0x3354103C, "Smart Array P420i", &SA5_access},
  139. {0x3355103C, "Smart Array P220i", &SA5_access},
  140. {0x3356103C, "Smart Array P721m", &SA5_access},
  141. {0x1921103C, "Smart Array P830i", &SA5_access},
  142. {0x1922103C, "Smart Array P430", &SA5_access},
  143. {0x1923103C, "Smart Array P431", &SA5_access},
  144. {0x1924103C, "Smart Array P830", &SA5_access},
  145. {0x1926103C, "Smart Array P731m", &SA5_access},
  146. {0x1928103C, "Smart Array P230i", &SA5_access},
  147. {0x1929103C, "Smart Array P530", &SA5_access},
  148. {0x21BD103C, "Smart Array", &SA5_access},
  149. {0x21BE103C, "Smart Array", &SA5_access},
  150. {0x21BF103C, "Smart Array", &SA5_access},
  151. {0x21C0103C, "Smart Array", &SA5_access},
  152. {0x21C1103C, "Smart Array", &SA5_access},
  153. {0x21C2103C, "Smart Array", &SA5_access},
  154. {0x21C3103C, "Smart Array", &SA5_access},
  155. {0x21C4103C, "Smart Array", &SA5_access},
  156. {0x21C5103C, "Smart Array", &SA5_access},
  157. {0x21C7103C, "Smart Array", &SA5_access},
  158. {0x21C8103C, "Smart Array", &SA5_access},
  159. {0x21C9103C, "Smart Array", &SA5_access},
  160. {0xFFFF103C, "Unknown Smart Array", &SA5_access},
  161. };
  162. static int number_of_controllers;
  163. static struct list_head hpsa_ctlr_list = LIST_HEAD_INIT(hpsa_ctlr_list);
  164. static spinlock_t lockup_detector_lock;
  165. static struct task_struct *hpsa_lockup_detector;
  166. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
  167. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
  168. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
  169. static void start_io(struct ctlr_info *h);
  170. #ifdef CONFIG_COMPAT
  171. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
  172. #endif
  173. static void cmd_free(struct ctlr_info *h, struct CommandList *c);
  174. static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
  175. static struct CommandList *cmd_alloc(struct ctlr_info *h);
  176. static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
  177. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  178. void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
  179. int cmd_type);
  180. static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  181. static void hpsa_scan_start(struct Scsi_Host *);
  182. static int hpsa_scan_finished(struct Scsi_Host *sh,
  183. unsigned long elapsed_time);
  184. static int hpsa_change_queue_depth(struct scsi_device *sdev,
  185. int qdepth, int reason);
  186. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
  187. static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
  188. static int hpsa_slave_alloc(struct scsi_device *sdev);
  189. static void hpsa_slave_destroy(struct scsi_device *sdev);
  190. static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
  191. static int check_for_unit_attention(struct ctlr_info *h,
  192. struct CommandList *c);
  193. static void check_ioctl_unit_attention(struct ctlr_info *h,
  194. struct CommandList *c);
  195. /* performant mode helper functions */
  196. static void calc_bucket_map(int *bucket, int num_buckets,
  197. int nsgs, int *bucket_map);
  198. static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
  199. static inline u32 next_command(struct ctlr_info *h, u8 q);
  200. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  201. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  202. u64 *cfg_offset);
  203. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  204. unsigned long *memory_bar);
  205. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
  206. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  207. int wait_for_ready);
  208. static inline void finish_cmd(struct CommandList *c);
  209. #define BOARD_NOT_READY 0
  210. #define BOARD_READY 1
  211. static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
  212. {
  213. unsigned long *priv = shost_priv(sdev->host);
  214. return (struct ctlr_info *) *priv;
  215. }
  216. static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
  217. {
  218. unsigned long *priv = shost_priv(sh);
  219. return (struct ctlr_info *) *priv;
  220. }
  221. static int check_for_unit_attention(struct ctlr_info *h,
  222. struct CommandList *c)
  223. {
  224. if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
  225. return 0;
  226. switch (c->err_info->SenseInfo[12]) {
  227. case STATE_CHANGED:
  228. dev_warn(&h->pdev->dev, HPSA "%d: a state change "
  229. "detected, command retried\n", h->ctlr);
  230. break;
  231. case LUN_FAILED:
  232. dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
  233. "detected, action required\n", h->ctlr);
  234. break;
  235. case REPORT_LUNS_CHANGED:
  236. dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
  237. "changed, action required\n", h->ctlr);
  238. /*
  239. * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
  240. * target (array) devices.
  241. */
  242. break;
  243. case POWER_OR_RESET:
  244. dev_warn(&h->pdev->dev, HPSA "%d: a power on "
  245. "or device reset detected\n", h->ctlr);
  246. break;
  247. case UNIT_ATTENTION_CLEARED:
  248. dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
  249. "cleared by another initiator\n", h->ctlr);
  250. break;
  251. default:
  252. dev_warn(&h->pdev->dev, HPSA "%d: unknown "
  253. "unit attention detected\n", h->ctlr);
  254. break;
  255. }
  256. return 1;
  257. }
  258. static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
  259. {
  260. if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
  261. (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
  262. c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
  263. return 0;
  264. dev_warn(&h->pdev->dev, HPSA "device busy");
  265. return 1;
  266. }
  267. static ssize_t host_store_rescan(struct device *dev,
  268. struct device_attribute *attr,
  269. const char *buf, size_t count)
  270. {
  271. struct ctlr_info *h;
  272. struct Scsi_Host *shost = class_to_shost(dev);
  273. h = shost_to_hba(shost);
  274. hpsa_scan_start(h->scsi_host);
  275. return count;
  276. }
  277. static ssize_t host_show_firmware_revision(struct device *dev,
  278. struct device_attribute *attr, char *buf)
  279. {
  280. struct ctlr_info *h;
  281. struct Scsi_Host *shost = class_to_shost(dev);
  282. unsigned char *fwrev;
  283. h = shost_to_hba(shost);
  284. if (!h->hba_inquiry_data)
  285. return 0;
  286. fwrev = &h->hba_inquiry_data[32];
  287. return snprintf(buf, 20, "%c%c%c%c\n",
  288. fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
  289. }
  290. static ssize_t host_show_commands_outstanding(struct device *dev,
  291. struct device_attribute *attr, char *buf)
  292. {
  293. struct Scsi_Host *shost = class_to_shost(dev);
  294. struct ctlr_info *h = shost_to_hba(shost);
  295. return snprintf(buf, 20, "%d\n", h->commands_outstanding);
  296. }
  297. static ssize_t host_show_transport_mode(struct device *dev,
  298. struct device_attribute *attr, char *buf)
  299. {
  300. struct ctlr_info *h;
  301. struct Scsi_Host *shost = class_to_shost(dev);
  302. h = shost_to_hba(shost);
  303. return snprintf(buf, 20, "%s\n",
  304. h->transMethod & CFGTBL_Trans_Performant ?
  305. "performant" : "simple");
  306. }
  307. /* List of controllers which cannot be hard reset on kexec with reset_devices */
  308. static u32 unresettable_controller[] = {
  309. 0x324a103C, /* Smart Array P712m */
  310. 0x324b103C, /* SmartArray P711m */
  311. 0x3223103C, /* Smart Array P800 */
  312. 0x3234103C, /* Smart Array P400 */
  313. 0x3235103C, /* Smart Array P400i */
  314. 0x3211103C, /* Smart Array E200i */
  315. 0x3212103C, /* Smart Array E200 */
  316. 0x3213103C, /* Smart Array E200i */
  317. 0x3214103C, /* Smart Array E200i */
  318. 0x3215103C, /* Smart Array E200i */
  319. 0x3237103C, /* Smart Array E500 */
  320. 0x323D103C, /* Smart Array P700m */
  321. 0x40800E11, /* Smart Array 5i */
  322. 0x409C0E11, /* Smart Array 6400 */
  323. 0x409D0E11, /* Smart Array 6400 EM */
  324. 0x40700E11, /* Smart Array 5300 */
  325. 0x40820E11, /* Smart Array 532 */
  326. 0x40830E11, /* Smart Array 5312 */
  327. 0x409A0E11, /* Smart Array 641 */
  328. 0x409B0E11, /* Smart Array 642 */
  329. 0x40910E11, /* Smart Array 6i */
  330. };
  331. /* List of controllers which cannot even be soft reset */
  332. static u32 soft_unresettable_controller[] = {
  333. 0x40800E11, /* Smart Array 5i */
  334. 0x40700E11, /* Smart Array 5300 */
  335. 0x40820E11, /* Smart Array 532 */
  336. 0x40830E11, /* Smart Array 5312 */
  337. 0x409A0E11, /* Smart Array 641 */
  338. 0x409B0E11, /* Smart Array 642 */
  339. 0x40910E11, /* Smart Array 6i */
  340. /* Exclude 640x boards. These are two pci devices in one slot
  341. * which share a battery backed cache module. One controls the
  342. * cache, the other accesses the cache through the one that controls
  343. * it. If we reset the one controlling the cache, the other will
  344. * likely not be happy. Just forbid resetting this conjoined mess.
  345. * The 640x isn't really supported by hpsa anyway.
  346. */
  347. 0x409C0E11, /* Smart Array 6400 */
  348. 0x409D0E11, /* Smart Array 6400 EM */
  349. };
  350. static int ctlr_is_hard_resettable(u32 board_id)
  351. {
  352. int i;
  353. for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
  354. if (unresettable_controller[i] == board_id)
  355. return 0;
  356. return 1;
  357. }
  358. static int ctlr_is_soft_resettable(u32 board_id)
  359. {
  360. int i;
  361. for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
  362. if (soft_unresettable_controller[i] == board_id)
  363. return 0;
  364. return 1;
  365. }
  366. static int ctlr_is_resettable(u32 board_id)
  367. {
  368. return ctlr_is_hard_resettable(board_id) ||
  369. ctlr_is_soft_resettable(board_id);
  370. }
  371. static ssize_t host_show_resettable(struct device *dev,
  372. struct device_attribute *attr, char *buf)
  373. {
  374. struct ctlr_info *h;
  375. struct Scsi_Host *shost = class_to_shost(dev);
  376. h = shost_to_hba(shost);
  377. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
  378. }
  379. static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
  380. {
  381. return (scsi3addr[3] & 0xC0) == 0x40;
  382. }
  383. static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
  384. "1(ADM)", "UNKNOWN"
  385. };
  386. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
  387. static ssize_t raid_level_show(struct device *dev,
  388. struct device_attribute *attr, char *buf)
  389. {
  390. ssize_t l = 0;
  391. unsigned char rlevel;
  392. struct ctlr_info *h;
  393. struct scsi_device *sdev;
  394. struct hpsa_scsi_dev_t *hdev;
  395. unsigned long flags;
  396. sdev = to_scsi_device(dev);
  397. h = sdev_to_hba(sdev);
  398. spin_lock_irqsave(&h->lock, flags);
  399. hdev = sdev->hostdata;
  400. if (!hdev) {
  401. spin_unlock_irqrestore(&h->lock, flags);
  402. return -ENODEV;
  403. }
  404. /* Is this even a logical drive? */
  405. if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
  406. spin_unlock_irqrestore(&h->lock, flags);
  407. l = snprintf(buf, PAGE_SIZE, "N/A\n");
  408. return l;
  409. }
  410. rlevel = hdev->raid_level;
  411. spin_unlock_irqrestore(&h->lock, flags);
  412. if (rlevel > RAID_UNKNOWN)
  413. rlevel = RAID_UNKNOWN;
  414. l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
  415. return l;
  416. }
  417. static ssize_t lunid_show(struct device *dev,
  418. struct device_attribute *attr, char *buf)
  419. {
  420. struct ctlr_info *h;
  421. struct scsi_device *sdev;
  422. struct hpsa_scsi_dev_t *hdev;
  423. unsigned long flags;
  424. unsigned char lunid[8];
  425. sdev = to_scsi_device(dev);
  426. h = sdev_to_hba(sdev);
  427. spin_lock_irqsave(&h->lock, flags);
  428. hdev = sdev->hostdata;
  429. if (!hdev) {
  430. spin_unlock_irqrestore(&h->lock, flags);
  431. return -ENODEV;
  432. }
  433. memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
  434. spin_unlock_irqrestore(&h->lock, flags);
  435. return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  436. lunid[0], lunid[1], lunid[2], lunid[3],
  437. lunid[4], lunid[5], lunid[6], lunid[7]);
  438. }
  439. static ssize_t unique_id_show(struct device *dev,
  440. struct device_attribute *attr, char *buf)
  441. {
  442. struct ctlr_info *h;
  443. struct scsi_device *sdev;
  444. struct hpsa_scsi_dev_t *hdev;
  445. unsigned long flags;
  446. unsigned char sn[16];
  447. sdev = to_scsi_device(dev);
  448. h = sdev_to_hba(sdev);
  449. spin_lock_irqsave(&h->lock, flags);
  450. hdev = sdev->hostdata;
  451. if (!hdev) {
  452. spin_unlock_irqrestore(&h->lock, flags);
  453. return -ENODEV;
  454. }
  455. memcpy(sn, hdev->device_id, sizeof(sn));
  456. spin_unlock_irqrestore(&h->lock, flags);
  457. return snprintf(buf, 16 * 2 + 2,
  458. "%02X%02X%02X%02X%02X%02X%02X%02X"
  459. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  460. sn[0], sn[1], sn[2], sn[3],
  461. sn[4], sn[5], sn[6], sn[7],
  462. sn[8], sn[9], sn[10], sn[11],
  463. sn[12], sn[13], sn[14], sn[15]);
  464. }
  465. static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
  466. static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
  467. static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
  468. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  469. static DEVICE_ATTR(firmware_revision, S_IRUGO,
  470. host_show_firmware_revision, NULL);
  471. static DEVICE_ATTR(commands_outstanding, S_IRUGO,
  472. host_show_commands_outstanding, NULL);
  473. static DEVICE_ATTR(transport_mode, S_IRUGO,
  474. host_show_transport_mode, NULL);
  475. static DEVICE_ATTR(resettable, S_IRUGO,
  476. host_show_resettable, NULL);
  477. static struct device_attribute *hpsa_sdev_attrs[] = {
  478. &dev_attr_raid_level,
  479. &dev_attr_lunid,
  480. &dev_attr_unique_id,
  481. NULL,
  482. };
  483. static struct device_attribute *hpsa_shost_attrs[] = {
  484. &dev_attr_rescan,
  485. &dev_attr_firmware_revision,
  486. &dev_attr_commands_outstanding,
  487. &dev_attr_transport_mode,
  488. &dev_attr_resettable,
  489. NULL,
  490. };
  491. static struct scsi_host_template hpsa_driver_template = {
  492. .module = THIS_MODULE,
  493. .name = HPSA,
  494. .proc_name = HPSA,
  495. .queuecommand = hpsa_scsi_queue_command,
  496. .scan_start = hpsa_scan_start,
  497. .scan_finished = hpsa_scan_finished,
  498. .change_queue_depth = hpsa_change_queue_depth,
  499. .this_id = -1,
  500. .use_clustering = ENABLE_CLUSTERING,
  501. .eh_abort_handler = hpsa_eh_abort_handler,
  502. .eh_device_reset_handler = hpsa_eh_device_reset_handler,
  503. .ioctl = hpsa_ioctl,
  504. .slave_alloc = hpsa_slave_alloc,
  505. .slave_destroy = hpsa_slave_destroy,
  506. #ifdef CONFIG_COMPAT
  507. .compat_ioctl = hpsa_compat_ioctl,
  508. #endif
  509. .sdev_attrs = hpsa_sdev_attrs,
  510. .shost_attrs = hpsa_shost_attrs,
  511. .max_sectors = 8192,
  512. };
  513. /* Enqueuing and dequeuing functions for cmdlists. */
  514. static inline void addQ(struct list_head *list, struct CommandList *c)
  515. {
  516. list_add_tail(&c->list, list);
  517. }
  518. static inline u32 next_command(struct ctlr_info *h, u8 q)
  519. {
  520. u32 a;
  521. struct reply_pool *rq = &h->reply_queue[q];
  522. unsigned long flags;
  523. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  524. return h->access.command_completed(h, q);
  525. if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
  526. a = rq->head[rq->current_entry];
  527. rq->current_entry++;
  528. spin_lock_irqsave(&h->lock, flags);
  529. h->commands_outstanding--;
  530. spin_unlock_irqrestore(&h->lock, flags);
  531. } else {
  532. a = FIFO_EMPTY;
  533. }
  534. /* Check for wraparound */
  535. if (rq->current_entry == h->max_commands) {
  536. rq->current_entry = 0;
  537. rq->wraparound ^= 1;
  538. }
  539. return a;
  540. }
  541. /* set_performant_mode: Modify the tag for cciss performant
  542. * set bit 0 for pull model, bits 3-1 for block fetch
  543. * register number
  544. */
  545. static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
  546. {
  547. if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
  548. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  549. if (likely(h->msix_vector))
  550. c->Header.ReplyQueue =
  551. raw_smp_processor_id() % h->nreply_queues;
  552. }
  553. }
  554. static int is_firmware_flash_cmd(u8 *cdb)
  555. {
  556. return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
  557. }
  558. /*
  559. * During firmware flash, the heartbeat register may not update as frequently
  560. * as it should. So we dial down lockup detection during firmware flash. and
  561. * dial it back up when firmware flash completes.
  562. */
  563. #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
  564. #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
  565. static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
  566. struct CommandList *c)
  567. {
  568. if (!is_firmware_flash_cmd(c->Request.CDB))
  569. return;
  570. atomic_inc(&h->firmware_flash_in_progress);
  571. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
  572. }
  573. static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
  574. struct CommandList *c)
  575. {
  576. if (is_firmware_flash_cmd(c->Request.CDB) &&
  577. atomic_dec_and_test(&h->firmware_flash_in_progress))
  578. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  579. }
  580. static void enqueue_cmd_and_start_io(struct ctlr_info *h,
  581. struct CommandList *c)
  582. {
  583. unsigned long flags;
  584. set_performant_mode(h, c);
  585. dial_down_lockup_detection_during_fw_flash(h, c);
  586. spin_lock_irqsave(&h->lock, flags);
  587. addQ(&h->reqQ, c);
  588. h->Qdepth++;
  589. spin_unlock_irqrestore(&h->lock, flags);
  590. start_io(h);
  591. }
  592. static inline void removeQ(struct CommandList *c)
  593. {
  594. if (WARN_ON(list_empty(&c->list)))
  595. return;
  596. list_del_init(&c->list);
  597. }
  598. static inline int is_hba_lunid(unsigned char scsi3addr[])
  599. {
  600. return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
  601. }
  602. static inline int is_scsi_rev_5(struct ctlr_info *h)
  603. {
  604. if (!h->hba_inquiry_data)
  605. return 0;
  606. if ((h->hba_inquiry_data[2] & 0x07) == 5)
  607. return 1;
  608. return 0;
  609. }
  610. static int hpsa_find_target_lun(struct ctlr_info *h,
  611. unsigned char scsi3addr[], int bus, int *target, int *lun)
  612. {
  613. /* finds an unused bus, target, lun for a new physical device
  614. * assumes h->devlock is held
  615. */
  616. int i, found = 0;
  617. DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
  618. bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
  619. for (i = 0; i < h->ndevices; i++) {
  620. if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
  621. __set_bit(h->dev[i]->target, lun_taken);
  622. }
  623. i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
  624. if (i < HPSA_MAX_DEVICES) {
  625. /* *bus = 1; */
  626. *target = i;
  627. *lun = 0;
  628. found = 1;
  629. }
  630. return !found;
  631. }
  632. /* Add an entry into h->dev[] array. */
  633. static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
  634. struct hpsa_scsi_dev_t *device,
  635. struct hpsa_scsi_dev_t *added[], int *nadded)
  636. {
  637. /* assumes h->devlock is held */
  638. int n = h->ndevices;
  639. int i;
  640. unsigned char addr1[8], addr2[8];
  641. struct hpsa_scsi_dev_t *sd;
  642. if (n >= HPSA_MAX_DEVICES) {
  643. dev_err(&h->pdev->dev, "too many devices, some will be "
  644. "inaccessible.\n");
  645. return -1;
  646. }
  647. /* physical devices do not have lun or target assigned until now. */
  648. if (device->lun != -1)
  649. /* Logical device, lun is already assigned. */
  650. goto lun_assigned;
  651. /* If this device a non-zero lun of a multi-lun device
  652. * byte 4 of the 8-byte LUN addr will contain the logical
  653. * unit no, zero otherise.
  654. */
  655. if (device->scsi3addr[4] == 0) {
  656. /* This is not a non-zero lun of a multi-lun device */
  657. if (hpsa_find_target_lun(h, device->scsi3addr,
  658. device->bus, &device->target, &device->lun) != 0)
  659. return -1;
  660. goto lun_assigned;
  661. }
  662. /* This is a non-zero lun of a multi-lun device.
  663. * Search through our list and find the device which
  664. * has the same 8 byte LUN address, excepting byte 4.
  665. * Assign the same bus and target for this new LUN.
  666. * Use the logical unit number from the firmware.
  667. */
  668. memcpy(addr1, device->scsi3addr, 8);
  669. addr1[4] = 0;
  670. for (i = 0; i < n; i++) {
  671. sd = h->dev[i];
  672. memcpy(addr2, sd->scsi3addr, 8);
  673. addr2[4] = 0;
  674. /* differ only in byte 4? */
  675. if (memcmp(addr1, addr2, 8) == 0) {
  676. device->bus = sd->bus;
  677. device->target = sd->target;
  678. device->lun = device->scsi3addr[4];
  679. break;
  680. }
  681. }
  682. if (device->lun == -1) {
  683. dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
  684. " suspect firmware bug or unsupported hardware "
  685. "configuration.\n");
  686. return -1;
  687. }
  688. lun_assigned:
  689. h->dev[n] = device;
  690. h->ndevices++;
  691. added[*nadded] = device;
  692. (*nadded)++;
  693. /* initially, (before registering with scsi layer) we don't
  694. * know our hostno and we don't want to print anything first
  695. * time anyway (the scsi layer's inquiries will show that info)
  696. */
  697. /* if (hostno != -1) */
  698. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
  699. scsi_device_type(device->devtype), hostno,
  700. device->bus, device->target, device->lun);
  701. return 0;
  702. }
  703. /* Update an entry in h->dev[] array. */
  704. static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
  705. int entry, struct hpsa_scsi_dev_t *new_entry)
  706. {
  707. /* assumes h->devlock is held */
  708. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  709. /* Raid level changed. */
  710. h->dev[entry]->raid_level = new_entry->raid_level;
  711. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
  712. scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
  713. new_entry->target, new_entry->lun);
  714. }
  715. /* Replace an entry from h->dev[] array. */
  716. static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
  717. int entry, struct hpsa_scsi_dev_t *new_entry,
  718. struct hpsa_scsi_dev_t *added[], int *nadded,
  719. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  720. {
  721. /* assumes h->devlock is held */
  722. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  723. removed[*nremoved] = h->dev[entry];
  724. (*nremoved)++;
  725. /*
  726. * New physical devices won't have target/lun assigned yet
  727. * so we need to preserve the values in the slot we are replacing.
  728. */
  729. if (new_entry->target == -1) {
  730. new_entry->target = h->dev[entry]->target;
  731. new_entry->lun = h->dev[entry]->lun;
  732. }
  733. h->dev[entry] = new_entry;
  734. added[*nadded] = new_entry;
  735. (*nadded)++;
  736. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
  737. scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
  738. new_entry->target, new_entry->lun);
  739. }
  740. /* Remove an entry from h->dev[] array. */
  741. static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
  742. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  743. {
  744. /* assumes h->devlock is held */
  745. int i;
  746. struct hpsa_scsi_dev_t *sd;
  747. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  748. sd = h->dev[entry];
  749. removed[*nremoved] = h->dev[entry];
  750. (*nremoved)++;
  751. for (i = entry; i < h->ndevices-1; i++)
  752. h->dev[i] = h->dev[i+1];
  753. h->ndevices--;
  754. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
  755. scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
  756. sd->lun);
  757. }
  758. #define SCSI3ADDR_EQ(a, b) ( \
  759. (a)[7] == (b)[7] && \
  760. (a)[6] == (b)[6] && \
  761. (a)[5] == (b)[5] && \
  762. (a)[4] == (b)[4] && \
  763. (a)[3] == (b)[3] && \
  764. (a)[2] == (b)[2] && \
  765. (a)[1] == (b)[1] && \
  766. (a)[0] == (b)[0])
  767. static void fixup_botched_add(struct ctlr_info *h,
  768. struct hpsa_scsi_dev_t *added)
  769. {
  770. /* called when scsi_add_device fails in order to re-adjust
  771. * h->dev[] to match the mid layer's view.
  772. */
  773. unsigned long flags;
  774. int i, j;
  775. spin_lock_irqsave(&h->lock, flags);
  776. for (i = 0; i < h->ndevices; i++) {
  777. if (h->dev[i] == added) {
  778. for (j = i; j < h->ndevices-1; j++)
  779. h->dev[j] = h->dev[j+1];
  780. h->ndevices--;
  781. break;
  782. }
  783. }
  784. spin_unlock_irqrestore(&h->lock, flags);
  785. kfree(added);
  786. }
  787. static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
  788. struct hpsa_scsi_dev_t *dev2)
  789. {
  790. /* we compare everything except lun and target as these
  791. * are not yet assigned. Compare parts likely
  792. * to differ first
  793. */
  794. if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
  795. sizeof(dev1->scsi3addr)) != 0)
  796. return 0;
  797. if (memcmp(dev1->device_id, dev2->device_id,
  798. sizeof(dev1->device_id)) != 0)
  799. return 0;
  800. if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
  801. return 0;
  802. if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
  803. return 0;
  804. if (dev1->devtype != dev2->devtype)
  805. return 0;
  806. if (dev1->bus != dev2->bus)
  807. return 0;
  808. return 1;
  809. }
  810. static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
  811. struct hpsa_scsi_dev_t *dev2)
  812. {
  813. /* Device attributes that can change, but don't mean
  814. * that the device is a different device, nor that the OS
  815. * needs to be told anything about the change.
  816. */
  817. if (dev1->raid_level != dev2->raid_level)
  818. return 1;
  819. return 0;
  820. }
  821. /* Find needle in haystack. If exact match found, return DEVICE_SAME,
  822. * and return needle location in *index. If scsi3addr matches, but not
  823. * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
  824. * location in *index.
  825. * In the case of a minor device attribute change, such as RAID level, just
  826. * return DEVICE_UPDATED, along with the updated device's location in index.
  827. * If needle not found, return DEVICE_NOT_FOUND.
  828. */
  829. static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
  830. struct hpsa_scsi_dev_t *haystack[], int haystack_size,
  831. int *index)
  832. {
  833. int i;
  834. #define DEVICE_NOT_FOUND 0
  835. #define DEVICE_CHANGED 1
  836. #define DEVICE_SAME 2
  837. #define DEVICE_UPDATED 3
  838. for (i = 0; i < haystack_size; i++) {
  839. if (haystack[i] == NULL) /* previously removed. */
  840. continue;
  841. if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
  842. *index = i;
  843. if (device_is_the_same(needle, haystack[i])) {
  844. if (device_updated(needle, haystack[i]))
  845. return DEVICE_UPDATED;
  846. return DEVICE_SAME;
  847. } else {
  848. return DEVICE_CHANGED;
  849. }
  850. }
  851. }
  852. *index = -1;
  853. return DEVICE_NOT_FOUND;
  854. }
  855. static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
  856. struct hpsa_scsi_dev_t *sd[], int nsds)
  857. {
  858. /* sd contains scsi3 addresses and devtypes, and inquiry
  859. * data. This function takes what's in sd to be the current
  860. * reality and updates h->dev[] to reflect that reality.
  861. */
  862. int i, entry, device_change, changes = 0;
  863. struct hpsa_scsi_dev_t *csd;
  864. unsigned long flags;
  865. struct hpsa_scsi_dev_t **added, **removed;
  866. int nadded, nremoved;
  867. struct Scsi_Host *sh = NULL;
  868. added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
  869. removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
  870. if (!added || !removed) {
  871. dev_warn(&h->pdev->dev, "out of memory in "
  872. "adjust_hpsa_scsi_table\n");
  873. goto free_and_out;
  874. }
  875. spin_lock_irqsave(&h->devlock, flags);
  876. /* find any devices in h->dev[] that are not in
  877. * sd[] and remove them from h->dev[], and for any
  878. * devices which have changed, remove the old device
  879. * info and add the new device info.
  880. * If minor device attributes change, just update
  881. * the existing device structure.
  882. */
  883. i = 0;
  884. nremoved = 0;
  885. nadded = 0;
  886. while (i < h->ndevices) {
  887. csd = h->dev[i];
  888. device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
  889. if (device_change == DEVICE_NOT_FOUND) {
  890. changes++;
  891. hpsa_scsi_remove_entry(h, hostno, i,
  892. removed, &nremoved);
  893. continue; /* remove ^^^, hence i not incremented */
  894. } else if (device_change == DEVICE_CHANGED) {
  895. changes++;
  896. hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
  897. added, &nadded, removed, &nremoved);
  898. /* Set it to NULL to prevent it from being freed
  899. * at the bottom of hpsa_update_scsi_devices()
  900. */
  901. sd[entry] = NULL;
  902. } else if (device_change == DEVICE_UPDATED) {
  903. hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
  904. }
  905. i++;
  906. }
  907. /* Now, make sure every device listed in sd[] is also
  908. * listed in h->dev[], adding them if they aren't found
  909. */
  910. for (i = 0; i < nsds; i++) {
  911. if (!sd[i]) /* if already added above. */
  912. continue;
  913. device_change = hpsa_scsi_find_entry(sd[i], h->dev,
  914. h->ndevices, &entry);
  915. if (device_change == DEVICE_NOT_FOUND) {
  916. changes++;
  917. if (hpsa_scsi_add_entry(h, hostno, sd[i],
  918. added, &nadded) != 0)
  919. break;
  920. sd[i] = NULL; /* prevent from being freed later. */
  921. } else if (device_change == DEVICE_CHANGED) {
  922. /* should never happen... */
  923. changes++;
  924. dev_warn(&h->pdev->dev,
  925. "device unexpectedly changed.\n");
  926. /* but if it does happen, we just ignore that device */
  927. }
  928. }
  929. spin_unlock_irqrestore(&h->devlock, flags);
  930. /* Don't notify scsi mid layer of any changes the first time through
  931. * (or if there are no changes) scsi_scan_host will do it later the
  932. * first time through.
  933. */
  934. if (hostno == -1 || !changes)
  935. goto free_and_out;
  936. sh = h->scsi_host;
  937. /* Notify scsi mid layer of any removed devices */
  938. for (i = 0; i < nremoved; i++) {
  939. struct scsi_device *sdev =
  940. scsi_device_lookup(sh, removed[i]->bus,
  941. removed[i]->target, removed[i]->lun);
  942. if (sdev != NULL) {
  943. scsi_remove_device(sdev);
  944. scsi_device_put(sdev);
  945. } else {
  946. /* We don't expect to get here.
  947. * future cmds to this device will get selection
  948. * timeout as if the device was gone.
  949. */
  950. dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
  951. " for removal.", hostno, removed[i]->bus,
  952. removed[i]->target, removed[i]->lun);
  953. }
  954. kfree(removed[i]);
  955. removed[i] = NULL;
  956. }
  957. /* Notify scsi mid layer of any added devices */
  958. for (i = 0; i < nadded; i++) {
  959. if (scsi_add_device(sh, added[i]->bus,
  960. added[i]->target, added[i]->lun) == 0)
  961. continue;
  962. dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
  963. "device not added.\n", hostno, added[i]->bus,
  964. added[i]->target, added[i]->lun);
  965. /* now we have to remove it from h->dev,
  966. * since it didn't get added to scsi mid layer
  967. */
  968. fixup_botched_add(h, added[i]);
  969. }
  970. free_and_out:
  971. kfree(added);
  972. kfree(removed);
  973. }
  974. /*
  975. * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
  976. * Assume's h->devlock is held.
  977. */
  978. static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
  979. int bus, int target, int lun)
  980. {
  981. int i;
  982. struct hpsa_scsi_dev_t *sd;
  983. for (i = 0; i < h->ndevices; i++) {
  984. sd = h->dev[i];
  985. if (sd->bus == bus && sd->target == target && sd->lun == lun)
  986. return sd;
  987. }
  988. return NULL;
  989. }
  990. /* link sdev->hostdata to our per-device structure. */
  991. static int hpsa_slave_alloc(struct scsi_device *sdev)
  992. {
  993. struct hpsa_scsi_dev_t *sd;
  994. unsigned long flags;
  995. struct ctlr_info *h;
  996. h = sdev_to_hba(sdev);
  997. spin_lock_irqsave(&h->devlock, flags);
  998. sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
  999. sdev_id(sdev), sdev->lun);
  1000. if (sd != NULL)
  1001. sdev->hostdata = sd;
  1002. spin_unlock_irqrestore(&h->devlock, flags);
  1003. return 0;
  1004. }
  1005. static void hpsa_slave_destroy(struct scsi_device *sdev)
  1006. {
  1007. /* nothing to do. */
  1008. }
  1009. static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
  1010. {
  1011. int i;
  1012. if (!h->cmd_sg_list)
  1013. return;
  1014. for (i = 0; i < h->nr_cmds; i++) {
  1015. kfree(h->cmd_sg_list[i]);
  1016. h->cmd_sg_list[i] = NULL;
  1017. }
  1018. kfree(h->cmd_sg_list);
  1019. h->cmd_sg_list = NULL;
  1020. }
  1021. static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
  1022. {
  1023. int i;
  1024. if (h->chainsize <= 0)
  1025. return 0;
  1026. h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
  1027. GFP_KERNEL);
  1028. if (!h->cmd_sg_list)
  1029. return -ENOMEM;
  1030. for (i = 0; i < h->nr_cmds; i++) {
  1031. h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
  1032. h->chainsize, GFP_KERNEL);
  1033. if (!h->cmd_sg_list[i])
  1034. goto clean;
  1035. }
  1036. return 0;
  1037. clean:
  1038. hpsa_free_sg_chain_blocks(h);
  1039. return -ENOMEM;
  1040. }
  1041. static int hpsa_map_sg_chain_block(struct ctlr_info *h,
  1042. struct CommandList *c)
  1043. {
  1044. struct SGDescriptor *chain_sg, *chain_block;
  1045. u64 temp64;
  1046. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  1047. chain_block = h->cmd_sg_list[c->cmdindex];
  1048. chain_sg->Ext = HPSA_SG_CHAIN;
  1049. chain_sg->Len = sizeof(*chain_sg) *
  1050. (c->Header.SGTotal - h->max_cmd_sg_entries);
  1051. temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
  1052. PCI_DMA_TODEVICE);
  1053. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  1054. /* prevent subsequent unmapping */
  1055. chain_sg->Addr.lower = 0;
  1056. chain_sg->Addr.upper = 0;
  1057. return -1;
  1058. }
  1059. chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
  1060. chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
  1061. return 0;
  1062. }
  1063. static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
  1064. struct CommandList *c)
  1065. {
  1066. struct SGDescriptor *chain_sg;
  1067. union u64bit temp64;
  1068. if (c->Header.SGTotal <= h->max_cmd_sg_entries)
  1069. return;
  1070. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  1071. temp64.val32.lower = chain_sg->Addr.lower;
  1072. temp64.val32.upper = chain_sg->Addr.upper;
  1073. pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
  1074. }
  1075. static void complete_scsi_command(struct CommandList *cp)
  1076. {
  1077. struct scsi_cmnd *cmd;
  1078. struct ctlr_info *h;
  1079. struct ErrorInfo *ei;
  1080. unsigned char sense_key;
  1081. unsigned char asc; /* additional sense code */
  1082. unsigned char ascq; /* additional sense code qualifier */
  1083. unsigned long sense_data_size;
  1084. ei = cp->err_info;
  1085. cmd = (struct scsi_cmnd *) cp->scsi_cmd;
  1086. h = cp->h;
  1087. scsi_dma_unmap(cmd); /* undo the DMA mappings */
  1088. if (cp->Header.SGTotal > h->max_cmd_sg_entries)
  1089. hpsa_unmap_sg_chain_block(h, cp);
  1090. cmd->result = (DID_OK << 16); /* host byte */
  1091. cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
  1092. cmd->result |= ei->ScsiStatus;
  1093. /* copy the sense data whether we need to or not. */
  1094. if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
  1095. sense_data_size = SCSI_SENSE_BUFFERSIZE;
  1096. else
  1097. sense_data_size = sizeof(ei->SenseInfo);
  1098. if (ei->SenseLen < sense_data_size)
  1099. sense_data_size = ei->SenseLen;
  1100. memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
  1101. scsi_set_resid(cmd, ei->ResidualCnt);
  1102. if (ei->CommandStatus == 0) {
  1103. cmd_free(h, cp);
  1104. cmd->scsi_done(cmd);
  1105. return;
  1106. }
  1107. /* an error has occurred */
  1108. switch (ei->CommandStatus) {
  1109. case CMD_TARGET_STATUS:
  1110. if (ei->ScsiStatus) {
  1111. /* Get sense key */
  1112. sense_key = 0xf & ei->SenseInfo[2];
  1113. /* Get additional sense code */
  1114. asc = ei->SenseInfo[12];
  1115. /* Get addition sense code qualifier */
  1116. ascq = ei->SenseInfo[13];
  1117. }
  1118. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
  1119. if (check_for_unit_attention(h, cp)) {
  1120. cmd->result = DID_SOFT_ERROR << 16;
  1121. break;
  1122. }
  1123. if (sense_key == ILLEGAL_REQUEST) {
  1124. /*
  1125. * SCSI REPORT_LUNS is commonly unsupported on
  1126. * Smart Array. Suppress noisy complaint.
  1127. */
  1128. if (cp->Request.CDB[0] == REPORT_LUNS)
  1129. break;
  1130. /* If ASC/ASCQ indicate Logical Unit
  1131. * Not Supported condition,
  1132. */
  1133. if ((asc == 0x25) && (ascq == 0x0)) {
  1134. dev_warn(&h->pdev->dev, "cp %p "
  1135. "has check condition\n", cp);
  1136. break;
  1137. }
  1138. }
  1139. if (sense_key == NOT_READY) {
  1140. /* If Sense is Not Ready, Logical Unit
  1141. * Not ready, Manual Intervention
  1142. * required
  1143. */
  1144. if ((asc == 0x04) && (ascq == 0x03)) {
  1145. dev_warn(&h->pdev->dev, "cp %p "
  1146. "has check condition: unit "
  1147. "not ready, manual "
  1148. "intervention required\n", cp);
  1149. break;
  1150. }
  1151. }
  1152. if (sense_key == ABORTED_COMMAND) {
  1153. /* Aborted command is retryable */
  1154. dev_warn(&h->pdev->dev, "cp %p "
  1155. "has check condition: aborted command: "
  1156. "ASC: 0x%x, ASCQ: 0x%x\n",
  1157. cp, asc, ascq);
  1158. cmd->result = DID_SOFT_ERROR << 16;
  1159. break;
  1160. }
  1161. /* Must be some other type of check condition */
  1162. dev_dbg(&h->pdev->dev, "cp %p has check condition: "
  1163. "unknown type: "
  1164. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  1165. "Returning result: 0x%x, "
  1166. "cmd=[%02x %02x %02x %02x %02x "
  1167. "%02x %02x %02x %02x %02x %02x "
  1168. "%02x %02x %02x %02x %02x]\n",
  1169. cp, sense_key, asc, ascq,
  1170. cmd->result,
  1171. cmd->cmnd[0], cmd->cmnd[1],
  1172. cmd->cmnd[2], cmd->cmnd[3],
  1173. cmd->cmnd[4], cmd->cmnd[5],
  1174. cmd->cmnd[6], cmd->cmnd[7],
  1175. cmd->cmnd[8], cmd->cmnd[9],
  1176. cmd->cmnd[10], cmd->cmnd[11],
  1177. cmd->cmnd[12], cmd->cmnd[13],
  1178. cmd->cmnd[14], cmd->cmnd[15]);
  1179. break;
  1180. }
  1181. /* Problem was not a check condition
  1182. * Pass it up to the upper layers...
  1183. */
  1184. if (ei->ScsiStatus) {
  1185. dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
  1186. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  1187. "Returning result: 0x%x\n",
  1188. cp, ei->ScsiStatus,
  1189. sense_key, asc, ascq,
  1190. cmd->result);
  1191. } else { /* scsi status is zero??? How??? */
  1192. dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
  1193. "Returning no connection.\n", cp),
  1194. /* Ordinarily, this case should never happen,
  1195. * but there is a bug in some released firmware
  1196. * revisions that allows it to happen if, for
  1197. * example, a 4100 backplane loses power and
  1198. * the tape drive is in it. We assume that
  1199. * it's a fatal error of some kind because we
  1200. * can't show that it wasn't. We will make it
  1201. * look like selection timeout since that is
  1202. * the most common reason for this to occur,
  1203. * and it's severe enough.
  1204. */
  1205. cmd->result = DID_NO_CONNECT << 16;
  1206. }
  1207. break;
  1208. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  1209. break;
  1210. case CMD_DATA_OVERRUN:
  1211. dev_warn(&h->pdev->dev, "cp %p has"
  1212. " completed with data overrun "
  1213. "reported\n", cp);
  1214. break;
  1215. case CMD_INVALID: {
  1216. /* print_bytes(cp, sizeof(*cp), 1, 0);
  1217. print_cmd(cp); */
  1218. /* We get CMD_INVALID if you address a non-existent device
  1219. * instead of a selection timeout (no response). You will
  1220. * see this if you yank out a drive, then try to access it.
  1221. * This is kind of a shame because it means that any other
  1222. * CMD_INVALID (e.g. driver bug) will get interpreted as a
  1223. * missing target. */
  1224. cmd->result = DID_NO_CONNECT << 16;
  1225. }
  1226. break;
  1227. case CMD_PROTOCOL_ERR:
  1228. cmd->result = DID_ERROR << 16;
  1229. dev_warn(&h->pdev->dev, "cp %p has "
  1230. "protocol error\n", cp);
  1231. break;
  1232. case CMD_HARDWARE_ERR:
  1233. cmd->result = DID_ERROR << 16;
  1234. dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
  1235. break;
  1236. case CMD_CONNECTION_LOST:
  1237. cmd->result = DID_ERROR << 16;
  1238. dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
  1239. break;
  1240. case CMD_ABORTED:
  1241. cmd->result = DID_ABORT << 16;
  1242. dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
  1243. cp, ei->ScsiStatus);
  1244. break;
  1245. case CMD_ABORT_FAILED:
  1246. cmd->result = DID_ERROR << 16;
  1247. dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
  1248. break;
  1249. case CMD_UNSOLICITED_ABORT:
  1250. cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
  1251. dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
  1252. "abort\n", cp);
  1253. break;
  1254. case CMD_TIMEOUT:
  1255. cmd->result = DID_TIME_OUT << 16;
  1256. dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
  1257. break;
  1258. case CMD_UNABORTABLE:
  1259. cmd->result = DID_ERROR << 16;
  1260. dev_warn(&h->pdev->dev, "Command unabortable\n");
  1261. break;
  1262. default:
  1263. cmd->result = DID_ERROR << 16;
  1264. dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
  1265. cp, ei->CommandStatus);
  1266. }
  1267. cmd_free(h, cp);
  1268. cmd->scsi_done(cmd);
  1269. }
  1270. static void hpsa_pci_unmap(struct pci_dev *pdev,
  1271. struct CommandList *c, int sg_used, int data_direction)
  1272. {
  1273. int i;
  1274. union u64bit addr64;
  1275. for (i = 0; i < sg_used; i++) {
  1276. addr64.val32.lower = c->SG[i].Addr.lower;
  1277. addr64.val32.upper = c->SG[i].Addr.upper;
  1278. pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
  1279. data_direction);
  1280. }
  1281. }
  1282. static int hpsa_map_one(struct pci_dev *pdev,
  1283. struct CommandList *cp,
  1284. unsigned char *buf,
  1285. size_t buflen,
  1286. int data_direction)
  1287. {
  1288. u64 addr64;
  1289. if (buflen == 0 || data_direction == PCI_DMA_NONE) {
  1290. cp->Header.SGList = 0;
  1291. cp->Header.SGTotal = 0;
  1292. return 0;
  1293. }
  1294. addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
  1295. if (dma_mapping_error(&pdev->dev, addr64)) {
  1296. /* Prevent subsequent unmap of something never mapped */
  1297. cp->Header.SGList = 0;
  1298. cp->Header.SGTotal = 0;
  1299. return -1;
  1300. }
  1301. cp->SG[0].Addr.lower =
  1302. (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
  1303. cp->SG[0].Addr.upper =
  1304. (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
  1305. cp->SG[0].Len = buflen;
  1306. cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
  1307. cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
  1308. return 0;
  1309. }
  1310. static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
  1311. struct CommandList *c)
  1312. {
  1313. DECLARE_COMPLETION_ONSTACK(wait);
  1314. c->waiting = &wait;
  1315. enqueue_cmd_and_start_io(h, c);
  1316. wait_for_completion(&wait);
  1317. }
  1318. static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
  1319. struct CommandList *c)
  1320. {
  1321. unsigned long flags;
  1322. /* If controller lockup detected, fake a hardware error. */
  1323. spin_lock_irqsave(&h->lock, flags);
  1324. if (unlikely(h->lockup_detected)) {
  1325. spin_unlock_irqrestore(&h->lock, flags);
  1326. c->err_info->CommandStatus = CMD_HARDWARE_ERR;
  1327. } else {
  1328. spin_unlock_irqrestore(&h->lock, flags);
  1329. hpsa_scsi_do_simple_cmd_core(h, c);
  1330. }
  1331. }
  1332. #define MAX_DRIVER_CMD_RETRIES 25
  1333. static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
  1334. struct CommandList *c, int data_direction)
  1335. {
  1336. int backoff_time = 10, retry_count = 0;
  1337. do {
  1338. memset(c->err_info, 0, sizeof(*c->err_info));
  1339. hpsa_scsi_do_simple_cmd_core(h, c);
  1340. retry_count++;
  1341. if (retry_count > 3) {
  1342. msleep(backoff_time);
  1343. if (backoff_time < 1000)
  1344. backoff_time *= 2;
  1345. }
  1346. } while ((check_for_unit_attention(h, c) ||
  1347. check_for_busy(h, c)) &&
  1348. retry_count <= MAX_DRIVER_CMD_RETRIES);
  1349. hpsa_pci_unmap(h->pdev, c, 1, data_direction);
  1350. }
  1351. static void hpsa_scsi_interpret_error(struct CommandList *cp)
  1352. {
  1353. struct ErrorInfo *ei;
  1354. struct device *d = &cp->h->pdev->dev;
  1355. ei = cp->err_info;
  1356. switch (ei->CommandStatus) {
  1357. case CMD_TARGET_STATUS:
  1358. dev_warn(d, "cmd %p has completed with errors\n", cp);
  1359. dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
  1360. ei->ScsiStatus);
  1361. if (ei->ScsiStatus == 0)
  1362. dev_warn(d, "SCSI status is abnormally zero. "
  1363. "(probably indicates selection timeout "
  1364. "reported incorrectly due to a known "
  1365. "firmware bug, circa July, 2001.)\n");
  1366. break;
  1367. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  1368. dev_info(d, "UNDERRUN\n");
  1369. break;
  1370. case CMD_DATA_OVERRUN:
  1371. dev_warn(d, "cp %p has completed with data overrun\n", cp);
  1372. break;
  1373. case CMD_INVALID: {
  1374. /* controller unfortunately reports SCSI passthru's
  1375. * to non-existent targets as invalid commands.
  1376. */
  1377. dev_warn(d, "cp %p is reported invalid (probably means "
  1378. "target device no longer present)\n", cp);
  1379. /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
  1380. print_cmd(cp); */
  1381. }
  1382. break;
  1383. case CMD_PROTOCOL_ERR:
  1384. dev_warn(d, "cp %p has protocol error \n", cp);
  1385. break;
  1386. case CMD_HARDWARE_ERR:
  1387. /* cmd->result = DID_ERROR << 16; */
  1388. dev_warn(d, "cp %p had hardware error\n", cp);
  1389. break;
  1390. case CMD_CONNECTION_LOST:
  1391. dev_warn(d, "cp %p had connection lost\n", cp);
  1392. break;
  1393. case CMD_ABORTED:
  1394. dev_warn(d, "cp %p was aborted\n", cp);
  1395. break;
  1396. case CMD_ABORT_FAILED:
  1397. dev_warn(d, "cp %p reports abort failed\n", cp);
  1398. break;
  1399. case CMD_UNSOLICITED_ABORT:
  1400. dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
  1401. break;
  1402. case CMD_TIMEOUT:
  1403. dev_warn(d, "cp %p timed out\n", cp);
  1404. break;
  1405. case CMD_UNABORTABLE:
  1406. dev_warn(d, "Command unabortable\n");
  1407. break;
  1408. default:
  1409. dev_warn(d, "cp %p returned unknown status %x\n", cp,
  1410. ei->CommandStatus);
  1411. }
  1412. }
  1413. static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
  1414. unsigned char page, unsigned char *buf,
  1415. unsigned char bufsize)
  1416. {
  1417. int rc = IO_OK;
  1418. struct CommandList *c;
  1419. struct ErrorInfo *ei;
  1420. c = cmd_special_alloc(h);
  1421. if (c == NULL) { /* trouble... */
  1422. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1423. return -ENOMEM;
  1424. }
  1425. if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
  1426. page, scsi3addr, TYPE_CMD)) {
  1427. rc = -1;
  1428. goto out;
  1429. }
  1430. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
  1431. ei = c->err_info;
  1432. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  1433. hpsa_scsi_interpret_error(c);
  1434. rc = -1;
  1435. }
  1436. out:
  1437. cmd_special_free(h, c);
  1438. return rc;
  1439. }
  1440. static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr)
  1441. {
  1442. int rc = IO_OK;
  1443. struct CommandList *c;
  1444. struct ErrorInfo *ei;
  1445. c = cmd_special_alloc(h);
  1446. if (c == NULL) { /* trouble... */
  1447. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1448. return -ENOMEM;
  1449. }
  1450. /* fill_cmd can't fail here, no data buffer to map. */
  1451. (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h,
  1452. NULL, 0, 0, scsi3addr, TYPE_MSG);
  1453. hpsa_scsi_do_simple_cmd_core(h, c);
  1454. /* no unmap needed here because no data xfer. */
  1455. ei = c->err_info;
  1456. if (ei->CommandStatus != 0) {
  1457. hpsa_scsi_interpret_error(c);
  1458. rc = -1;
  1459. }
  1460. cmd_special_free(h, c);
  1461. return rc;
  1462. }
  1463. static void hpsa_get_raid_level(struct ctlr_info *h,
  1464. unsigned char *scsi3addr, unsigned char *raid_level)
  1465. {
  1466. int rc;
  1467. unsigned char *buf;
  1468. *raid_level = RAID_UNKNOWN;
  1469. buf = kzalloc(64, GFP_KERNEL);
  1470. if (!buf)
  1471. return;
  1472. rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
  1473. if (rc == 0)
  1474. *raid_level = buf[8];
  1475. if (*raid_level > RAID_UNKNOWN)
  1476. *raid_level = RAID_UNKNOWN;
  1477. kfree(buf);
  1478. return;
  1479. }
  1480. /* Get the device id from inquiry page 0x83 */
  1481. static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
  1482. unsigned char *device_id, int buflen)
  1483. {
  1484. int rc;
  1485. unsigned char *buf;
  1486. if (buflen > 16)
  1487. buflen = 16;
  1488. buf = kzalloc(64, GFP_KERNEL);
  1489. if (!buf)
  1490. return -1;
  1491. rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
  1492. if (rc == 0)
  1493. memcpy(device_id, &buf[8], buflen);
  1494. kfree(buf);
  1495. return rc != 0;
  1496. }
  1497. static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
  1498. struct ReportLUNdata *buf, int bufsize,
  1499. int extended_response)
  1500. {
  1501. int rc = IO_OK;
  1502. struct CommandList *c;
  1503. unsigned char scsi3addr[8];
  1504. struct ErrorInfo *ei;
  1505. c = cmd_special_alloc(h);
  1506. if (c == NULL) { /* trouble... */
  1507. dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1508. return -1;
  1509. }
  1510. /* address the controller */
  1511. memset(scsi3addr, 0, sizeof(scsi3addr));
  1512. if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
  1513. buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
  1514. rc = -1;
  1515. goto out;
  1516. }
  1517. if (extended_response)
  1518. c->Request.CDB[1] = extended_response;
  1519. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
  1520. ei = c->err_info;
  1521. if (ei->CommandStatus != 0 &&
  1522. ei->CommandStatus != CMD_DATA_UNDERRUN) {
  1523. hpsa_scsi_interpret_error(c);
  1524. rc = -1;
  1525. }
  1526. out:
  1527. cmd_special_free(h, c);
  1528. return rc;
  1529. }
  1530. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  1531. struct ReportLUNdata *buf,
  1532. int bufsize, int extended_response)
  1533. {
  1534. return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
  1535. }
  1536. static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
  1537. struct ReportLUNdata *buf, int bufsize)
  1538. {
  1539. return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
  1540. }
  1541. static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
  1542. int bus, int target, int lun)
  1543. {
  1544. device->bus = bus;
  1545. device->target = target;
  1546. device->lun = lun;
  1547. }
  1548. static int hpsa_update_device_info(struct ctlr_info *h,
  1549. unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
  1550. unsigned char *is_OBDR_device)
  1551. {
  1552. #define OBDR_SIG_OFFSET 43
  1553. #define OBDR_TAPE_SIG "$DR-10"
  1554. #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
  1555. #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
  1556. unsigned char *inq_buff;
  1557. unsigned char *obdr_sig;
  1558. inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
  1559. if (!inq_buff)
  1560. goto bail_out;
  1561. /* Do an inquiry to the device to see what it is. */
  1562. if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
  1563. (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
  1564. /* Inquiry failed (msg printed already) */
  1565. dev_err(&h->pdev->dev,
  1566. "hpsa_update_device_info: inquiry failed\n");
  1567. goto bail_out;
  1568. }
  1569. this_device->devtype = (inq_buff[0] & 0x1f);
  1570. memcpy(this_device->scsi3addr, scsi3addr, 8);
  1571. memcpy(this_device->vendor, &inq_buff[8],
  1572. sizeof(this_device->vendor));
  1573. memcpy(this_device->model, &inq_buff[16],
  1574. sizeof(this_device->model));
  1575. memset(this_device->device_id, 0,
  1576. sizeof(this_device->device_id));
  1577. hpsa_get_device_id(h, scsi3addr, this_device->device_id,
  1578. sizeof(this_device->device_id));
  1579. if (this_device->devtype == TYPE_DISK &&
  1580. is_logical_dev_addr_mode(scsi3addr))
  1581. hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
  1582. else
  1583. this_device->raid_level = RAID_UNKNOWN;
  1584. if (is_OBDR_device) {
  1585. /* See if this is a One-Button-Disaster-Recovery device
  1586. * by looking for "$DR-10" at offset 43 in inquiry data.
  1587. */
  1588. obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
  1589. *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
  1590. strncmp(obdr_sig, OBDR_TAPE_SIG,
  1591. OBDR_SIG_LEN) == 0);
  1592. }
  1593. kfree(inq_buff);
  1594. return 0;
  1595. bail_out:
  1596. kfree(inq_buff);
  1597. return 1;
  1598. }
  1599. static unsigned char *ext_target_model[] = {
  1600. "MSA2012",
  1601. "MSA2024",
  1602. "MSA2312",
  1603. "MSA2324",
  1604. "P2000 G3 SAS",
  1605. NULL,
  1606. };
  1607. static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
  1608. {
  1609. int i;
  1610. for (i = 0; ext_target_model[i]; i++)
  1611. if (strncmp(device->model, ext_target_model[i],
  1612. strlen(ext_target_model[i])) == 0)
  1613. return 1;
  1614. return 0;
  1615. }
  1616. /* Helper function to assign bus, target, lun mapping of devices.
  1617. * Puts non-external target logical volumes on bus 0, external target logical
  1618. * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
  1619. * Logical drive target and lun are assigned at this time, but
  1620. * physical device lun and target assignment are deferred (assigned
  1621. * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
  1622. */
  1623. static void figure_bus_target_lun(struct ctlr_info *h,
  1624. u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
  1625. {
  1626. u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
  1627. if (!is_logical_dev_addr_mode(lunaddrbytes)) {
  1628. /* physical device, target and lun filled in later */
  1629. if (is_hba_lunid(lunaddrbytes))
  1630. hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
  1631. else
  1632. /* defer target, lun assignment for physical devices */
  1633. hpsa_set_bus_target_lun(device, 2, -1, -1);
  1634. return;
  1635. }
  1636. /* It's a logical device */
  1637. if (is_ext_target(h, device)) {
  1638. /* external target way, put logicals on bus 1
  1639. * and match target/lun numbers box
  1640. * reports, other smart array, bus 0, target 0, match lunid
  1641. */
  1642. hpsa_set_bus_target_lun(device,
  1643. 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
  1644. return;
  1645. }
  1646. hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
  1647. }
  1648. /*
  1649. * If there is no lun 0 on a target, linux won't find any devices.
  1650. * For the external targets (arrays), we have to manually detect the enclosure
  1651. * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
  1652. * it for some reason. *tmpdevice is the target we're adding,
  1653. * this_device is a pointer into the current element of currentsd[]
  1654. * that we're building up in update_scsi_devices(), below.
  1655. * lunzerobits is a bitmap that tracks which targets already have a
  1656. * lun 0 assigned.
  1657. * Returns 1 if an enclosure was added, 0 if not.
  1658. */
  1659. static int add_ext_target_dev(struct ctlr_info *h,
  1660. struct hpsa_scsi_dev_t *tmpdevice,
  1661. struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
  1662. unsigned long lunzerobits[], int *n_ext_target_devs)
  1663. {
  1664. unsigned char scsi3addr[8];
  1665. if (test_bit(tmpdevice->target, lunzerobits))
  1666. return 0; /* There is already a lun 0 on this target. */
  1667. if (!is_logical_dev_addr_mode(lunaddrbytes))
  1668. return 0; /* It's the logical targets that may lack lun 0. */
  1669. if (!is_ext_target(h, tmpdevice))
  1670. return 0; /* Only external target devices have this problem. */
  1671. if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
  1672. return 0;
  1673. memset(scsi3addr, 0, 8);
  1674. scsi3addr[3] = tmpdevice->target;
  1675. if (is_hba_lunid(scsi3addr))
  1676. return 0; /* Don't add the RAID controller here. */
  1677. if (is_scsi_rev_5(h))
  1678. return 0; /* p1210m doesn't need to do this. */
  1679. if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
  1680. dev_warn(&h->pdev->dev, "Maximum number of external "
  1681. "target devices exceeded. Check your hardware "
  1682. "configuration.");
  1683. return 0;
  1684. }
  1685. if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
  1686. return 0;
  1687. (*n_ext_target_devs)++;
  1688. hpsa_set_bus_target_lun(this_device,
  1689. tmpdevice->bus, tmpdevice->target, 0);
  1690. set_bit(tmpdevice->target, lunzerobits);
  1691. return 1;
  1692. }
  1693. /*
  1694. * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
  1695. * logdev. The number of luns in physdev and logdev are returned in
  1696. * *nphysicals and *nlogicals, respectively.
  1697. * Returns 0 on success, -1 otherwise.
  1698. */
  1699. static int hpsa_gather_lun_info(struct ctlr_info *h,
  1700. int reportlunsize,
  1701. struct ReportLUNdata *physdev, u32 *nphysicals,
  1702. struct ReportLUNdata *logdev, u32 *nlogicals)
  1703. {
  1704. if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize, 0)) {
  1705. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  1706. return -1;
  1707. }
  1708. *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 8;
  1709. if (*nphysicals > HPSA_MAX_PHYS_LUN) {
  1710. dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
  1711. " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  1712. *nphysicals - HPSA_MAX_PHYS_LUN);
  1713. *nphysicals = HPSA_MAX_PHYS_LUN;
  1714. }
  1715. if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
  1716. dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
  1717. return -1;
  1718. }
  1719. *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
  1720. /* Reject Logicals in excess of our max capability. */
  1721. if (*nlogicals > HPSA_MAX_LUN) {
  1722. dev_warn(&h->pdev->dev,
  1723. "maximum logical LUNs (%d) exceeded. "
  1724. "%d LUNs ignored.\n", HPSA_MAX_LUN,
  1725. *nlogicals - HPSA_MAX_LUN);
  1726. *nlogicals = HPSA_MAX_LUN;
  1727. }
  1728. if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
  1729. dev_warn(&h->pdev->dev,
  1730. "maximum logical + physical LUNs (%d) exceeded. "
  1731. "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  1732. *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
  1733. *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
  1734. }
  1735. return 0;
  1736. }
  1737. u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
  1738. int nphysicals, int nlogicals, struct ReportLUNdata *physdev_list,
  1739. struct ReportLUNdata *logdev_list)
  1740. {
  1741. /* Helper function, figure out where the LUN ID info is coming from
  1742. * given index i, lists of physical and logical devices, where in
  1743. * the list the raid controller is supposed to appear (first or last)
  1744. */
  1745. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  1746. int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
  1747. if (i == raid_ctlr_position)
  1748. return RAID_CTLR_LUNID;
  1749. if (i < logicals_start)
  1750. return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
  1751. if (i < last_device)
  1752. return &logdev_list->LUN[i - nphysicals -
  1753. (raid_ctlr_position == 0)][0];
  1754. BUG();
  1755. return NULL;
  1756. }
  1757. static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
  1758. {
  1759. /* the idea here is we could get notified
  1760. * that some devices have changed, so we do a report
  1761. * physical luns and report logical luns cmd, and adjust
  1762. * our list of devices accordingly.
  1763. *
  1764. * The scsi3addr's of devices won't change so long as the
  1765. * adapter is not reset. That means we can rescan and
  1766. * tell which devices we already know about, vs. new
  1767. * devices, vs. disappearing devices.
  1768. */
  1769. struct ReportLUNdata *physdev_list = NULL;
  1770. struct ReportLUNdata *logdev_list = NULL;
  1771. u32 nphysicals = 0;
  1772. u32 nlogicals = 0;
  1773. u32 ndev_allocated = 0;
  1774. struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
  1775. int ncurrent = 0;
  1776. int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 8;
  1777. int i, n_ext_target_devs, ndevs_to_allocate;
  1778. int raid_ctlr_position;
  1779. DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
  1780. currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
  1781. physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
  1782. logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
  1783. tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
  1784. if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
  1785. dev_err(&h->pdev->dev, "out of memory\n");
  1786. goto out;
  1787. }
  1788. memset(lunzerobits, 0, sizeof(lunzerobits));
  1789. if (hpsa_gather_lun_info(h, reportlunsize, physdev_list, &nphysicals,
  1790. logdev_list, &nlogicals))
  1791. goto out;
  1792. /* We might see up to the maximum number of logical and physical disks
  1793. * plus external target devices, and a device for the local RAID
  1794. * controller.
  1795. */
  1796. ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
  1797. /* Allocate the per device structures */
  1798. for (i = 0; i < ndevs_to_allocate; i++) {
  1799. if (i >= HPSA_MAX_DEVICES) {
  1800. dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
  1801. " %d devices ignored.\n", HPSA_MAX_DEVICES,
  1802. ndevs_to_allocate - HPSA_MAX_DEVICES);
  1803. break;
  1804. }
  1805. currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
  1806. if (!currentsd[i]) {
  1807. dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
  1808. __FILE__, __LINE__);
  1809. goto out;
  1810. }
  1811. ndev_allocated++;
  1812. }
  1813. if (unlikely(is_scsi_rev_5(h)))
  1814. raid_ctlr_position = 0;
  1815. else
  1816. raid_ctlr_position = nphysicals + nlogicals;
  1817. /* adjust our table of devices */
  1818. n_ext_target_devs = 0;
  1819. for (i = 0; i < nphysicals + nlogicals + 1; i++) {
  1820. u8 *lunaddrbytes, is_OBDR = 0;
  1821. /* Figure out where the LUN ID info is coming from */
  1822. lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
  1823. i, nphysicals, nlogicals, physdev_list, logdev_list);
  1824. /* skip masked physical devices. */
  1825. if (lunaddrbytes[3] & 0xC0 &&
  1826. i < nphysicals + (raid_ctlr_position == 0))
  1827. continue;
  1828. /* Get device type, vendor, model, device id */
  1829. if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
  1830. &is_OBDR))
  1831. continue; /* skip it if we can't talk to it. */
  1832. figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
  1833. this_device = currentsd[ncurrent];
  1834. /*
  1835. * For external target devices, we have to insert a LUN 0 which
  1836. * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
  1837. * is nonetheless an enclosure device there. We have to
  1838. * present that otherwise linux won't find anything if
  1839. * there is no lun 0.
  1840. */
  1841. if (add_ext_target_dev(h, tmpdevice, this_device,
  1842. lunaddrbytes, lunzerobits,
  1843. &n_ext_target_devs)) {
  1844. ncurrent++;
  1845. this_device = currentsd[ncurrent];
  1846. }
  1847. *this_device = *tmpdevice;
  1848. switch (this_device->devtype) {
  1849. case TYPE_ROM:
  1850. /* We don't *really* support actual CD-ROM devices,
  1851. * just "One Button Disaster Recovery" tape drive
  1852. * which temporarily pretends to be a CD-ROM drive.
  1853. * So we check that the device is really an OBDR tape
  1854. * device by checking for "$DR-10" in bytes 43-48 of
  1855. * the inquiry data.
  1856. */
  1857. if (is_OBDR)
  1858. ncurrent++;
  1859. break;
  1860. case TYPE_DISK:
  1861. if (i < nphysicals)
  1862. break;
  1863. ncurrent++;
  1864. break;
  1865. case TYPE_TAPE:
  1866. case TYPE_MEDIUM_CHANGER:
  1867. ncurrent++;
  1868. break;
  1869. case TYPE_RAID:
  1870. /* Only present the Smartarray HBA as a RAID controller.
  1871. * If it's a RAID controller other than the HBA itself
  1872. * (an external RAID controller, MSA500 or similar)
  1873. * don't present it.
  1874. */
  1875. if (!is_hba_lunid(lunaddrbytes))
  1876. break;
  1877. ncurrent++;
  1878. break;
  1879. default:
  1880. break;
  1881. }
  1882. if (ncurrent >= HPSA_MAX_DEVICES)
  1883. break;
  1884. }
  1885. adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
  1886. out:
  1887. kfree(tmpdevice);
  1888. for (i = 0; i < ndev_allocated; i++)
  1889. kfree(currentsd[i]);
  1890. kfree(currentsd);
  1891. kfree(physdev_list);
  1892. kfree(logdev_list);
  1893. }
  1894. /* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
  1895. * dma mapping and fills in the scatter gather entries of the
  1896. * hpsa command, cp.
  1897. */
  1898. static int hpsa_scatter_gather(struct ctlr_info *h,
  1899. struct CommandList *cp,
  1900. struct scsi_cmnd *cmd)
  1901. {
  1902. unsigned int len;
  1903. struct scatterlist *sg;
  1904. u64 addr64;
  1905. int use_sg, i, sg_index, chained;
  1906. struct SGDescriptor *curr_sg;
  1907. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  1908. use_sg = scsi_dma_map(cmd);
  1909. if (use_sg < 0)
  1910. return use_sg;
  1911. if (!use_sg)
  1912. goto sglist_finished;
  1913. curr_sg = cp->SG;
  1914. chained = 0;
  1915. sg_index = 0;
  1916. scsi_for_each_sg(cmd, sg, use_sg, i) {
  1917. if (i == h->max_cmd_sg_entries - 1 &&
  1918. use_sg > h->max_cmd_sg_entries) {
  1919. chained = 1;
  1920. curr_sg = h->cmd_sg_list[cp->cmdindex];
  1921. sg_index = 0;
  1922. }
  1923. addr64 = (u64) sg_dma_address(sg);
  1924. len = sg_dma_len(sg);
  1925. curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
  1926. curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
  1927. curr_sg->Len = len;
  1928. curr_sg->Ext = 0; /* we are not chaining */
  1929. curr_sg++;
  1930. }
  1931. if (use_sg + chained > h->maxSG)
  1932. h->maxSG = use_sg + chained;
  1933. if (chained) {
  1934. cp->Header.SGList = h->max_cmd_sg_entries;
  1935. cp->Header.SGTotal = (u16) (use_sg + 1);
  1936. if (hpsa_map_sg_chain_block(h, cp)) {
  1937. scsi_dma_unmap(cmd);
  1938. return -1;
  1939. }
  1940. return 0;
  1941. }
  1942. sglist_finished:
  1943. cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
  1944. cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
  1945. return 0;
  1946. }
  1947. static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
  1948. void (*done)(struct scsi_cmnd *))
  1949. {
  1950. struct ctlr_info *h;
  1951. struct hpsa_scsi_dev_t *dev;
  1952. unsigned char scsi3addr[8];
  1953. struct CommandList *c;
  1954. unsigned long flags;
  1955. /* Get the ptr to our adapter structure out of cmd->host. */
  1956. h = sdev_to_hba(cmd->device);
  1957. dev = cmd->device->hostdata;
  1958. if (!dev) {
  1959. cmd->result = DID_NO_CONNECT << 16;
  1960. done(cmd);
  1961. return 0;
  1962. }
  1963. memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
  1964. spin_lock_irqsave(&h->lock, flags);
  1965. if (unlikely(h->lockup_detected)) {
  1966. spin_unlock_irqrestore(&h->lock, flags);
  1967. cmd->result = DID_ERROR << 16;
  1968. done(cmd);
  1969. return 0;
  1970. }
  1971. spin_unlock_irqrestore(&h->lock, flags);
  1972. c = cmd_alloc(h);
  1973. if (c == NULL) { /* trouble... */
  1974. dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
  1975. return SCSI_MLQUEUE_HOST_BUSY;
  1976. }
  1977. /* Fill in the command list header */
  1978. cmd->scsi_done = done; /* save this for use by completion code */
  1979. /* save c in case we have to abort it */
  1980. cmd->host_scribble = (unsigned char *) c;
  1981. c->cmd_type = CMD_SCSI;
  1982. c->scsi_cmd = cmd;
  1983. c->Header.ReplyQueue = 0; /* unused in simple mode */
  1984. memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
  1985. c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
  1986. c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
  1987. /* Fill in the request block... */
  1988. c->Request.Timeout = 0;
  1989. memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
  1990. BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
  1991. c->Request.CDBLen = cmd->cmd_len;
  1992. memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
  1993. c->Request.Type.Type = TYPE_CMD;
  1994. c->Request.Type.Attribute = ATTR_SIMPLE;
  1995. switch (cmd->sc_data_direction) {
  1996. case DMA_TO_DEVICE:
  1997. c->Request.Type.Direction = XFER_WRITE;
  1998. break;
  1999. case DMA_FROM_DEVICE:
  2000. c->Request.Type.Direction = XFER_READ;
  2001. break;
  2002. case DMA_NONE:
  2003. c->Request.Type.Direction = XFER_NONE;
  2004. break;
  2005. case DMA_BIDIRECTIONAL:
  2006. /* This can happen if a buggy application does a scsi passthru
  2007. * and sets both inlen and outlen to non-zero. ( see
  2008. * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
  2009. */
  2010. c->Request.Type.Direction = XFER_RSVD;
  2011. /* This is technically wrong, and hpsa controllers should
  2012. * reject it with CMD_INVALID, which is the most correct
  2013. * response, but non-fibre backends appear to let it
  2014. * slide by, and give the same results as if this field
  2015. * were set correctly. Either way is acceptable for
  2016. * our purposes here.
  2017. */
  2018. break;
  2019. default:
  2020. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  2021. cmd->sc_data_direction);
  2022. BUG();
  2023. break;
  2024. }
  2025. if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
  2026. cmd_free(h, c);
  2027. return SCSI_MLQUEUE_HOST_BUSY;
  2028. }
  2029. enqueue_cmd_and_start_io(h, c);
  2030. /* the cmd'll come back via intr handler in complete_scsi_command() */
  2031. return 0;
  2032. }
  2033. static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
  2034. static void hpsa_scan_start(struct Scsi_Host *sh)
  2035. {
  2036. struct ctlr_info *h = shost_to_hba(sh);
  2037. unsigned long flags;
  2038. /* wait until any scan already in progress is finished. */
  2039. while (1) {
  2040. spin_lock_irqsave(&h->scan_lock, flags);
  2041. if (h->scan_finished)
  2042. break;
  2043. spin_unlock_irqrestore(&h->scan_lock, flags);
  2044. wait_event(h->scan_wait_queue, h->scan_finished);
  2045. /* Note: We don't need to worry about a race between this
  2046. * thread and driver unload because the midlayer will
  2047. * have incremented the reference count, so unload won't
  2048. * happen if we're in here.
  2049. */
  2050. }
  2051. h->scan_finished = 0; /* mark scan as in progress */
  2052. spin_unlock_irqrestore(&h->scan_lock, flags);
  2053. hpsa_update_scsi_devices(h, h->scsi_host->host_no);
  2054. spin_lock_irqsave(&h->scan_lock, flags);
  2055. h->scan_finished = 1; /* mark scan as finished. */
  2056. wake_up_all(&h->scan_wait_queue);
  2057. spin_unlock_irqrestore(&h->scan_lock, flags);
  2058. }
  2059. static int hpsa_scan_finished(struct Scsi_Host *sh,
  2060. unsigned long elapsed_time)
  2061. {
  2062. struct ctlr_info *h = shost_to_hba(sh);
  2063. unsigned long flags;
  2064. int finished;
  2065. spin_lock_irqsave(&h->scan_lock, flags);
  2066. finished = h->scan_finished;
  2067. spin_unlock_irqrestore(&h->scan_lock, flags);
  2068. return finished;
  2069. }
  2070. static int hpsa_change_queue_depth(struct scsi_device *sdev,
  2071. int qdepth, int reason)
  2072. {
  2073. struct ctlr_info *h = sdev_to_hba(sdev);
  2074. if (reason != SCSI_QDEPTH_DEFAULT)
  2075. return -ENOTSUPP;
  2076. if (qdepth < 1)
  2077. qdepth = 1;
  2078. else
  2079. if (qdepth > h->nr_cmds)
  2080. qdepth = h->nr_cmds;
  2081. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  2082. return sdev->queue_depth;
  2083. }
  2084. static void hpsa_unregister_scsi(struct ctlr_info *h)
  2085. {
  2086. /* we are being forcibly unloaded, and may not refuse. */
  2087. scsi_remove_host(h->scsi_host);
  2088. scsi_host_put(h->scsi_host);
  2089. h->scsi_host = NULL;
  2090. }
  2091. static int hpsa_register_scsi(struct ctlr_info *h)
  2092. {
  2093. struct Scsi_Host *sh;
  2094. int error;
  2095. sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
  2096. if (sh == NULL)
  2097. goto fail;
  2098. sh->io_port = 0;
  2099. sh->n_io_port = 0;
  2100. sh->this_id = -1;
  2101. sh->max_channel = 3;
  2102. sh->max_cmd_len = MAX_COMMAND_SIZE;
  2103. sh->max_lun = HPSA_MAX_LUN;
  2104. sh->max_id = HPSA_MAX_LUN;
  2105. sh->can_queue = h->nr_cmds;
  2106. sh->cmd_per_lun = h->nr_cmds;
  2107. sh->sg_tablesize = h->maxsgentries;
  2108. h->scsi_host = sh;
  2109. sh->hostdata[0] = (unsigned long) h;
  2110. sh->irq = h->intr[h->intr_mode];
  2111. sh->unique_id = sh->irq;
  2112. error = scsi_add_host(sh, &h->pdev->dev);
  2113. if (error)
  2114. goto fail_host_put;
  2115. scsi_scan_host(sh);
  2116. return 0;
  2117. fail_host_put:
  2118. dev_err(&h->pdev->dev, "%s: scsi_add_host"
  2119. " failed for controller %d\n", __func__, h->ctlr);
  2120. scsi_host_put(sh);
  2121. return error;
  2122. fail:
  2123. dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
  2124. " failed for controller %d\n", __func__, h->ctlr);
  2125. return -ENOMEM;
  2126. }
  2127. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  2128. unsigned char lunaddr[])
  2129. {
  2130. int rc = 0;
  2131. int count = 0;
  2132. int waittime = 1; /* seconds */
  2133. struct CommandList *c;
  2134. c = cmd_special_alloc(h);
  2135. if (!c) {
  2136. dev_warn(&h->pdev->dev, "out of memory in "
  2137. "wait_for_device_to_become_ready.\n");
  2138. return IO_ERROR;
  2139. }
  2140. /* Send test unit ready until device ready, or give up. */
  2141. while (count < HPSA_TUR_RETRY_LIMIT) {
  2142. /* Wait for a bit. do this first, because if we send
  2143. * the TUR right away, the reset will just abort it.
  2144. */
  2145. msleep(1000 * waittime);
  2146. count++;
  2147. /* Increase wait time with each try, up to a point. */
  2148. if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
  2149. waittime = waittime * 2;
  2150. /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
  2151. (void) fill_cmd(c, TEST_UNIT_READY, h,
  2152. NULL, 0, 0, lunaddr, TYPE_CMD);
  2153. hpsa_scsi_do_simple_cmd_core(h, c);
  2154. /* no unmap needed here because no data xfer. */
  2155. if (c->err_info->CommandStatus == CMD_SUCCESS)
  2156. break;
  2157. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  2158. c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
  2159. (c->err_info->SenseInfo[2] == NO_SENSE ||
  2160. c->err_info->SenseInfo[2] == UNIT_ATTENTION))
  2161. break;
  2162. dev_warn(&h->pdev->dev, "waiting %d secs "
  2163. "for device to become ready.\n", waittime);
  2164. rc = 1; /* device not ready. */
  2165. }
  2166. if (rc)
  2167. dev_warn(&h->pdev->dev, "giving up on device.\n");
  2168. else
  2169. dev_warn(&h->pdev->dev, "device is ready.\n");
  2170. cmd_special_free(h, c);
  2171. return rc;
  2172. }
  2173. /* Need at least one of these error handlers to keep ../scsi/hosts.c from
  2174. * complaining. Doing a host- or bus-reset can't do anything good here.
  2175. */
  2176. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
  2177. {
  2178. int rc;
  2179. struct ctlr_info *h;
  2180. struct hpsa_scsi_dev_t *dev;
  2181. /* find the controller to which the command to be aborted was sent */
  2182. h = sdev_to_hba(scsicmd->device);
  2183. if (h == NULL) /* paranoia */
  2184. return FAILED;
  2185. dev = scsicmd->device->hostdata;
  2186. if (!dev) {
  2187. dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
  2188. "device lookup failed.\n");
  2189. return FAILED;
  2190. }
  2191. dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
  2192. h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
  2193. /* send a reset to the SCSI LUN which the command was sent to */
  2194. rc = hpsa_send_reset(h, dev->scsi3addr);
  2195. if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
  2196. return SUCCESS;
  2197. dev_warn(&h->pdev->dev, "resetting device failed.\n");
  2198. return FAILED;
  2199. }
  2200. static void swizzle_abort_tag(u8 *tag)
  2201. {
  2202. u8 original_tag[8];
  2203. memcpy(original_tag, tag, 8);
  2204. tag[0] = original_tag[3];
  2205. tag[1] = original_tag[2];
  2206. tag[2] = original_tag[1];
  2207. tag[3] = original_tag[0];
  2208. tag[4] = original_tag[7];
  2209. tag[5] = original_tag[6];
  2210. tag[6] = original_tag[5];
  2211. tag[7] = original_tag[4];
  2212. }
  2213. static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
  2214. struct CommandList *abort, int swizzle)
  2215. {
  2216. int rc = IO_OK;
  2217. struct CommandList *c;
  2218. struct ErrorInfo *ei;
  2219. c = cmd_special_alloc(h);
  2220. if (c == NULL) { /* trouble... */
  2221. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  2222. return -ENOMEM;
  2223. }
  2224. /* fill_cmd can't fail here, no buffer to map */
  2225. (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
  2226. 0, 0, scsi3addr, TYPE_MSG);
  2227. if (swizzle)
  2228. swizzle_abort_tag(&c->Request.CDB[4]);
  2229. hpsa_scsi_do_simple_cmd_core(h, c);
  2230. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
  2231. __func__, abort->Header.Tag.upper, abort->Header.Tag.lower);
  2232. /* no unmap needed here because no data xfer. */
  2233. ei = c->err_info;
  2234. switch (ei->CommandStatus) {
  2235. case CMD_SUCCESS:
  2236. break;
  2237. case CMD_UNABORTABLE: /* Very common, don't make noise. */
  2238. rc = -1;
  2239. break;
  2240. default:
  2241. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
  2242. __func__, abort->Header.Tag.upper,
  2243. abort->Header.Tag.lower);
  2244. hpsa_scsi_interpret_error(c);
  2245. rc = -1;
  2246. break;
  2247. }
  2248. cmd_special_free(h, c);
  2249. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
  2250. abort->Header.Tag.upper, abort->Header.Tag.lower);
  2251. return rc;
  2252. }
  2253. /*
  2254. * hpsa_find_cmd_in_queue
  2255. *
  2256. * Used to determine whether a command (find) is still present
  2257. * in queue_head. Optionally excludes the last element of queue_head.
  2258. *
  2259. * This is used to avoid unnecessary aborts. Commands in h->reqQ have
  2260. * not yet been submitted, and so can be aborted by the driver without
  2261. * sending an abort to the hardware.
  2262. *
  2263. * Returns pointer to command if found in queue, NULL otherwise.
  2264. */
  2265. static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
  2266. struct scsi_cmnd *find, struct list_head *queue_head)
  2267. {
  2268. unsigned long flags;
  2269. struct CommandList *c = NULL; /* ptr into cmpQ */
  2270. if (!find)
  2271. return 0;
  2272. spin_lock_irqsave(&h->lock, flags);
  2273. list_for_each_entry(c, queue_head, list) {
  2274. if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
  2275. continue;
  2276. if (c->scsi_cmd == find) {
  2277. spin_unlock_irqrestore(&h->lock, flags);
  2278. return c;
  2279. }
  2280. }
  2281. spin_unlock_irqrestore(&h->lock, flags);
  2282. return NULL;
  2283. }
  2284. static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
  2285. u8 *tag, struct list_head *queue_head)
  2286. {
  2287. unsigned long flags;
  2288. struct CommandList *c;
  2289. spin_lock_irqsave(&h->lock, flags);
  2290. list_for_each_entry(c, queue_head, list) {
  2291. if (memcmp(&c->Header.Tag, tag, 8) != 0)
  2292. continue;
  2293. spin_unlock_irqrestore(&h->lock, flags);
  2294. return c;
  2295. }
  2296. spin_unlock_irqrestore(&h->lock, flags);
  2297. return NULL;
  2298. }
  2299. /* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
  2300. * tell which kind we're dealing with, so we send the abort both ways. There
  2301. * shouldn't be any collisions between swizzled and unswizzled tags due to the
  2302. * way we construct our tags but we check anyway in case the assumptions which
  2303. * make this true someday become false.
  2304. */
  2305. static int hpsa_send_abort_both_ways(struct ctlr_info *h,
  2306. unsigned char *scsi3addr, struct CommandList *abort)
  2307. {
  2308. u8 swizzled_tag[8];
  2309. struct CommandList *c;
  2310. int rc = 0, rc2 = 0;
  2311. /* we do not expect to find the swizzled tag in our queue, but
  2312. * check anyway just to be sure the assumptions which make this
  2313. * the case haven't become wrong.
  2314. */
  2315. memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
  2316. swizzle_abort_tag(swizzled_tag);
  2317. c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
  2318. if (c != NULL) {
  2319. dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
  2320. return hpsa_send_abort(h, scsi3addr, abort, 0);
  2321. }
  2322. rc = hpsa_send_abort(h, scsi3addr, abort, 0);
  2323. /* if the command is still in our queue, we can't conclude that it was
  2324. * aborted (it might have just completed normally) but in any case
  2325. * we don't need to try to abort it another way.
  2326. */
  2327. c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
  2328. if (c)
  2329. rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
  2330. return rc && rc2;
  2331. }
  2332. /* Send an abort for the specified command.
  2333. * If the device and controller support it,
  2334. * send a task abort request.
  2335. */
  2336. static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
  2337. {
  2338. int i, rc;
  2339. struct ctlr_info *h;
  2340. struct hpsa_scsi_dev_t *dev;
  2341. struct CommandList *abort; /* pointer to command to be aborted */
  2342. struct CommandList *found;
  2343. struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
  2344. char msg[256]; /* For debug messaging. */
  2345. int ml = 0;
  2346. /* Find the controller of the command to be aborted */
  2347. h = sdev_to_hba(sc->device);
  2348. if (WARN(h == NULL,
  2349. "ABORT REQUEST FAILED, Controller lookup failed.\n"))
  2350. return FAILED;
  2351. /* Check that controller supports some kind of task abort */
  2352. if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
  2353. !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
  2354. return FAILED;
  2355. memset(msg, 0, sizeof(msg));
  2356. ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
  2357. h->scsi_host->host_no, sc->device->channel,
  2358. sc->device->id, sc->device->lun);
  2359. /* Find the device of the command to be aborted */
  2360. dev = sc->device->hostdata;
  2361. if (!dev) {
  2362. dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
  2363. msg);
  2364. return FAILED;
  2365. }
  2366. /* Get SCSI command to be aborted */
  2367. abort = (struct CommandList *) sc->host_scribble;
  2368. if (abort == NULL) {
  2369. dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
  2370. msg);
  2371. return FAILED;
  2372. }
  2373. ml += sprintf(msg+ml, "Tag:0x%08x:%08x ",
  2374. abort->Header.Tag.upper, abort->Header.Tag.lower);
  2375. as = (struct scsi_cmnd *) abort->scsi_cmd;
  2376. if (as != NULL)
  2377. ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
  2378. as->cmnd[0], as->serial_number);
  2379. dev_dbg(&h->pdev->dev, "%s\n", msg);
  2380. dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
  2381. h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
  2382. /* Search reqQ to See if command is queued but not submitted,
  2383. * if so, complete the command with aborted status and remove
  2384. * it from the reqQ.
  2385. */
  2386. found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
  2387. if (found) {
  2388. found->err_info->CommandStatus = CMD_ABORTED;
  2389. finish_cmd(found);
  2390. dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
  2391. msg);
  2392. return SUCCESS;
  2393. }
  2394. /* not in reqQ, if also not in cmpQ, must have already completed */
  2395. found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
  2396. if (!found) {
  2397. dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
  2398. msg);
  2399. return SUCCESS;
  2400. }
  2401. /*
  2402. * Command is in flight, or possibly already completed
  2403. * by the firmware (but not to the scsi mid layer) but we can't
  2404. * distinguish which. Send the abort down.
  2405. */
  2406. rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
  2407. if (rc != 0) {
  2408. dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
  2409. dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
  2410. h->scsi_host->host_no,
  2411. dev->bus, dev->target, dev->lun);
  2412. return FAILED;
  2413. }
  2414. dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
  2415. /* If the abort(s) above completed and actually aborted the
  2416. * command, then the command to be aborted should already be
  2417. * completed. If not, wait around a bit more to see if they
  2418. * manage to complete normally.
  2419. */
  2420. #define ABORT_COMPLETE_WAIT_SECS 30
  2421. for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
  2422. found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
  2423. if (!found)
  2424. return SUCCESS;
  2425. msleep(100);
  2426. }
  2427. dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
  2428. msg, ABORT_COMPLETE_WAIT_SECS);
  2429. return FAILED;
  2430. }
  2431. /*
  2432. * For operations that cannot sleep, a command block is allocated at init,
  2433. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  2434. * which ones are free or in use. Lock must be held when calling this.
  2435. * cmd_free() is the complement.
  2436. */
  2437. static struct CommandList *cmd_alloc(struct ctlr_info *h)
  2438. {
  2439. struct CommandList *c;
  2440. int i;
  2441. union u64bit temp64;
  2442. dma_addr_t cmd_dma_handle, err_dma_handle;
  2443. unsigned long flags;
  2444. spin_lock_irqsave(&h->lock, flags);
  2445. do {
  2446. i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
  2447. if (i == h->nr_cmds) {
  2448. spin_unlock_irqrestore(&h->lock, flags);
  2449. return NULL;
  2450. }
  2451. } while (test_and_set_bit
  2452. (i & (BITS_PER_LONG - 1),
  2453. h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
  2454. spin_unlock_irqrestore(&h->lock, flags);
  2455. c = h->cmd_pool + i;
  2456. memset(c, 0, sizeof(*c));
  2457. cmd_dma_handle = h->cmd_pool_dhandle
  2458. + i * sizeof(*c);
  2459. c->err_info = h->errinfo_pool + i;
  2460. memset(c->err_info, 0, sizeof(*c->err_info));
  2461. err_dma_handle = h->errinfo_pool_dhandle
  2462. + i * sizeof(*c->err_info);
  2463. c->cmdindex = i;
  2464. INIT_LIST_HEAD(&c->list);
  2465. c->busaddr = (u32) cmd_dma_handle;
  2466. temp64.val = (u64) err_dma_handle;
  2467. c->ErrDesc.Addr.lower = temp64.val32.lower;
  2468. c->ErrDesc.Addr.upper = temp64.val32.upper;
  2469. c->ErrDesc.Len = sizeof(*c->err_info);
  2470. c->h = h;
  2471. return c;
  2472. }
  2473. /* For operations that can wait for kmalloc to possibly sleep,
  2474. * this routine can be called. Lock need not be held to call
  2475. * cmd_special_alloc. cmd_special_free() is the complement.
  2476. */
  2477. static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
  2478. {
  2479. struct CommandList *c;
  2480. union u64bit temp64;
  2481. dma_addr_t cmd_dma_handle, err_dma_handle;
  2482. c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
  2483. if (c == NULL)
  2484. return NULL;
  2485. memset(c, 0, sizeof(*c));
  2486. c->cmdindex = -1;
  2487. c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
  2488. &err_dma_handle);
  2489. if (c->err_info == NULL) {
  2490. pci_free_consistent(h->pdev,
  2491. sizeof(*c), c, cmd_dma_handle);
  2492. return NULL;
  2493. }
  2494. memset(c->err_info, 0, sizeof(*c->err_info));
  2495. INIT_LIST_HEAD(&c->list);
  2496. c->busaddr = (u32) cmd_dma_handle;
  2497. temp64.val = (u64) err_dma_handle;
  2498. c->ErrDesc.Addr.lower = temp64.val32.lower;
  2499. c->ErrDesc.Addr.upper = temp64.val32.upper;
  2500. c->ErrDesc.Len = sizeof(*c->err_info);
  2501. c->h = h;
  2502. return c;
  2503. }
  2504. static void cmd_free(struct ctlr_info *h, struct CommandList *c)
  2505. {
  2506. int i;
  2507. unsigned long flags;
  2508. i = c - h->cmd_pool;
  2509. spin_lock_irqsave(&h->lock, flags);
  2510. clear_bit(i & (BITS_PER_LONG - 1),
  2511. h->cmd_pool_bits + (i / BITS_PER_LONG));
  2512. spin_unlock_irqrestore(&h->lock, flags);
  2513. }
  2514. static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
  2515. {
  2516. union u64bit temp64;
  2517. temp64.val32.lower = c->ErrDesc.Addr.lower;
  2518. temp64.val32.upper = c->ErrDesc.Addr.upper;
  2519. pci_free_consistent(h->pdev, sizeof(*c->err_info),
  2520. c->err_info, (dma_addr_t) temp64.val);
  2521. pci_free_consistent(h->pdev, sizeof(*c),
  2522. c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
  2523. }
  2524. #ifdef CONFIG_COMPAT
  2525. static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
  2526. {
  2527. IOCTL32_Command_struct __user *arg32 =
  2528. (IOCTL32_Command_struct __user *) arg;
  2529. IOCTL_Command_struct arg64;
  2530. IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
  2531. int err;
  2532. u32 cp;
  2533. memset(&arg64, 0, sizeof(arg64));
  2534. err = 0;
  2535. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  2536. sizeof(arg64.LUN_info));
  2537. err |= copy_from_user(&arg64.Request, &arg32->Request,
  2538. sizeof(arg64.Request));
  2539. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  2540. sizeof(arg64.error_info));
  2541. err |= get_user(arg64.buf_size, &arg32->buf_size);
  2542. err |= get_user(cp, &arg32->buf);
  2543. arg64.buf = compat_ptr(cp);
  2544. err |= copy_to_user(p, &arg64, sizeof(arg64));
  2545. if (err)
  2546. return -EFAULT;
  2547. err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
  2548. if (err)
  2549. return err;
  2550. err |= copy_in_user(&arg32->error_info, &p->error_info,
  2551. sizeof(arg32->error_info));
  2552. if (err)
  2553. return -EFAULT;
  2554. return err;
  2555. }
  2556. static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
  2557. int cmd, void *arg)
  2558. {
  2559. BIG_IOCTL32_Command_struct __user *arg32 =
  2560. (BIG_IOCTL32_Command_struct __user *) arg;
  2561. BIG_IOCTL_Command_struct arg64;
  2562. BIG_IOCTL_Command_struct __user *p =
  2563. compat_alloc_user_space(sizeof(arg64));
  2564. int err;
  2565. u32 cp;
  2566. memset(&arg64, 0, sizeof(arg64));
  2567. err = 0;
  2568. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  2569. sizeof(arg64.LUN_info));
  2570. err |= copy_from_user(&arg64.Request, &arg32->Request,
  2571. sizeof(arg64.Request));
  2572. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  2573. sizeof(arg64.error_info));
  2574. err |= get_user(arg64.buf_size, &arg32->buf_size);
  2575. err |= get_user(arg64.malloc_size, &arg32->malloc_size);
  2576. err |= get_user(cp, &arg32->buf);
  2577. arg64.buf = compat_ptr(cp);
  2578. err |= copy_to_user(p, &arg64, sizeof(arg64));
  2579. if (err)
  2580. return -EFAULT;
  2581. err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
  2582. if (err)
  2583. return err;
  2584. err |= copy_in_user(&arg32->error_info, &p->error_info,
  2585. sizeof(arg32->error_info));
  2586. if (err)
  2587. return -EFAULT;
  2588. return err;
  2589. }
  2590. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
  2591. {
  2592. switch (cmd) {
  2593. case CCISS_GETPCIINFO:
  2594. case CCISS_GETINTINFO:
  2595. case CCISS_SETINTINFO:
  2596. case CCISS_GETNODENAME:
  2597. case CCISS_SETNODENAME:
  2598. case CCISS_GETHEARTBEAT:
  2599. case CCISS_GETBUSTYPES:
  2600. case CCISS_GETFIRMVER:
  2601. case CCISS_GETDRIVVER:
  2602. case CCISS_REVALIDVOLS:
  2603. case CCISS_DEREGDISK:
  2604. case CCISS_REGNEWDISK:
  2605. case CCISS_REGNEWD:
  2606. case CCISS_RESCANDISK:
  2607. case CCISS_GETLUNINFO:
  2608. return hpsa_ioctl(dev, cmd, arg);
  2609. case CCISS_PASSTHRU32:
  2610. return hpsa_ioctl32_passthru(dev, cmd, arg);
  2611. case CCISS_BIG_PASSTHRU32:
  2612. return hpsa_ioctl32_big_passthru(dev, cmd, arg);
  2613. default:
  2614. return -ENOIOCTLCMD;
  2615. }
  2616. }
  2617. #endif
  2618. static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
  2619. {
  2620. struct hpsa_pci_info pciinfo;
  2621. if (!argp)
  2622. return -EINVAL;
  2623. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  2624. pciinfo.bus = h->pdev->bus->number;
  2625. pciinfo.dev_fn = h->pdev->devfn;
  2626. pciinfo.board_id = h->board_id;
  2627. if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
  2628. return -EFAULT;
  2629. return 0;
  2630. }
  2631. static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
  2632. {
  2633. DriverVer_type DriverVer;
  2634. unsigned char vmaj, vmin, vsubmin;
  2635. int rc;
  2636. rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
  2637. &vmaj, &vmin, &vsubmin);
  2638. if (rc != 3) {
  2639. dev_info(&h->pdev->dev, "driver version string '%s' "
  2640. "unrecognized.", HPSA_DRIVER_VERSION);
  2641. vmaj = 0;
  2642. vmin = 0;
  2643. vsubmin = 0;
  2644. }
  2645. DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
  2646. if (!argp)
  2647. return -EINVAL;
  2648. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  2649. return -EFAULT;
  2650. return 0;
  2651. }
  2652. static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  2653. {
  2654. IOCTL_Command_struct iocommand;
  2655. struct CommandList *c;
  2656. char *buff = NULL;
  2657. union u64bit temp64;
  2658. int rc = 0;
  2659. if (!argp)
  2660. return -EINVAL;
  2661. if (!capable(CAP_SYS_RAWIO))
  2662. return -EPERM;
  2663. if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
  2664. return -EFAULT;
  2665. if ((iocommand.buf_size < 1) &&
  2666. (iocommand.Request.Type.Direction != XFER_NONE)) {
  2667. return -EINVAL;
  2668. }
  2669. if (iocommand.buf_size > 0) {
  2670. buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
  2671. if (buff == NULL)
  2672. return -EFAULT;
  2673. if (iocommand.Request.Type.Direction == XFER_WRITE) {
  2674. /* Copy the data into the buffer we created */
  2675. if (copy_from_user(buff, iocommand.buf,
  2676. iocommand.buf_size)) {
  2677. rc = -EFAULT;
  2678. goto out_kfree;
  2679. }
  2680. } else {
  2681. memset(buff, 0, iocommand.buf_size);
  2682. }
  2683. }
  2684. c = cmd_special_alloc(h);
  2685. if (c == NULL) {
  2686. rc = -ENOMEM;
  2687. goto out_kfree;
  2688. }
  2689. /* Fill in the command type */
  2690. c->cmd_type = CMD_IOCTL_PEND;
  2691. /* Fill in Command Header */
  2692. c->Header.ReplyQueue = 0; /* unused in simple mode */
  2693. if (iocommand.buf_size > 0) { /* buffer to fill */
  2694. c->Header.SGList = 1;
  2695. c->Header.SGTotal = 1;
  2696. } else { /* no buffers to fill */
  2697. c->Header.SGList = 0;
  2698. c->Header.SGTotal = 0;
  2699. }
  2700. memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
  2701. /* use the kernel address the cmd block for tag */
  2702. c->Header.Tag.lower = c->busaddr;
  2703. /* Fill in Request block */
  2704. memcpy(&c->Request, &iocommand.Request,
  2705. sizeof(c->Request));
  2706. /* Fill in the scatter gather information */
  2707. if (iocommand.buf_size > 0) {
  2708. temp64.val = pci_map_single(h->pdev, buff,
  2709. iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
  2710. if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
  2711. c->SG[0].Addr.lower = 0;
  2712. c->SG[0].Addr.upper = 0;
  2713. c->SG[0].Len = 0;
  2714. rc = -ENOMEM;
  2715. goto out;
  2716. }
  2717. c->SG[0].Addr.lower = temp64.val32.lower;
  2718. c->SG[0].Addr.upper = temp64.val32.upper;
  2719. c->SG[0].Len = iocommand.buf_size;
  2720. c->SG[0].Ext = 0; /* we are not chaining*/
  2721. }
  2722. hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
  2723. if (iocommand.buf_size > 0)
  2724. hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
  2725. check_ioctl_unit_attention(h, c);
  2726. /* Copy the error information out */
  2727. memcpy(&iocommand.error_info, c->err_info,
  2728. sizeof(iocommand.error_info));
  2729. if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
  2730. rc = -EFAULT;
  2731. goto out;
  2732. }
  2733. if (iocommand.Request.Type.Direction == XFER_READ &&
  2734. iocommand.buf_size > 0) {
  2735. /* Copy the data out of the buffer we created */
  2736. if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
  2737. rc = -EFAULT;
  2738. goto out;
  2739. }
  2740. }
  2741. out:
  2742. cmd_special_free(h, c);
  2743. out_kfree:
  2744. kfree(buff);
  2745. return rc;
  2746. }
  2747. static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  2748. {
  2749. BIG_IOCTL_Command_struct *ioc;
  2750. struct CommandList *c;
  2751. unsigned char **buff = NULL;
  2752. int *buff_size = NULL;
  2753. union u64bit temp64;
  2754. BYTE sg_used = 0;
  2755. int status = 0;
  2756. int i;
  2757. u32 left;
  2758. u32 sz;
  2759. BYTE __user *data_ptr;
  2760. if (!argp)
  2761. return -EINVAL;
  2762. if (!capable(CAP_SYS_RAWIO))
  2763. return -EPERM;
  2764. ioc = (BIG_IOCTL_Command_struct *)
  2765. kmalloc(sizeof(*ioc), GFP_KERNEL);
  2766. if (!ioc) {
  2767. status = -ENOMEM;
  2768. goto cleanup1;
  2769. }
  2770. if (copy_from_user(ioc, argp, sizeof(*ioc))) {
  2771. status = -EFAULT;
  2772. goto cleanup1;
  2773. }
  2774. if ((ioc->buf_size < 1) &&
  2775. (ioc->Request.Type.Direction != XFER_NONE)) {
  2776. status = -EINVAL;
  2777. goto cleanup1;
  2778. }
  2779. /* Check kmalloc limits using all SGs */
  2780. if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
  2781. status = -EINVAL;
  2782. goto cleanup1;
  2783. }
  2784. if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
  2785. status = -EINVAL;
  2786. goto cleanup1;
  2787. }
  2788. buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
  2789. if (!buff) {
  2790. status = -ENOMEM;
  2791. goto cleanup1;
  2792. }
  2793. buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
  2794. if (!buff_size) {
  2795. status = -ENOMEM;
  2796. goto cleanup1;
  2797. }
  2798. left = ioc->buf_size;
  2799. data_ptr = ioc->buf;
  2800. while (left) {
  2801. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  2802. buff_size[sg_used] = sz;
  2803. buff[sg_used] = kmalloc(sz, GFP_KERNEL);
  2804. if (buff[sg_used] == NULL) {
  2805. status = -ENOMEM;
  2806. goto cleanup1;
  2807. }
  2808. if (ioc->Request.Type.Direction == XFER_WRITE) {
  2809. if (copy_from_user(buff[sg_used], data_ptr, sz)) {
  2810. status = -ENOMEM;
  2811. goto cleanup1;
  2812. }
  2813. } else
  2814. memset(buff[sg_used], 0, sz);
  2815. left -= sz;
  2816. data_ptr += sz;
  2817. sg_used++;
  2818. }
  2819. c = cmd_special_alloc(h);
  2820. if (c == NULL) {
  2821. status = -ENOMEM;
  2822. goto cleanup1;
  2823. }
  2824. c->cmd_type = CMD_IOCTL_PEND;
  2825. c->Header.ReplyQueue = 0;
  2826. c->Header.SGList = c->Header.SGTotal = sg_used;
  2827. memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
  2828. c->Header.Tag.lower = c->busaddr;
  2829. memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
  2830. if (ioc->buf_size > 0) {
  2831. int i;
  2832. for (i = 0; i < sg_used; i++) {
  2833. temp64.val = pci_map_single(h->pdev, buff[i],
  2834. buff_size[i], PCI_DMA_BIDIRECTIONAL);
  2835. if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
  2836. c->SG[i].Addr.lower = 0;
  2837. c->SG[i].Addr.upper = 0;
  2838. c->SG[i].Len = 0;
  2839. hpsa_pci_unmap(h->pdev, c, i,
  2840. PCI_DMA_BIDIRECTIONAL);
  2841. status = -ENOMEM;
  2842. goto cleanup1;
  2843. }
  2844. c->SG[i].Addr.lower = temp64.val32.lower;
  2845. c->SG[i].Addr.upper = temp64.val32.upper;
  2846. c->SG[i].Len = buff_size[i];
  2847. /* we are not chaining */
  2848. c->SG[i].Ext = 0;
  2849. }
  2850. }
  2851. hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
  2852. if (sg_used)
  2853. hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
  2854. check_ioctl_unit_attention(h, c);
  2855. /* Copy the error information out */
  2856. memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
  2857. if (copy_to_user(argp, ioc, sizeof(*ioc))) {
  2858. cmd_special_free(h, c);
  2859. status = -EFAULT;
  2860. goto cleanup1;
  2861. }
  2862. if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
  2863. /* Copy the data out of the buffer we created */
  2864. BYTE __user *ptr = ioc->buf;
  2865. for (i = 0; i < sg_used; i++) {
  2866. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  2867. cmd_special_free(h, c);
  2868. status = -EFAULT;
  2869. goto cleanup1;
  2870. }
  2871. ptr += buff_size[i];
  2872. }
  2873. }
  2874. cmd_special_free(h, c);
  2875. status = 0;
  2876. cleanup1:
  2877. if (buff) {
  2878. for (i = 0; i < sg_used; i++)
  2879. kfree(buff[i]);
  2880. kfree(buff);
  2881. }
  2882. kfree(buff_size);
  2883. kfree(ioc);
  2884. return status;
  2885. }
  2886. static void check_ioctl_unit_attention(struct ctlr_info *h,
  2887. struct CommandList *c)
  2888. {
  2889. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  2890. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  2891. (void) check_for_unit_attention(h, c);
  2892. }
  2893. /*
  2894. * ioctl
  2895. */
  2896. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
  2897. {
  2898. struct ctlr_info *h;
  2899. void __user *argp = (void __user *)arg;
  2900. h = sdev_to_hba(dev);
  2901. switch (cmd) {
  2902. case CCISS_DEREGDISK:
  2903. case CCISS_REGNEWDISK:
  2904. case CCISS_REGNEWD:
  2905. hpsa_scan_start(h->scsi_host);
  2906. return 0;
  2907. case CCISS_GETPCIINFO:
  2908. return hpsa_getpciinfo_ioctl(h, argp);
  2909. case CCISS_GETDRIVVER:
  2910. return hpsa_getdrivver_ioctl(h, argp);
  2911. case CCISS_PASSTHRU:
  2912. return hpsa_passthru_ioctl(h, argp);
  2913. case CCISS_BIG_PASSTHRU:
  2914. return hpsa_big_passthru_ioctl(h, argp);
  2915. default:
  2916. return -ENOTTY;
  2917. }
  2918. }
  2919. static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
  2920. u8 reset_type)
  2921. {
  2922. struct CommandList *c;
  2923. c = cmd_alloc(h);
  2924. if (!c)
  2925. return -ENOMEM;
  2926. /* fill_cmd can't fail here, no data buffer to map */
  2927. (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
  2928. RAID_CTLR_LUNID, TYPE_MSG);
  2929. c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
  2930. c->waiting = NULL;
  2931. enqueue_cmd_and_start_io(h, c);
  2932. /* Don't wait for completion, the reset won't complete. Don't free
  2933. * the command either. This is the last command we will send before
  2934. * re-initializing everything, so it doesn't matter and won't leak.
  2935. */
  2936. return 0;
  2937. }
  2938. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  2939. void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
  2940. int cmd_type)
  2941. {
  2942. int pci_dir = XFER_NONE;
  2943. struct CommandList *a; /* for commands to be aborted */
  2944. c->cmd_type = CMD_IOCTL_PEND;
  2945. c->Header.ReplyQueue = 0;
  2946. if (buff != NULL && size > 0) {
  2947. c->Header.SGList = 1;
  2948. c->Header.SGTotal = 1;
  2949. } else {
  2950. c->Header.SGList = 0;
  2951. c->Header.SGTotal = 0;
  2952. }
  2953. c->Header.Tag.lower = c->busaddr;
  2954. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  2955. c->Request.Type.Type = cmd_type;
  2956. if (cmd_type == TYPE_CMD) {
  2957. switch (cmd) {
  2958. case HPSA_INQUIRY:
  2959. /* are we trying to read a vital product page */
  2960. if (page_code != 0) {
  2961. c->Request.CDB[1] = 0x01;
  2962. c->Request.CDB[2] = page_code;
  2963. }
  2964. c->Request.CDBLen = 6;
  2965. c->Request.Type.Attribute = ATTR_SIMPLE;
  2966. c->Request.Type.Direction = XFER_READ;
  2967. c->Request.Timeout = 0;
  2968. c->Request.CDB[0] = HPSA_INQUIRY;
  2969. c->Request.CDB[4] = size & 0xFF;
  2970. break;
  2971. case HPSA_REPORT_LOG:
  2972. case HPSA_REPORT_PHYS:
  2973. /* Talking to controller so It's a physical command
  2974. mode = 00 target = 0. Nothing to write.
  2975. */
  2976. c->Request.CDBLen = 12;
  2977. c->Request.Type.Attribute = ATTR_SIMPLE;
  2978. c->Request.Type.Direction = XFER_READ;
  2979. c->Request.Timeout = 0;
  2980. c->Request.CDB[0] = cmd;
  2981. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  2982. c->Request.CDB[7] = (size >> 16) & 0xFF;
  2983. c->Request.CDB[8] = (size >> 8) & 0xFF;
  2984. c->Request.CDB[9] = size & 0xFF;
  2985. break;
  2986. case HPSA_CACHE_FLUSH:
  2987. c->Request.CDBLen = 12;
  2988. c->Request.Type.Attribute = ATTR_SIMPLE;
  2989. c->Request.Type.Direction = XFER_WRITE;
  2990. c->Request.Timeout = 0;
  2991. c->Request.CDB[0] = BMIC_WRITE;
  2992. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  2993. c->Request.CDB[7] = (size >> 8) & 0xFF;
  2994. c->Request.CDB[8] = size & 0xFF;
  2995. break;
  2996. case TEST_UNIT_READY:
  2997. c->Request.CDBLen = 6;
  2998. c->Request.Type.Attribute = ATTR_SIMPLE;
  2999. c->Request.Type.Direction = XFER_NONE;
  3000. c->Request.Timeout = 0;
  3001. break;
  3002. default:
  3003. dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
  3004. BUG();
  3005. return -1;
  3006. }
  3007. } else if (cmd_type == TYPE_MSG) {
  3008. switch (cmd) {
  3009. case HPSA_DEVICE_RESET_MSG:
  3010. c->Request.CDBLen = 16;
  3011. c->Request.Type.Type = 1; /* It is a MSG not a CMD */
  3012. c->Request.Type.Attribute = ATTR_SIMPLE;
  3013. c->Request.Type.Direction = XFER_NONE;
  3014. c->Request.Timeout = 0; /* Don't time out */
  3015. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  3016. c->Request.CDB[0] = cmd;
  3017. c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
  3018. /* If bytes 4-7 are zero, it means reset the */
  3019. /* LunID device */
  3020. c->Request.CDB[4] = 0x00;
  3021. c->Request.CDB[5] = 0x00;
  3022. c->Request.CDB[6] = 0x00;
  3023. c->Request.CDB[7] = 0x00;
  3024. break;
  3025. case HPSA_ABORT_MSG:
  3026. a = buff; /* point to command to be aborted */
  3027. dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
  3028. a->Header.Tag.upper, a->Header.Tag.lower,
  3029. c->Header.Tag.upper, c->Header.Tag.lower);
  3030. c->Request.CDBLen = 16;
  3031. c->Request.Type.Type = TYPE_MSG;
  3032. c->Request.Type.Attribute = ATTR_SIMPLE;
  3033. c->Request.Type.Direction = XFER_WRITE;
  3034. c->Request.Timeout = 0; /* Don't time out */
  3035. c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
  3036. c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
  3037. c->Request.CDB[2] = 0x00; /* reserved */
  3038. c->Request.CDB[3] = 0x00; /* reserved */
  3039. /* Tag to abort goes in CDB[4]-CDB[11] */
  3040. c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
  3041. c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
  3042. c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
  3043. c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
  3044. c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
  3045. c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
  3046. c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
  3047. c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
  3048. c->Request.CDB[12] = 0x00; /* reserved */
  3049. c->Request.CDB[13] = 0x00; /* reserved */
  3050. c->Request.CDB[14] = 0x00; /* reserved */
  3051. c->Request.CDB[15] = 0x00; /* reserved */
  3052. break;
  3053. default:
  3054. dev_warn(&h->pdev->dev, "unknown message type %d\n",
  3055. cmd);
  3056. BUG();
  3057. }
  3058. } else {
  3059. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  3060. BUG();
  3061. }
  3062. switch (c->Request.Type.Direction) {
  3063. case XFER_READ:
  3064. pci_dir = PCI_DMA_FROMDEVICE;
  3065. break;
  3066. case XFER_WRITE:
  3067. pci_dir = PCI_DMA_TODEVICE;
  3068. break;
  3069. case XFER_NONE:
  3070. pci_dir = PCI_DMA_NONE;
  3071. break;
  3072. default:
  3073. pci_dir = PCI_DMA_BIDIRECTIONAL;
  3074. }
  3075. if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
  3076. return -1;
  3077. return 0;
  3078. }
  3079. /*
  3080. * Map (physical) PCI mem into (virtual) kernel space
  3081. */
  3082. static void __iomem *remap_pci_mem(ulong base, ulong size)
  3083. {
  3084. ulong page_base = ((ulong) base) & PAGE_MASK;
  3085. ulong page_offs = ((ulong) base) - page_base;
  3086. void __iomem *page_remapped = ioremap_nocache(page_base,
  3087. page_offs + size);
  3088. return page_remapped ? (page_remapped + page_offs) : NULL;
  3089. }
  3090. /* Takes cmds off the submission queue and sends them to the hardware,
  3091. * then puts them on the queue of cmds waiting for completion.
  3092. */
  3093. static void start_io(struct ctlr_info *h)
  3094. {
  3095. struct CommandList *c;
  3096. unsigned long flags;
  3097. spin_lock_irqsave(&h->lock, flags);
  3098. while (!list_empty(&h->reqQ)) {
  3099. c = list_entry(h->reqQ.next, struct CommandList, list);
  3100. /* can't do anything if fifo is full */
  3101. if ((h->access.fifo_full(h))) {
  3102. dev_warn(&h->pdev->dev, "fifo full\n");
  3103. break;
  3104. }
  3105. /* Get the first entry from the Request Q */
  3106. removeQ(c);
  3107. h->Qdepth--;
  3108. /* Put job onto the completed Q */
  3109. addQ(&h->cmpQ, c);
  3110. /* Must increment commands_outstanding before unlocking
  3111. * and submitting to avoid race checking for fifo full
  3112. * condition.
  3113. */
  3114. h->commands_outstanding++;
  3115. if (h->commands_outstanding > h->max_outstanding)
  3116. h->max_outstanding = h->commands_outstanding;
  3117. /* Tell the controller execute command */
  3118. spin_unlock_irqrestore(&h->lock, flags);
  3119. h->access.submit_command(h, c);
  3120. spin_lock_irqsave(&h->lock, flags);
  3121. }
  3122. spin_unlock_irqrestore(&h->lock, flags);
  3123. }
  3124. static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
  3125. {
  3126. return h->access.command_completed(h, q);
  3127. }
  3128. static inline bool interrupt_pending(struct ctlr_info *h)
  3129. {
  3130. return h->access.intr_pending(h);
  3131. }
  3132. static inline long interrupt_not_for_us(struct ctlr_info *h)
  3133. {
  3134. return (h->access.intr_pending(h) == 0) ||
  3135. (h->interrupts_enabled == 0);
  3136. }
  3137. static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
  3138. u32 raw_tag)
  3139. {
  3140. if (unlikely(tag_index >= h->nr_cmds)) {
  3141. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  3142. return 1;
  3143. }
  3144. return 0;
  3145. }
  3146. static inline void finish_cmd(struct CommandList *c)
  3147. {
  3148. unsigned long flags;
  3149. spin_lock_irqsave(&c->h->lock, flags);
  3150. removeQ(c);
  3151. spin_unlock_irqrestore(&c->h->lock, flags);
  3152. dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
  3153. if (likely(c->cmd_type == CMD_SCSI))
  3154. complete_scsi_command(c);
  3155. else if (c->cmd_type == CMD_IOCTL_PEND)
  3156. complete(c->waiting);
  3157. }
  3158. static inline u32 hpsa_tag_contains_index(u32 tag)
  3159. {
  3160. return tag & DIRECT_LOOKUP_BIT;
  3161. }
  3162. static inline u32 hpsa_tag_to_index(u32 tag)
  3163. {
  3164. return tag >> DIRECT_LOOKUP_SHIFT;
  3165. }
  3166. static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
  3167. {
  3168. #define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
  3169. #define HPSA_SIMPLE_ERROR_BITS 0x03
  3170. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  3171. return tag & ~HPSA_SIMPLE_ERROR_BITS;
  3172. return tag & ~HPSA_PERF_ERROR_BITS;
  3173. }
  3174. /* process completion of an indexed ("direct lookup") command */
  3175. static inline void process_indexed_cmd(struct ctlr_info *h,
  3176. u32 raw_tag)
  3177. {
  3178. u32 tag_index;
  3179. struct CommandList *c;
  3180. tag_index = hpsa_tag_to_index(raw_tag);
  3181. if (!bad_tag(h, tag_index, raw_tag)) {
  3182. c = h->cmd_pool + tag_index;
  3183. finish_cmd(c);
  3184. }
  3185. }
  3186. /* process completion of a non-indexed command */
  3187. static inline void process_nonindexed_cmd(struct ctlr_info *h,
  3188. u32 raw_tag)
  3189. {
  3190. u32 tag;
  3191. struct CommandList *c = NULL;
  3192. unsigned long flags;
  3193. tag = hpsa_tag_discard_error_bits(h, raw_tag);
  3194. spin_lock_irqsave(&h->lock, flags);
  3195. list_for_each_entry(c, &h->cmpQ, list) {
  3196. if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
  3197. spin_unlock_irqrestore(&h->lock, flags);
  3198. finish_cmd(c);
  3199. return;
  3200. }
  3201. }
  3202. spin_unlock_irqrestore(&h->lock, flags);
  3203. bad_tag(h, h->nr_cmds + 1, raw_tag);
  3204. }
  3205. /* Some controllers, like p400, will give us one interrupt
  3206. * after a soft reset, even if we turned interrupts off.
  3207. * Only need to check for this in the hpsa_xxx_discard_completions
  3208. * functions.
  3209. */
  3210. static int ignore_bogus_interrupt(struct ctlr_info *h)
  3211. {
  3212. if (likely(!reset_devices))
  3213. return 0;
  3214. if (likely(h->interrupts_enabled))
  3215. return 0;
  3216. dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
  3217. "(known firmware bug.) Ignoring.\n");
  3218. return 1;
  3219. }
  3220. /*
  3221. * Convert &h->q[x] (passed to interrupt handlers) back to h.
  3222. * Relies on (h-q[x] == x) being true for x such that
  3223. * 0 <= x < MAX_REPLY_QUEUES.
  3224. */
  3225. static struct ctlr_info *queue_to_hba(u8 *queue)
  3226. {
  3227. return container_of((queue - *queue), struct ctlr_info, q[0]);
  3228. }
  3229. static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
  3230. {
  3231. struct ctlr_info *h = queue_to_hba(queue);
  3232. u8 q = *(u8 *) queue;
  3233. u32 raw_tag;
  3234. if (ignore_bogus_interrupt(h))
  3235. return IRQ_NONE;
  3236. if (interrupt_not_for_us(h))
  3237. return IRQ_NONE;
  3238. h->last_intr_timestamp = get_jiffies_64();
  3239. while (interrupt_pending(h)) {
  3240. raw_tag = get_next_completion(h, q);
  3241. while (raw_tag != FIFO_EMPTY)
  3242. raw_tag = next_command(h, q);
  3243. }
  3244. return IRQ_HANDLED;
  3245. }
  3246. static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
  3247. {
  3248. struct ctlr_info *h = queue_to_hba(queue);
  3249. u32 raw_tag;
  3250. u8 q = *(u8 *) queue;
  3251. if (ignore_bogus_interrupt(h))
  3252. return IRQ_NONE;
  3253. h->last_intr_timestamp = get_jiffies_64();
  3254. raw_tag = get_next_completion(h, q);
  3255. while (raw_tag != FIFO_EMPTY)
  3256. raw_tag = next_command(h, q);
  3257. return IRQ_HANDLED;
  3258. }
  3259. static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
  3260. {
  3261. struct ctlr_info *h = queue_to_hba((u8 *) queue);
  3262. u32 raw_tag;
  3263. u8 q = *(u8 *) queue;
  3264. if (interrupt_not_for_us(h))
  3265. return IRQ_NONE;
  3266. h->last_intr_timestamp = get_jiffies_64();
  3267. while (interrupt_pending(h)) {
  3268. raw_tag = get_next_completion(h, q);
  3269. while (raw_tag != FIFO_EMPTY) {
  3270. if (likely(hpsa_tag_contains_index(raw_tag)))
  3271. process_indexed_cmd(h, raw_tag);
  3272. else
  3273. process_nonindexed_cmd(h, raw_tag);
  3274. raw_tag = next_command(h, q);
  3275. }
  3276. }
  3277. return IRQ_HANDLED;
  3278. }
  3279. static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
  3280. {
  3281. struct ctlr_info *h = queue_to_hba(queue);
  3282. u32 raw_tag;
  3283. u8 q = *(u8 *) queue;
  3284. h->last_intr_timestamp = get_jiffies_64();
  3285. raw_tag = get_next_completion(h, q);
  3286. while (raw_tag != FIFO_EMPTY) {
  3287. if (likely(hpsa_tag_contains_index(raw_tag)))
  3288. process_indexed_cmd(h, raw_tag);
  3289. else
  3290. process_nonindexed_cmd(h, raw_tag);
  3291. raw_tag = next_command(h, q);
  3292. }
  3293. return IRQ_HANDLED;
  3294. }
  3295. /* Send a message CDB to the firmware. Careful, this only works
  3296. * in simple mode, not performant mode due to the tag lookup.
  3297. * We only ever use this immediately after a controller reset.
  3298. */
  3299. static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
  3300. unsigned char type)
  3301. {
  3302. struct Command {
  3303. struct CommandListHeader CommandHeader;
  3304. struct RequestBlock Request;
  3305. struct ErrDescriptor ErrorDescriptor;
  3306. };
  3307. struct Command *cmd;
  3308. static const size_t cmd_sz = sizeof(*cmd) +
  3309. sizeof(cmd->ErrorDescriptor);
  3310. dma_addr_t paddr64;
  3311. uint32_t paddr32, tag;
  3312. void __iomem *vaddr;
  3313. int i, err;
  3314. vaddr = pci_ioremap_bar(pdev, 0);
  3315. if (vaddr == NULL)
  3316. return -ENOMEM;
  3317. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  3318. * CCISS commands, so they must be allocated from the lower 4GiB of
  3319. * memory.
  3320. */
  3321. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3322. if (err) {
  3323. iounmap(vaddr);
  3324. return -ENOMEM;
  3325. }
  3326. cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
  3327. if (cmd == NULL) {
  3328. iounmap(vaddr);
  3329. return -ENOMEM;
  3330. }
  3331. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  3332. * although there's no guarantee, we assume that the address is at
  3333. * least 4-byte aligned (most likely, it's page-aligned).
  3334. */
  3335. paddr32 = paddr64;
  3336. cmd->CommandHeader.ReplyQueue = 0;
  3337. cmd->CommandHeader.SGList = 0;
  3338. cmd->CommandHeader.SGTotal = 0;
  3339. cmd->CommandHeader.Tag.lower = paddr32;
  3340. cmd->CommandHeader.Tag.upper = 0;
  3341. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  3342. cmd->Request.CDBLen = 16;
  3343. cmd->Request.Type.Type = TYPE_MSG;
  3344. cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
  3345. cmd->Request.Type.Direction = XFER_NONE;
  3346. cmd->Request.Timeout = 0; /* Don't time out */
  3347. cmd->Request.CDB[0] = opcode;
  3348. cmd->Request.CDB[1] = type;
  3349. memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
  3350. cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
  3351. cmd->ErrorDescriptor.Addr.upper = 0;
  3352. cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
  3353. writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
  3354. for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
  3355. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  3356. if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
  3357. break;
  3358. msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
  3359. }
  3360. iounmap(vaddr);
  3361. /* we leak the DMA buffer here ... no choice since the controller could
  3362. * still complete the command.
  3363. */
  3364. if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
  3365. dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
  3366. opcode, type);
  3367. return -ETIMEDOUT;
  3368. }
  3369. pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
  3370. if (tag & HPSA_ERROR_BIT) {
  3371. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  3372. opcode, type);
  3373. return -EIO;
  3374. }
  3375. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  3376. opcode, type);
  3377. return 0;
  3378. }
  3379. #define hpsa_noop(p) hpsa_message(p, 3, 0)
  3380. static int hpsa_controller_hard_reset(struct pci_dev *pdev,
  3381. void * __iomem vaddr, u32 use_doorbell)
  3382. {
  3383. u16 pmcsr;
  3384. int pos;
  3385. if (use_doorbell) {
  3386. /* For everything after the P600, the PCI power state method
  3387. * of resetting the controller doesn't work, so we have this
  3388. * other way using the doorbell register.
  3389. */
  3390. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  3391. writel(use_doorbell, vaddr + SA5_DOORBELL);
  3392. } else { /* Try to do it the PCI power state way */
  3393. /* Quoting from the Open CISS Specification: "The Power
  3394. * Management Control/Status Register (CSR) controls the power
  3395. * state of the device. The normal operating state is D0,
  3396. * CSR=00h. The software off state is D3, CSR=03h. To reset
  3397. * the controller, place the interface device in D3 then to D0,
  3398. * this causes a secondary PCI reset which will reset the
  3399. * controller." */
  3400. pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
  3401. if (pos == 0) {
  3402. dev_err(&pdev->dev,
  3403. "hpsa_reset_controller: "
  3404. "PCI PM not supported\n");
  3405. return -ENODEV;
  3406. }
  3407. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  3408. /* enter the D3hot power management state */
  3409. pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
  3410. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  3411. pmcsr |= PCI_D3hot;
  3412. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  3413. msleep(500);
  3414. /* enter the D0 power management state */
  3415. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  3416. pmcsr |= PCI_D0;
  3417. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  3418. /*
  3419. * The P600 requires a small delay when changing states.
  3420. * Otherwise we may think the board did not reset and we bail.
  3421. * This for kdump only and is particular to the P600.
  3422. */
  3423. msleep(500);
  3424. }
  3425. return 0;
  3426. }
  3427. static void init_driver_version(char *driver_version, int len)
  3428. {
  3429. memset(driver_version, 0, len);
  3430. strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
  3431. }
  3432. static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
  3433. {
  3434. char *driver_version;
  3435. int i, size = sizeof(cfgtable->driver_version);
  3436. driver_version = kmalloc(size, GFP_KERNEL);
  3437. if (!driver_version)
  3438. return -ENOMEM;
  3439. init_driver_version(driver_version, size);
  3440. for (i = 0; i < size; i++)
  3441. writeb(driver_version[i], &cfgtable->driver_version[i]);
  3442. kfree(driver_version);
  3443. return 0;
  3444. }
  3445. static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
  3446. unsigned char *driver_ver)
  3447. {
  3448. int i;
  3449. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  3450. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  3451. }
  3452. static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
  3453. {
  3454. char *driver_ver, *old_driver_ver;
  3455. int rc, size = sizeof(cfgtable->driver_version);
  3456. old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
  3457. if (!old_driver_ver)
  3458. return -ENOMEM;
  3459. driver_ver = old_driver_ver + size;
  3460. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  3461. * should have been changed, otherwise we know the reset failed.
  3462. */
  3463. init_driver_version(old_driver_ver, size);
  3464. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  3465. rc = !memcmp(driver_ver, old_driver_ver, size);
  3466. kfree(old_driver_ver);
  3467. return rc;
  3468. }
  3469. /* This does a hard reset of the controller using PCI power management
  3470. * states or the using the doorbell register.
  3471. */
  3472. static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
  3473. {
  3474. u64 cfg_offset;
  3475. u32 cfg_base_addr;
  3476. u64 cfg_base_addr_index;
  3477. void __iomem *vaddr;
  3478. unsigned long paddr;
  3479. u32 misc_fw_support;
  3480. int rc;
  3481. struct CfgTable __iomem *cfgtable;
  3482. u32 use_doorbell;
  3483. u32 board_id;
  3484. u16 command_register;
  3485. /* For controllers as old as the P600, this is very nearly
  3486. * the same thing as
  3487. *
  3488. * pci_save_state(pci_dev);
  3489. * pci_set_power_state(pci_dev, PCI_D3hot);
  3490. * pci_set_power_state(pci_dev, PCI_D0);
  3491. * pci_restore_state(pci_dev);
  3492. *
  3493. * For controllers newer than the P600, the pci power state
  3494. * method of resetting doesn't work so we have another way
  3495. * using the doorbell register.
  3496. */
  3497. rc = hpsa_lookup_board_id(pdev, &board_id);
  3498. if (rc < 0 || !ctlr_is_resettable(board_id)) {
  3499. dev_warn(&pdev->dev, "Not resetting device.\n");
  3500. return -ENODEV;
  3501. }
  3502. /* if controller is soft- but not hard resettable... */
  3503. if (!ctlr_is_hard_resettable(board_id))
  3504. return -ENOTSUPP; /* try soft reset later. */
  3505. /* Save the PCI command register */
  3506. pci_read_config_word(pdev, 4, &command_register);
  3507. /* Turn the board off. This is so that later pci_restore_state()
  3508. * won't turn the board on before the rest of config space is ready.
  3509. */
  3510. pci_disable_device(pdev);
  3511. pci_save_state(pdev);
  3512. /* find the first memory BAR, so we can find the cfg table */
  3513. rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
  3514. if (rc)
  3515. return rc;
  3516. vaddr = remap_pci_mem(paddr, 0x250);
  3517. if (!vaddr)
  3518. return -ENOMEM;
  3519. /* find cfgtable in order to check if reset via doorbell is supported */
  3520. rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  3521. &cfg_base_addr_index, &cfg_offset);
  3522. if (rc)
  3523. goto unmap_vaddr;
  3524. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  3525. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  3526. if (!cfgtable) {
  3527. rc = -ENOMEM;
  3528. goto unmap_vaddr;
  3529. }
  3530. rc = write_driver_ver_to_cfgtable(cfgtable);
  3531. if (rc)
  3532. goto unmap_vaddr;
  3533. /* If reset via doorbell register is supported, use that.
  3534. * There are two such methods. Favor the newest method.
  3535. */
  3536. misc_fw_support = readl(&cfgtable->misc_fw_support);
  3537. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
  3538. if (use_doorbell) {
  3539. use_doorbell = DOORBELL_CTLR_RESET2;
  3540. } else {
  3541. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  3542. if (use_doorbell) {
  3543. dev_warn(&pdev->dev, "Soft reset not supported. "
  3544. "Firmware update is required.\n");
  3545. rc = -ENOTSUPP; /* try soft reset */
  3546. goto unmap_cfgtable;
  3547. }
  3548. }
  3549. rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
  3550. if (rc)
  3551. goto unmap_cfgtable;
  3552. pci_restore_state(pdev);
  3553. rc = pci_enable_device(pdev);
  3554. if (rc) {
  3555. dev_warn(&pdev->dev, "failed to enable device.\n");
  3556. goto unmap_cfgtable;
  3557. }
  3558. pci_write_config_word(pdev, 4, command_register);
  3559. /* Some devices (notably the HP Smart Array 5i Controller)
  3560. need a little pause here */
  3561. msleep(HPSA_POST_RESET_PAUSE_MSECS);
  3562. /* Wait for board to become not ready, then ready. */
  3563. dev_info(&pdev->dev, "Waiting for board to reset.\n");
  3564. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
  3565. if (rc) {
  3566. dev_warn(&pdev->dev,
  3567. "failed waiting for board to reset."
  3568. " Will try soft reset.\n");
  3569. rc = -ENOTSUPP; /* Not expected, but try soft reset later */
  3570. goto unmap_cfgtable;
  3571. }
  3572. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
  3573. if (rc) {
  3574. dev_warn(&pdev->dev,
  3575. "failed waiting for board to become ready "
  3576. "after hard reset\n");
  3577. goto unmap_cfgtable;
  3578. }
  3579. rc = controller_reset_failed(vaddr);
  3580. if (rc < 0)
  3581. goto unmap_cfgtable;
  3582. if (rc) {
  3583. dev_warn(&pdev->dev, "Unable to successfully reset "
  3584. "controller. Will try soft reset.\n");
  3585. rc = -ENOTSUPP;
  3586. } else {
  3587. dev_info(&pdev->dev, "board ready after hard reset.\n");
  3588. }
  3589. unmap_cfgtable:
  3590. iounmap(cfgtable);
  3591. unmap_vaddr:
  3592. iounmap(vaddr);
  3593. return rc;
  3594. }
  3595. /*
  3596. * We cannot read the structure directly, for portability we must use
  3597. * the io functions.
  3598. * This is for debug only.
  3599. */
  3600. static void print_cfg_table(struct device *dev, struct CfgTable *tb)
  3601. {
  3602. #ifdef HPSA_DEBUG
  3603. int i;
  3604. char temp_name[17];
  3605. dev_info(dev, "Controller Configuration information\n");
  3606. dev_info(dev, "------------------------------------\n");
  3607. for (i = 0; i < 4; i++)
  3608. temp_name[i] = readb(&(tb->Signature[i]));
  3609. temp_name[4] = '\0';
  3610. dev_info(dev, " Signature = %s\n", temp_name);
  3611. dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
  3612. dev_info(dev, " Transport methods supported = 0x%x\n",
  3613. readl(&(tb->TransportSupport)));
  3614. dev_info(dev, " Transport methods active = 0x%x\n",
  3615. readl(&(tb->TransportActive)));
  3616. dev_info(dev, " Requested transport Method = 0x%x\n",
  3617. readl(&(tb->HostWrite.TransportRequest)));
  3618. dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
  3619. readl(&(tb->HostWrite.CoalIntDelay)));
  3620. dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
  3621. readl(&(tb->HostWrite.CoalIntCount)));
  3622. dev_info(dev, " Max outstanding commands = 0x%d\n",
  3623. readl(&(tb->CmdsOutMax)));
  3624. dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
  3625. for (i = 0; i < 16; i++)
  3626. temp_name[i] = readb(&(tb->ServerName[i]));
  3627. temp_name[16] = '\0';
  3628. dev_info(dev, " Server Name = %s\n", temp_name);
  3629. dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
  3630. readl(&(tb->HeartBeat)));
  3631. #endif /* HPSA_DEBUG */
  3632. }
  3633. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  3634. {
  3635. int i, offset, mem_type, bar_type;
  3636. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  3637. return 0;
  3638. offset = 0;
  3639. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  3640. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  3641. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  3642. offset += 4;
  3643. else {
  3644. mem_type = pci_resource_flags(pdev, i) &
  3645. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  3646. switch (mem_type) {
  3647. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  3648. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  3649. offset += 4; /* 32 bit */
  3650. break;
  3651. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  3652. offset += 8;
  3653. break;
  3654. default: /* reserved in PCI 2.2 */
  3655. dev_warn(&pdev->dev,
  3656. "base address is invalid\n");
  3657. return -1;
  3658. break;
  3659. }
  3660. }
  3661. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  3662. return i + 1;
  3663. }
  3664. return -1;
  3665. }
  3666. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  3667. * controllers that are capable. If not, we use IO-APIC mode.
  3668. */
  3669. static void hpsa_interrupt_mode(struct ctlr_info *h)
  3670. {
  3671. #ifdef CONFIG_PCI_MSI
  3672. int err, i;
  3673. struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
  3674. for (i = 0; i < MAX_REPLY_QUEUES; i++) {
  3675. hpsa_msix_entries[i].vector = 0;
  3676. hpsa_msix_entries[i].entry = i;
  3677. }
  3678. /* Some boards advertise MSI but don't really support it */
  3679. if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
  3680. (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
  3681. goto default_int_mode;
  3682. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
  3683. dev_info(&h->pdev->dev, "MSIX\n");
  3684. err = pci_enable_msix(h->pdev, hpsa_msix_entries,
  3685. MAX_REPLY_QUEUES);
  3686. if (!err) {
  3687. for (i = 0; i < MAX_REPLY_QUEUES; i++)
  3688. h->intr[i] = hpsa_msix_entries[i].vector;
  3689. h->msix_vector = 1;
  3690. return;
  3691. }
  3692. if (err > 0) {
  3693. dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
  3694. "available\n", err);
  3695. goto default_int_mode;
  3696. } else {
  3697. dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
  3698. err);
  3699. goto default_int_mode;
  3700. }
  3701. }
  3702. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
  3703. dev_info(&h->pdev->dev, "MSI\n");
  3704. if (!pci_enable_msi(h->pdev))
  3705. h->msi_vector = 1;
  3706. else
  3707. dev_warn(&h->pdev->dev, "MSI init failed\n");
  3708. }
  3709. default_int_mode:
  3710. #endif /* CONFIG_PCI_MSI */
  3711. /* if we get here we're going to use the default interrupt mode */
  3712. h->intr[h->intr_mode] = h->pdev->irq;
  3713. }
  3714. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
  3715. {
  3716. int i;
  3717. u32 subsystem_vendor_id, subsystem_device_id;
  3718. subsystem_vendor_id = pdev->subsystem_vendor;
  3719. subsystem_device_id = pdev->subsystem_device;
  3720. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  3721. subsystem_vendor_id;
  3722. for (i = 0; i < ARRAY_SIZE(products); i++)
  3723. if (*board_id == products[i].board_id)
  3724. return i;
  3725. if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
  3726. subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
  3727. !hpsa_allow_any) {
  3728. dev_warn(&pdev->dev, "unrecognized board ID: "
  3729. "0x%08x, ignoring.\n", *board_id);
  3730. return -ENODEV;
  3731. }
  3732. return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
  3733. }
  3734. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  3735. unsigned long *memory_bar)
  3736. {
  3737. int i;
  3738. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  3739. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  3740. /* addressing mode bits already removed */
  3741. *memory_bar = pci_resource_start(pdev, i);
  3742. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  3743. *memory_bar);
  3744. return 0;
  3745. }
  3746. dev_warn(&pdev->dev, "no memory BAR found\n");
  3747. return -ENODEV;
  3748. }
  3749. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  3750. int wait_for_ready)
  3751. {
  3752. int i, iterations;
  3753. u32 scratchpad;
  3754. if (wait_for_ready)
  3755. iterations = HPSA_BOARD_READY_ITERATIONS;
  3756. else
  3757. iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
  3758. for (i = 0; i < iterations; i++) {
  3759. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  3760. if (wait_for_ready) {
  3761. if (scratchpad == HPSA_FIRMWARE_READY)
  3762. return 0;
  3763. } else {
  3764. if (scratchpad != HPSA_FIRMWARE_READY)
  3765. return 0;
  3766. }
  3767. msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
  3768. }
  3769. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  3770. return -ENODEV;
  3771. }
  3772. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  3773. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  3774. u64 *cfg_offset)
  3775. {
  3776. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  3777. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  3778. *cfg_base_addr &= (u32) 0x0000ffff;
  3779. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  3780. if (*cfg_base_addr_index == -1) {
  3781. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
  3782. return -ENODEV;
  3783. }
  3784. return 0;
  3785. }
  3786. static int hpsa_find_cfgtables(struct ctlr_info *h)
  3787. {
  3788. u64 cfg_offset;
  3789. u32 cfg_base_addr;
  3790. u64 cfg_base_addr_index;
  3791. u32 trans_offset;
  3792. int rc;
  3793. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  3794. &cfg_base_addr_index, &cfg_offset);
  3795. if (rc)
  3796. return rc;
  3797. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  3798. cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
  3799. if (!h->cfgtable)
  3800. return -ENOMEM;
  3801. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  3802. if (rc)
  3803. return rc;
  3804. /* Find performant mode table. */
  3805. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  3806. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  3807. cfg_base_addr_index)+cfg_offset+trans_offset,
  3808. sizeof(*h->transtable));
  3809. if (!h->transtable)
  3810. return -ENOMEM;
  3811. return 0;
  3812. }
  3813. static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
  3814. {
  3815. h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
  3816. /* Limit commands in memory limited kdump scenario. */
  3817. if (reset_devices && h->max_commands > 32)
  3818. h->max_commands = 32;
  3819. if (h->max_commands < 16) {
  3820. dev_warn(&h->pdev->dev, "Controller reports "
  3821. "max supported commands of %d, an obvious lie. "
  3822. "Using 16. Ensure that firmware is up to date.\n",
  3823. h->max_commands);
  3824. h->max_commands = 16;
  3825. }
  3826. }
  3827. /* Interrogate the hardware for some limits:
  3828. * max commands, max SG elements without chaining, and with chaining,
  3829. * SG chain block size, etc.
  3830. */
  3831. static void hpsa_find_board_params(struct ctlr_info *h)
  3832. {
  3833. hpsa_get_max_perf_mode_cmds(h);
  3834. h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
  3835. h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
  3836. /*
  3837. * Limit in-command s/g elements to 32 save dma'able memory.
  3838. * Howvever spec says if 0, use 31
  3839. */
  3840. h->max_cmd_sg_entries = 31;
  3841. if (h->maxsgentries > 512) {
  3842. h->max_cmd_sg_entries = 32;
  3843. h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
  3844. h->maxsgentries--; /* save one for chain pointer */
  3845. } else {
  3846. h->maxsgentries = 31; /* default to traditional values */
  3847. h->chainsize = 0;
  3848. }
  3849. /* Find out what task management functions are supported and cache */
  3850. h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
  3851. }
  3852. static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
  3853. {
  3854. if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
  3855. dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
  3856. return false;
  3857. }
  3858. return true;
  3859. }
  3860. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  3861. static inline void hpsa_enable_scsi_prefetch(struct ctlr_info *h)
  3862. {
  3863. #ifdef CONFIG_X86
  3864. u32 prefetch;
  3865. prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
  3866. prefetch |= 0x100;
  3867. writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
  3868. #endif
  3869. }
  3870. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  3871. * in a prefetch beyond physical memory.
  3872. */
  3873. static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
  3874. {
  3875. u32 dma_prefetch;
  3876. if (h->board_id != 0x3225103C)
  3877. return;
  3878. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  3879. dma_prefetch |= 0x8000;
  3880. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  3881. }
  3882. static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
  3883. {
  3884. int i;
  3885. u32 doorbell_value;
  3886. unsigned long flags;
  3887. /* under certain very rare conditions, this can take awhile.
  3888. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  3889. * as we enter this code.)
  3890. */
  3891. for (i = 0; i < MAX_CONFIG_WAIT; i++) {
  3892. spin_lock_irqsave(&h->lock, flags);
  3893. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  3894. spin_unlock_irqrestore(&h->lock, flags);
  3895. if (!(doorbell_value & CFGTBL_ChangeReq))
  3896. break;
  3897. /* delay and try again */
  3898. usleep_range(10000, 20000);
  3899. }
  3900. }
  3901. static int hpsa_enter_simple_mode(struct ctlr_info *h)
  3902. {
  3903. u32 trans_support;
  3904. trans_support = readl(&(h->cfgtable->TransportSupport));
  3905. if (!(trans_support & SIMPLE_MODE))
  3906. return -ENOTSUPP;
  3907. h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
  3908. /* Update the field, and then ring the doorbell */
  3909. writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
  3910. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  3911. hpsa_wait_for_mode_change_ack(h);
  3912. print_cfg_table(&h->pdev->dev, h->cfgtable);
  3913. if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
  3914. dev_warn(&h->pdev->dev,
  3915. "unable to get board into simple mode\n");
  3916. return -ENODEV;
  3917. }
  3918. h->transMethod = CFGTBL_Trans_Simple;
  3919. return 0;
  3920. }
  3921. static int hpsa_pci_init(struct ctlr_info *h)
  3922. {
  3923. int prod_index, err;
  3924. prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
  3925. if (prod_index < 0)
  3926. return -ENODEV;
  3927. h->product_name = products[prod_index].product_name;
  3928. h->access = *(products[prod_index].access);
  3929. pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
  3930. PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
  3931. err = pci_enable_device(h->pdev);
  3932. if (err) {
  3933. dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
  3934. return err;
  3935. }
  3936. /* Enable bus mastering (pci_disable_device may disable this) */
  3937. pci_set_master(h->pdev);
  3938. err = pci_request_regions(h->pdev, HPSA);
  3939. if (err) {
  3940. dev_err(&h->pdev->dev,
  3941. "cannot obtain PCI resources, aborting\n");
  3942. return err;
  3943. }
  3944. hpsa_interrupt_mode(h);
  3945. err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
  3946. if (err)
  3947. goto err_out_free_res;
  3948. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  3949. if (!h->vaddr) {
  3950. err = -ENOMEM;
  3951. goto err_out_free_res;
  3952. }
  3953. err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  3954. if (err)
  3955. goto err_out_free_res;
  3956. err = hpsa_find_cfgtables(h);
  3957. if (err)
  3958. goto err_out_free_res;
  3959. hpsa_find_board_params(h);
  3960. if (!hpsa_CISS_signature_present(h)) {
  3961. err = -ENODEV;
  3962. goto err_out_free_res;
  3963. }
  3964. hpsa_enable_scsi_prefetch(h);
  3965. hpsa_p600_dma_prefetch_quirk(h);
  3966. err = hpsa_enter_simple_mode(h);
  3967. if (err)
  3968. goto err_out_free_res;
  3969. return 0;
  3970. err_out_free_res:
  3971. if (h->transtable)
  3972. iounmap(h->transtable);
  3973. if (h->cfgtable)
  3974. iounmap(h->cfgtable);
  3975. if (h->vaddr)
  3976. iounmap(h->vaddr);
  3977. pci_disable_device(h->pdev);
  3978. pci_release_regions(h->pdev);
  3979. return err;
  3980. }
  3981. static void hpsa_hba_inquiry(struct ctlr_info *h)
  3982. {
  3983. int rc;
  3984. #define HBA_INQUIRY_BYTE_COUNT 64
  3985. h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
  3986. if (!h->hba_inquiry_data)
  3987. return;
  3988. rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
  3989. h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
  3990. if (rc != 0) {
  3991. kfree(h->hba_inquiry_data);
  3992. h->hba_inquiry_data = NULL;
  3993. }
  3994. }
  3995. static int hpsa_init_reset_devices(struct pci_dev *pdev)
  3996. {
  3997. int rc, i;
  3998. if (!reset_devices)
  3999. return 0;
  4000. /* Reset the controller with a PCI power-cycle or via doorbell */
  4001. rc = hpsa_kdump_hard_reset_controller(pdev);
  4002. /* -ENOTSUPP here means we cannot reset the controller
  4003. * but it's already (and still) up and running in
  4004. * "performant mode". Or, it might be 640x, which can't reset
  4005. * due to concerns about shared bbwc between 6402/6404 pair.
  4006. */
  4007. if (rc == -ENOTSUPP)
  4008. return rc; /* just try to do the kdump anyhow. */
  4009. if (rc)
  4010. return -ENODEV;
  4011. /* Now try to get the controller to respond to a no-op */
  4012. dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
  4013. for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
  4014. if (hpsa_noop(pdev) == 0)
  4015. break;
  4016. else
  4017. dev_warn(&pdev->dev, "no-op failed%s\n",
  4018. (i < 11 ? "; re-trying" : ""));
  4019. }
  4020. return 0;
  4021. }
  4022. static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
  4023. {
  4024. h->cmd_pool_bits = kzalloc(
  4025. DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
  4026. sizeof(unsigned long), GFP_KERNEL);
  4027. h->cmd_pool = pci_alloc_consistent(h->pdev,
  4028. h->nr_cmds * sizeof(*h->cmd_pool),
  4029. &(h->cmd_pool_dhandle));
  4030. h->errinfo_pool = pci_alloc_consistent(h->pdev,
  4031. h->nr_cmds * sizeof(*h->errinfo_pool),
  4032. &(h->errinfo_pool_dhandle));
  4033. if ((h->cmd_pool_bits == NULL)
  4034. || (h->cmd_pool == NULL)
  4035. || (h->errinfo_pool == NULL)) {
  4036. dev_err(&h->pdev->dev, "out of memory in %s", __func__);
  4037. return -ENOMEM;
  4038. }
  4039. return 0;
  4040. }
  4041. static void hpsa_free_cmd_pool(struct ctlr_info *h)
  4042. {
  4043. kfree(h->cmd_pool_bits);
  4044. if (h->cmd_pool)
  4045. pci_free_consistent(h->pdev,
  4046. h->nr_cmds * sizeof(struct CommandList),
  4047. h->cmd_pool, h->cmd_pool_dhandle);
  4048. if (h->errinfo_pool)
  4049. pci_free_consistent(h->pdev,
  4050. h->nr_cmds * sizeof(struct ErrorInfo),
  4051. h->errinfo_pool,
  4052. h->errinfo_pool_dhandle);
  4053. }
  4054. static int hpsa_request_irq(struct ctlr_info *h,
  4055. irqreturn_t (*msixhandler)(int, void *),
  4056. irqreturn_t (*intxhandler)(int, void *))
  4057. {
  4058. int rc, i;
  4059. /*
  4060. * initialize h->q[x] = x so that interrupt handlers know which
  4061. * queue to process.
  4062. */
  4063. for (i = 0; i < MAX_REPLY_QUEUES; i++)
  4064. h->q[i] = (u8) i;
  4065. if (h->intr_mode == PERF_MODE_INT && h->msix_vector) {
  4066. /* If performant mode and MSI-X, use multiple reply queues */
  4067. for (i = 0; i < MAX_REPLY_QUEUES; i++)
  4068. rc = request_irq(h->intr[i], msixhandler,
  4069. 0, h->devname,
  4070. &h->q[i]);
  4071. } else {
  4072. /* Use single reply pool */
  4073. if (h->msix_vector || h->msi_vector) {
  4074. rc = request_irq(h->intr[h->intr_mode],
  4075. msixhandler, 0, h->devname,
  4076. &h->q[h->intr_mode]);
  4077. } else {
  4078. rc = request_irq(h->intr[h->intr_mode],
  4079. intxhandler, IRQF_SHARED, h->devname,
  4080. &h->q[h->intr_mode]);
  4081. }
  4082. }
  4083. if (rc) {
  4084. dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
  4085. h->intr[h->intr_mode], h->devname);
  4086. return -ENODEV;
  4087. }
  4088. return 0;
  4089. }
  4090. static int hpsa_kdump_soft_reset(struct ctlr_info *h)
  4091. {
  4092. if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
  4093. HPSA_RESET_TYPE_CONTROLLER)) {
  4094. dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
  4095. return -EIO;
  4096. }
  4097. dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
  4098. if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
  4099. dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
  4100. return -1;
  4101. }
  4102. dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
  4103. if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
  4104. dev_warn(&h->pdev->dev, "Board failed to become ready "
  4105. "after soft reset.\n");
  4106. return -1;
  4107. }
  4108. return 0;
  4109. }
  4110. static void free_irqs(struct ctlr_info *h)
  4111. {
  4112. int i;
  4113. if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
  4114. /* Single reply queue, only one irq to free */
  4115. i = h->intr_mode;
  4116. free_irq(h->intr[i], &h->q[i]);
  4117. return;
  4118. }
  4119. for (i = 0; i < MAX_REPLY_QUEUES; i++)
  4120. free_irq(h->intr[i], &h->q[i]);
  4121. }
  4122. static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
  4123. {
  4124. free_irqs(h);
  4125. #ifdef CONFIG_PCI_MSI
  4126. if (h->msix_vector) {
  4127. if (h->pdev->msix_enabled)
  4128. pci_disable_msix(h->pdev);
  4129. } else if (h->msi_vector) {
  4130. if (h->pdev->msi_enabled)
  4131. pci_disable_msi(h->pdev);
  4132. }
  4133. #endif /* CONFIG_PCI_MSI */
  4134. }
  4135. static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
  4136. {
  4137. hpsa_free_irqs_and_disable_msix(h);
  4138. hpsa_free_sg_chain_blocks(h);
  4139. hpsa_free_cmd_pool(h);
  4140. kfree(h->blockFetchTable);
  4141. pci_free_consistent(h->pdev, h->reply_pool_size,
  4142. h->reply_pool, h->reply_pool_dhandle);
  4143. if (h->vaddr)
  4144. iounmap(h->vaddr);
  4145. if (h->transtable)
  4146. iounmap(h->transtable);
  4147. if (h->cfgtable)
  4148. iounmap(h->cfgtable);
  4149. pci_release_regions(h->pdev);
  4150. kfree(h);
  4151. }
  4152. static void remove_ctlr_from_lockup_detector_list(struct ctlr_info *h)
  4153. {
  4154. assert_spin_locked(&lockup_detector_lock);
  4155. if (!hpsa_lockup_detector)
  4156. return;
  4157. if (h->lockup_detected)
  4158. return; /* already stopped the lockup detector */
  4159. list_del(&h->lockup_list);
  4160. }
  4161. /* Called when controller lockup detected. */
  4162. static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
  4163. {
  4164. struct CommandList *c = NULL;
  4165. assert_spin_locked(&h->lock);
  4166. /* Mark all outstanding commands as failed and complete them. */
  4167. while (!list_empty(list)) {
  4168. c = list_entry(list->next, struct CommandList, list);
  4169. c->err_info->CommandStatus = CMD_HARDWARE_ERR;
  4170. finish_cmd(c);
  4171. }
  4172. }
  4173. static void controller_lockup_detected(struct ctlr_info *h)
  4174. {
  4175. unsigned long flags;
  4176. assert_spin_locked(&lockup_detector_lock);
  4177. remove_ctlr_from_lockup_detector_list(h);
  4178. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  4179. spin_lock_irqsave(&h->lock, flags);
  4180. h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  4181. spin_unlock_irqrestore(&h->lock, flags);
  4182. dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
  4183. h->lockup_detected);
  4184. pci_disable_device(h->pdev);
  4185. spin_lock_irqsave(&h->lock, flags);
  4186. fail_all_cmds_on_list(h, &h->cmpQ);
  4187. fail_all_cmds_on_list(h, &h->reqQ);
  4188. spin_unlock_irqrestore(&h->lock, flags);
  4189. }
  4190. static void detect_controller_lockup(struct ctlr_info *h)
  4191. {
  4192. u64 now;
  4193. u32 heartbeat;
  4194. unsigned long flags;
  4195. assert_spin_locked(&lockup_detector_lock);
  4196. now = get_jiffies_64();
  4197. /* If we've received an interrupt recently, we're ok. */
  4198. if (time_after64(h->last_intr_timestamp +
  4199. (h->heartbeat_sample_interval), now))
  4200. return;
  4201. /*
  4202. * If we've already checked the heartbeat recently, we're ok.
  4203. * This could happen if someone sends us a signal. We
  4204. * otherwise don't care about signals in this thread.
  4205. */
  4206. if (time_after64(h->last_heartbeat_timestamp +
  4207. (h->heartbeat_sample_interval), now))
  4208. return;
  4209. /* If heartbeat has not changed since we last looked, we're not ok. */
  4210. spin_lock_irqsave(&h->lock, flags);
  4211. heartbeat = readl(&h->cfgtable->HeartBeat);
  4212. spin_unlock_irqrestore(&h->lock, flags);
  4213. if (h->last_heartbeat == heartbeat) {
  4214. controller_lockup_detected(h);
  4215. return;
  4216. }
  4217. /* We're ok. */
  4218. h->last_heartbeat = heartbeat;
  4219. h->last_heartbeat_timestamp = now;
  4220. }
  4221. static int detect_controller_lockup_thread(void *notused)
  4222. {
  4223. struct ctlr_info *h;
  4224. unsigned long flags;
  4225. while (1) {
  4226. struct list_head *this, *tmp;
  4227. schedule_timeout_interruptible(HEARTBEAT_SAMPLE_INTERVAL);
  4228. if (kthread_should_stop())
  4229. break;
  4230. spin_lock_irqsave(&lockup_detector_lock, flags);
  4231. list_for_each_safe(this, tmp, &hpsa_ctlr_list) {
  4232. h = list_entry(this, struct ctlr_info, lockup_list);
  4233. detect_controller_lockup(h);
  4234. }
  4235. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  4236. }
  4237. return 0;
  4238. }
  4239. static void add_ctlr_to_lockup_detector_list(struct ctlr_info *h)
  4240. {
  4241. unsigned long flags;
  4242. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  4243. spin_lock_irqsave(&lockup_detector_lock, flags);
  4244. list_add_tail(&h->lockup_list, &hpsa_ctlr_list);
  4245. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  4246. }
  4247. static void start_controller_lockup_detector(struct ctlr_info *h)
  4248. {
  4249. /* Start the lockup detector thread if not already started */
  4250. if (!hpsa_lockup_detector) {
  4251. spin_lock_init(&lockup_detector_lock);
  4252. hpsa_lockup_detector =
  4253. kthread_run(detect_controller_lockup_thread,
  4254. NULL, HPSA);
  4255. }
  4256. if (!hpsa_lockup_detector) {
  4257. dev_warn(&h->pdev->dev,
  4258. "Could not start lockup detector thread\n");
  4259. return;
  4260. }
  4261. add_ctlr_to_lockup_detector_list(h);
  4262. }
  4263. static void stop_controller_lockup_detector(struct ctlr_info *h)
  4264. {
  4265. unsigned long flags;
  4266. spin_lock_irqsave(&lockup_detector_lock, flags);
  4267. remove_ctlr_from_lockup_detector_list(h);
  4268. /* If the list of ctlr's to monitor is empty, stop the thread */
  4269. if (list_empty(&hpsa_ctlr_list)) {
  4270. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  4271. kthread_stop(hpsa_lockup_detector);
  4272. spin_lock_irqsave(&lockup_detector_lock, flags);
  4273. hpsa_lockup_detector = NULL;
  4274. }
  4275. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  4276. }
  4277. static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  4278. {
  4279. int dac, rc;
  4280. struct ctlr_info *h;
  4281. int try_soft_reset = 0;
  4282. unsigned long flags;
  4283. if (number_of_controllers == 0)
  4284. printk(KERN_INFO DRIVER_NAME "\n");
  4285. rc = hpsa_init_reset_devices(pdev);
  4286. if (rc) {
  4287. if (rc != -ENOTSUPP)
  4288. return rc;
  4289. /* If the reset fails in a particular way (it has no way to do
  4290. * a proper hard reset, so returns -ENOTSUPP) we can try to do
  4291. * a soft reset once we get the controller configured up to the
  4292. * point that it can accept a command.
  4293. */
  4294. try_soft_reset = 1;
  4295. rc = 0;
  4296. }
  4297. reinit_after_soft_reset:
  4298. /* Command structures must be aligned on a 32-byte boundary because
  4299. * the 5 lower bits of the address are used by the hardware. and by
  4300. * the driver. See comments in hpsa.h for more info.
  4301. */
  4302. #define COMMANDLIST_ALIGNMENT 32
  4303. BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
  4304. h = kzalloc(sizeof(*h), GFP_KERNEL);
  4305. if (!h)
  4306. return -ENOMEM;
  4307. h->pdev = pdev;
  4308. h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
  4309. INIT_LIST_HEAD(&h->cmpQ);
  4310. INIT_LIST_HEAD(&h->reqQ);
  4311. spin_lock_init(&h->lock);
  4312. spin_lock_init(&h->scan_lock);
  4313. rc = hpsa_pci_init(h);
  4314. if (rc != 0)
  4315. goto clean1;
  4316. sprintf(h->devname, HPSA "%d", number_of_controllers);
  4317. h->ctlr = number_of_controllers;
  4318. number_of_controllers++;
  4319. /* configure PCI DMA stuff */
  4320. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  4321. if (rc == 0) {
  4322. dac = 1;
  4323. } else {
  4324. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  4325. if (rc == 0) {
  4326. dac = 0;
  4327. } else {
  4328. dev_err(&pdev->dev, "no suitable DMA available\n");
  4329. goto clean1;
  4330. }
  4331. }
  4332. /* make sure the board interrupts are off */
  4333. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  4334. if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
  4335. goto clean2;
  4336. dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
  4337. h->devname, pdev->device,
  4338. h->intr[h->intr_mode], dac ? "" : " not");
  4339. if (hpsa_allocate_cmd_pool(h))
  4340. goto clean4;
  4341. if (hpsa_allocate_sg_chain_blocks(h))
  4342. goto clean4;
  4343. init_waitqueue_head(&h->scan_wait_queue);
  4344. h->scan_finished = 1; /* no scan currently in progress */
  4345. pci_set_drvdata(pdev, h);
  4346. h->ndevices = 0;
  4347. h->scsi_host = NULL;
  4348. spin_lock_init(&h->devlock);
  4349. hpsa_put_ctlr_into_performant_mode(h);
  4350. /* At this point, the controller is ready to take commands.
  4351. * Now, if reset_devices and the hard reset didn't work, try
  4352. * the soft reset and see if that works.
  4353. */
  4354. if (try_soft_reset) {
  4355. /* This is kind of gross. We may or may not get a completion
  4356. * from the soft reset command, and if we do, then the value
  4357. * from the fifo may or may not be valid. So, we wait 10 secs
  4358. * after the reset throwing away any completions we get during
  4359. * that time. Unregister the interrupt handler and register
  4360. * fake ones to scoop up any residual completions.
  4361. */
  4362. spin_lock_irqsave(&h->lock, flags);
  4363. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  4364. spin_unlock_irqrestore(&h->lock, flags);
  4365. free_irqs(h);
  4366. rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
  4367. hpsa_intx_discard_completions);
  4368. if (rc) {
  4369. dev_warn(&h->pdev->dev, "Failed to request_irq after "
  4370. "soft reset.\n");
  4371. goto clean4;
  4372. }
  4373. rc = hpsa_kdump_soft_reset(h);
  4374. if (rc)
  4375. /* Neither hard nor soft reset worked, we're hosed. */
  4376. goto clean4;
  4377. dev_info(&h->pdev->dev, "Board READY.\n");
  4378. dev_info(&h->pdev->dev,
  4379. "Waiting for stale completions to drain.\n");
  4380. h->access.set_intr_mask(h, HPSA_INTR_ON);
  4381. msleep(10000);
  4382. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  4383. rc = controller_reset_failed(h->cfgtable);
  4384. if (rc)
  4385. dev_info(&h->pdev->dev,
  4386. "Soft reset appears to have failed.\n");
  4387. /* since the controller's reset, we have to go back and re-init
  4388. * everything. Easiest to just forget what we've done and do it
  4389. * all over again.
  4390. */
  4391. hpsa_undo_allocations_after_kdump_soft_reset(h);
  4392. try_soft_reset = 0;
  4393. if (rc)
  4394. /* don't go to clean4, we already unallocated */
  4395. return -ENODEV;
  4396. goto reinit_after_soft_reset;
  4397. }
  4398. /* Turn the interrupts on so we can service requests */
  4399. h->access.set_intr_mask(h, HPSA_INTR_ON);
  4400. hpsa_hba_inquiry(h);
  4401. hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
  4402. start_controller_lockup_detector(h);
  4403. return 1;
  4404. clean4:
  4405. hpsa_free_sg_chain_blocks(h);
  4406. hpsa_free_cmd_pool(h);
  4407. free_irqs(h);
  4408. clean2:
  4409. clean1:
  4410. kfree(h);
  4411. return rc;
  4412. }
  4413. static void hpsa_flush_cache(struct ctlr_info *h)
  4414. {
  4415. char *flush_buf;
  4416. struct CommandList *c;
  4417. flush_buf = kzalloc(4, GFP_KERNEL);
  4418. if (!flush_buf)
  4419. return;
  4420. c = cmd_special_alloc(h);
  4421. if (!c) {
  4422. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  4423. goto out_of_memory;
  4424. }
  4425. if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
  4426. RAID_CTLR_LUNID, TYPE_CMD)) {
  4427. goto out;
  4428. }
  4429. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
  4430. if (c->err_info->CommandStatus != 0)
  4431. out:
  4432. dev_warn(&h->pdev->dev,
  4433. "error flushing cache on controller\n");
  4434. cmd_special_free(h, c);
  4435. out_of_memory:
  4436. kfree(flush_buf);
  4437. }
  4438. static void hpsa_shutdown(struct pci_dev *pdev)
  4439. {
  4440. struct ctlr_info *h;
  4441. h = pci_get_drvdata(pdev);
  4442. /* Turn board interrupts off and send the flush cache command
  4443. * sendcmd will turn off interrupt, and send the flush...
  4444. * To write all data in the battery backed cache to disks
  4445. */
  4446. hpsa_flush_cache(h);
  4447. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  4448. hpsa_free_irqs_and_disable_msix(h);
  4449. }
  4450. static void hpsa_free_device_info(struct ctlr_info *h)
  4451. {
  4452. int i;
  4453. for (i = 0; i < h->ndevices; i++)
  4454. kfree(h->dev[i]);
  4455. }
  4456. static void hpsa_remove_one(struct pci_dev *pdev)
  4457. {
  4458. struct ctlr_info *h;
  4459. if (pci_get_drvdata(pdev) == NULL) {
  4460. dev_err(&pdev->dev, "unable to remove device\n");
  4461. return;
  4462. }
  4463. h = pci_get_drvdata(pdev);
  4464. stop_controller_lockup_detector(h);
  4465. hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
  4466. hpsa_shutdown(pdev);
  4467. iounmap(h->vaddr);
  4468. iounmap(h->transtable);
  4469. iounmap(h->cfgtable);
  4470. hpsa_free_device_info(h);
  4471. hpsa_free_sg_chain_blocks(h);
  4472. pci_free_consistent(h->pdev,
  4473. h->nr_cmds * sizeof(struct CommandList),
  4474. h->cmd_pool, h->cmd_pool_dhandle);
  4475. pci_free_consistent(h->pdev,
  4476. h->nr_cmds * sizeof(struct ErrorInfo),
  4477. h->errinfo_pool, h->errinfo_pool_dhandle);
  4478. pci_free_consistent(h->pdev, h->reply_pool_size,
  4479. h->reply_pool, h->reply_pool_dhandle);
  4480. kfree(h->cmd_pool_bits);
  4481. kfree(h->blockFetchTable);
  4482. kfree(h->hba_inquiry_data);
  4483. pci_disable_device(pdev);
  4484. pci_release_regions(pdev);
  4485. kfree(h);
  4486. }
  4487. static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
  4488. __attribute__((unused)) pm_message_t state)
  4489. {
  4490. return -ENOSYS;
  4491. }
  4492. static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
  4493. {
  4494. return -ENOSYS;
  4495. }
  4496. static struct pci_driver hpsa_pci_driver = {
  4497. .name = HPSA,
  4498. .probe = hpsa_init_one,
  4499. .remove = hpsa_remove_one,
  4500. .id_table = hpsa_pci_device_id, /* id_table */
  4501. .shutdown = hpsa_shutdown,
  4502. .suspend = hpsa_suspend,
  4503. .resume = hpsa_resume,
  4504. };
  4505. /* Fill in bucket_map[], given nsgs (the max number of
  4506. * scatter gather elements supported) and bucket[],
  4507. * which is an array of 8 integers. The bucket[] array
  4508. * contains 8 different DMA transfer sizes (in 16
  4509. * byte increments) which the controller uses to fetch
  4510. * commands. This function fills in bucket_map[], which
  4511. * maps a given number of scatter gather elements to one of
  4512. * the 8 DMA transfer sizes. The point of it is to allow the
  4513. * controller to only do as much DMA as needed to fetch the
  4514. * command, with the DMA transfer size encoded in the lower
  4515. * bits of the command address.
  4516. */
  4517. static void calc_bucket_map(int bucket[], int num_buckets,
  4518. int nsgs, int *bucket_map)
  4519. {
  4520. int i, j, b, size;
  4521. /* even a command with 0 SGs requires 4 blocks */
  4522. #define MINIMUM_TRANSFER_BLOCKS 4
  4523. #define NUM_BUCKETS 8
  4524. /* Note, bucket_map must have nsgs+1 entries. */
  4525. for (i = 0; i <= nsgs; i++) {
  4526. /* Compute size of a command with i SG entries */
  4527. size = i + MINIMUM_TRANSFER_BLOCKS;
  4528. b = num_buckets; /* Assume the biggest bucket */
  4529. /* Find the bucket that is just big enough */
  4530. for (j = 0; j < 8; j++) {
  4531. if (bucket[j] >= size) {
  4532. b = j;
  4533. break;
  4534. }
  4535. }
  4536. /* for a command with i SG entries, use bucket b. */
  4537. bucket_map[i] = b;
  4538. }
  4539. }
  4540. static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 use_short_tags)
  4541. {
  4542. int i;
  4543. unsigned long register_value;
  4544. /* This is a bit complicated. There are 8 registers on
  4545. * the controller which we write to to tell it 8 different
  4546. * sizes of commands which there may be. It's a way of
  4547. * reducing the DMA done to fetch each command. Encoded into
  4548. * each command's tag are 3 bits which communicate to the controller
  4549. * which of the eight sizes that command fits within. The size of
  4550. * each command depends on how many scatter gather entries there are.
  4551. * Each SG entry requires 16 bytes. The eight registers are programmed
  4552. * with the number of 16-byte blocks a command of that size requires.
  4553. * The smallest command possible requires 5 such 16 byte blocks.
  4554. * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
  4555. * blocks. Note, this only extends to the SG entries contained
  4556. * within the command block, and does not extend to chained blocks
  4557. * of SG elements. bft[] contains the eight values we write to
  4558. * the registers. They are not evenly distributed, but have more
  4559. * sizes for small commands, and fewer sizes for larger commands.
  4560. */
  4561. int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
  4562. BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
  4563. /* 5 = 1 s/g entry or 4k
  4564. * 6 = 2 s/g entry or 8k
  4565. * 8 = 4 s/g entry or 16k
  4566. * 10 = 6 s/g entry or 24k
  4567. */
  4568. /* Controller spec: zero out this buffer. */
  4569. memset(h->reply_pool, 0, h->reply_pool_size);
  4570. bft[7] = SG_ENTRIES_IN_CMD + 4;
  4571. calc_bucket_map(bft, ARRAY_SIZE(bft),
  4572. SG_ENTRIES_IN_CMD, h->blockFetchTable);
  4573. for (i = 0; i < 8; i++)
  4574. writel(bft[i], &h->transtable->BlockFetch[i]);
  4575. /* size of controller ring buffer */
  4576. writel(h->max_commands, &h->transtable->RepQSize);
  4577. writel(h->nreply_queues, &h->transtable->RepQCount);
  4578. writel(0, &h->transtable->RepQCtrAddrLow32);
  4579. writel(0, &h->transtable->RepQCtrAddrHigh32);
  4580. for (i = 0; i < h->nreply_queues; i++) {
  4581. writel(0, &h->transtable->RepQAddr[i].upper);
  4582. writel(h->reply_pool_dhandle +
  4583. (h->max_commands * sizeof(u64) * i),
  4584. &h->transtable->RepQAddr[i].lower);
  4585. }
  4586. writel(CFGTBL_Trans_Performant | use_short_tags |
  4587. CFGTBL_Trans_enable_directed_msix,
  4588. &(h->cfgtable->HostWrite.TransportRequest));
  4589. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  4590. hpsa_wait_for_mode_change_ack(h);
  4591. register_value = readl(&(h->cfgtable->TransportActive));
  4592. if (!(register_value & CFGTBL_Trans_Performant)) {
  4593. dev_warn(&h->pdev->dev, "unable to get board into"
  4594. " performant mode\n");
  4595. return;
  4596. }
  4597. /* Change the access methods to the performant access methods */
  4598. h->access = SA5_performant_access;
  4599. h->transMethod = CFGTBL_Trans_Performant;
  4600. }
  4601. static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
  4602. {
  4603. u32 trans_support;
  4604. int i;
  4605. if (hpsa_simple_mode)
  4606. return;
  4607. trans_support = readl(&(h->cfgtable->TransportSupport));
  4608. if (!(trans_support & PERFORMANT_MODE))
  4609. return;
  4610. h->nreply_queues = h->msix_vector ? MAX_REPLY_QUEUES : 1;
  4611. hpsa_get_max_perf_mode_cmds(h);
  4612. /* Performant mode ring buffer and supporting data structures */
  4613. h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
  4614. h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
  4615. &(h->reply_pool_dhandle));
  4616. for (i = 0; i < h->nreply_queues; i++) {
  4617. h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
  4618. h->reply_queue[i].size = h->max_commands;
  4619. h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
  4620. h->reply_queue[i].current_entry = 0;
  4621. }
  4622. /* Need a block fetch table for performant mode */
  4623. h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
  4624. sizeof(u32)), GFP_KERNEL);
  4625. if ((h->reply_pool == NULL)
  4626. || (h->blockFetchTable == NULL))
  4627. goto clean_up;
  4628. hpsa_enter_performant_mode(h,
  4629. trans_support & CFGTBL_Trans_use_short_tags);
  4630. return;
  4631. clean_up:
  4632. if (h->reply_pool)
  4633. pci_free_consistent(h->pdev, h->reply_pool_size,
  4634. h->reply_pool, h->reply_pool_dhandle);
  4635. kfree(h->blockFetchTable);
  4636. }
  4637. /*
  4638. * This is it. Register the PCI driver information for the cards we control
  4639. * the OS will call our registered routines when it finds one of our cards.
  4640. */
  4641. static int __init hpsa_init(void)
  4642. {
  4643. return pci_register_driver(&hpsa_pci_driver);
  4644. }
  4645. static void __exit hpsa_cleanup(void)
  4646. {
  4647. pci_unregister_driver(&hpsa_pci_driver);
  4648. }
  4649. module_init(hpsa_init);
  4650. module_exit(hpsa_cleanup);