qeth_core_main.c 124 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546
  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/ipv6.h>
  19. #include <linux/tcp.h>
  20. #include <linux/mii.h>
  21. #include <linux/kthread.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include <asm/s390_rdev.h>
  25. #include "qeth_core.h"
  26. #include "qeth_core_offl.h"
  27. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  28. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  29. /* N P A M L V H */
  30. [QETH_DBF_SETUP] = {"qeth_setup",
  31. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_QERR] = {"qeth_qerr",
  33. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_TRACE] = {"qeth_trace",
  35. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  36. [QETH_DBF_MSG] = {"qeth_msg",
  37. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  38. [QETH_DBF_SENSE] = {"qeth_sense",
  39. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_MISC] = {"qeth_misc",
  41. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  42. [QETH_DBF_CTRL] = {"qeth_control",
  43. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  44. };
  45. EXPORT_SYMBOL_GPL(qeth_dbf);
  46. struct qeth_card_list_struct qeth_core_card_list;
  47. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  48. struct kmem_cache *qeth_core_header_cache;
  49. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  50. static struct device *qeth_core_root_dev;
  51. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  52. static struct lock_class_key qdio_out_skb_queue_key;
  53. static void qeth_send_control_data_cb(struct qeth_channel *,
  54. struct qeth_cmd_buffer *);
  55. static int qeth_issue_next_read(struct qeth_card *);
  56. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  57. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  58. static void qeth_free_buffer_pool(struct qeth_card *);
  59. static int qeth_qdio_establish(struct qeth_card *);
  60. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  61. struct qdio_buffer *buffer, int is_tso,
  62. int *next_element_to_fill)
  63. {
  64. struct skb_frag_struct *frag;
  65. int fragno;
  66. unsigned long addr;
  67. int element, cnt, dlen;
  68. fragno = skb_shinfo(skb)->nr_frags;
  69. element = *next_element_to_fill;
  70. dlen = 0;
  71. if (is_tso)
  72. buffer->element[element].flags =
  73. SBAL_FLAGS_MIDDLE_FRAG;
  74. else
  75. buffer->element[element].flags =
  76. SBAL_FLAGS_FIRST_FRAG;
  77. dlen = skb->len - skb->data_len;
  78. if (dlen) {
  79. buffer->element[element].addr = skb->data;
  80. buffer->element[element].length = dlen;
  81. element++;
  82. }
  83. for (cnt = 0; cnt < fragno; cnt++) {
  84. frag = &skb_shinfo(skb)->frags[cnt];
  85. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  86. frag->page_offset;
  87. buffer->element[element].addr = (char *)addr;
  88. buffer->element[element].length = frag->size;
  89. if (cnt < (fragno - 1))
  90. buffer->element[element].flags =
  91. SBAL_FLAGS_MIDDLE_FRAG;
  92. else
  93. buffer->element[element].flags =
  94. SBAL_FLAGS_LAST_FRAG;
  95. element++;
  96. }
  97. *next_element_to_fill = element;
  98. }
  99. static inline const char *qeth_get_cardname(struct qeth_card *card)
  100. {
  101. if (card->info.guestlan) {
  102. switch (card->info.type) {
  103. case QETH_CARD_TYPE_OSAE:
  104. return " Guest LAN QDIO";
  105. case QETH_CARD_TYPE_IQD:
  106. return " Guest LAN Hiper";
  107. default:
  108. return " unknown";
  109. }
  110. } else {
  111. switch (card->info.type) {
  112. case QETH_CARD_TYPE_OSAE:
  113. return " OSD Express";
  114. case QETH_CARD_TYPE_IQD:
  115. return " HiperSockets";
  116. case QETH_CARD_TYPE_OSN:
  117. return " OSN QDIO";
  118. default:
  119. return " unknown";
  120. }
  121. }
  122. return " n/a";
  123. }
  124. /* max length to be returned: 14 */
  125. const char *qeth_get_cardname_short(struct qeth_card *card)
  126. {
  127. if (card->info.guestlan) {
  128. switch (card->info.type) {
  129. case QETH_CARD_TYPE_OSAE:
  130. return "GuestLAN QDIO";
  131. case QETH_CARD_TYPE_IQD:
  132. return "GuestLAN Hiper";
  133. default:
  134. return "unknown";
  135. }
  136. } else {
  137. switch (card->info.type) {
  138. case QETH_CARD_TYPE_OSAE:
  139. switch (card->info.link_type) {
  140. case QETH_LINK_TYPE_FAST_ETH:
  141. return "OSD_100";
  142. case QETH_LINK_TYPE_HSTR:
  143. return "HSTR";
  144. case QETH_LINK_TYPE_GBIT_ETH:
  145. return "OSD_1000";
  146. case QETH_LINK_TYPE_10GBIT_ETH:
  147. return "OSD_10GIG";
  148. case QETH_LINK_TYPE_LANE_ETH100:
  149. return "OSD_FE_LANE";
  150. case QETH_LINK_TYPE_LANE_TR:
  151. return "OSD_TR_LANE";
  152. case QETH_LINK_TYPE_LANE_ETH1000:
  153. return "OSD_GbE_LANE";
  154. case QETH_LINK_TYPE_LANE:
  155. return "OSD_ATM_LANE";
  156. default:
  157. return "OSD_Express";
  158. }
  159. case QETH_CARD_TYPE_IQD:
  160. return "HiperSockets";
  161. case QETH_CARD_TYPE_OSN:
  162. return "OSN";
  163. default:
  164. return "unknown";
  165. }
  166. }
  167. return "n/a";
  168. }
  169. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  170. int clear_start_mask)
  171. {
  172. unsigned long flags;
  173. spin_lock_irqsave(&card->thread_mask_lock, flags);
  174. card->thread_allowed_mask = threads;
  175. if (clear_start_mask)
  176. card->thread_start_mask &= threads;
  177. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  178. wake_up(&card->wait_q);
  179. }
  180. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  181. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  182. {
  183. unsigned long flags;
  184. int rc = 0;
  185. spin_lock_irqsave(&card->thread_mask_lock, flags);
  186. rc = (card->thread_running_mask & threads);
  187. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  188. return rc;
  189. }
  190. EXPORT_SYMBOL_GPL(qeth_threads_running);
  191. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  192. {
  193. return wait_event_interruptible(card->wait_q,
  194. qeth_threads_running(card, threads) == 0);
  195. }
  196. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  197. void qeth_clear_working_pool_list(struct qeth_card *card)
  198. {
  199. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  200. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  201. list_for_each_entry_safe(pool_entry, tmp,
  202. &card->qdio.in_buf_pool.entry_list, list){
  203. list_del(&pool_entry->list);
  204. }
  205. }
  206. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  207. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  208. {
  209. struct qeth_buffer_pool_entry *pool_entry;
  210. void *ptr;
  211. int i, j;
  212. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  213. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  214. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  215. if (!pool_entry) {
  216. qeth_free_buffer_pool(card);
  217. return -ENOMEM;
  218. }
  219. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  220. ptr = (void *) __get_free_page(GFP_KERNEL);
  221. if (!ptr) {
  222. while (j > 0)
  223. free_page((unsigned long)
  224. pool_entry->elements[--j]);
  225. kfree(pool_entry);
  226. qeth_free_buffer_pool(card);
  227. return -ENOMEM;
  228. }
  229. pool_entry->elements[j] = ptr;
  230. }
  231. list_add(&pool_entry->init_list,
  232. &card->qdio.init_pool.entry_list);
  233. }
  234. return 0;
  235. }
  236. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  237. {
  238. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  239. if ((card->state != CARD_STATE_DOWN) &&
  240. (card->state != CARD_STATE_RECOVER))
  241. return -EPERM;
  242. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  243. qeth_clear_working_pool_list(card);
  244. qeth_free_buffer_pool(card);
  245. card->qdio.in_buf_pool.buf_count = bufcnt;
  246. card->qdio.init_pool.buf_count = bufcnt;
  247. return qeth_alloc_buffer_pool(card);
  248. }
  249. int qeth_set_large_send(struct qeth_card *card,
  250. enum qeth_large_send_types type)
  251. {
  252. int rc = 0;
  253. if (card->dev == NULL) {
  254. card->options.large_send = type;
  255. return 0;
  256. }
  257. if (card->state == CARD_STATE_UP)
  258. netif_tx_disable(card->dev);
  259. card->options.large_send = type;
  260. switch (card->options.large_send) {
  261. case QETH_LARGE_SEND_EDDP:
  262. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  263. NETIF_F_HW_CSUM;
  264. break;
  265. case QETH_LARGE_SEND_TSO:
  266. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  267. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  268. NETIF_F_HW_CSUM;
  269. } else {
  270. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  271. NETIF_F_HW_CSUM);
  272. card->options.large_send = QETH_LARGE_SEND_NO;
  273. rc = -EOPNOTSUPP;
  274. }
  275. break;
  276. default: /* includes QETH_LARGE_SEND_NO */
  277. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  278. NETIF_F_HW_CSUM);
  279. break;
  280. }
  281. if (card->state == CARD_STATE_UP)
  282. netif_wake_queue(card->dev);
  283. return rc;
  284. }
  285. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  286. static int qeth_issue_next_read(struct qeth_card *card)
  287. {
  288. int rc;
  289. struct qeth_cmd_buffer *iob;
  290. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  291. if (card->read.state != CH_STATE_UP)
  292. return -EIO;
  293. iob = qeth_get_buffer(&card->read);
  294. if (!iob) {
  295. dev_warn(&card->gdev->dev, "The qeth device driver "
  296. "failed to recover an error on the device\n");
  297. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  298. "available\n", dev_name(&card->gdev->dev));
  299. return -ENOMEM;
  300. }
  301. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  302. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  303. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  304. (addr_t) iob, 0, 0);
  305. if (rc) {
  306. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  307. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  308. atomic_set(&card->read.irq_pending, 0);
  309. qeth_schedule_recovery(card);
  310. wake_up(&card->wait_q);
  311. }
  312. return rc;
  313. }
  314. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  315. {
  316. struct qeth_reply *reply;
  317. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  318. if (reply) {
  319. atomic_set(&reply->refcnt, 1);
  320. atomic_set(&reply->received, 0);
  321. reply->card = card;
  322. };
  323. return reply;
  324. }
  325. static void qeth_get_reply(struct qeth_reply *reply)
  326. {
  327. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  328. atomic_inc(&reply->refcnt);
  329. }
  330. static void qeth_put_reply(struct qeth_reply *reply)
  331. {
  332. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  333. if (atomic_dec_and_test(&reply->refcnt))
  334. kfree(reply);
  335. }
  336. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  337. struct qeth_card *card)
  338. {
  339. char *ipa_name;
  340. int com = cmd->hdr.command;
  341. ipa_name = qeth_get_ipa_cmd_name(com);
  342. if (rc)
  343. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  344. ipa_name, com, QETH_CARD_IFNAME(card),
  345. rc, qeth_get_ipa_msg(rc));
  346. else
  347. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  348. ipa_name, com, QETH_CARD_IFNAME(card));
  349. }
  350. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  351. struct qeth_cmd_buffer *iob)
  352. {
  353. struct qeth_ipa_cmd *cmd = NULL;
  354. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  355. if (IS_IPA(iob->data)) {
  356. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  357. if (IS_IPA_REPLY(cmd)) {
  358. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  359. cmd->hdr.command > IPA_CMD_MODCCID)
  360. qeth_issue_ipa_msg(cmd,
  361. cmd->hdr.return_code, card);
  362. return cmd;
  363. } else {
  364. switch (cmd->hdr.command) {
  365. case IPA_CMD_STOPLAN:
  366. dev_warn(&card->gdev->dev,
  367. "The link for interface %s on CHPID"
  368. " 0x%X failed\n",
  369. QETH_CARD_IFNAME(card),
  370. card->info.chpid);
  371. card->lan_online = 0;
  372. if (card->dev && netif_carrier_ok(card->dev))
  373. netif_carrier_off(card->dev);
  374. return NULL;
  375. case IPA_CMD_STARTLAN:
  376. dev_info(&card->gdev->dev,
  377. "The link for %s on CHPID 0x%X has"
  378. " been restored\n",
  379. QETH_CARD_IFNAME(card),
  380. card->info.chpid);
  381. netif_carrier_on(card->dev);
  382. card->lan_online = 1;
  383. qeth_schedule_recovery(card);
  384. return NULL;
  385. case IPA_CMD_MODCCID:
  386. return cmd;
  387. case IPA_CMD_REGISTER_LOCAL_ADDR:
  388. QETH_DBF_TEXT(TRACE, 3, "irla");
  389. break;
  390. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  391. QETH_DBF_TEXT(TRACE, 3, "urla");
  392. break;
  393. default:
  394. QETH_DBF_MESSAGE(2, "Received data is IPA "
  395. "but not a reply!\n");
  396. break;
  397. }
  398. }
  399. }
  400. return cmd;
  401. }
  402. void qeth_clear_ipacmd_list(struct qeth_card *card)
  403. {
  404. struct qeth_reply *reply, *r;
  405. unsigned long flags;
  406. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  407. spin_lock_irqsave(&card->lock, flags);
  408. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  409. qeth_get_reply(reply);
  410. reply->rc = -EIO;
  411. atomic_inc(&reply->received);
  412. list_del_init(&reply->list);
  413. wake_up(&reply->wait_q);
  414. qeth_put_reply(reply);
  415. }
  416. spin_unlock_irqrestore(&card->lock, flags);
  417. }
  418. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  419. static int qeth_check_idx_response(unsigned char *buffer)
  420. {
  421. if (!buffer)
  422. return 0;
  423. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  424. if ((buffer[2] & 0xc0) == 0xc0) {
  425. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  426. "with cause code 0x%02x%s\n",
  427. buffer[4],
  428. ((buffer[4] == 0x22) ?
  429. " -- try another portname" : ""));
  430. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  431. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  432. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  433. return -EIO;
  434. }
  435. return 0;
  436. }
  437. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  438. __u32 len)
  439. {
  440. struct qeth_card *card;
  441. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  442. card = CARD_FROM_CDEV(channel->ccwdev);
  443. if (channel == &card->read)
  444. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  445. else
  446. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  447. channel->ccw.count = len;
  448. channel->ccw.cda = (__u32) __pa(iob);
  449. }
  450. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  451. {
  452. __u8 index;
  453. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  454. index = channel->io_buf_no;
  455. do {
  456. if (channel->iob[index].state == BUF_STATE_FREE) {
  457. channel->iob[index].state = BUF_STATE_LOCKED;
  458. channel->io_buf_no = (channel->io_buf_no + 1) %
  459. QETH_CMD_BUFFER_NO;
  460. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  461. return channel->iob + index;
  462. }
  463. index = (index + 1) % QETH_CMD_BUFFER_NO;
  464. } while (index != channel->io_buf_no);
  465. return NULL;
  466. }
  467. void qeth_release_buffer(struct qeth_channel *channel,
  468. struct qeth_cmd_buffer *iob)
  469. {
  470. unsigned long flags;
  471. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  472. spin_lock_irqsave(&channel->iob_lock, flags);
  473. memset(iob->data, 0, QETH_BUFSIZE);
  474. iob->state = BUF_STATE_FREE;
  475. iob->callback = qeth_send_control_data_cb;
  476. iob->rc = 0;
  477. spin_unlock_irqrestore(&channel->iob_lock, flags);
  478. }
  479. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  480. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  481. {
  482. struct qeth_cmd_buffer *buffer = NULL;
  483. unsigned long flags;
  484. spin_lock_irqsave(&channel->iob_lock, flags);
  485. buffer = __qeth_get_buffer(channel);
  486. spin_unlock_irqrestore(&channel->iob_lock, flags);
  487. return buffer;
  488. }
  489. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  490. {
  491. struct qeth_cmd_buffer *buffer;
  492. wait_event(channel->wait_q,
  493. ((buffer = qeth_get_buffer(channel)) != NULL));
  494. return buffer;
  495. }
  496. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  497. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  498. {
  499. int cnt;
  500. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  501. qeth_release_buffer(channel, &channel->iob[cnt]);
  502. channel->buf_no = 0;
  503. channel->io_buf_no = 0;
  504. }
  505. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  506. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  507. struct qeth_cmd_buffer *iob)
  508. {
  509. struct qeth_card *card;
  510. struct qeth_reply *reply, *r;
  511. struct qeth_ipa_cmd *cmd;
  512. unsigned long flags;
  513. int keep_reply;
  514. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  515. card = CARD_FROM_CDEV(channel->ccwdev);
  516. if (qeth_check_idx_response(iob->data)) {
  517. qeth_clear_ipacmd_list(card);
  518. qeth_schedule_recovery(card);
  519. goto out;
  520. }
  521. cmd = qeth_check_ipa_data(card, iob);
  522. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  523. goto out;
  524. /*in case of OSN : check if cmd is set */
  525. if (card->info.type == QETH_CARD_TYPE_OSN &&
  526. cmd &&
  527. cmd->hdr.command != IPA_CMD_STARTLAN &&
  528. card->osn_info.assist_cb != NULL) {
  529. card->osn_info.assist_cb(card->dev, cmd);
  530. goto out;
  531. }
  532. spin_lock_irqsave(&card->lock, flags);
  533. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  534. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  535. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  536. qeth_get_reply(reply);
  537. list_del_init(&reply->list);
  538. spin_unlock_irqrestore(&card->lock, flags);
  539. keep_reply = 0;
  540. if (reply->callback != NULL) {
  541. if (cmd) {
  542. reply->offset = (__u16)((char *)cmd -
  543. (char *)iob->data);
  544. keep_reply = reply->callback(card,
  545. reply,
  546. (unsigned long)cmd);
  547. } else
  548. keep_reply = reply->callback(card,
  549. reply,
  550. (unsigned long)iob);
  551. }
  552. if (cmd)
  553. reply->rc = (u16) cmd->hdr.return_code;
  554. else if (iob->rc)
  555. reply->rc = iob->rc;
  556. if (keep_reply) {
  557. spin_lock_irqsave(&card->lock, flags);
  558. list_add_tail(&reply->list,
  559. &card->cmd_waiter_list);
  560. spin_unlock_irqrestore(&card->lock, flags);
  561. } else {
  562. atomic_inc(&reply->received);
  563. wake_up(&reply->wait_q);
  564. }
  565. qeth_put_reply(reply);
  566. goto out;
  567. }
  568. }
  569. spin_unlock_irqrestore(&card->lock, flags);
  570. out:
  571. memcpy(&card->seqno.pdu_hdr_ack,
  572. QETH_PDU_HEADER_SEQ_NO(iob->data),
  573. QETH_SEQ_NO_LENGTH);
  574. qeth_release_buffer(channel, iob);
  575. }
  576. static int qeth_setup_channel(struct qeth_channel *channel)
  577. {
  578. int cnt;
  579. QETH_DBF_TEXT(SETUP, 2, "setupch");
  580. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  581. channel->iob[cnt].data = (char *)
  582. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  583. if (channel->iob[cnt].data == NULL)
  584. break;
  585. channel->iob[cnt].state = BUF_STATE_FREE;
  586. channel->iob[cnt].channel = channel;
  587. channel->iob[cnt].callback = qeth_send_control_data_cb;
  588. channel->iob[cnt].rc = 0;
  589. }
  590. if (cnt < QETH_CMD_BUFFER_NO) {
  591. while (cnt-- > 0)
  592. kfree(channel->iob[cnt].data);
  593. return -ENOMEM;
  594. }
  595. channel->buf_no = 0;
  596. channel->io_buf_no = 0;
  597. atomic_set(&channel->irq_pending, 0);
  598. spin_lock_init(&channel->iob_lock);
  599. init_waitqueue_head(&channel->wait_q);
  600. return 0;
  601. }
  602. static int qeth_set_thread_start_bit(struct qeth_card *card,
  603. unsigned long thread)
  604. {
  605. unsigned long flags;
  606. spin_lock_irqsave(&card->thread_mask_lock, flags);
  607. if (!(card->thread_allowed_mask & thread) ||
  608. (card->thread_start_mask & thread)) {
  609. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  610. return -EPERM;
  611. }
  612. card->thread_start_mask |= thread;
  613. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  614. return 0;
  615. }
  616. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  617. {
  618. unsigned long flags;
  619. spin_lock_irqsave(&card->thread_mask_lock, flags);
  620. card->thread_start_mask &= ~thread;
  621. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  622. wake_up(&card->wait_q);
  623. }
  624. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  625. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  626. {
  627. unsigned long flags;
  628. spin_lock_irqsave(&card->thread_mask_lock, flags);
  629. card->thread_running_mask &= ~thread;
  630. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  631. wake_up(&card->wait_q);
  632. }
  633. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  634. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  635. {
  636. unsigned long flags;
  637. int rc = 0;
  638. spin_lock_irqsave(&card->thread_mask_lock, flags);
  639. if (card->thread_start_mask & thread) {
  640. if ((card->thread_allowed_mask & thread) &&
  641. !(card->thread_running_mask & thread)) {
  642. rc = 1;
  643. card->thread_start_mask &= ~thread;
  644. card->thread_running_mask |= thread;
  645. } else
  646. rc = -EPERM;
  647. }
  648. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  649. return rc;
  650. }
  651. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  652. {
  653. int rc = 0;
  654. wait_event(card->wait_q,
  655. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  656. return rc;
  657. }
  658. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  659. void qeth_schedule_recovery(struct qeth_card *card)
  660. {
  661. QETH_DBF_TEXT(TRACE, 2, "startrec");
  662. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  663. schedule_work(&card->kernel_thread_starter);
  664. }
  665. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  666. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  667. {
  668. int dstat, cstat;
  669. char *sense;
  670. sense = (char *) irb->ecw;
  671. cstat = irb->scsw.cmd.cstat;
  672. dstat = irb->scsw.cmd.dstat;
  673. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  674. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  675. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  676. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  677. dev_warn(&cdev->dev, "The qeth device driver "
  678. "failed to recover an error on the device\n");
  679. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  680. dev_name(&cdev->dev), dstat, cstat);
  681. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  682. 16, 1, irb, 64, 1);
  683. return 1;
  684. }
  685. if (dstat & DEV_STAT_UNIT_CHECK) {
  686. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  687. SENSE_RESETTING_EVENT_FLAG) {
  688. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  689. return 1;
  690. }
  691. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  692. SENSE_COMMAND_REJECT_FLAG) {
  693. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  694. return 1;
  695. }
  696. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  697. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  698. return 1;
  699. }
  700. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  701. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  702. return 0;
  703. }
  704. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  705. return 1;
  706. }
  707. return 0;
  708. }
  709. static long __qeth_check_irb_error(struct ccw_device *cdev,
  710. unsigned long intparm, struct irb *irb)
  711. {
  712. if (!IS_ERR(irb))
  713. return 0;
  714. switch (PTR_ERR(irb)) {
  715. case -EIO:
  716. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  717. dev_name(&cdev->dev));
  718. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  719. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  720. break;
  721. case -ETIMEDOUT:
  722. dev_warn(&cdev->dev, "A hardware operation timed out"
  723. " on the device\n");
  724. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  725. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  726. if (intparm == QETH_RCD_PARM) {
  727. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  728. if (card && (card->data.ccwdev == cdev)) {
  729. card->data.state = CH_STATE_DOWN;
  730. wake_up(&card->wait_q);
  731. }
  732. }
  733. break;
  734. default:
  735. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  736. dev_name(&cdev->dev), PTR_ERR(irb));
  737. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  738. QETH_DBF_TEXT(TRACE, 2, " rc???");
  739. }
  740. return PTR_ERR(irb);
  741. }
  742. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  743. struct irb *irb)
  744. {
  745. int rc;
  746. int cstat, dstat;
  747. struct qeth_cmd_buffer *buffer;
  748. struct qeth_channel *channel;
  749. struct qeth_card *card;
  750. struct qeth_cmd_buffer *iob;
  751. __u8 index;
  752. QETH_DBF_TEXT(TRACE, 5, "irq");
  753. if (__qeth_check_irb_error(cdev, intparm, irb))
  754. return;
  755. cstat = irb->scsw.cmd.cstat;
  756. dstat = irb->scsw.cmd.dstat;
  757. card = CARD_FROM_CDEV(cdev);
  758. if (!card)
  759. return;
  760. if (card->read.ccwdev == cdev) {
  761. channel = &card->read;
  762. QETH_DBF_TEXT(TRACE, 5, "read");
  763. } else if (card->write.ccwdev == cdev) {
  764. channel = &card->write;
  765. QETH_DBF_TEXT(TRACE, 5, "write");
  766. } else {
  767. channel = &card->data;
  768. QETH_DBF_TEXT(TRACE, 5, "data");
  769. }
  770. atomic_set(&channel->irq_pending, 0);
  771. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  772. channel->state = CH_STATE_STOPPED;
  773. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  774. channel->state = CH_STATE_HALTED;
  775. /*let's wake up immediately on data channel*/
  776. if ((channel == &card->data) && (intparm != 0) &&
  777. (intparm != QETH_RCD_PARM))
  778. goto out;
  779. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  780. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  781. /* we don't have to handle this further */
  782. intparm = 0;
  783. }
  784. if (intparm == QETH_HALT_CHANNEL_PARM) {
  785. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  786. /* we don't have to handle this further */
  787. intparm = 0;
  788. }
  789. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  790. (dstat & DEV_STAT_UNIT_CHECK) ||
  791. (cstat)) {
  792. if (irb->esw.esw0.erw.cons) {
  793. dev_warn(&channel->ccwdev->dev,
  794. "The qeth device driver failed to recover "
  795. "an error on the device\n");
  796. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  797. "0x%X dstat 0x%X\n",
  798. dev_name(&channel->ccwdev->dev), cstat, dstat);
  799. print_hex_dump(KERN_WARNING, "qeth: irb ",
  800. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  801. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  802. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  803. }
  804. if (intparm == QETH_RCD_PARM) {
  805. channel->state = CH_STATE_DOWN;
  806. goto out;
  807. }
  808. rc = qeth_get_problem(cdev, irb);
  809. if (rc) {
  810. qeth_clear_ipacmd_list(card);
  811. qeth_schedule_recovery(card);
  812. goto out;
  813. }
  814. }
  815. if (intparm == QETH_RCD_PARM) {
  816. channel->state = CH_STATE_RCD_DONE;
  817. goto out;
  818. }
  819. if (intparm) {
  820. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  821. buffer->state = BUF_STATE_PROCESSED;
  822. }
  823. if (channel == &card->data)
  824. return;
  825. if (channel == &card->read &&
  826. channel->state == CH_STATE_UP)
  827. qeth_issue_next_read(card);
  828. iob = channel->iob;
  829. index = channel->buf_no;
  830. while (iob[index].state == BUF_STATE_PROCESSED) {
  831. if (iob[index].callback != NULL)
  832. iob[index].callback(channel, iob + index);
  833. index = (index + 1) % QETH_CMD_BUFFER_NO;
  834. }
  835. channel->buf_no = index;
  836. out:
  837. wake_up(&card->wait_q);
  838. return;
  839. }
  840. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  841. struct qeth_qdio_out_buffer *buf)
  842. {
  843. int i;
  844. struct sk_buff *skb;
  845. /* is PCI flag set on buffer? */
  846. if (buf->buffer->element[0].flags & 0x40)
  847. atomic_dec(&queue->set_pci_flags_count);
  848. skb = skb_dequeue(&buf->skb_list);
  849. while (skb) {
  850. atomic_dec(&skb->users);
  851. dev_kfree_skb_any(skb);
  852. skb = skb_dequeue(&buf->skb_list);
  853. }
  854. qeth_eddp_buf_release_contexts(buf);
  855. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  856. if (buf->buffer->element[i].addr && buf->is_header[i])
  857. kmem_cache_free(qeth_core_header_cache,
  858. buf->buffer->element[i].addr);
  859. buf->is_header[i] = 0;
  860. buf->buffer->element[i].length = 0;
  861. buf->buffer->element[i].addr = NULL;
  862. buf->buffer->element[i].flags = 0;
  863. }
  864. buf->next_element_to_fill = 0;
  865. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  866. }
  867. void qeth_clear_qdio_buffers(struct qeth_card *card)
  868. {
  869. int i, j;
  870. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  871. /* clear outbound buffers to free skbs */
  872. for (i = 0; i < card->qdio.no_out_queues; ++i)
  873. if (card->qdio.out_qs[i]) {
  874. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  875. qeth_clear_output_buffer(card->qdio.out_qs[i],
  876. &card->qdio.out_qs[i]->bufs[j]);
  877. }
  878. }
  879. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  880. static void qeth_free_buffer_pool(struct qeth_card *card)
  881. {
  882. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  883. int i = 0;
  884. QETH_DBF_TEXT(TRACE, 5, "freepool");
  885. list_for_each_entry_safe(pool_entry, tmp,
  886. &card->qdio.init_pool.entry_list, init_list){
  887. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  888. free_page((unsigned long)pool_entry->elements[i]);
  889. list_del(&pool_entry->init_list);
  890. kfree(pool_entry);
  891. }
  892. }
  893. static void qeth_free_qdio_buffers(struct qeth_card *card)
  894. {
  895. int i, j;
  896. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  897. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  898. QETH_QDIO_UNINITIALIZED)
  899. return;
  900. kfree(card->qdio.in_q);
  901. card->qdio.in_q = NULL;
  902. /* inbound buffer pool */
  903. qeth_free_buffer_pool(card);
  904. /* free outbound qdio_qs */
  905. if (card->qdio.out_qs) {
  906. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  907. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  908. qeth_clear_output_buffer(card->qdio.out_qs[i],
  909. &card->qdio.out_qs[i]->bufs[j]);
  910. kfree(card->qdio.out_qs[i]);
  911. }
  912. kfree(card->qdio.out_qs);
  913. card->qdio.out_qs = NULL;
  914. }
  915. }
  916. static void qeth_clean_channel(struct qeth_channel *channel)
  917. {
  918. int cnt;
  919. QETH_DBF_TEXT(SETUP, 2, "freech");
  920. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  921. kfree(channel->iob[cnt].data);
  922. }
  923. static int qeth_is_1920_device(struct qeth_card *card)
  924. {
  925. int single_queue = 0;
  926. struct ccw_device *ccwdev;
  927. struct channelPath_dsc {
  928. u8 flags;
  929. u8 lsn;
  930. u8 desc;
  931. u8 chpid;
  932. u8 swla;
  933. u8 zeroes;
  934. u8 chla;
  935. u8 chpp;
  936. } *chp_dsc;
  937. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  938. ccwdev = card->data.ccwdev;
  939. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  940. if (chp_dsc != NULL) {
  941. /* CHPP field bit 6 == 1 -> single queue */
  942. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  943. kfree(chp_dsc);
  944. }
  945. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  946. return single_queue;
  947. }
  948. static void qeth_init_qdio_info(struct qeth_card *card)
  949. {
  950. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  951. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  952. /* inbound */
  953. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  954. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  955. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  956. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  957. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  958. }
  959. static void qeth_set_intial_options(struct qeth_card *card)
  960. {
  961. card->options.route4.type = NO_ROUTER;
  962. card->options.route6.type = NO_ROUTER;
  963. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  964. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  965. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  966. card->options.fake_broadcast = 0;
  967. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  968. card->options.fake_ll = 0;
  969. card->options.performance_stats = 0;
  970. card->options.rx_sg_cb = QETH_RX_SG_CB;
  971. }
  972. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  973. {
  974. unsigned long flags;
  975. int rc = 0;
  976. spin_lock_irqsave(&card->thread_mask_lock, flags);
  977. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  978. (u8) card->thread_start_mask,
  979. (u8) card->thread_allowed_mask,
  980. (u8) card->thread_running_mask);
  981. rc = (card->thread_start_mask & thread);
  982. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  983. return rc;
  984. }
  985. static void qeth_start_kernel_thread(struct work_struct *work)
  986. {
  987. struct qeth_card *card = container_of(work, struct qeth_card,
  988. kernel_thread_starter);
  989. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  990. if (card->read.state != CH_STATE_UP &&
  991. card->write.state != CH_STATE_UP)
  992. return;
  993. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  994. kthread_run(card->discipline.recover, (void *) card,
  995. "qeth_recover");
  996. }
  997. static int qeth_setup_card(struct qeth_card *card)
  998. {
  999. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1000. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1001. card->read.state = CH_STATE_DOWN;
  1002. card->write.state = CH_STATE_DOWN;
  1003. card->data.state = CH_STATE_DOWN;
  1004. card->state = CARD_STATE_DOWN;
  1005. card->lan_online = 0;
  1006. card->use_hard_stop = 0;
  1007. card->dev = NULL;
  1008. spin_lock_init(&card->vlanlock);
  1009. spin_lock_init(&card->mclock);
  1010. card->vlangrp = NULL;
  1011. spin_lock_init(&card->lock);
  1012. spin_lock_init(&card->ip_lock);
  1013. spin_lock_init(&card->thread_mask_lock);
  1014. card->thread_start_mask = 0;
  1015. card->thread_allowed_mask = 0;
  1016. card->thread_running_mask = 0;
  1017. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1018. INIT_LIST_HEAD(&card->ip_list);
  1019. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1020. if (!card->ip_tbd_list) {
  1021. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1022. return -ENOMEM;
  1023. }
  1024. INIT_LIST_HEAD(card->ip_tbd_list);
  1025. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1026. init_waitqueue_head(&card->wait_q);
  1027. /* intial options */
  1028. qeth_set_intial_options(card);
  1029. /* IP address takeover */
  1030. INIT_LIST_HEAD(&card->ipato.entries);
  1031. card->ipato.enabled = 0;
  1032. card->ipato.invert4 = 0;
  1033. card->ipato.invert6 = 0;
  1034. /* init QDIO stuff */
  1035. qeth_init_qdio_info(card);
  1036. return 0;
  1037. }
  1038. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1039. {
  1040. struct qeth_card *card = container_of(slr, struct qeth_card,
  1041. qeth_service_level);
  1042. seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card),
  1043. card->info.mcl_level);
  1044. }
  1045. static struct qeth_card *qeth_alloc_card(void)
  1046. {
  1047. struct qeth_card *card;
  1048. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1049. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1050. if (!card)
  1051. return NULL;
  1052. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1053. if (qeth_setup_channel(&card->read)) {
  1054. kfree(card);
  1055. return NULL;
  1056. }
  1057. if (qeth_setup_channel(&card->write)) {
  1058. qeth_clean_channel(&card->read);
  1059. kfree(card);
  1060. return NULL;
  1061. }
  1062. card->options.layer2 = -1;
  1063. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1064. register_service_level(&card->qeth_service_level);
  1065. return card;
  1066. }
  1067. static int qeth_determine_card_type(struct qeth_card *card)
  1068. {
  1069. int i = 0;
  1070. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1071. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1072. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1073. while (known_devices[i][4]) {
  1074. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1075. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1076. card->info.type = known_devices[i][4];
  1077. card->qdio.no_out_queues = known_devices[i][8];
  1078. card->info.is_multicast_different = known_devices[i][9];
  1079. if (qeth_is_1920_device(card)) {
  1080. dev_info(&card->gdev->dev,
  1081. "Priority Queueing not supported\n");
  1082. card->qdio.no_out_queues = 1;
  1083. card->qdio.default_out_queue = 0;
  1084. }
  1085. return 0;
  1086. }
  1087. i++;
  1088. }
  1089. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1090. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1091. "unknown type\n");
  1092. return -ENOENT;
  1093. }
  1094. static int qeth_clear_channel(struct qeth_channel *channel)
  1095. {
  1096. unsigned long flags;
  1097. struct qeth_card *card;
  1098. int rc;
  1099. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1100. card = CARD_FROM_CDEV(channel->ccwdev);
  1101. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1102. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1103. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1104. if (rc)
  1105. return rc;
  1106. rc = wait_event_interruptible_timeout(card->wait_q,
  1107. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1108. if (rc == -ERESTARTSYS)
  1109. return rc;
  1110. if (channel->state != CH_STATE_STOPPED)
  1111. return -ETIME;
  1112. channel->state = CH_STATE_DOWN;
  1113. return 0;
  1114. }
  1115. static int qeth_halt_channel(struct qeth_channel *channel)
  1116. {
  1117. unsigned long flags;
  1118. struct qeth_card *card;
  1119. int rc;
  1120. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1121. card = CARD_FROM_CDEV(channel->ccwdev);
  1122. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1123. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1124. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1125. if (rc)
  1126. return rc;
  1127. rc = wait_event_interruptible_timeout(card->wait_q,
  1128. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1129. if (rc == -ERESTARTSYS)
  1130. return rc;
  1131. if (channel->state != CH_STATE_HALTED)
  1132. return -ETIME;
  1133. return 0;
  1134. }
  1135. static int qeth_halt_channels(struct qeth_card *card)
  1136. {
  1137. int rc1 = 0, rc2 = 0, rc3 = 0;
  1138. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1139. rc1 = qeth_halt_channel(&card->read);
  1140. rc2 = qeth_halt_channel(&card->write);
  1141. rc3 = qeth_halt_channel(&card->data);
  1142. if (rc1)
  1143. return rc1;
  1144. if (rc2)
  1145. return rc2;
  1146. return rc3;
  1147. }
  1148. static int qeth_clear_channels(struct qeth_card *card)
  1149. {
  1150. int rc1 = 0, rc2 = 0, rc3 = 0;
  1151. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1152. rc1 = qeth_clear_channel(&card->read);
  1153. rc2 = qeth_clear_channel(&card->write);
  1154. rc3 = qeth_clear_channel(&card->data);
  1155. if (rc1)
  1156. return rc1;
  1157. if (rc2)
  1158. return rc2;
  1159. return rc3;
  1160. }
  1161. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1162. {
  1163. int rc = 0;
  1164. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1165. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1166. if (halt)
  1167. rc = qeth_halt_channels(card);
  1168. if (rc)
  1169. return rc;
  1170. return qeth_clear_channels(card);
  1171. }
  1172. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1173. {
  1174. int rc = 0;
  1175. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1176. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1177. QETH_QDIO_CLEANING)) {
  1178. case QETH_QDIO_ESTABLISHED:
  1179. if (card->info.type == QETH_CARD_TYPE_IQD)
  1180. rc = qdio_cleanup(CARD_DDEV(card),
  1181. QDIO_FLAG_CLEANUP_USING_HALT);
  1182. else
  1183. rc = qdio_cleanup(CARD_DDEV(card),
  1184. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1185. if (rc)
  1186. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1187. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1188. break;
  1189. case QETH_QDIO_CLEANING:
  1190. return rc;
  1191. default:
  1192. break;
  1193. }
  1194. rc = qeth_clear_halt_card(card, use_halt);
  1195. if (rc)
  1196. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1197. card->state = CARD_STATE_DOWN;
  1198. return rc;
  1199. }
  1200. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1201. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1202. int *length)
  1203. {
  1204. struct ciw *ciw;
  1205. char *rcd_buf;
  1206. int ret;
  1207. struct qeth_channel *channel = &card->data;
  1208. unsigned long flags;
  1209. /*
  1210. * scan for RCD command in extended SenseID data
  1211. */
  1212. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1213. if (!ciw || ciw->cmd == 0)
  1214. return -EOPNOTSUPP;
  1215. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1216. if (!rcd_buf)
  1217. return -ENOMEM;
  1218. channel->ccw.cmd_code = ciw->cmd;
  1219. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1220. channel->ccw.count = ciw->count;
  1221. channel->ccw.flags = CCW_FLAG_SLI;
  1222. channel->state = CH_STATE_RCD;
  1223. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1224. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1225. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1226. QETH_RCD_TIMEOUT);
  1227. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1228. if (!ret)
  1229. wait_event(card->wait_q,
  1230. (channel->state == CH_STATE_RCD_DONE ||
  1231. channel->state == CH_STATE_DOWN));
  1232. if (channel->state == CH_STATE_DOWN)
  1233. ret = -EIO;
  1234. else
  1235. channel->state = CH_STATE_DOWN;
  1236. if (ret) {
  1237. kfree(rcd_buf);
  1238. *buffer = NULL;
  1239. *length = 0;
  1240. } else {
  1241. *length = ciw->count;
  1242. *buffer = rcd_buf;
  1243. }
  1244. return ret;
  1245. }
  1246. static int qeth_get_unitaddr(struct qeth_card *card)
  1247. {
  1248. int length;
  1249. char *prcd;
  1250. int rc;
  1251. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1252. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1253. if (rc) {
  1254. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  1255. dev_name(&card->gdev->dev), rc);
  1256. return rc;
  1257. }
  1258. card->info.chpid = prcd[30];
  1259. card->info.unit_addr2 = prcd[31];
  1260. card->info.cula = prcd[63];
  1261. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1262. (prcd[0x11] == _ascebc['M']));
  1263. kfree(prcd);
  1264. return 0;
  1265. }
  1266. static void qeth_init_tokens(struct qeth_card *card)
  1267. {
  1268. card->token.issuer_rm_w = 0x00010103UL;
  1269. card->token.cm_filter_w = 0x00010108UL;
  1270. card->token.cm_connection_w = 0x0001010aUL;
  1271. card->token.ulp_filter_w = 0x0001010bUL;
  1272. card->token.ulp_connection_w = 0x0001010dUL;
  1273. }
  1274. static void qeth_init_func_level(struct qeth_card *card)
  1275. {
  1276. if (card->ipato.enabled) {
  1277. if (card->info.type == QETH_CARD_TYPE_IQD)
  1278. card->info.func_level =
  1279. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1280. else
  1281. card->info.func_level =
  1282. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1283. } else {
  1284. if (card->info.type == QETH_CARD_TYPE_IQD)
  1285. /*FIXME:why do we have same values for dis and ena for
  1286. osae??? */
  1287. card->info.func_level =
  1288. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1289. else
  1290. card->info.func_level =
  1291. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1292. }
  1293. }
  1294. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1295. void (*idx_reply_cb)(struct qeth_channel *,
  1296. struct qeth_cmd_buffer *))
  1297. {
  1298. struct qeth_cmd_buffer *iob;
  1299. unsigned long flags;
  1300. int rc;
  1301. struct qeth_card *card;
  1302. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1303. card = CARD_FROM_CDEV(channel->ccwdev);
  1304. iob = qeth_get_buffer(channel);
  1305. iob->callback = idx_reply_cb;
  1306. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1307. channel->ccw.count = QETH_BUFSIZE;
  1308. channel->ccw.cda = (__u32) __pa(iob->data);
  1309. wait_event(card->wait_q,
  1310. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1311. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1312. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1313. rc = ccw_device_start(channel->ccwdev,
  1314. &channel->ccw, (addr_t) iob, 0, 0);
  1315. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1316. if (rc) {
  1317. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1318. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1319. atomic_set(&channel->irq_pending, 0);
  1320. wake_up(&card->wait_q);
  1321. return rc;
  1322. }
  1323. rc = wait_event_interruptible_timeout(card->wait_q,
  1324. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1325. if (rc == -ERESTARTSYS)
  1326. return rc;
  1327. if (channel->state != CH_STATE_UP) {
  1328. rc = -ETIME;
  1329. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1330. qeth_clear_cmd_buffers(channel);
  1331. } else
  1332. rc = 0;
  1333. return rc;
  1334. }
  1335. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1336. void (*idx_reply_cb)(struct qeth_channel *,
  1337. struct qeth_cmd_buffer *))
  1338. {
  1339. struct qeth_card *card;
  1340. struct qeth_cmd_buffer *iob;
  1341. unsigned long flags;
  1342. __u16 temp;
  1343. __u8 tmp;
  1344. int rc;
  1345. struct ccw_dev_id temp_devid;
  1346. card = CARD_FROM_CDEV(channel->ccwdev);
  1347. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1348. iob = qeth_get_buffer(channel);
  1349. iob->callback = idx_reply_cb;
  1350. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1351. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1352. channel->ccw.cda = (__u32) __pa(iob->data);
  1353. if (channel == &card->write) {
  1354. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1355. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1356. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1357. card->seqno.trans_hdr++;
  1358. } else {
  1359. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1360. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1361. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1362. }
  1363. tmp = ((__u8)card->info.portno) | 0x80;
  1364. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1365. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1366. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1367. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1368. &card->info.func_level, sizeof(__u16));
  1369. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1370. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1371. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1372. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1373. wait_event(card->wait_q,
  1374. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1375. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1376. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1377. rc = ccw_device_start(channel->ccwdev,
  1378. &channel->ccw, (addr_t) iob, 0, 0);
  1379. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1380. if (rc) {
  1381. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1382. rc);
  1383. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1384. atomic_set(&channel->irq_pending, 0);
  1385. wake_up(&card->wait_q);
  1386. return rc;
  1387. }
  1388. rc = wait_event_interruptible_timeout(card->wait_q,
  1389. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1390. if (rc == -ERESTARTSYS)
  1391. return rc;
  1392. if (channel->state != CH_STATE_ACTIVATING) {
  1393. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1394. " failed to recover an error on the device\n");
  1395. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1396. dev_name(&channel->ccwdev->dev));
  1397. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1398. qeth_clear_cmd_buffers(channel);
  1399. return -ETIME;
  1400. }
  1401. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1402. }
  1403. static int qeth_peer_func_level(int level)
  1404. {
  1405. if ((level & 0xff) == 8)
  1406. return (level & 0xff) + 0x400;
  1407. if (((level >> 8) & 3) == 1)
  1408. return (level & 0xff) + 0x200;
  1409. return level;
  1410. }
  1411. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1412. struct qeth_cmd_buffer *iob)
  1413. {
  1414. struct qeth_card *card;
  1415. __u16 temp;
  1416. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1417. if (channel->state == CH_STATE_DOWN) {
  1418. channel->state = CH_STATE_ACTIVATING;
  1419. goto out;
  1420. }
  1421. card = CARD_FROM_CDEV(channel->ccwdev);
  1422. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1423. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1424. dev_err(&card->write.ccwdev->dev,
  1425. "The adapter is used exclusively by another "
  1426. "host\n");
  1427. else
  1428. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1429. " negative reply\n",
  1430. dev_name(&card->write.ccwdev->dev));
  1431. goto out;
  1432. }
  1433. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1434. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1435. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1436. "function level mismatch (sent: 0x%x, received: "
  1437. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1438. card->info.func_level, temp);
  1439. goto out;
  1440. }
  1441. channel->state = CH_STATE_UP;
  1442. out:
  1443. qeth_release_buffer(channel, iob);
  1444. }
  1445. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1446. struct qeth_cmd_buffer *iob)
  1447. {
  1448. struct qeth_card *card;
  1449. __u16 temp;
  1450. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1451. if (channel->state == CH_STATE_DOWN) {
  1452. channel->state = CH_STATE_ACTIVATING;
  1453. goto out;
  1454. }
  1455. card = CARD_FROM_CDEV(channel->ccwdev);
  1456. if (qeth_check_idx_response(iob->data))
  1457. goto out;
  1458. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1459. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1460. dev_err(&card->write.ccwdev->dev,
  1461. "The adapter is used exclusively by another "
  1462. "host\n");
  1463. else
  1464. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1465. " negative reply\n",
  1466. dev_name(&card->read.ccwdev->dev));
  1467. goto out;
  1468. }
  1469. /**
  1470. * temporary fix for microcode bug
  1471. * to revert it,replace OR by AND
  1472. */
  1473. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1474. (card->info.type == QETH_CARD_TYPE_OSAE))
  1475. card->info.portname_required = 1;
  1476. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1477. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1478. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1479. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1480. dev_name(&card->read.ccwdev->dev),
  1481. card->info.func_level, temp);
  1482. goto out;
  1483. }
  1484. memcpy(&card->token.issuer_rm_r,
  1485. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1486. QETH_MPC_TOKEN_LENGTH);
  1487. memcpy(&card->info.mcl_level[0],
  1488. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1489. channel->state = CH_STATE_UP;
  1490. out:
  1491. qeth_release_buffer(channel, iob);
  1492. }
  1493. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1494. struct qeth_cmd_buffer *iob)
  1495. {
  1496. qeth_setup_ccw(&card->write, iob->data, len);
  1497. iob->callback = qeth_release_buffer;
  1498. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1499. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1500. card->seqno.trans_hdr++;
  1501. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1502. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1503. card->seqno.pdu_hdr++;
  1504. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1505. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1506. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1507. }
  1508. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1509. int qeth_send_control_data(struct qeth_card *card, int len,
  1510. struct qeth_cmd_buffer *iob,
  1511. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1512. unsigned long),
  1513. void *reply_param)
  1514. {
  1515. int rc;
  1516. unsigned long flags;
  1517. struct qeth_reply *reply = NULL;
  1518. unsigned long timeout;
  1519. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1520. reply = qeth_alloc_reply(card);
  1521. if (!reply) {
  1522. return -ENOMEM;
  1523. }
  1524. reply->callback = reply_cb;
  1525. reply->param = reply_param;
  1526. if (card->state == CARD_STATE_DOWN)
  1527. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1528. else
  1529. reply->seqno = card->seqno.ipa++;
  1530. init_waitqueue_head(&reply->wait_q);
  1531. spin_lock_irqsave(&card->lock, flags);
  1532. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1533. spin_unlock_irqrestore(&card->lock, flags);
  1534. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1535. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1536. qeth_prepare_control_data(card, len, iob);
  1537. if (IS_IPA(iob->data))
  1538. timeout = jiffies + QETH_IPA_TIMEOUT;
  1539. else
  1540. timeout = jiffies + QETH_TIMEOUT;
  1541. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1542. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1543. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1544. (addr_t) iob, 0, 0);
  1545. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1546. if (rc) {
  1547. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1548. "ccw_device_start rc = %i\n",
  1549. dev_name(&card->write.ccwdev->dev), rc);
  1550. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1551. spin_lock_irqsave(&card->lock, flags);
  1552. list_del_init(&reply->list);
  1553. qeth_put_reply(reply);
  1554. spin_unlock_irqrestore(&card->lock, flags);
  1555. qeth_release_buffer(iob->channel, iob);
  1556. atomic_set(&card->write.irq_pending, 0);
  1557. wake_up(&card->wait_q);
  1558. return rc;
  1559. }
  1560. while (!atomic_read(&reply->received)) {
  1561. if (time_after(jiffies, timeout)) {
  1562. spin_lock_irqsave(&reply->card->lock, flags);
  1563. list_del_init(&reply->list);
  1564. spin_unlock_irqrestore(&reply->card->lock, flags);
  1565. reply->rc = -ETIME;
  1566. atomic_inc(&reply->received);
  1567. wake_up(&reply->wait_q);
  1568. }
  1569. cpu_relax();
  1570. };
  1571. rc = reply->rc;
  1572. qeth_put_reply(reply);
  1573. return rc;
  1574. }
  1575. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1576. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1577. unsigned long data)
  1578. {
  1579. struct qeth_cmd_buffer *iob;
  1580. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1581. iob = (struct qeth_cmd_buffer *) data;
  1582. memcpy(&card->token.cm_filter_r,
  1583. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1584. QETH_MPC_TOKEN_LENGTH);
  1585. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1586. return 0;
  1587. }
  1588. static int qeth_cm_enable(struct qeth_card *card)
  1589. {
  1590. int rc;
  1591. struct qeth_cmd_buffer *iob;
  1592. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1593. iob = qeth_wait_for_buffer(&card->write);
  1594. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1595. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1596. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1597. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1598. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1599. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1600. qeth_cm_enable_cb, NULL);
  1601. return rc;
  1602. }
  1603. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1604. unsigned long data)
  1605. {
  1606. struct qeth_cmd_buffer *iob;
  1607. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1608. iob = (struct qeth_cmd_buffer *) data;
  1609. memcpy(&card->token.cm_connection_r,
  1610. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1611. QETH_MPC_TOKEN_LENGTH);
  1612. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1613. return 0;
  1614. }
  1615. static int qeth_cm_setup(struct qeth_card *card)
  1616. {
  1617. int rc;
  1618. struct qeth_cmd_buffer *iob;
  1619. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1620. iob = qeth_wait_for_buffer(&card->write);
  1621. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1622. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1623. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1624. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1625. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1626. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1627. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1628. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1629. qeth_cm_setup_cb, NULL);
  1630. return rc;
  1631. }
  1632. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1633. {
  1634. switch (card->info.type) {
  1635. case QETH_CARD_TYPE_UNKNOWN:
  1636. return 1500;
  1637. case QETH_CARD_TYPE_IQD:
  1638. return card->info.max_mtu;
  1639. case QETH_CARD_TYPE_OSAE:
  1640. switch (card->info.link_type) {
  1641. case QETH_LINK_TYPE_HSTR:
  1642. case QETH_LINK_TYPE_LANE_TR:
  1643. return 2000;
  1644. default:
  1645. return 1492;
  1646. }
  1647. default:
  1648. return 1500;
  1649. }
  1650. }
  1651. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1652. {
  1653. switch (cardtype) {
  1654. case QETH_CARD_TYPE_UNKNOWN:
  1655. case QETH_CARD_TYPE_OSAE:
  1656. case QETH_CARD_TYPE_OSN:
  1657. return 61440;
  1658. case QETH_CARD_TYPE_IQD:
  1659. return 57344;
  1660. default:
  1661. return 1500;
  1662. }
  1663. }
  1664. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1665. {
  1666. switch (cardtype) {
  1667. case QETH_CARD_TYPE_IQD:
  1668. return 1;
  1669. default:
  1670. return 0;
  1671. }
  1672. }
  1673. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1674. {
  1675. switch (framesize) {
  1676. case 0x4000:
  1677. return 8192;
  1678. case 0x6000:
  1679. return 16384;
  1680. case 0xa000:
  1681. return 32768;
  1682. case 0xffff:
  1683. return 57344;
  1684. default:
  1685. return 0;
  1686. }
  1687. }
  1688. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1689. {
  1690. switch (card->info.type) {
  1691. case QETH_CARD_TYPE_OSAE:
  1692. return ((mtu >= 576) && (mtu <= 61440));
  1693. case QETH_CARD_TYPE_IQD:
  1694. return ((mtu >= 576) &&
  1695. (mtu <= card->info.max_mtu + 4096 - 32));
  1696. case QETH_CARD_TYPE_OSN:
  1697. case QETH_CARD_TYPE_UNKNOWN:
  1698. default:
  1699. return 1;
  1700. }
  1701. }
  1702. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1703. unsigned long data)
  1704. {
  1705. __u16 mtu, framesize;
  1706. __u16 len;
  1707. __u8 link_type;
  1708. struct qeth_cmd_buffer *iob;
  1709. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1710. iob = (struct qeth_cmd_buffer *) data;
  1711. memcpy(&card->token.ulp_filter_r,
  1712. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1713. QETH_MPC_TOKEN_LENGTH);
  1714. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1715. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1716. mtu = qeth_get_mtu_outof_framesize(framesize);
  1717. if (!mtu) {
  1718. iob->rc = -EINVAL;
  1719. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1720. return 0;
  1721. }
  1722. card->info.max_mtu = mtu;
  1723. card->info.initial_mtu = mtu;
  1724. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1725. } else {
  1726. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1727. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1728. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1729. }
  1730. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1731. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1732. memcpy(&link_type,
  1733. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1734. card->info.link_type = link_type;
  1735. } else
  1736. card->info.link_type = 0;
  1737. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1738. return 0;
  1739. }
  1740. static int qeth_ulp_enable(struct qeth_card *card)
  1741. {
  1742. int rc;
  1743. char prot_type;
  1744. struct qeth_cmd_buffer *iob;
  1745. /*FIXME: trace view callbacks*/
  1746. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1747. iob = qeth_wait_for_buffer(&card->write);
  1748. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1749. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1750. (__u8) card->info.portno;
  1751. if (card->options.layer2)
  1752. if (card->info.type == QETH_CARD_TYPE_OSN)
  1753. prot_type = QETH_PROT_OSN2;
  1754. else
  1755. prot_type = QETH_PROT_LAYER2;
  1756. else
  1757. prot_type = QETH_PROT_TCPIP;
  1758. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1759. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1760. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1761. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1762. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1763. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1764. card->info.portname, 9);
  1765. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1766. qeth_ulp_enable_cb, NULL);
  1767. return rc;
  1768. }
  1769. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1770. unsigned long data)
  1771. {
  1772. struct qeth_cmd_buffer *iob;
  1773. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1774. iob = (struct qeth_cmd_buffer *) data;
  1775. memcpy(&card->token.ulp_connection_r,
  1776. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1777. QETH_MPC_TOKEN_LENGTH);
  1778. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1779. return 0;
  1780. }
  1781. static int qeth_ulp_setup(struct qeth_card *card)
  1782. {
  1783. int rc;
  1784. __u16 temp;
  1785. struct qeth_cmd_buffer *iob;
  1786. struct ccw_dev_id dev_id;
  1787. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1788. iob = qeth_wait_for_buffer(&card->write);
  1789. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1790. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1791. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1792. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1793. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1794. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1795. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1796. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1797. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1798. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1799. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1800. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1801. qeth_ulp_setup_cb, NULL);
  1802. return rc;
  1803. }
  1804. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1805. {
  1806. int i, j;
  1807. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1808. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1809. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1810. return 0;
  1811. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1812. GFP_KERNEL);
  1813. if (!card->qdio.in_q)
  1814. goto out_nomem;
  1815. QETH_DBF_TEXT(SETUP, 2, "inq");
  1816. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1817. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1818. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1819. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1820. card->qdio.in_q->bufs[i].buffer =
  1821. &card->qdio.in_q->qdio_bufs[i];
  1822. /* inbound buffer pool */
  1823. if (qeth_alloc_buffer_pool(card))
  1824. goto out_freeinq;
  1825. /* outbound */
  1826. card->qdio.out_qs =
  1827. kmalloc(card->qdio.no_out_queues *
  1828. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1829. if (!card->qdio.out_qs)
  1830. goto out_freepool;
  1831. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1832. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1833. GFP_KERNEL);
  1834. if (!card->qdio.out_qs[i])
  1835. goto out_freeoutq;
  1836. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1837. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1838. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1839. card->qdio.out_qs[i]->queue_no = i;
  1840. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1841. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1842. card->qdio.out_qs[i]->bufs[j].buffer =
  1843. &card->qdio.out_qs[i]->qdio_bufs[j];
  1844. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1845. skb_list);
  1846. lockdep_set_class(
  1847. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1848. &qdio_out_skb_queue_key);
  1849. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1850. }
  1851. }
  1852. return 0;
  1853. out_freeoutq:
  1854. while (i > 0)
  1855. kfree(card->qdio.out_qs[--i]);
  1856. kfree(card->qdio.out_qs);
  1857. card->qdio.out_qs = NULL;
  1858. out_freepool:
  1859. qeth_free_buffer_pool(card);
  1860. out_freeinq:
  1861. kfree(card->qdio.in_q);
  1862. card->qdio.in_q = NULL;
  1863. out_nomem:
  1864. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1865. return -ENOMEM;
  1866. }
  1867. static void qeth_create_qib_param_field(struct qeth_card *card,
  1868. char *param_field)
  1869. {
  1870. param_field[0] = _ascebc['P'];
  1871. param_field[1] = _ascebc['C'];
  1872. param_field[2] = _ascebc['I'];
  1873. param_field[3] = _ascebc['T'];
  1874. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1875. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1876. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1877. }
  1878. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1879. char *param_field)
  1880. {
  1881. param_field[16] = _ascebc['B'];
  1882. param_field[17] = _ascebc['L'];
  1883. param_field[18] = _ascebc['K'];
  1884. param_field[19] = _ascebc['T'];
  1885. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1886. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1887. *((unsigned int *) (&param_field[28])) =
  1888. card->info.blkt.inter_packet_jumbo;
  1889. }
  1890. static int qeth_qdio_activate(struct qeth_card *card)
  1891. {
  1892. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1893. return qdio_activate(CARD_DDEV(card));
  1894. }
  1895. static int qeth_dm_act(struct qeth_card *card)
  1896. {
  1897. int rc;
  1898. struct qeth_cmd_buffer *iob;
  1899. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1900. iob = qeth_wait_for_buffer(&card->write);
  1901. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1902. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1903. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1904. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1905. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1906. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1907. return rc;
  1908. }
  1909. static int qeth_mpc_initialize(struct qeth_card *card)
  1910. {
  1911. int rc;
  1912. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1913. rc = qeth_issue_next_read(card);
  1914. if (rc) {
  1915. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1916. return rc;
  1917. }
  1918. rc = qeth_cm_enable(card);
  1919. if (rc) {
  1920. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1921. goto out_qdio;
  1922. }
  1923. rc = qeth_cm_setup(card);
  1924. if (rc) {
  1925. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1926. goto out_qdio;
  1927. }
  1928. rc = qeth_ulp_enable(card);
  1929. if (rc) {
  1930. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1931. goto out_qdio;
  1932. }
  1933. rc = qeth_ulp_setup(card);
  1934. if (rc) {
  1935. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1936. goto out_qdio;
  1937. }
  1938. rc = qeth_alloc_qdio_buffers(card);
  1939. if (rc) {
  1940. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1941. goto out_qdio;
  1942. }
  1943. rc = qeth_qdio_establish(card);
  1944. if (rc) {
  1945. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1946. qeth_free_qdio_buffers(card);
  1947. goto out_qdio;
  1948. }
  1949. rc = qeth_qdio_activate(card);
  1950. if (rc) {
  1951. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1952. goto out_qdio;
  1953. }
  1954. rc = qeth_dm_act(card);
  1955. if (rc) {
  1956. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1957. goto out_qdio;
  1958. }
  1959. return 0;
  1960. out_qdio:
  1961. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1962. return rc;
  1963. }
  1964. static void qeth_print_status_with_portname(struct qeth_card *card)
  1965. {
  1966. char dbf_text[15];
  1967. int i;
  1968. sprintf(dbf_text, "%s", card->info.portname + 1);
  1969. for (i = 0; i < 8; i++)
  1970. dbf_text[i] =
  1971. (char) _ebcasc[(__u8) dbf_text[i]];
  1972. dbf_text[8] = 0;
  1973. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1974. "with link type %s (portname: %s)\n",
  1975. qeth_get_cardname(card),
  1976. (card->info.mcl_level[0]) ? " (level: " : "",
  1977. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1978. (card->info.mcl_level[0]) ? ")" : "",
  1979. qeth_get_cardname_short(card),
  1980. dbf_text);
  1981. }
  1982. static void qeth_print_status_no_portname(struct qeth_card *card)
  1983. {
  1984. if (card->info.portname[0])
  1985. dev_info(&card->gdev->dev, "Device is a%s "
  1986. "card%s%s%s\nwith link type %s "
  1987. "(no portname needed by interface).\n",
  1988. qeth_get_cardname(card),
  1989. (card->info.mcl_level[0]) ? " (level: " : "",
  1990. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1991. (card->info.mcl_level[0]) ? ")" : "",
  1992. qeth_get_cardname_short(card));
  1993. else
  1994. dev_info(&card->gdev->dev, "Device is a%s "
  1995. "card%s%s%s\nwith link type %s.\n",
  1996. qeth_get_cardname(card),
  1997. (card->info.mcl_level[0]) ? " (level: " : "",
  1998. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1999. (card->info.mcl_level[0]) ? ")" : "",
  2000. qeth_get_cardname_short(card));
  2001. }
  2002. void qeth_print_status_message(struct qeth_card *card)
  2003. {
  2004. switch (card->info.type) {
  2005. case QETH_CARD_TYPE_OSAE:
  2006. /* VM will use a non-zero first character
  2007. * to indicate a HiperSockets like reporting
  2008. * of the level OSA sets the first character to zero
  2009. * */
  2010. if (!card->info.mcl_level[0]) {
  2011. sprintf(card->info.mcl_level, "%02x%02x",
  2012. card->info.mcl_level[2],
  2013. card->info.mcl_level[3]);
  2014. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2015. break;
  2016. }
  2017. /* fallthrough */
  2018. case QETH_CARD_TYPE_IQD:
  2019. if ((card->info.guestlan) ||
  2020. (card->info.mcl_level[0] & 0x80)) {
  2021. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2022. card->info.mcl_level[0]];
  2023. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2024. card->info.mcl_level[1]];
  2025. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2026. card->info.mcl_level[2]];
  2027. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2028. card->info.mcl_level[3]];
  2029. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2030. }
  2031. break;
  2032. default:
  2033. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2034. }
  2035. if (card->info.portname_required)
  2036. qeth_print_status_with_portname(card);
  2037. else
  2038. qeth_print_status_no_portname(card);
  2039. }
  2040. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2041. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2042. {
  2043. struct qeth_buffer_pool_entry *entry;
  2044. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2045. list_for_each_entry(entry,
  2046. &card->qdio.init_pool.entry_list, init_list) {
  2047. qeth_put_buffer_pool_entry(card, entry);
  2048. }
  2049. }
  2050. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2051. struct qeth_card *card)
  2052. {
  2053. struct list_head *plh;
  2054. struct qeth_buffer_pool_entry *entry;
  2055. int i, free;
  2056. struct page *page;
  2057. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2058. return NULL;
  2059. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2060. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2061. free = 1;
  2062. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2063. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2064. free = 0;
  2065. break;
  2066. }
  2067. }
  2068. if (free) {
  2069. list_del_init(&entry->list);
  2070. return entry;
  2071. }
  2072. }
  2073. /* no free buffer in pool so take first one and swap pages */
  2074. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2075. struct qeth_buffer_pool_entry, list);
  2076. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2077. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2078. page = alloc_page(GFP_ATOMIC);
  2079. if (!page) {
  2080. return NULL;
  2081. } else {
  2082. free_page((unsigned long)entry->elements[i]);
  2083. entry->elements[i] = page_address(page);
  2084. if (card->options.performance_stats)
  2085. card->perf_stats.sg_alloc_page_rx++;
  2086. }
  2087. }
  2088. }
  2089. list_del_init(&entry->list);
  2090. return entry;
  2091. }
  2092. static int qeth_init_input_buffer(struct qeth_card *card,
  2093. struct qeth_qdio_buffer *buf)
  2094. {
  2095. struct qeth_buffer_pool_entry *pool_entry;
  2096. int i;
  2097. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2098. if (!pool_entry)
  2099. return 1;
  2100. /*
  2101. * since the buffer is accessed only from the input_tasklet
  2102. * there shouldn't be a need to synchronize; also, since we use
  2103. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2104. * buffers
  2105. */
  2106. buf->pool_entry = pool_entry;
  2107. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2108. buf->buffer->element[i].length = PAGE_SIZE;
  2109. buf->buffer->element[i].addr = pool_entry->elements[i];
  2110. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2111. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2112. else
  2113. buf->buffer->element[i].flags = 0;
  2114. }
  2115. return 0;
  2116. }
  2117. int qeth_init_qdio_queues(struct qeth_card *card)
  2118. {
  2119. int i, j;
  2120. int rc;
  2121. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2122. /* inbound queue */
  2123. memset(card->qdio.in_q->qdio_bufs, 0,
  2124. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2125. qeth_initialize_working_pool_list(card);
  2126. /*give only as many buffers to hardware as we have buffer pool entries*/
  2127. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2128. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2129. card->qdio.in_q->next_buf_to_init =
  2130. card->qdio.in_buf_pool.buf_count - 1;
  2131. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2132. card->qdio.in_buf_pool.buf_count - 1);
  2133. if (rc) {
  2134. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2135. return rc;
  2136. }
  2137. /* outbound queue */
  2138. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2139. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2140. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2141. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2142. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2143. &card->qdio.out_qs[i]->bufs[j]);
  2144. }
  2145. card->qdio.out_qs[i]->card = card;
  2146. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2147. card->qdio.out_qs[i]->do_pack = 0;
  2148. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2149. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2150. atomic_set(&card->qdio.out_qs[i]->state,
  2151. QETH_OUT_Q_UNLOCKED);
  2152. }
  2153. return 0;
  2154. }
  2155. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2156. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2157. {
  2158. switch (link_type) {
  2159. case QETH_LINK_TYPE_HSTR:
  2160. return 2;
  2161. default:
  2162. return 1;
  2163. }
  2164. }
  2165. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2166. struct qeth_ipa_cmd *cmd, __u8 command,
  2167. enum qeth_prot_versions prot)
  2168. {
  2169. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2170. cmd->hdr.command = command;
  2171. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2172. cmd->hdr.seqno = card->seqno.ipa;
  2173. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2174. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2175. if (card->options.layer2)
  2176. cmd->hdr.prim_version_no = 2;
  2177. else
  2178. cmd->hdr.prim_version_no = 1;
  2179. cmd->hdr.param_count = 1;
  2180. cmd->hdr.prot_version = prot;
  2181. cmd->hdr.ipa_supported = 0;
  2182. cmd->hdr.ipa_enabled = 0;
  2183. }
  2184. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2185. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2186. {
  2187. struct qeth_cmd_buffer *iob;
  2188. struct qeth_ipa_cmd *cmd;
  2189. iob = qeth_wait_for_buffer(&card->write);
  2190. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2191. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2192. return iob;
  2193. }
  2194. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2195. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2196. char prot_type)
  2197. {
  2198. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2199. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2200. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2201. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2202. }
  2203. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2204. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2205. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2206. unsigned long),
  2207. void *reply_param)
  2208. {
  2209. int rc;
  2210. char prot_type;
  2211. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2212. if (card->options.layer2)
  2213. if (card->info.type == QETH_CARD_TYPE_OSN)
  2214. prot_type = QETH_PROT_OSN2;
  2215. else
  2216. prot_type = QETH_PROT_LAYER2;
  2217. else
  2218. prot_type = QETH_PROT_TCPIP;
  2219. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2220. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2221. iob, reply_cb, reply_param);
  2222. return rc;
  2223. }
  2224. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2225. static int qeth_send_startstoplan(struct qeth_card *card,
  2226. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2227. {
  2228. int rc;
  2229. struct qeth_cmd_buffer *iob;
  2230. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2231. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2232. return rc;
  2233. }
  2234. int qeth_send_startlan(struct qeth_card *card)
  2235. {
  2236. int rc;
  2237. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2238. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2239. return rc;
  2240. }
  2241. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2242. int qeth_send_stoplan(struct qeth_card *card)
  2243. {
  2244. int rc = 0;
  2245. /*
  2246. * TODO: according to the IPA format document page 14,
  2247. * TCP/IP (we!) never issue a STOPLAN
  2248. * is this right ?!?
  2249. */
  2250. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2251. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2252. return rc;
  2253. }
  2254. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2255. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2256. struct qeth_reply *reply, unsigned long data)
  2257. {
  2258. struct qeth_ipa_cmd *cmd;
  2259. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2260. cmd = (struct qeth_ipa_cmd *) data;
  2261. if (cmd->hdr.return_code == 0)
  2262. cmd->hdr.return_code =
  2263. cmd->data.setadapterparms.hdr.return_code;
  2264. return 0;
  2265. }
  2266. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2267. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2268. struct qeth_reply *reply, unsigned long data)
  2269. {
  2270. struct qeth_ipa_cmd *cmd;
  2271. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2272. cmd = (struct qeth_ipa_cmd *) data;
  2273. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2274. card->info.link_type =
  2275. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2276. card->options.adp.supported_funcs =
  2277. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2278. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2279. }
  2280. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2281. __u32 command, __u32 cmdlen)
  2282. {
  2283. struct qeth_cmd_buffer *iob;
  2284. struct qeth_ipa_cmd *cmd;
  2285. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2286. QETH_PROT_IPV4);
  2287. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2288. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2289. cmd->data.setadapterparms.hdr.command_code = command;
  2290. cmd->data.setadapterparms.hdr.used_total = 1;
  2291. cmd->data.setadapterparms.hdr.seq_no = 1;
  2292. return iob;
  2293. }
  2294. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2295. int qeth_query_setadapterparms(struct qeth_card *card)
  2296. {
  2297. int rc;
  2298. struct qeth_cmd_buffer *iob;
  2299. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2300. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2301. sizeof(struct qeth_ipacmd_setadpparms));
  2302. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2303. return rc;
  2304. }
  2305. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2306. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2307. const char *dbftext)
  2308. {
  2309. if (qdio_error) {
  2310. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2311. QETH_DBF_TEXT(QERR, 2, dbftext);
  2312. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2313. buf->element[15].flags & 0xff);
  2314. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2315. buf->element[14].flags & 0xff);
  2316. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2317. return 1;
  2318. }
  2319. return 0;
  2320. }
  2321. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2322. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2323. {
  2324. struct qeth_qdio_q *queue = card->qdio.in_q;
  2325. int count;
  2326. int i;
  2327. int rc;
  2328. int newcount = 0;
  2329. count = (index < queue->next_buf_to_init)?
  2330. card->qdio.in_buf_pool.buf_count -
  2331. (queue->next_buf_to_init - index) :
  2332. card->qdio.in_buf_pool.buf_count -
  2333. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2334. /* only requeue at a certain threshold to avoid SIGAs */
  2335. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2336. for (i = queue->next_buf_to_init;
  2337. i < queue->next_buf_to_init + count; ++i) {
  2338. if (qeth_init_input_buffer(card,
  2339. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2340. break;
  2341. } else {
  2342. newcount++;
  2343. }
  2344. }
  2345. if (newcount < count) {
  2346. /* we are in memory shortage so we switch back to
  2347. traditional skb allocation and drop packages */
  2348. atomic_set(&card->force_alloc_skb, 3);
  2349. count = newcount;
  2350. } else {
  2351. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2352. }
  2353. /*
  2354. * according to old code it should be avoided to requeue all
  2355. * 128 buffers in order to benefit from PCI avoidance.
  2356. * this function keeps at least one buffer (the buffer at
  2357. * 'index') un-requeued -> this buffer is the first buffer that
  2358. * will be requeued the next time
  2359. */
  2360. if (card->options.performance_stats) {
  2361. card->perf_stats.inbound_do_qdio_cnt++;
  2362. card->perf_stats.inbound_do_qdio_start_time =
  2363. qeth_get_micros();
  2364. }
  2365. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2366. queue->next_buf_to_init, count);
  2367. if (card->options.performance_stats)
  2368. card->perf_stats.inbound_do_qdio_time +=
  2369. qeth_get_micros() -
  2370. card->perf_stats.inbound_do_qdio_start_time;
  2371. if (rc) {
  2372. dev_warn(&card->gdev->dev,
  2373. "QDIO reported an error, rc=%i\n", rc);
  2374. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2375. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2376. }
  2377. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2378. QDIO_MAX_BUFFERS_PER_Q;
  2379. }
  2380. }
  2381. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2382. static int qeth_handle_send_error(struct qeth_card *card,
  2383. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2384. {
  2385. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2386. int cc = qdio_err & 3;
  2387. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2388. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2389. switch (cc) {
  2390. case 0:
  2391. if (qdio_err) {
  2392. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2393. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2394. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2395. (u16)qdio_err, (u8)sbalf15);
  2396. return QETH_SEND_ERROR_LINK_FAILURE;
  2397. }
  2398. return QETH_SEND_ERROR_NONE;
  2399. case 2:
  2400. if (qdio_err & QDIO_ERROR_SIGA_BUSY) {
  2401. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2402. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2403. return QETH_SEND_ERROR_KICK_IT;
  2404. }
  2405. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2406. return QETH_SEND_ERROR_RETRY;
  2407. return QETH_SEND_ERROR_LINK_FAILURE;
  2408. /* look at qdio_error and sbalf 15 */
  2409. case 1:
  2410. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2411. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2412. return QETH_SEND_ERROR_LINK_FAILURE;
  2413. case 3:
  2414. default:
  2415. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2416. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2417. return QETH_SEND_ERROR_KICK_IT;
  2418. }
  2419. }
  2420. /*
  2421. * Switched to packing state if the number of used buffers on a queue
  2422. * reaches a certain limit.
  2423. */
  2424. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2425. {
  2426. if (!queue->do_pack) {
  2427. if (atomic_read(&queue->used_buffers)
  2428. >= QETH_HIGH_WATERMARK_PACK){
  2429. /* switch non-PACKING -> PACKING */
  2430. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2431. if (queue->card->options.performance_stats)
  2432. queue->card->perf_stats.sc_dp_p++;
  2433. queue->do_pack = 1;
  2434. }
  2435. }
  2436. }
  2437. /*
  2438. * Switches from packing to non-packing mode. If there is a packing
  2439. * buffer on the queue this buffer will be prepared to be flushed.
  2440. * In that case 1 is returned to inform the caller. If no buffer
  2441. * has to be flushed, zero is returned.
  2442. */
  2443. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2444. {
  2445. struct qeth_qdio_out_buffer *buffer;
  2446. int flush_count = 0;
  2447. if (queue->do_pack) {
  2448. if (atomic_read(&queue->used_buffers)
  2449. <= QETH_LOW_WATERMARK_PACK) {
  2450. /* switch PACKING -> non-PACKING */
  2451. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2452. if (queue->card->options.performance_stats)
  2453. queue->card->perf_stats.sc_p_dp++;
  2454. queue->do_pack = 0;
  2455. /* flush packing buffers */
  2456. buffer = &queue->bufs[queue->next_buf_to_fill];
  2457. if ((atomic_read(&buffer->state) ==
  2458. QETH_QDIO_BUF_EMPTY) &&
  2459. (buffer->next_element_to_fill > 0)) {
  2460. atomic_set(&buffer->state,
  2461. QETH_QDIO_BUF_PRIMED);
  2462. flush_count++;
  2463. queue->next_buf_to_fill =
  2464. (queue->next_buf_to_fill + 1) %
  2465. QDIO_MAX_BUFFERS_PER_Q;
  2466. }
  2467. }
  2468. }
  2469. return flush_count;
  2470. }
  2471. /*
  2472. * Called to flush a packing buffer if no more pci flags are on the queue.
  2473. * Checks if there is a packing buffer and prepares it to be flushed.
  2474. * In that case returns 1, otherwise zero.
  2475. */
  2476. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2477. {
  2478. struct qeth_qdio_out_buffer *buffer;
  2479. buffer = &queue->bufs[queue->next_buf_to_fill];
  2480. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2481. (buffer->next_element_to_fill > 0)) {
  2482. /* it's a packing buffer */
  2483. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2484. queue->next_buf_to_fill =
  2485. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2486. return 1;
  2487. }
  2488. return 0;
  2489. }
  2490. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2491. int count)
  2492. {
  2493. struct qeth_qdio_out_buffer *buf;
  2494. int rc;
  2495. int i;
  2496. unsigned int qdio_flags;
  2497. for (i = index; i < index + count; ++i) {
  2498. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2499. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2500. SBAL_FLAGS_LAST_ENTRY;
  2501. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2502. continue;
  2503. if (!queue->do_pack) {
  2504. if ((atomic_read(&queue->used_buffers) >=
  2505. (QETH_HIGH_WATERMARK_PACK -
  2506. QETH_WATERMARK_PACK_FUZZ)) &&
  2507. !atomic_read(&queue->set_pci_flags_count)) {
  2508. /* it's likely that we'll go to packing
  2509. * mode soon */
  2510. atomic_inc(&queue->set_pci_flags_count);
  2511. buf->buffer->element[0].flags |= 0x40;
  2512. }
  2513. } else {
  2514. if (!atomic_read(&queue->set_pci_flags_count)) {
  2515. /*
  2516. * there's no outstanding PCI any more, so we
  2517. * have to request a PCI to be sure the the PCI
  2518. * will wake at some time in the future then we
  2519. * can flush packed buffers that might still be
  2520. * hanging around, which can happen if no
  2521. * further send was requested by the stack
  2522. */
  2523. atomic_inc(&queue->set_pci_flags_count);
  2524. buf->buffer->element[0].flags |= 0x40;
  2525. }
  2526. }
  2527. }
  2528. queue->card->dev->trans_start = jiffies;
  2529. if (queue->card->options.performance_stats) {
  2530. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2531. queue->card->perf_stats.outbound_do_qdio_start_time =
  2532. qeth_get_micros();
  2533. }
  2534. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2535. if (atomic_read(&queue->set_pci_flags_count))
  2536. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2537. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2538. queue->queue_no, index, count);
  2539. if (queue->card->options.performance_stats)
  2540. queue->card->perf_stats.outbound_do_qdio_time +=
  2541. qeth_get_micros() -
  2542. queue->card->perf_stats.outbound_do_qdio_start_time;
  2543. if (rc) {
  2544. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2545. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2546. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2547. queue->card->stats.tx_errors += count;
  2548. /* this must not happen under normal circumstances. if it
  2549. * happens something is really wrong -> recover */
  2550. qeth_schedule_recovery(queue->card);
  2551. return;
  2552. }
  2553. atomic_add(count, &queue->used_buffers);
  2554. if (queue->card->options.performance_stats)
  2555. queue->card->perf_stats.bufs_sent += count;
  2556. }
  2557. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2558. {
  2559. int index;
  2560. int flush_cnt = 0;
  2561. int q_was_packing = 0;
  2562. /*
  2563. * check if weed have to switch to non-packing mode or if
  2564. * we have to get a pci flag out on the queue
  2565. */
  2566. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2567. !atomic_read(&queue->set_pci_flags_count)) {
  2568. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2569. QETH_OUT_Q_UNLOCKED) {
  2570. /*
  2571. * If we get in here, there was no action in
  2572. * do_send_packet. So, we check if there is a
  2573. * packing buffer to be flushed here.
  2574. */
  2575. netif_stop_queue(queue->card->dev);
  2576. index = queue->next_buf_to_fill;
  2577. q_was_packing = queue->do_pack;
  2578. /* queue->do_pack may change */
  2579. barrier();
  2580. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2581. if (!flush_cnt &&
  2582. !atomic_read(&queue->set_pci_flags_count))
  2583. flush_cnt +=
  2584. qeth_flush_buffers_on_no_pci(queue);
  2585. if (queue->card->options.performance_stats &&
  2586. q_was_packing)
  2587. queue->card->perf_stats.bufs_sent_pack +=
  2588. flush_cnt;
  2589. if (flush_cnt)
  2590. qeth_flush_buffers(queue, index, flush_cnt);
  2591. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2592. }
  2593. }
  2594. }
  2595. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2596. unsigned int qdio_error, int __queue, int first_element,
  2597. int count, unsigned long card_ptr)
  2598. {
  2599. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2600. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2601. struct qeth_qdio_out_buffer *buffer;
  2602. int i;
  2603. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2604. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2605. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2606. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2607. netif_stop_queue(card->dev);
  2608. qeth_schedule_recovery(card);
  2609. return;
  2610. }
  2611. if (card->options.performance_stats) {
  2612. card->perf_stats.outbound_handler_cnt++;
  2613. card->perf_stats.outbound_handler_start_time =
  2614. qeth_get_micros();
  2615. }
  2616. for (i = first_element; i < (first_element + count); ++i) {
  2617. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2618. /*we only handle the KICK_IT error by doing a recovery */
  2619. if (qeth_handle_send_error(card, buffer, qdio_error)
  2620. == QETH_SEND_ERROR_KICK_IT){
  2621. netif_stop_queue(card->dev);
  2622. qeth_schedule_recovery(card);
  2623. return;
  2624. }
  2625. qeth_clear_output_buffer(queue, buffer);
  2626. }
  2627. atomic_sub(count, &queue->used_buffers);
  2628. /* check if we need to do something on this outbound queue */
  2629. if (card->info.type != QETH_CARD_TYPE_IQD)
  2630. qeth_check_outbound_queue(queue);
  2631. netif_wake_queue(queue->card->dev);
  2632. if (card->options.performance_stats)
  2633. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2634. card->perf_stats.outbound_handler_start_time;
  2635. }
  2636. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2637. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2638. {
  2639. int cast_type = RTN_UNSPEC;
  2640. if (card->info.type == QETH_CARD_TYPE_OSN)
  2641. return cast_type;
  2642. if (skb->dst && skb->dst->neighbour) {
  2643. cast_type = skb->dst->neighbour->type;
  2644. if ((cast_type == RTN_BROADCAST) ||
  2645. (cast_type == RTN_MULTICAST) ||
  2646. (cast_type == RTN_ANYCAST))
  2647. return cast_type;
  2648. else
  2649. return RTN_UNSPEC;
  2650. }
  2651. /* try something else */
  2652. if (skb->protocol == ETH_P_IPV6)
  2653. return (skb_network_header(skb)[24] == 0xff) ?
  2654. RTN_MULTICAST : 0;
  2655. else if (skb->protocol == ETH_P_IP)
  2656. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2657. RTN_MULTICAST : 0;
  2658. /* ... */
  2659. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2660. return RTN_BROADCAST;
  2661. else {
  2662. u16 hdr_mac;
  2663. hdr_mac = *((u16 *)skb->data);
  2664. /* tr multicast? */
  2665. switch (card->info.link_type) {
  2666. case QETH_LINK_TYPE_HSTR:
  2667. case QETH_LINK_TYPE_LANE_TR:
  2668. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2669. (hdr_mac == QETH_TR_MAC_C))
  2670. return RTN_MULTICAST;
  2671. break;
  2672. /* eth or so multicast? */
  2673. default:
  2674. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2675. (hdr_mac == QETH_ETH_MAC_V6))
  2676. return RTN_MULTICAST;
  2677. }
  2678. }
  2679. return cast_type;
  2680. }
  2681. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2682. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2683. int ipv, int cast_type)
  2684. {
  2685. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2686. return card->qdio.default_out_queue;
  2687. switch (card->qdio.no_out_queues) {
  2688. case 4:
  2689. if (cast_type && card->info.is_multicast_different)
  2690. return card->info.is_multicast_different &
  2691. (card->qdio.no_out_queues - 1);
  2692. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2693. const u8 tos = ip_hdr(skb)->tos;
  2694. if (card->qdio.do_prio_queueing ==
  2695. QETH_PRIO_Q_ING_TOS) {
  2696. if (tos & IP_TOS_NOTIMPORTANT)
  2697. return 3;
  2698. if (tos & IP_TOS_HIGHRELIABILITY)
  2699. return 2;
  2700. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2701. return 1;
  2702. if (tos & IP_TOS_LOWDELAY)
  2703. return 0;
  2704. }
  2705. if (card->qdio.do_prio_queueing ==
  2706. QETH_PRIO_Q_ING_PREC)
  2707. return 3 - (tos >> 6);
  2708. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2709. /* TODO: IPv6!!! */
  2710. }
  2711. return card->qdio.default_out_queue;
  2712. case 1: /* fallthrough for single-out-queue 1920-device */
  2713. default:
  2714. return card->qdio.default_out_queue;
  2715. }
  2716. }
  2717. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2718. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2719. struct sk_buff *skb, int elems)
  2720. {
  2721. int elements_needed = 0;
  2722. if (skb_shinfo(skb)->nr_frags > 0)
  2723. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2724. if (elements_needed == 0)
  2725. elements_needed = 1 + (((((unsigned long) skb->data) %
  2726. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2727. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2728. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2729. "(Number=%d / Length=%d). Discarded.\n",
  2730. (elements_needed+elems), skb->len);
  2731. return 0;
  2732. }
  2733. return elements_needed;
  2734. }
  2735. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2736. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2737. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2738. int offset)
  2739. {
  2740. int length = skb->len;
  2741. int length_here;
  2742. int element;
  2743. char *data;
  2744. int first_lap ;
  2745. element = *next_element_to_fill;
  2746. data = skb->data;
  2747. first_lap = (is_tso == 0 ? 1 : 0);
  2748. if (offset >= 0) {
  2749. data = skb->data + offset;
  2750. length -= offset;
  2751. first_lap = 0;
  2752. }
  2753. while (length > 0) {
  2754. /* length_here is the remaining amount of data in this page */
  2755. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2756. if (length < length_here)
  2757. length_here = length;
  2758. buffer->element[element].addr = data;
  2759. buffer->element[element].length = length_here;
  2760. length -= length_here;
  2761. if (!length) {
  2762. if (first_lap)
  2763. buffer->element[element].flags = 0;
  2764. else
  2765. buffer->element[element].flags =
  2766. SBAL_FLAGS_LAST_FRAG;
  2767. } else {
  2768. if (first_lap)
  2769. buffer->element[element].flags =
  2770. SBAL_FLAGS_FIRST_FRAG;
  2771. else
  2772. buffer->element[element].flags =
  2773. SBAL_FLAGS_MIDDLE_FRAG;
  2774. }
  2775. data += length_here;
  2776. element++;
  2777. first_lap = 0;
  2778. }
  2779. *next_element_to_fill = element;
  2780. }
  2781. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2782. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2783. struct qeth_hdr *hdr, int offset, int hd_len)
  2784. {
  2785. struct qdio_buffer *buffer;
  2786. int flush_cnt = 0, hdr_len, large_send = 0;
  2787. buffer = buf->buffer;
  2788. atomic_inc(&skb->users);
  2789. skb_queue_tail(&buf->skb_list, skb);
  2790. /*check first on TSO ....*/
  2791. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2792. int element = buf->next_element_to_fill;
  2793. hdr_len = sizeof(struct qeth_hdr_tso) +
  2794. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2795. /*fill first buffer entry only with header information */
  2796. buffer->element[element].addr = skb->data;
  2797. buffer->element[element].length = hdr_len;
  2798. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2799. buf->next_element_to_fill++;
  2800. skb->data += hdr_len;
  2801. skb->len -= hdr_len;
  2802. large_send = 1;
  2803. }
  2804. if (offset >= 0) {
  2805. int element = buf->next_element_to_fill;
  2806. buffer->element[element].addr = hdr;
  2807. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2808. hd_len;
  2809. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2810. buf->is_header[element] = 1;
  2811. buf->next_element_to_fill++;
  2812. }
  2813. if (skb_shinfo(skb)->nr_frags == 0)
  2814. __qeth_fill_buffer(skb, buffer, large_send,
  2815. (int *)&buf->next_element_to_fill, offset);
  2816. else
  2817. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2818. (int *)&buf->next_element_to_fill);
  2819. if (!queue->do_pack) {
  2820. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2821. /* set state to PRIMED -> will be flushed */
  2822. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2823. flush_cnt = 1;
  2824. } else {
  2825. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2826. if (queue->card->options.performance_stats)
  2827. queue->card->perf_stats.skbs_sent_pack++;
  2828. if (buf->next_element_to_fill >=
  2829. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2830. /*
  2831. * packed buffer if full -> set state PRIMED
  2832. * -> will be flushed
  2833. */
  2834. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2835. flush_cnt = 1;
  2836. }
  2837. }
  2838. return flush_cnt;
  2839. }
  2840. int qeth_do_send_packet_fast(struct qeth_card *card,
  2841. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2842. struct qeth_hdr *hdr, int elements_needed,
  2843. struct qeth_eddp_context *ctx, int offset, int hd_len)
  2844. {
  2845. struct qeth_qdio_out_buffer *buffer;
  2846. int buffers_needed = 0;
  2847. int flush_cnt = 0;
  2848. int index;
  2849. /* spin until we get the queue ... */
  2850. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2851. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2852. /* ... now we've got the queue */
  2853. index = queue->next_buf_to_fill;
  2854. buffer = &queue->bufs[queue->next_buf_to_fill];
  2855. /*
  2856. * check if buffer is empty to make sure that we do not 'overtake'
  2857. * ourselves and try to fill a buffer that is already primed
  2858. */
  2859. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2860. goto out;
  2861. if (ctx == NULL)
  2862. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2863. QDIO_MAX_BUFFERS_PER_Q;
  2864. else {
  2865. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2866. ctx);
  2867. if (buffers_needed < 0)
  2868. goto out;
  2869. queue->next_buf_to_fill =
  2870. (queue->next_buf_to_fill + buffers_needed) %
  2871. QDIO_MAX_BUFFERS_PER_Q;
  2872. }
  2873. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2874. if (ctx == NULL) {
  2875. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2876. qeth_flush_buffers(queue, index, 1);
  2877. } else {
  2878. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2879. WARN_ON(buffers_needed != flush_cnt);
  2880. qeth_flush_buffers(queue, index, flush_cnt);
  2881. }
  2882. return 0;
  2883. out:
  2884. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2885. return -EBUSY;
  2886. }
  2887. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2888. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2889. struct sk_buff *skb, struct qeth_hdr *hdr,
  2890. int elements_needed, struct qeth_eddp_context *ctx)
  2891. {
  2892. struct qeth_qdio_out_buffer *buffer;
  2893. int start_index;
  2894. int flush_count = 0;
  2895. int do_pack = 0;
  2896. int tmp;
  2897. int rc = 0;
  2898. /* spin until we get the queue ... */
  2899. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2900. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2901. start_index = queue->next_buf_to_fill;
  2902. buffer = &queue->bufs[queue->next_buf_to_fill];
  2903. /*
  2904. * check if buffer is empty to make sure that we do not 'overtake'
  2905. * ourselves and try to fill a buffer that is already primed
  2906. */
  2907. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2908. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2909. return -EBUSY;
  2910. }
  2911. /* check if we need to switch packing state of this queue */
  2912. qeth_switch_to_packing_if_needed(queue);
  2913. if (queue->do_pack) {
  2914. do_pack = 1;
  2915. if (ctx == NULL) {
  2916. /* does packet fit in current buffer? */
  2917. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2918. buffer->next_element_to_fill) < elements_needed) {
  2919. /* ... no -> set state PRIMED */
  2920. atomic_set(&buffer->state,
  2921. QETH_QDIO_BUF_PRIMED);
  2922. flush_count++;
  2923. queue->next_buf_to_fill =
  2924. (queue->next_buf_to_fill + 1) %
  2925. QDIO_MAX_BUFFERS_PER_Q;
  2926. buffer = &queue->bufs[queue->next_buf_to_fill];
  2927. /* we did a step forward, so check buffer state
  2928. * again */
  2929. if (atomic_read(&buffer->state) !=
  2930. QETH_QDIO_BUF_EMPTY){
  2931. qeth_flush_buffers(queue, start_index,
  2932. flush_count);
  2933. atomic_set(&queue->state,
  2934. QETH_OUT_Q_UNLOCKED);
  2935. return -EBUSY;
  2936. }
  2937. }
  2938. } else {
  2939. /* check if we have enough elements (including following
  2940. * free buffers) to handle eddp context */
  2941. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2942. < 0) {
  2943. rc = -EBUSY;
  2944. goto out;
  2945. }
  2946. }
  2947. }
  2948. if (ctx == NULL)
  2949. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2950. else {
  2951. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2952. queue->next_buf_to_fill);
  2953. if (tmp < 0) {
  2954. rc = -EBUSY;
  2955. goto out;
  2956. }
  2957. }
  2958. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2959. QDIO_MAX_BUFFERS_PER_Q;
  2960. flush_count += tmp;
  2961. out:
  2962. if (flush_count)
  2963. qeth_flush_buffers(queue, start_index, flush_count);
  2964. else if (!atomic_read(&queue->set_pci_flags_count))
  2965. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2966. /*
  2967. * queue->state will go from LOCKED -> UNLOCKED or from
  2968. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2969. * (switch packing state or flush buffer to get another pci flag out).
  2970. * In that case we will enter this loop
  2971. */
  2972. while (atomic_dec_return(&queue->state)) {
  2973. flush_count = 0;
  2974. start_index = queue->next_buf_to_fill;
  2975. /* check if we can go back to non-packing state */
  2976. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2977. /*
  2978. * check if we need to flush a packing buffer to get a pci
  2979. * flag out on the queue
  2980. */
  2981. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2982. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2983. if (flush_count)
  2984. qeth_flush_buffers(queue, start_index, flush_count);
  2985. }
  2986. /* at this point the queue is UNLOCKED again */
  2987. if (queue->card->options.performance_stats && do_pack)
  2988. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2989. return rc;
  2990. }
  2991. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2992. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2993. struct qeth_reply *reply, unsigned long data)
  2994. {
  2995. struct qeth_ipa_cmd *cmd;
  2996. struct qeth_ipacmd_setadpparms *setparms;
  2997. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2998. cmd = (struct qeth_ipa_cmd *) data;
  2999. setparms = &(cmd->data.setadapterparms);
  3000. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3001. if (cmd->hdr.return_code) {
  3002. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3003. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3004. }
  3005. card->info.promisc_mode = setparms->data.mode;
  3006. return 0;
  3007. }
  3008. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3009. {
  3010. enum qeth_ipa_promisc_modes mode;
  3011. struct net_device *dev = card->dev;
  3012. struct qeth_cmd_buffer *iob;
  3013. struct qeth_ipa_cmd *cmd;
  3014. QETH_DBF_TEXT(TRACE, 4, "setprom");
  3015. if (((dev->flags & IFF_PROMISC) &&
  3016. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3017. (!(dev->flags & IFF_PROMISC) &&
  3018. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3019. return;
  3020. mode = SET_PROMISC_MODE_OFF;
  3021. if (dev->flags & IFF_PROMISC)
  3022. mode = SET_PROMISC_MODE_ON;
  3023. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  3024. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3025. sizeof(struct qeth_ipacmd_setadpparms));
  3026. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3027. cmd->data.setadapterparms.data.mode = mode;
  3028. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3029. }
  3030. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3031. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3032. {
  3033. struct qeth_card *card;
  3034. char dbf_text[15];
  3035. card = dev->ml_priv;
  3036. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3037. sprintf(dbf_text, "%8x", new_mtu);
  3038. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3039. if (new_mtu < 64)
  3040. return -EINVAL;
  3041. if (new_mtu > 65535)
  3042. return -EINVAL;
  3043. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3044. (!qeth_mtu_is_valid(card, new_mtu)))
  3045. return -EINVAL;
  3046. dev->mtu = new_mtu;
  3047. return 0;
  3048. }
  3049. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3050. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3051. {
  3052. struct qeth_card *card;
  3053. card = dev->ml_priv;
  3054. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3055. return &card->stats;
  3056. }
  3057. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3058. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3059. struct qeth_reply *reply, unsigned long data)
  3060. {
  3061. struct qeth_ipa_cmd *cmd;
  3062. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3063. cmd = (struct qeth_ipa_cmd *) data;
  3064. if (!card->options.layer2 ||
  3065. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3066. memcpy(card->dev->dev_addr,
  3067. &cmd->data.setadapterparms.data.change_addr.addr,
  3068. OSA_ADDR_LEN);
  3069. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3070. }
  3071. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3072. return 0;
  3073. }
  3074. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3075. {
  3076. int rc;
  3077. struct qeth_cmd_buffer *iob;
  3078. struct qeth_ipa_cmd *cmd;
  3079. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3080. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3081. sizeof(struct qeth_ipacmd_setadpparms));
  3082. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3083. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3084. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3085. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3086. card->dev->dev_addr, OSA_ADDR_LEN);
  3087. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3088. NULL);
  3089. return rc;
  3090. }
  3091. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3092. void qeth_tx_timeout(struct net_device *dev)
  3093. {
  3094. struct qeth_card *card;
  3095. card = dev->ml_priv;
  3096. card->stats.tx_errors++;
  3097. qeth_schedule_recovery(card);
  3098. }
  3099. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3100. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3101. {
  3102. struct qeth_card *card = dev->ml_priv;
  3103. int rc = 0;
  3104. switch (regnum) {
  3105. case MII_BMCR: /* Basic mode control register */
  3106. rc = BMCR_FULLDPLX;
  3107. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3108. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3109. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3110. rc |= BMCR_SPEED100;
  3111. break;
  3112. case MII_BMSR: /* Basic mode status register */
  3113. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3114. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3115. BMSR_100BASE4;
  3116. break;
  3117. case MII_PHYSID1: /* PHYS ID 1 */
  3118. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3119. dev->dev_addr[2];
  3120. rc = (rc >> 5) & 0xFFFF;
  3121. break;
  3122. case MII_PHYSID2: /* PHYS ID 2 */
  3123. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3124. break;
  3125. case MII_ADVERTISE: /* Advertisement control reg */
  3126. rc = ADVERTISE_ALL;
  3127. break;
  3128. case MII_LPA: /* Link partner ability reg */
  3129. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3130. LPA_100BASE4 | LPA_LPACK;
  3131. break;
  3132. case MII_EXPANSION: /* Expansion register */
  3133. break;
  3134. case MII_DCOUNTER: /* disconnect counter */
  3135. break;
  3136. case MII_FCSCOUNTER: /* false carrier counter */
  3137. break;
  3138. case MII_NWAYTEST: /* N-way auto-neg test register */
  3139. break;
  3140. case MII_RERRCOUNTER: /* rx error counter */
  3141. rc = card->stats.rx_errors;
  3142. break;
  3143. case MII_SREVISION: /* silicon revision */
  3144. break;
  3145. case MII_RESV1: /* reserved 1 */
  3146. break;
  3147. case MII_LBRERROR: /* loopback, rx, bypass error */
  3148. break;
  3149. case MII_PHYADDR: /* physical address */
  3150. break;
  3151. case MII_RESV2: /* reserved 2 */
  3152. break;
  3153. case MII_TPISTATUS: /* TPI status for 10mbps */
  3154. break;
  3155. case MII_NCONFIG: /* network interface config */
  3156. break;
  3157. default:
  3158. break;
  3159. }
  3160. return rc;
  3161. }
  3162. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3163. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3164. struct qeth_cmd_buffer *iob, int len,
  3165. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3166. unsigned long),
  3167. void *reply_param)
  3168. {
  3169. u16 s1, s2;
  3170. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3171. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3172. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3173. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3174. /* adjust PDU length fields in IPA_PDU_HEADER */
  3175. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3176. s2 = (u32) len;
  3177. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3178. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3179. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3180. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3181. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3182. reply_cb, reply_param);
  3183. }
  3184. static int qeth_snmp_command_cb(struct qeth_card *card,
  3185. struct qeth_reply *reply, unsigned long sdata)
  3186. {
  3187. struct qeth_ipa_cmd *cmd;
  3188. struct qeth_arp_query_info *qinfo;
  3189. struct qeth_snmp_cmd *snmp;
  3190. unsigned char *data;
  3191. __u16 data_len;
  3192. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3193. cmd = (struct qeth_ipa_cmd *) sdata;
  3194. data = (unsigned char *)((char *)cmd - reply->offset);
  3195. qinfo = (struct qeth_arp_query_info *) reply->param;
  3196. snmp = &cmd->data.setadapterparms.data.snmp;
  3197. if (cmd->hdr.return_code) {
  3198. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3199. return 0;
  3200. }
  3201. if (cmd->data.setadapterparms.hdr.return_code) {
  3202. cmd->hdr.return_code =
  3203. cmd->data.setadapterparms.hdr.return_code;
  3204. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3205. return 0;
  3206. }
  3207. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3208. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3209. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3210. else
  3211. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3212. /* check if there is enough room in userspace */
  3213. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3214. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3215. cmd->hdr.return_code = -ENOMEM;
  3216. return 0;
  3217. }
  3218. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3219. cmd->data.setadapterparms.hdr.used_total);
  3220. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3221. cmd->data.setadapterparms.hdr.seq_no);
  3222. /*copy entries to user buffer*/
  3223. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3224. memcpy(qinfo->udata + qinfo->udata_offset,
  3225. (char *)snmp,
  3226. data_len + offsetof(struct qeth_snmp_cmd, data));
  3227. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3228. } else {
  3229. memcpy(qinfo->udata + qinfo->udata_offset,
  3230. (char *)&snmp->request, data_len);
  3231. }
  3232. qinfo->udata_offset += data_len;
  3233. /* check if all replies received ... */
  3234. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3235. cmd->data.setadapterparms.hdr.used_total);
  3236. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3237. cmd->data.setadapterparms.hdr.seq_no);
  3238. if (cmd->data.setadapterparms.hdr.seq_no <
  3239. cmd->data.setadapterparms.hdr.used_total)
  3240. return 1;
  3241. return 0;
  3242. }
  3243. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3244. {
  3245. struct qeth_cmd_buffer *iob;
  3246. struct qeth_ipa_cmd *cmd;
  3247. struct qeth_snmp_ureq *ureq;
  3248. int req_len;
  3249. struct qeth_arp_query_info qinfo = {0, };
  3250. int rc = 0;
  3251. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3252. if (card->info.guestlan)
  3253. return -EOPNOTSUPP;
  3254. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3255. (!card->options.layer2)) {
  3256. return -EOPNOTSUPP;
  3257. }
  3258. /* skip 4 bytes (data_len struct member) to get req_len */
  3259. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3260. return -EFAULT;
  3261. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3262. if (!ureq) {
  3263. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3264. return -ENOMEM;
  3265. }
  3266. if (copy_from_user(ureq, udata,
  3267. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3268. kfree(ureq);
  3269. return -EFAULT;
  3270. }
  3271. qinfo.udata_len = ureq->hdr.data_len;
  3272. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3273. if (!qinfo.udata) {
  3274. kfree(ureq);
  3275. return -ENOMEM;
  3276. }
  3277. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3278. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3279. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3280. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3281. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3282. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3283. qeth_snmp_command_cb, (void *)&qinfo);
  3284. if (rc)
  3285. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3286. QETH_CARD_IFNAME(card), rc);
  3287. else {
  3288. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3289. rc = -EFAULT;
  3290. }
  3291. kfree(ureq);
  3292. kfree(qinfo.udata);
  3293. return rc;
  3294. }
  3295. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3296. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3297. {
  3298. switch (card->info.type) {
  3299. case QETH_CARD_TYPE_IQD:
  3300. return 2;
  3301. default:
  3302. return 0;
  3303. }
  3304. }
  3305. static int qeth_qdio_establish(struct qeth_card *card)
  3306. {
  3307. struct qdio_initialize init_data;
  3308. char *qib_param_field;
  3309. struct qdio_buffer **in_sbal_ptrs;
  3310. struct qdio_buffer **out_sbal_ptrs;
  3311. int i, j, k;
  3312. int rc = 0;
  3313. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3314. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3315. GFP_KERNEL);
  3316. if (!qib_param_field)
  3317. return -ENOMEM;
  3318. qeth_create_qib_param_field(card, qib_param_field);
  3319. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3320. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3321. GFP_KERNEL);
  3322. if (!in_sbal_ptrs) {
  3323. kfree(qib_param_field);
  3324. return -ENOMEM;
  3325. }
  3326. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3327. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3328. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3329. out_sbal_ptrs =
  3330. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3331. sizeof(void *), GFP_KERNEL);
  3332. if (!out_sbal_ptrs) {
  3333. kfree(in_sbal_ptrs);
  3334. kfree(qib_param_field);
  3335. return -ENOMEM;
  3336. }
  3337. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3338. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3339. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3340. card->qdio.out_qs[i]->bufs[j].buffer);
  3341. }
  3342. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3343. init_data.cdev = CARD_DDEV(card);
  3344. init_data.q_format = qeth_get_qdio_q_format(card);
  3345. init_data.qib_param_field_format = 0;
  3346. init_data.qib_param_field = qib_param_field;
  3347. init_data.no_input_qs = 1;
  3348. init_data.no_output_qs = card->qdio.no_out_queues;
  3349. init_data.input_handler = card->discipline.input_handler;
  3350. init_data.output_handler = card->discipline.output_handler;
  3351. init_data.int_parm = (unsigned long) card;
  3352. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3353. QDIO_OUTBOUND_0COPY_SBALS |
  3354. QDIO_USE_OUTBOUND_PCIS;
  3355. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3356. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3357. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3358. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3359. rc = qdio_initialize(&init_data);
  3360. if (rc)
  3361. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3362. }
  3363. kfree(out_sbal_ptrs);
  3364. kfree(in_sbal_ptrs);
  3365. kfree(qib_param_field);
  3366. return rc;
  3367. }
  3368. static void qeth_core_free_card(struct qeth_card *card)
  3369. {
  3370. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3371. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3372. qeth_clean_channel(&card->read);
  3373. qeth_clean_channel(&card->write);
  3374. if (card->dev)
  3375. free_netdev(card->dev);
  3376. kfree(card->ip_tbd_list);
  3377. qeth_free_qdio_buffers(card);
  3378. unregister_service_level(&card->qeth_service_level);
  3379. kfree(card);
  3380. }
  3381. static struct ccw_device_id qeth_ids[] = {
  3382. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3383. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3384. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3385. {},
  3386. };
  3387. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3388. static struct ccw_driver qeth_ccw_driver = {
  3389. .name = "qeth",
  3390. .ids = qeth_ids,
  3391. .probe = ccwgroup_probe_ccwdev,
  3392. .remove = ccwgroup_remove_ccwdev,
  3393. };
  3394. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3395. unsigned long driver_id)
  3396. {
  3397. return ccwgroup_create_from_string(root_dev, driver_id,
  3398. &qeth_ccw_driver, 3, buf);
  3399. }
  3400. int qeth_core_hardsetup_card(struct qeth_card *card)
  3401. {
  3402. struct qdio_ssqd_desc *ssqd;
  3403. int retries = 3;
  3404. int mpno = 0;
  3405. int rc;
  3406. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3407. atomic_set(&card->force_alloc_skb, 0);
  3408. retry:
  3409. if (retries < 3) {
  3410. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3411. dev_name(&card->gdev->dev));
  3412. ccw_device_set_offline(CARD_DDEV(card));
  3413. ccw_device_set_offline(CARD_WDEV(card));
  3414. ccw_device_set_offline(CARD_RDEV(card));
  3415. ccw_device_set_online(CARD_RDEV(card));
  3416. ccw_device_set_online(CARD_WDEV(card));
  3417. ccw_device_set_online(CARD_DDEV(card));
  3418. }
  3419. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3420. if (rc == -ERESTARTSYS) {
  3421. QETH_DBF_TEXT(SETUP, 2, "break1");
  3422. return rc;
  3423. } else if (rc) {
  3424. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3425. if (--retries < 0)
  3426. goto out;
  3427. else
  3428. goto retry;
  3429. }
  3430. rc = qeth_get_unitaddr(card);
  3431. if (rc) {
  3432. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3433. return rc;
  3434. }
  3435. ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
  3436. if (!ssqd) {
  3437. rc = -ENOMEM;
  3438. goto out;
  3439. }
  3440. rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
  3441. if (rc == 0)
  3442. mpno = ssqd->pcnt;
  3443. kfree(ssqd);
  3444. if (mpno)
  3445. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3446. if (card->info.portno > mpno) {
  3447. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3448. "\n.", CARD_BUS_ID(card), card->info.portno);
  3449. rc = -ENODEV;
  3450. goto out;
  3451. }
  3452. qeth_init_tokens(card);
  3453. qeth_init_func_level(card);
  3454. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3455. if (rc == -ERESTARTSYS) {
  3456. QETH_DBF_TEXT(SETUP, 2, "break2");
  3457. return rc;
  3458. } else if (rc) {
  3459. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3460. if (--retries < 0)
  3461. goto out;
  3462. else
  3463. goto retry;
  3464. }
  3465. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3466. if (rc == -ERESTARTSYS) {
  3467. QETH_DBF_TEXT(SETUP, 2, "break3");
  3468. return rc;
  3469. } else if (rc) {
  3470. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3471. if (--retries < 0)
  3472. goto out;
  3473. else
  3474. goto retry;
  3475. }
  3476. rc = qeth_mpc_initialize(card);
  3477. if (rc) {
  3478. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3479. goto out;
  3480. }
  3481. return 0;
  3482. out:
  3483. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3484. "an error on the device\n");
  3485. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3486. dev_name(&card->gdev->dev), rc);
  3487. return rc;
  3488. }
  3489. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3490. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3491. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3492. {
  3493. struct page *page = virt_to_page(element->addr);
  3494. if (*pskb == NULL) {
  3495. /* the upper protocol layers assume that there is data in the
  3496. * skb itself. Copy a small amount (64 bytes) to make them
  3497. * happy. */
  3498. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3499. if (!(*pskb))
  3500. return -ENOMEM;
  3501. skb_reserve(*pskb, ETH_HLEN);
  3502. if (data_len <= 64) {
  3503. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3504. data_len);
  3505. } else {
  3506. get_page(page);
  3507. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3508. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3509. data_len - 64);
  3510. (*pskb)->data_len += data_len - 64;
  3511. (*pskb)->len += data_len - 64;
  3512. (*pskb)->truesize += data_len - 64;
  3513. (*pfrag)++;
  3514. }
  3515. } else {
  3516. get_page(page);
  3517. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3518. (*pskb)->data_len += data_len;
  3519. (*pskb)->len += data_len;
  3520. (*pskb)->truesize += data_len;
  3521. (*pfrag)++;
  3522. }
  3523. return 0;
  3524. }
  3525. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3526. struct qdio_buffer *buffer,
  3527. struct qdio_buffer_element **__element, int *__offset,
  3528. struct qeth_hdr **hdr)
  3529. {
  3530. struct qdio_buffer_element *element = *__element;
  3531. int offset = *__offset;
  3532. struct sk_buff *skb = NULL;
  3533. int skb_len;
  3534. void *data_ptr;
  3535. int data_len;
  3536. int headroom = 0;
  3537. int use_rx_sg = 0;
  3538. int frag = 0;
  3539. /* qeth_hdr must not cross element boundaries */
  3540. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3541. if (qeth_is_last_sbale(element))
  3542. return NULL;
  3543. element++;
  3544. offset = 0;
  3545. if (element->length < sizeof(struct qeth_hdr))
  3546. return NULL;
  3547. }
  3548. *hdr = element->addr + offset;
  3549. offset += sizeof(struct qeth_hdr);
  3550. if (card->options.layer2) {
  3551. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3552. skb_len = (*hdr)->hdr.osn.pdu_length;
  3553. headroom = sizeof(struct qeth_hdr);
  3554. } else {
  3555. skb_len = (*hdr)->hdr.l2.pkt_length;
  3556. }
  3557. } else {
  3558. skb_len = (*hdr)->hdr.l3.length;
  3559. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3560. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3561. headroom = TR_HLEN;
  3562. else
  3563. headroom = ETH_HLEN;
  3564. }
  3565. if (!skb_len)
  3566. return NULL;
  3567. if ((skb_len >= card->options.rx_sg_cb) &&
  3568. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3569. (!atomic_read(&card->force_alloc_skb))) {
  3570. use_rx_sg = 1;
  3571. } else {
  3572. skb = dev_alloc_skb(skb_len + headroom);
  3573. if (!skb)
  3574. goto no_mem;
  3575. if (headroom)
  3576. skb_reserve(skb, headroom);
  3577. }
  3578. data_ptr = element->addr + offset;
  3579. while (skb_len) {
  3580. data_len = min(skb_len, (int)(element->length - offset));
  3581. if (data_len) {
  3582. if (use_rx_sg) {
  3583. if (qeth_create_skb_frag(element, &skb, offset,
  3584. &frag, data_len))
  3585. goto no_mem;
  3586. } else {
  3587. memcpy(skb_put(skb, data_len), data_ptr,
  3588. data_len);
  3589. }
  3590. }
  3591. skb_len -= data_len;
  3592. if (skb_len) {
  3593. if (qeth_is_last_sbale(element)) {
  3594. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3595. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3596. CARD_BUS_ID(card));
  3597. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3598. QETH_DBF_TEXT_(QERR, 2, "%s",
  3599. CARD_BUS_ID(card));
  3600. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3601. dev_kfree_skb_any(skb);
  3602. card->stats.rx_errors++;
  3603. return NULL;
  3604. }
  3605. element++;
  3606. offset = 0;
  3607. data_ptr = element->addr;
  3608. } else {
  3609. offset += data_len;
  3610. }
  3611. }
  3612. *__element = element;
  3613. *__offset = offset;
  3614. if (use_rx_sg && card->options.performance_stats) {
  3615. card->perf_stats.sg_skbs_rx++;
  3616. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3617. }
  3618. return skb;
  3619. no_mem:
  3620. if (net_ratelimit()) {
  3621. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3622. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3623. }
  3624. card->stats.rx_dropped++;
  3625. return NULL;
  3626. }
  3627. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3628. static void qeth_unregister_dbf_views(void)
  3629. {
  3630. int x;
  3631. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3632. debug_unregister(qeth_dbf[x].id);
  3633. qeth_dbf[x].id = NULL;
  3634. }
  3635. }
  3636. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3637. {
  3638. char dbf_txt_buf[32];
  3639. va_list args;
  3640. if (level > (qeth_dbf[dbf_nix].id)->level)
  3641. return;
  3642. va_start(args, fmt);
  3643. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3644. va_end(args);
  3645. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3646. }
  3647. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3648. static int qeth_register_dbf_views(void)
  3649. {
  3650. int ret;
  3651. int x;
  3652. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3653. /* register the areas */
  3654. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3655. qeth_dbf[x].pages,
  3656. qeth_dbf[x].areas,
  3657. qeth_dbf[x].len);
  3658. if (qeth_dbf[x].id == NULL) {
  3659. qeth_unregister_dbf_views();
  3660. return -ENOMEM;
  3661. }
  3662. /* register a view */
  3663. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3664. if (ret) {
  3665. qeth_unregister_dbf_views();
  3666. return ret;
  3667. }
  3668. /* set a passing level */
  3669. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3670. }
  3671. return 0;
  3672. }
  3673. int qeth_core_load_discipline(struct qeth_card *card,
  3674. enum qeth_discipline_id discipline)
  3675. {
  3676. int rc = 0;
  3677. switch (discipline) {
  3678. case QETH_DISCIPLINE_LAYER3:
  3679. card->discipline.ccwgdriver = try_then_request_module(
  3680. symbol_get(qeth_l3_ccwgroup_driver),
  3681. "qeth_l3");
  3682. break;
  3683. case QETH_DISCIPLINE_LAYER2:
  3684. card->discipline.ccwgdriver = try_then_request_module(
  3685. symbol_get(qeth_l2_ccwgroup_driver),
  3686. "qeth_l2");
  3687. break;
  3688. }
  3689. if (!card->discipline.ccwgdriver) {
  3690. dev_err(&card->gdev->dev, "There is no kernel module to "
  3691. "support discipline %d\n", discipline);
  3692. rc = -EINVAL;
  3693. }
  3694. return rc;
  3695. }
  3696. void qeth_core_free_discipline(struct qeth_card *card)
  3697. {
  3698. if (card->options.layer2)
  3699. symbol_put(qeth_l2_ccwgroup_driver);
  3700. else
  3701. symbol_put(qeth_l3_ccwgroup_driver);
  3702. card->discipline.ccwgdriver = NULL;
  3703. }
  3704. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3705. {
  3706. struct qeth_card *card;
  3707. struct device *dev;
  3708. int rc;
  3709. unsigned long flags;
  3710. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3711. dev = &gdev->dev;
  3712. if (!get_device(dev))
  3713. return -ENODEV;
  3714. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3715. card = qeth_alloc_card();
  3716. if (!card) {
  3717. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3718. rc = -ENOMEM;
  3719. goto err_dev;
  3720. }
  3721. card->read.ccwdev = gdev->cdev[0];
  3722. card->write.ccwdev = gdev->cdev[1];
  3723. card->data.ccwdev = gdev->cdev[2];
  3724. dev_set_drvdata(&gdev->dev, card);
  3725. card->gdev = gdev;
  3726. gdev->cdev[0]->handler = qeth_irq;
  3727. gdev->cdev[1]->handler = qeth_irq;
  3728. gdev->cdev[2]->handler = qeth_irq;
  3729. rc = qeth_determine_card_type(card);
  3730. if (rc) {
  3731. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3732. goto err_card;
  3733. }
  3734. rc = qeth_setup_card(card);
  3735. if (rc) {
  3736. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3737. goto err_card;
  3738. }
  3739. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3740. rc = qeth_core_create_osn_attributes(dev);
  3741. if (rc)
  3742. goto err_card;
  3743. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3744. if (rc) {
  3745. qeth_core_remove_osn_attributes(dev);
  3746. goto err_card;
  3747. }
  3748. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3749. if (rc) {
  3750. qeth_core_free_discipline(card);
  3751. qeth_core_remove_osn_attributes(dev);
  3752. goto err_card;
  3753. }
  3754. } else {
  3755. rc = qeth_core_create_device_attributes(dev);
  3756. if (rc)
  3757. goto err_card;
  3758. }
  3759. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3760. list_add_tail(&card->list, &qeth_core_card_list.list);
  3761. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3762. return 0;
  3763. err_card:
  3764. qeth_core_free_card(card);
  3765. err_dev:
  3766. put_device(dev);
  3767. return rc;
  3768. }
  3769. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3770. {
  3771. unsigned long flags;
  3772. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3773. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3774. if (card->discipline.ccwgdriver) {
  3775. card->discipline.ccwgdriver->remove(gdev);
  3776. qeth_core_free_discipline(card);
  3777. }
  3778. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3779. qeth_core_remove_osn_attributes(&gdev->dev);
  3780. } else {
  3781. qeth_core_remove_device_attributes(&gdev->dev);
  3782. }
  3783. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3784. list_del(&card->list);
  3785. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3786. qeth_core_free_card(card);
  3787. dev_set_drvdata(&gdev->dev, NULL);
  3788. put_device(&gdev->dev);
  3789. return;
  3790. }
  3791. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3792. {
  3793. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3794. int rc = 0;
  3795. int def_discipline;
  3796. if (!card->discipline.ccwgdriver) {
  3797. if (card->info.type == QETH_CARD_TYPE_IQD)
  3798. def_discipline = QETH_DISCIPLINE_LAYER3;
  3799. else
  3800. def_discipline = QETH_DISCIPLINE_LAYER2;
  3801. rc = qeth_core_load_discipline(card, def_discipline);
  3802. if (rc)
  3803. goto err;
  3804. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3805. if (rc)
  3806. goto err;
  3807. }
  3808. rc = card->discipline.ccwgdriver->set_online(gdev);
  3809. err:
  3810. return rc;
  3811. }
  3812. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3813. {
  3814. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3815. return card->discipline.ccwgdriver->set_offline(gdev);
  3816. }
  3817. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3818. {
  3819. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3820. if (card->discipline.ccwgdriver &&
  3821. card->discipline.ccwgdriver->shutdown)
  3822. card->discipline.ccwgdriver->shutdown(gdev);
  3823. }
  3824. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3825. .owner = THIS_MODULE,
  3826. .name = "qeth",
  3827. .driver_id = 0xD8C5E3C8,
  3828. .probe = qeth_core_probe_device,
  3829. .remove = qeth_core_remove_device,
  3830. .set_online = qeth_core_set_online,
  3831. .set_offline = qeth_core_set_offline,
  3832. .shutdown = qeth_core_shutdown,
  3833. };
  3834. static ssize_t
  3835. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3836. size_t count)
  3837. {
  3838. int err;
  3839. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3840. qeth_core_ccwgroup_driver.driver_id);
  3841. if (err)
  3842. return err;
  3843. else
  3844. return count;
  3845. }
  3846. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3847. static struct {
  3848. const char str[ETH_GSTRING_LEN];
  3849. } qeth_ethtool_stats_keys[] = {
  3850. /* 0 */{"rx skbs"},
  3851. {"rx buffers"},
  3852. {"tx skbs"},
  3853. {"tx buffers"},
  3854. {"tx skbs no packing"},
  3855. {"tx buffers no packing"},
  3856. {"tx skbs packing"},
  3857. {"tx buffers packing"},
  3858. {"tx sg skbs"},
  3859. {"tx sg frags"},
  3860. /* 10 */{"rx sg skbs"},
  3861. {"rx sg frags"},
  3862. {"rx sg page allocs"},
  3863. {"tx large kbytes"},
  3864. {"tx large count"},
  3865. {"tx pk state ch n->p"},
  3866. {"tx pk state ch p->n"},
  3867. {"tx pk watermark low"},
  3868. {"tx pk watermark high"},
  3869. {"queue 0 buffer usage"},
  3870. /* 20 */{"queue 1 buffer usage"},
  3871. {"queue 2 buffer usage"},
  3872. {"queue 3 buffer usage"},
  3873. {"rx handler time"},
  3874. {"rx handler count"},
  3875. {"rx do_QDIO time"},
  3876. {"rx do_QDIO count"},
  3877. {"tx handler time"},
  3878. {"tx handler count"},
  3879. {"tx time"},
  3880. /* 30 */{"tx count"},
  3881. {"tx do_QDIO time"},
  3882. {"tx do_QDIO count"},
  3883. };
  3884. int qeth_core_get_stats_count(struct net_device *dev)
  3885. {
  3886. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3887. }
  3888. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3889. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3890. struct ethtool_stats *stats, u64 *data)
  3891. {
  3892. struct qeth_card *card = dev->ml_priv;
  3893. data[0] = card->stats.rx_packets -
  3894. card->perf_stats.initial_rx_packets;
  3895. data[1] = card->perf_stats.bufs_rec;
  3896. data[2] = card->stats.tx_packets -
  3897. card->perf_stats.initial_tx_packets;
  3898. data[3] = card->perf_stats.bufs_sent;
  3899. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3900. - card->perf_stats.skbs_sent_pack;
  3901. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3902. data[6] = card->perf_stats.skbs_sent_pack;
  3903. data[7] = card->perf_stats.bufs_sent_pack;
  3904. data[8] = card->perf_stats.sg_skbs_sent;
  3905. data[9] = card->perf_stats.sg_frags_sent;
  3906. data[10] = card->perf_stats.sg_skbs_rx;
  3907. data[11] = card->perf_stats.sg_frags_rx;
  3908. data[12] = card->perf_stats.sg_alloc_page_rx;
  3909. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3910. data[14] = card->perf_stats.large_send_cnt;
  3911. data[15] = card->perf_stats.sc_dp_p;
  3912. data[16] = card->perf_stats.sc_p_dp;
  3913. data[17] = QETH_LOW_WATERMARK_PACK;
  3914. data[18] = QETH_HIGH_WATERMARK_PACK;
  3915. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3916. data[20] = (card->qdio.no_out_queues > 1) ?
  3917. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3918. data[21] = (card->qdio.no_out_queues > 2) ?
  3919. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3920. data[22] = (card->qdio.no_out_queues > 3) ?
  3921. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3922. data[23] = card->perf_stats.inbound_time;
  3923. data[24] = card->perf_stats.inbound_cnt;
  3924. data[25] = card->perf_stats.inbound_do_qdio_time;
  3925. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3926. data[27] = card->perf_stats.outbound_handler_time;
  3927. data[28] = card->perf_stats.outbound_handler_cnt;
  3928. data[29] = card->perf_stats.outbound_time;
  3929. data[30] = card->perf_stats.outbound_cnt;
  3930. data[31] = card->perf_stats.outbound_do_qdio_time;
  3931. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3932. }
  3933. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3934. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3935. {
  3936. switch (stringset) {
  3937. case ETH_SS_STATS:
  3938. memcpy(data, &qeth_ethtool_stats_keys,
  3939. sizeof(qeth_ethtool_stats_keys));
  3940. break;
  3941. default:
  3942. WARN_ON(1);
  3943. break;
  3944. }
  3945. }
  3946. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3947. void qeth_core_get_drvinfo(struct net_device *dev,
  3948. struct ethtool_drvinfo *info)
  3949. {
  3950. struct qeth_card *card = dev->ml_priv;
  3951. if (card->options.layer2)
  3952. strcpy(info->driver, "qeth_l2");
  3953. else
  3954. strcpy(info->driver, "qeth_l3");
  3955. strcpy(info->version, "1.0");
  3956. strcpy(info->fw_version, card->info.mcl_level);
  3957. sprintf(info->bus_info, "%s/%s/%s",
  3958. CARD_RDEV_ID(card),
  3959. CARD_WDEV_ID(card),
  3960. CARD_DDEV_ID(card));
  3961. }
  3962. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3963. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3964. struct ethtool_cmd *ecmd)
  3965. {
  3966. struct qeth_card *card = netdev->ml_priv;
  3967. enum qeth_link_types link_type;
  3968. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3969. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3970. else
  3971. link_type = card->info.link_type;
  3972. ecmd->transceiver = XCVR_INTERNAL;
  3973. ecmd->supported = SUPPORTED_Autoneg;
  3974. ecmd->advertising = ADVERTISED_Autoneg;
  3975. ecmd->duplex = DUPLEX_FULL;
  3976. ecmd->autoneg = AUTONEG_ENABLE;
  3977. switch (link_type) {
  3978. case QETH_LINK_TYPE_FAST_ETH:
  3979. case QETH_LINK_TYPE_LANE_ETH100:
  3980. ecmd->supported |= SUPPORTED_10baseT_Half |
  3981. SUPPORTED_10baseT_Full |
  3982. SUPPORTED_100baseT_Half |
  3983. SUPPORTED_100baseT_Full |
  3984. SUPPORTED_TP;
  3985. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3986. ADVERTISED_10baseT_Full |
  3987. ADVERTISED_100baseT_Half |
  3988. ADVERTISED_100baseT_Full |
  3989. ADVERTISED_TP;
  3990. ecmd->speed = SPEED_100;
  3991. ecmd->port = PORT_TP;
  3992. break;
  3993. case QETH_LINK_TYPE_GBIT_ETH:
  3994. case QETH_LINK_TYPE_LANE_ETH1000:
  3995. ecmd->supported |= SUPPORTED_10baseT_Half |
  3996. SUPPORTED_10baseT_Full |
  3997. SUPPORTED_100baseT_Half |
  3998. SUPPORTED_100baseT_Full |
  3999. SUPPORTED_1000baseT_Half |
  4000. SUPPORTED_1000baseT_Full |
  4001. SUPPORTED_FIBRE;
  4002. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4003. ADVERTISED_10baseT_Full |
  4004. ADVERTISED_100baseT_Half |
  4005. ADVERTISED_100baseT_Full |
  4006. ADVERTISED_1000baseT_Half |
  4007. ADVERTISED_1000baseT_Full |
  4008. ADVERTISED_FIBRE;
  4009. ecmd->speed = SPEED_1000;
  4010. ecmd->port = PORT_FIBRE;
  4011. break;
  4012. case QETH_LINK_TYPE_10GBIT_ETH:
  4013. ecmd->supported |= SUPPORTED_10baseT_Half |
  4014. SUPPORTED_10baseT_Full |
  4015. SUPPORTED_100baseT_Half |
  4016. SUPPORTED_100baseT_Full |
  4017. SUPPORTED_1000baseT_Half |
  4018. SUPPORTED_1000baseT_Full |
  4019. SUPPORTED_10000baseT_Full |
  4020. SUPPORTED_FIBRE;
  4021. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4022. ADVERTISED_10baseT_Full |
  4023. ADVERTISED_100baseT_Half |
  4024. ADVERTISED_100baseT_Full |
  4025. ADVERTISED_1000baseT_Half |
  4026. ADVERTISED_1000baseT_Full |
  4027. ADVERTISED_10000baseT_Full |
  4028. ADVERTISED_FIBRE;
  4029. ecmd->speed = SPEED_10000;
  4030. ecmd->port = PORT_FIBRE;
  4031. break;
  4032. default:
  4033. ecmd->supported |= SUPPORTED_10baseT_Half |
  4034. SUPPORTED_10baseT_Full |
  4035. SUPPORTED_TP;
  4036. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4037. ADVERTISED_10baseT_Full |
  4038. ADVERTISED_TP;
  4039. ecmd->speed = SPEED_10;
  4040. ecmd->port = PORT_TP;
  4041. }
  4042. return 0;
  4043. }
  4044. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4045. static int __init qeth_core_init(void)
  4046. {
  4047. int rc;
  4048. pr_info("loading core functions\n");
  4049. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4050. rwlock_init(&qeth_core_card_list.rwlock);
  4051. rc = qeth_register_dbf_views();
  4052. if (rc)
  4053. goto out_err;
  4054. rc = ccw_driver_register(&qeth_ccw_driver);
  4055. if (rc)
  4056. goto ccw_err;
  4057. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4058. if (rc)
  4059. goto ccwgroup_err;
  4060. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4061. &driver_attr_group);
  4062. if (rc)
  4063. goto driver_err;
  4064. qeth_core_root_dev = s390_root_dev_register("qeth");
  4065. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4066. if (rc)
  4067. goto register_err;
  4068. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4069. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4070. if (!qeth_core_header_cache) {
  4071. rc = -ENOMEM;
  4072. goto slab_err;
  4073. }
  4074. return 0;
  4075. slab_err:
  4076. s390_root_dev_unregister(qeth_core_root_dev);
  4077. register_err:
  4078. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4079. &driver_attr_group);
  4080. driver_err:
  4081. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4082. ccwgroup_err:
  4083. ccw_driver_unregister(&qeth_ccw_driver);
  4084. ccw_err:
  4085. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4086. qeth_unregister_dbf_views();
  4087. out_err:
  4088. pr_err("Initializing the qeth device driver failed\n");
  4089. return rc;
  4090. }
  4091. static void __exit qeth_core_exit(void)
  4092. {
  4093. s390_root_dev_unregister(qeth_core_root_dev);
  4094. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4095. &driver_attr_group);
  4096. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4097. ccw_driver_unregister(&qeth_ccw_driver);
  4098. kmem_cache_destroy(qeth_core_header_cache);
  4099. qeth_unregister_dbf_views();
  4100. pr_info("core functions removed\n");
  4101. }
  4102. module_init(qeth_core_init);
  4103. module_exit(qeth_core_exit);
  4104. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4105. MODULE_DESCRIPTION("qeth core functions");
  4106. MODULE_LICENSE("GPL");